Method, system and storage medium for wiring layering of very large scale integrated circuits

Abstract

The present invention discloses a wiring layering method, system and storage medium for a very large scale integrated circuit, comprising: obtaining an artificial configuration file, establishing a wire net frame of the wire net; calculating feasible solutions and weights for allocating the wire net to each layer; iteratively calculating the number of wire nets N under the current k wiring layering schemes; m The i-th feasible solution is assigned to any optional layer L m The wiring weight w i (N m , L), update the feasible solution s of each network layer during iteration i (N1,…,N m ), and the feasible solution weight w i (N1,…,N m ), the feasible solution corresponding to the feasible solution weight with the smallest value is used as the optimal layering scheme of the network cable. The wiring layering scheme of the present invention can not only make the wiring meet the constraint conditions, but also can efficiently obtain the optimal wiring layering scheme.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a wiring layering method, system and storage medium for ultra-large-scale integrated circuits. Background Art

[0002] A very large scale integrated circuit (VLSI) is an integrated circuit that combines a large number of transistors into a single chip, achieving a higher level of integration than an LSI. The number of integrated transistors varies across different standards. In VLSI design, routing aims to physically connect the various modules within the circuit within a specified routing area. It is a critical step in VLSI physical design, and the most crucial step in routing is determining the layer on which each device is routed within the VLSI.

[0003] In VLSI design, each circuit layer (i.e., metal layer) has regularly arranged routing channels (routing tracks). Routing must occur within these channels and meet certain DRC constraints, such as line width and spacing. Existing techniques require manual routing of specific nets based on these constraints, and then routing other nets based on this. This results in a high routing workload and low efficiency. Summary of the Invention

[0004] In view of the above problems, the present application provides a wiring layering method for a very large scale integrated circuit, which is used to solve the technical problem of low efficiency of wiring layering of the very large scale integrated circuit.

[0005] To achieve the above object, a wiring layering method for a very large scale integrated circuit is provided, comprising the following steps:

[0006] Obtaining an artificial configuration file, and configuring constraints for network routing according to the artificial configuration file;

[0007] Establishing a wire mesh frame of the wire mesh;

[0008] Calculating feasible solutions for allocating each of the nets to each of the layers in the VLSI according to the constraint conditions, and weights corresponding to each of the feasible solutions;

[0009] Iterative calculation under the current k kinds of wiring layering schemes, the line network N m The i-th feasible solution is assigned to any optional layer L m The wiring weight w i (N m, L); the wiring weight is the ratio of the area of ​​the remaining portion of the wire mesh frame in the layer to the total area of ​​the wire mesh frame; wherein 1≤m≤k,1≤i≤k;

[0010] The wiring weight w obtained by iterative calculation i (N m , L), update the feasible solution s for each layer of the network i (N1,...,N m ), and the feasible solution weight w i (N1,...,N m );

[0011] The feasible solution corresponding to the feasible solution weight with the smallest value is used as the optimal layering solution for the network cable.

[0012] Furthermore, the constraint conditions in the manual configuration file include any one or more parameters of the designated routing layer, prohibited routing layer, routing width, and line width of the network cable.

[0013] Furthermore, the method further includes obtaining a routing channel, wherein the wire net is routed within the routing channel in the feasible solution.

[0014] Furthermore, the wire mesh border is a minimum rectangle that surrounds all pins corresponding to the wire mesh, and the wire mesh border is aligned with the wiring channel.

[0015] Furthermore, after establishing the wire mesh frame, the method further includes:

[0016] The areas of the wire mesh frames are calculated, and the wire mesh frames are sorted from largest to smallest according to the areas.

[0017] Furthermore, the number of components on the ultra-large-scale integrated circuit exceeds 100,000.

[0018] To solve the above technical problems, this application also provides another technical solution:

[0019] A wiring layer system for a very large scale integrated circuit, comprising:

[0020] An acquisition module is used to acquire a manual configuration file and a routing channel, and configure the constraints for routing the wire network according to the manual configuration file;

[0021] An establishment module, configured to establish a mesh frame of the mesh, and calculate feasible solutions for allocating each mesh to each layer in the VLSI according to the constraint conditions, as well as weights corresponding to each feasible solution;

[0022] Iteration module, used for iterative calculation under the current k kinds of wiring layering schemes, m The i-th feasible solution is assigned to any optional layer L m The wiring weight w i (N m , L); the wiring weight is the ratio of the area of ​​the remaining portion of the wire mesh frame in the layer to the total area of ​​the wire mesh frame; wherein, 1≤m≤k,1≤i≤k; and the wiring weight w obtained by iterative calculation i (N m , L), update the feasible solution s for each layer of the network i (N1,...,N m ), and the feasible solution weight w i (N1,...,N m );

[0023] The output module is used to use the feasible solution corresponding to the feasible solution weight with the smallest value as the optimal layering solution of the network cable.

[0024] Furthermore, the wire mesh border is a minimum rectangle that surrounds all pins corresponding to the wire mesh, and the wire mesh border is aligned with the wiring channel.

[0025] Furthermore, the manual configuration file includes any one or more parameters of the network cable: the designated routing layer, the prohibited routing layer, the routing width, and the line width.

[0026] To solve the above technical problems, this application also provides another technical solution:

[0027] A computer-readable storage medium stores a computer program, which, when executed by a processor, executes the wiring layering method for a very large-scale integrated circuit described in any one of the above technical solutions.

[0028] Unlike existing technologies, the above-mentioned technical solution provides a routing layering scheme for VLSIs based on dynamic programming. This scheme not only supports manual configuration of network constraints during routing, but also, given k feasible solutions, dynamically plans the layering of each network using these k feasible solutions, ultimately achieving an overall optimal layering scheme for each network. This routing layering scheme not only ensures that routing meets constraints but also efficiently achieves the optimal routing layering scheme.

[0029] The above-mentioned records related to the content of the invention are only an overview of the technical solution of this application. In order to enable ordinary technicians in this field to understand the technical solution of this application more clearly, and then implement it according to the text of the specification and the contents recorded in the drawings, and to make the above-mentioned purposes and other purposes, features and advantages of this application easier to understand, the following is an explanation in combination with the specific implementation methods and drawings of this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings are only used to illustrate the principles, implementation methods, applications, features and effects of the specific embodiments of the present invention and other related contents, and are not to be considered as limiting the present application.

[0031] In the drawings of the specification:

[0032] Figure 1 A flowchart of a wiring layering method for a very large scale integrated circuit according to a specific embodiment;

[0033] Figure 2 It is a structural diagram of the wire mesh frame described in the specific implementation method;

[0034] Figure 3 It is a schematic diagram of the projection area of ​​the wire mesh on the layer where it is located according to the specific implementation method;

[0035] Figure 4 A schematic diagram of the projection area of ​​the wire mesh on the layer in another specific embodiment;

[0036] Figure 5 A specific flow chart of the wiring layering of a very large scale integrated circuit according to a specific embodiment;

[0037] Figure 6 A block diagram of a wiring layer system for a very large scale integrated circuit according to a specific embodiment;

[0038] Figure 7 A schematic diagram of a computer-readable storage medium according to a specific embodiment;

[0039] The reference numerals in the above drawings are described as follows:

[0040] 600. A hierarchical wiring system for a very large scale integrated circuit; 601. An acquisition module; 602. An establishment module; 603. An iteration module; 604. An output module; 700. A computer-readable storage medium. DETAILED DESCRIPTION

[0041] In order to explain in detail the possible application scenarios, technical principles, specific solutions that can be implemented, and the purpose and effects of this application, the following is a detailed description of the specific embodiments listed in conjunction with the accompanying drawings. The embodiments described herein are only used to more clearly illustrate the technical solutions of this application and are therefore only examples and are not intended to limit the scope of protection of this application.

[0042] References to "embodiments" herein mean that the specific features, structures, or characteristics described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the word "embodiment" in various places in the specification does not necessarily refer to the same embodiment, nor does it particularly limit its independence or relevance to other embodiments. In principle, in this application, as long as there are no technical contradictions or conflicts, the various technical features mentioned in the embodiments can be combined in any manner to form a corresponding implementable technical solution.

[0043] Unless otherwise defined, the technical terms used herein have the same meanings as those generally understood by those skilled in the art to which this application belongs; the use of relevant terms herein is only for describing specific embodiments and is not intended to limit this application.

[0044] In the description of this application, the term "and / or" is used to describe a logical relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A exists, B exists, and both A and B exist. In addition, the character " / " in this document generally indicates that the objects before and after are in a logical "or" relationship.

[0045] In this application, terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual quantity, priority or sequence relationship between these entities or operations.

[0046] Without further limitations, in this application, the words "include", "comprise", "have" or other similar open-ended expressions used in sentences are intended to cover non-exclusive inclusion. These expressions do not exclude the presence of additional elements in the process, method or product that includes the elements, so that the process, method or product that includes a series of elements may include not only those defined elements, but also other elements that are not explicitly listed, or also include elements that are inherent to such process, method or product.

[0047] Consistent with the understanding in the Examination Guidelines, in this application, expressions such as "greater than," "less than," and "exceed" are understood to exclude the number itself; expressions such as "above," "below," and "within" are understood to include the number itself. Furthermore, in the description of the embodiments of this application, "multiple" means more than two (including two), and similar expressions related to "multiple" are also understood in this manner, such as "multiple groups," "multiple times," etc., unless otherwise specifically defined.

[0048] In the description of the embodiments of the present application, the space-related expressions used, such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "vertical", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicate the orientation or position relationship based on the orientation or position relationship shown in the specific embodiments or drawings, and are only for the convenience of describing the specific embodiments of the present application or facilitating the reader's understanding, and do not indicate or imply that the device or component referred to must have a specific position, a specific orientation, or be constructed or operated in a specific orientation. Therefore, it should not be understood as a limitation on the embodiments of the present application.

[0049] Unless otherwise expressly specified or limited, in the description of the embodiments of the present application, the terms "installed", "connected", "connected", "fixed", "set", etc. used should be understood in a broad sense. For example, the "connection" can be a fixed connection, a detachable connection, or an integrated setting; it can be a mechanical connection, an electrical connection, or a communication connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. For those skilled in the art of the present application, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0050] See also Figures 1 to 5 This embodiment provides a layered routing method for a very large scale integrated circuit (VLSI). This layered routing method can be used to automatically route wire nets within the routing channels of each layer of a VLSI, electrically connecting the various modules within the circuit. The layer is a metal layer having metal conductors disposed thereon, and the VLSI refers to an integrated circuit having more than 100,000 components. This layered routing method can be used to set routing constraints such as line width and spacing for each wire net. It can also be used to iteratively calculate the layer to which each wire net is routed, thereby improving routing efficiency.

[0051] like Figure 1 As shown, the wiring layering method of the ultra-large-scale integrated circuit includes the following steps:

[0052] S101, obtaining a manual configuration file, and configuring network routing constraints according to the manual configuration file;

[0053] S102, establishing a wire mesh frame of the wire mesh;

[0054] S103, calculating feasible solutions for allocating each of the nets to each of the layers in the VLSI according to the constraint conditions, and weights corresponding to each of the feasible solutions;

[0055] S104, iteratively calculate the network N under the current k types of wiring layering schemes. m The i-th feasible solution is assigned to any optional layer L m The wiring weight w i (N m , L); the wiring weight is the ratio of the area of ​​the remaining portion of the wire mesh frame in the layer to the total area of ​​the wire mesh frame; wherein 1≤m≤k,1≤i≤k;

[0056] S105: The wiring weight w obtained by iterative calculation i (N m , L), update the feasible solution s for each layer of the network i (N1,...,N m ), and the feasible solution weight w i (N1,...,N m );

[0057] S106: The feasible solution corresponding to the feasible solution weight with the smallest value is used as the optimal layering solution for the network cable.

[0058] In step S101, the manual configuration file can be pre-set according to the electrical performance requirements of the VLSI, and then each wire net to be routed is configured and set according to the manual configuration file before automatic layering. The constraint conditions in the manual configuration file include any one or more parameters of the designated routing layer, prohibited routing layer, routing width, and line width of the wire net. For example, for each wire net N i , let Li be the set of layers where the net can be routed. If manual configuration allows routing only on a certain layer, then Li is designated as that layer. If routing is prohibited on a certain layer, then Li is taken as the set of all layers except that layer.

[0059] In step S102, for each net N i , the wire mesh border can be established according to the positions of all pins in the wire mesh, and the wire mesh border is recorded as Bi. Figure 2 As shown, Figure 2If the four blue squares in the figure represent the four pins of a certain net, then the net border of the net is the smallest rectangle that encloses these four pins (blue squares), and the smallest rectangle is aligned with the routing channel. In some embodiments, after establishing the net border of the net, the method further includes: calculating the area of ​​the net border, and sorting the net borders from largest to smallest according to the area.

[0060] In step S103, the established mesh line border is initialized, and under the condition that the constraints of step S101 are satisfied, the feasible solutions and weights of each mesh line assigned to each layer in the VLSI are calculated. For example, for mesh N1, s1(N1), ..., s k (N1) is a feasible solution to place the network N1 on each layer, and record its weights w1(N1),...,w k (N1).

[0061] After the initialization of step S103, the process proceeds to step S104 and step S105 to perform iterative calculations on each network. In steps S104 and S105, the dynamic programming algorithm is used to recursively calculate the routing scheme s for each network for m=1, ..., k. i (N1,...,N m ) and routing weight w i (N1,...,N m ). The wiring weight is calculated as the ratio of the area of ​​the empty part surrounded by the pin of the current network in the L layer to the total area. The weight corresponds to the network N m The blank area in the projection area of ​​this layer. Figure 3 and Figure 4 As shown, Figure 3 and Figure 4 In the network N m Located on different layers, Figure 3 In the network N m There is overlap with the network N2 and N3, and Figure 4 Centerline Network N m There is no overlap with N2 and N3, so Figure 4 Centerline Network N m The wiring weight is greater than Figure 3 The weight in .

[0062] In steps S104 and S105, for any m≥1 and network N m , for any layer L in Lm, use w i (N m , L) is the result of the current stratification, N m Assign the wiring weight of the L layer in the recorded i-th feasible solution. And record s1(N1,...,Nm-1 ),...,s k (N1,...,N m-1 ) is the network N1, ..., N m-1 The k schemes have recorded the allocation scheme, that is, the layer to which each network should be allocated is recorded, and the corresponding weights are w1(N1, ..., N m-1 ), ..., w k (N1,...,N m-1 Consider the network N m , and its optional layer set Lm, for any layer L in Lm, N m Route to the L layer, calculate its optimal weight, and take the minimum value: for any 1≤i≤k; w i (N1,...,N m )=min{w i (N1,...,N m-1 )+w i (N m ,L)|L∈L m}..

[0063] Assuming there are t wire nets, execute steps S104 and S105 until m=t, and finally get the optimal solution s1(N1, ..., N m-1 ),...,s k (N1,...,N m-1 ).

[0064] In step S106, the final end is s i (N1,...,N t ), that is, the allocation scheme with the smallest weight among all the network N1, ..., N m tiered scheme.

[0065] like Figure 5 As shown, in a specific embodiment of a wiring layering method for a very large scale integrated circuit, the following steps are included:

[0066] Get all the nets and routing channels of the cell layout (i.e. Figure 5 channels in ) and manual profiles.

[0067] For each wire mesh, its wire mesh border is calculated. The calculation method of the wire mesh border is the same as the method of establishing the wire mesh border in the above embodiment.

[0068] Sort the above wire mesh frames by area from largest to smallest;

[0069] Let m = 0, calculate w1(N1), ..., w k (N1), that is, to initialize, record s1(N1), ..., s1 for the line network N1.k (N1) is a feasible solution to place the network N1 on each layer, and record its weights w1(N1),...,w k (N1);

[0070] Then enter the iterative process, including: judging m <t是否成立,若是,则对任意i,以及N m The possible layer L of the calculation is based on the result of the current layer, and M m The wiring weight w when allocating the L layers in the i-th feasible solution of the record i (N m , L); if not, then for any i, update w i (N1,...,N m ); for any 1≤i≤k, w i (N1,...,N m )=min{w i (N1,...,N m-1 )+w i (N m ,L)|L∈L m}; That is, in any layer L among all layers Lm of any VLSI, the line network N m Route to L layer and calculate its optimal weight, w i (N1,...,N m ) takes the minimum value among all rights.

[0071] Remember to make w i (N1,...,N t )The smallest subscript is j, output s i (N1,...,N t ).

[0072] Assume there are t wire meshes, execute the above iterative process until m=t, and finally get the optimal solution s1(N1,...,N m-1 ),...,s k (N1,...,N m-1 ), and finally output the feasible solution with the smallest weight among these k feasible solutions.

[0073] In this specific embodiment, the dynamic programming algorithm is used to recursively calculate w for m=1,...,k, i (N1,...,N m ) and s i (N1,...,N m ), and finally at the end i (N1,...,N t ), that is, the allocation scheme with the smallest weight among all the network N1, ..., N ma hierarchical scheme.

[0074] As shown in Figure 6 , in an embodiment, a wiring hierarchical system 600 of a very large scale integrated circuit is provided. The wiring hierarchical system 600 of the very large scale integrated circuit comprises an obtaining module 601, a building module 602, an iterating module 603 and an outputting module 604.

[0075] The obtaining module 601 is configured to obtain a manual configuration file and a wiring channel, and obtain constraint conditions for configuring a wire net when wiring.

[0076] The building module 602 is configured to build a wire net frame of the wire net, and calculate feasible solutions of distributing each of the wire nets to each layer of the very large scale integrated circuit according to the constraint conditions, and weights corresponding to each of the feasible solutions.

[0077] The iterating module 603 is configured to iteratively calculate a wiring weight w m (N m , L) of distributing an i-th feasible solution of the wire net N i to any optional layer L m under a current k-th wiring hierarchical scheme; the wiring weight is a ratio of an area of a residual part surrounded by the wire net frame in the layer to a total area of the wire net frame; wherein 1≤m≤k, 1≤i≤k; and update each of the feasible solutions s i (N1,..., N m ) and the feasible solution weight w i (N1,..., N m ) of each of the wire net hierarchical solutions according to the wiring weight w i (N m , L) obtained by the iterative calculation.

[0078] The outputting module 604 is configured to take the feasible solution corresponding to the minimum feasible solution weight as an optimal hierarchical scheme of the wire net.

[0079] In the above embodiment, the wire net frame is a minimum rectangle surrounding all pins of the corresponding wire net, and the wire net frame is aligned with the wiring channel. Wherein, for each wire net N i , a wire net frame can be built according to the positions of all pins in the wire net, and the wire net frame is denoted as Bi. As shown in Figure 2 , four blue squares in Figure 2 are four pins of a wire net, and the wire net frame of the wire net is a minimum rectangle surrounding the four pins (blue squares), and the minimum rectangle is aligned to the wiring channel.

[0080] In the above embodiment, the manual configuration file includes any one or more parameters of the designated routing layer, prohibited routing layer, routing width, and line width of the network line. The manual configuration file can be pre-set according to the electrical performance requirements of the ultra-large-scale integrated circuit, and then each network to be routed is configured and set according to the manual configuration file before automatic stratification. The constraint conditions in the manual configuration file include any one or more parameters of the designated routing layer, prohibited routing layer, routing width, and line width of the network line. For example, for each network N i , let Li be the set of layers where the net can be routed. If manual configuration allows routing only on a certain layer, then Li is designated as that layer. If routing is prohibited on a certain layer, then Li is taken as the set of all layers except that layer.

[0081] In this embodiment, the VLSI routing hierarchical system 600 not only supports manual configuration of net constraints during routing, but also, given k feasible solutions, dynamically plans the hierarchical layout of each net using these k feasible solutions, ultimately achieving an overall optimal hierarchical layout for each net. This hierarchical routing solution not only ensures that routing satisfies constraints but also efficiently achieves the optimal routing hierarchical layout.

[0082] like Figure 7 As shown, in one embodiment, a computer-readable storage medium 700 is provided, in which a computer program is stored. When the computer program is executed by a processor, the wiring layering method of a very large-scale integrated circuit described in any one of the above embodiments is executed.

[0083] Finally, it should be noted that although the above embodiments have been described in the specification and drawings of this application, this does not limit the scope of patent protection of this application. All technical solutions generated by replacing or modifying equivalent structures or equivalent processes based on the essential concepts of this application using the contents recorded in the specification and drawings of this application, as well as directly or indirectly implementing the technical solutions of the above embodiments in other related technical fields, are included in the scope of patent protection of this application.

Claims

1. A wiring layering method for a very large scale integrated circuit, characterized in that: The following steps are involved: Obtaining an artificial configuration file, and configuring constraints for network routing according to the artificial configuration file; Establishing a wire mesh frame of the wire mesh; Calculating feasible solutions for allocating each of the nets to each layer of the VLSI according to the constraint conditions, and weights corresponding to each of the feasible solutions; Iterative calculation under the current k kinds of wiring layering schemes, the line network N m The i-th feasible solution is assigned to any optional layer L m The wiring weight w i (N m , L); the wiring weight is the ratio of the area of ​​the remaining portion of the wire mesh frame in the layer to the total area of ​​the wire mesh frame; wherein 1≤m≤k,1≤i≤k; The wiring weight w obtained by iterative calculation i (N m , L), update the feasible solution s for each layer of the network i (N1,...,N m ), and the feasible solution weight w i (N1,...,N m ); The feasible solution corresponding to the feasible solution weight with the smallest value is used as the optimal layering solution for the network cable.

2. The wiring layering method of a very large scale integrated circuit according to claim 1, wherein: The constraint conditions in the manual configuration file include any one or more parameters of the designated routing layer, prohibited routing layer, routing width, and line width of the network line.

3. The wiring layering method for a very large scale integrated circuit according to claim 1, wherein: The method further includes obtaining a routing channel, wherein the wire net is routed within the routing channel in the feasible solution.

4. The wiring layering method of a very large scale integrated circuit according to claim 3, wherein: The wire mesh border is a minimum rectangle that surrounds all pins corresponding to the wire mesh, and the wire mesh border is aligned with the wiring channel.

5. The wiring layering method for a very large scale integrated circuit according to claim 1, wherein: After establishing the wire mesh frame of the wire mesh, the method further includes: The areas of the wire mesh frames are calculated, and the wire mesh frames are sorted from largest to smallest according to the areas.

6. The wiring layering method for a very large scale integrated circuit according to claim 1, wherein: The number of components on the ultra-large-scale integrated circuit exceeds 100,000.

7. A wiring layer system for a very large scale integrated circuit, characterized in that: include: An acquisition module is used to acquire a manual configuration file and a routing channel, and configure the constraints for routing the wire network according to the manual configuration file; An establishment module, configured to establish a mesh frame of the mesh, and calculate feasible solutions for allocating each mesh to each layer of the VLSI according to the constraint conditions, as well as weights corresponding to each feasible solution; Iteration module, used for iterative calculation under the current k kinds of wiring layering schemes, m The i-th feasible solution is assigned to any optional layer L m The wiring weight w i (N m , L); the wiring weight is the ratio of the area of ​​the remaining portion of the wire mesh frame in the layer to the total area of ​​the wire mesh frame; wherein, 1≤m≤k, 1≤i≤k; and the wiring weight w obtained by iterative calculation i (N m , L), update the feasible solution s for each layer of the network i (N1,...,N m ), and the feasible solution weight w i (N1,...,N m ); The output module is used to use the feasible solution corresponding to the feasible solution weight with the smallest value as the optimal layering solution of the network cable.

8. The wiring layer system for a very large scale integrated circuit according to claim 7, wherein: The wire mesh border is a minimum rectangle that surrounds all pins corresponding to the wire mesh, and the wire mesh border is aligned with the wiring channel.

9. The wiring layer system for a very large scale integrated circuit according to claim 7, wherein: The manual configuration file includes any one or more parameters of the network cable including the designated routing layer, prohibited routing layer, routing width, and line width.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the wiring layering method for a very large scale integrated circuit according to any one of claims 1 to 5 is executed.

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