Power semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a power semiconductor device and a manufacturing method thereof. The power semiconductor device comprises at least one gate-commutated thyristor unit, the gate-commutated thyristor unit comprises a first conductive type base region, the first conductive type base region comprises a first sub-base region, a second sub-base region and a third sub-base region with different doping concentrations, the first sub-base region and the second sub-base region are independently arranged and separated by the third sub-base region; the gate-commutated thyristor unit also comprises a second conductive type emitter region, a cathode electrode and a gate electrode, the second conductive type emitter region is arranged on the first sub-base region, the first sub-base region covers the side and bottom surfaces of the second conductive type emitter region, the cathode electrode is arranged on the second conductive type emitter region, and the gate electrode is arranged on the second sub-base region, thereby improving the turn-off current of the gate-commutated thyristor unit and improving the anti-triggering ability of the gate-commutated thyristor unit during commutation.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a power semiconductor device and a method for manufacturing the same. Background Art

[0002] Integrated Gate Commutated Thyristor (IGCT) is a new type of semiconductor switching device. IGCT device is formed by integrating gate drive circuit with gate commutated thyristor GCT. IGCT device is a megawatt-level, medium and high voltage switching device. IGCT device has the same high blocking capability and low on-state voltage drop as turn-off thyristor (GTO). IGCT device has similar switching performance as insulated gate bipolar transistor (IGBT). IGCT device is widely used in voltage source inverter, current source inverter, chopper, static circuit breaker and many other topology circuits.

[0003] GCT chip is a whole wafer structure, such as Figure 1 A top view of a GCT chip is shown, wherein the GCT chip comprises a terminal area S1, an active area AA and a gate contact ring S2, wherein the terminal area S1 surrounds the periphery of the active area AA, the active area AA comprises a plurality of parallel gate-commutated thyristor units, and the active area AA is displayed as a plurality of concentric cathode rings in the top view, each cathode ring is provided with a plurality of cathode comb strip areas distributed radially, the area outside the cathode comb strip area in each cathode ring is a gate area, the gate areas are connected to each other and surround the cathode comb strip area to form an independent island structure, the gate contact ring S2 is located inside the chip, the gate contact ring S2 is connected to each gate area, and the gate contact ring S2 is used to transmit gate signals and derive current from the cathode commutation of the gate-commutated thyristor unit to the gate when the gate-commutated thyristor unit is turned off.

[0004] The cross-section of the gate-commutated thyristor unit is shown in Figure 2As shown, the gate-commutated thyristor unit includes a P+ emitter region 101', an N buffer region 102', an N-drift region 103', a P base region 104', a P+ short base region 105' and an N+ emitter region 106' (i.e., the cathode comb region of the active region) which are arranged in sequence from the anode to the cathode. The P+ emitter region 101' and the N buffer region 102' form a PN junction J1, the N-drift region 102' and the P base region 104' form a PN junction J2, and the P+ short base region 105' and the N+ emitter region 106' form a PN junction J3. The anode electrode 111' is arranged on the bottom surface of the P+ emitter region and is in ohmic contact with the P+ emitter region, the cathode electrode 112' is arranged on the N+ emitter region 106' and is in ohmic contact with the N+ emitter region, the gate electrode 113' is arranged on the P+ short base region and is in ohmic contact with the P+ short base region 105', an insulating layer 114' is arranged between the cathode electrode 112' and the gate electrode 113', and the cathode electrode 112' and the gate electrode 113' are electrically isolated by the insulating layer 114'. The upper surfaces of the gate electrode 113' and the insulating layer 114' are covered by a passivation layer.

[0005] When the GCT device is turned off, a negative bias voltage V is applied between the cathode electrode 112' and the gate contact ring S2. GK , negative bias voltage V GK The voltage value cannot exceed the reverse breakdown voltage of the J3 junction, which is usually -20V. Figure 3 As shown, after receiving the electrical signal, the gate contact ring S2 transmits the electrical signal to the gate electrode 113', so as to apply a negative voltage to the gate of each gate-commutated thyristor unit, so that the PN junction J3 of the gate-commutated thyristor unit is reverse biased, and before the voltage of the PN junction J2 rises, the cathode electrode 112' completely commutates the current to the gate electrode 113' through the P+ short base region, and the turn-off current of the gate-commutated thyristor unit is positively correlated with the negative bias voltage applied to the gate cathode, that is, the greater the negative bias voltage applied to the gate cathode, the greater the turn-off current of the gate-commutated thyristor unit. For a single gate-commutated thyristor unit, increasing the reverse bias voltage between its gate cathodes can increase its turn-off current, but the reverse bias voltage between the gate cathodes is limited by the reverse breakdown voltage of the PN junction J3, and the reverse breakdown voltage of the PN junction J3 mainly depends on the concentration of the P+ short base region. The reverse breakdown voltage of the PN junction J3 decreases with the increase of the doping concentration of the P+ short base region 105', that is, reducing the concentration of the P+ short base region 105' can increase the reverse breakdown voltage of the PN junction J3, increase the reverse bias voltage of the gate cathode, and thus increase the turn-off current of the gate-commutated thyristor unit.

[0006] For the entire GCT chip, Figure 4 As shown, when the GCT device is turned off, a negative bias voltage V is applied between the cathode electrode 112' and the gate contact ring S2. GK, then the gate contact ring S2 transfers the negative bias voltage to the gate electrode 113' of each gate-commutated thyristor unit. The distance between the gate contact ring S2 and the gate electrode 113' located at different cathode rings is different, and the resistance R between the gate contact ring S2 and the gate electrode 113' located at different cathode rings is different. Mi The voltage drop generated by the gate contact ring transferring the negative bias voltage to the gate electrode 113' is also different. The voltage V between the gate cathodes of the gate-commutated thyristor units actually applied to each cathode ring is different. GKi After the gate contact ring S2 transfers the negative bias voltage to the gate electrode 113' of each gate-commutated thyristor unit, since the gate electrode 113' is connected to the P+ short base region 105', and the cathode electrode 112' is connected to the N+ emitter region, a resistance R is generated between the boundary of the gate electrode 113' and the P+ short base region 105' between the N+ emitter region. P+ , the N+ emitter region generates resistance R N+ , the electrical signal from the gate contact ring electrode to the gate electrode, the resistance R P+ , resistor R N+ A voltage drop will also occur, causing the voltage V actually applied to the gate cathodes of each gate-commutated thyristor unit to GKi’ is the voltage of the gate contact ring V GK Subtract the voltage drop generated by the gate electrode, subtract the voltage drop generated by the P+ short base region between the gate electrode boundary and the cathode region, and then subtract the voltage drop generated by the N+ emitter region. Specifically, the farther away from the gate contact ring S2, the greater the resistance between the gate electrode and the gate contact ring S2, the greater the voltage drop generated by the gate contact ring S2 transmitting the negative bias to the gate electrode 113', and the voltage V applied to the gate cathode of the gate-commutated thyristor unit GKi The smaller, that is, the farther the gate-commutated thyristor unit is from the gate contact ring S2, the smaller the turn-off current. The turn-off current of the gate-commutated thyristor unit is positively correlated with the speed of removing the cathode charge. Therefore, the charge of the cathode electrode 112' of the gate-commutated thyristor unit close to the gate contact ring S2 can be removed more quickly, and the gate-commutated thyristor unit close to the gate contact ring S2 can be turned off quickly. The gate-commutated thyristor unit far from the gate contact ring S2 is in the on state for a longer time and may be overloaded, which may eventually damage the entire GCT chip.

[0007] When the GCT chip is commutating, Figure 5As shown, the excess carriers of the N-drift region 103' pass through the P+ emitter region 101' and are drawn away by the anode electrode, and the holes of the N-drift region 103' pass through the P+ short base region 105' and are drawn away via the gate electrode 113'. As the voltage between the anode electrode 111' and the cathode electrode 112' continues to rise, under the high stress of high voltage and high current shutdown, the device enters a dynamic avalanche, and the holes generated by the avalanche and the holes directly below the N+ emitter region 106' flow along the P+ short base region 105' to the gate electrode 113'. Usually, the width of the N+ emitter region 106' is greater than 100um, so the distance that the holes travel along the P+ short base region 105' to the gate electrode 113' is very long. When the holes pass through the strong bend of the P / N+ junction, the resistance current reaches the maximum value, which easily reaches the turn-on voltage of the PN junction, causing the device to be re-triggered, and the device loses the gate control function, resulting in latch failure. Therefore, during the shutdown process, the device should be prevented from being re-triggered. From the perspective of structural design, the concentration of the P+ short base region 105' should be as high as possible, which conflicts with the requirement of the reverse-bias breakdown voltage of the PN junction J3. Summary of the invention

[0008] Based on this, the present application provides a power semiconductor device with high shutdown capability and a method for manufacturing the same.

[0009] In order to achieve the above object, a first aspect of the present invention provides a power semiconductor device, comprising at least one gate-commutated thyristor unit, wherein the gate-commutated thyristor unit comprises a first conductive type base region, wherein the first conductive type base region comprises a first sub-base region, a second sub-base region and a third sub-base region with different doping concentrations, wherein the first sub-base region and the second sub-base region are independently arranged and separated by the third sub-base region;

[0010] The gate-commutated thyristor unit also includes a second conductive type emitter region, a cathode electrode and a gate electrode, the second conductive type emitter region is arranged on the first sub-base region, the first sub-base region covers the side and bottom surfaces of the second conductive type emitter region, the cathode electrode is arranged on the second conductive type emitter region, and the gate electrode is arranged on the second sub-base region.

[0011] In one embodiment, the doping concentration of the first sub-base region is less than the doping concentration of the third sub-base region; and the doping concentration of the second sub-base region is greater than the doping concentration of the third sub-base region.

[0012] In one embodiment, the bottom of the second conductive type emitter region is buried in the first sub-base region, the top of the second conductive type emitter region is raised relative to the first sub-base region, or the top surface of the second conductive type emitter region is flush with the top surface of the first sub-base region.

[0013] In one of the embodiments, a first conductivity type short base region is further provided in the first conductivity type base region, and the first conductivity type short base region is located below the first sub-base region.

[0014] In one of the embodiments, a depth to which the second sub-base region extends in the first conductive type base region is less than or equal to a depth to which the first sub-base region extends in the first conductive type base region.

[0015] In one of the embodiments, the depth to which the second sub-base region extends in the first conductive type base region is greater than the depth to which the first sub-base region extends in the first conductive type base region.

[0016] In one embodiment, the second sub-base region extends into the first conductive type short base region.

[0017] In one embodiment, the power semiconductor device includes at least one gate contact ring and a plurality of concentric cathode rings, each of the cathode rings includes a plurality of cathode comb strip regions arranged radially along the cathode ring, the second conductive type emitter region is arranged in the cathode comb strip region, the second sub-base region is arranged between adjacent second conductive type emitter regions of the cathode ring, and the second sub-base region is connected to the gate contact ring through the first conductive type base region.

[0018] In one embodiment, taking the direction perpendicular to the radial direction of the cathode ring as the lateral direction, the width of the second sub-base region in the lateral direction is positively correlated with the distance between the second sub-base region and the gate contact ring.

[0019] A second aspect of the present invention provides a method for manufacturing a power semiconductor device, comprising the following steps:

[0020] Providing a substrate, the substrate having a second conductivity type, the substrate comprising a first side and a second side disposed opposite to each other;

[0021] forming a first conductive type base region, wherein the first conductive type base region is disposed on the first side of the substrate;

[0022] forming a first sub-base region, wherein the first sub-base region extends from a top surface of the first conductive type base region toward the substrate;

[0023] forming a second conductive type emitter region, wherein the second conductive type emitter region is formed in the first sub-base region, the side surface and the top surface of the second conductive type emitter region are covered by the first sub-base region, and the first sub-base region is arranged between the second conductive type emitter region and the first conductive type base region;

[0024] A second sub-base region is formed, and the second sub-base region extends from the top surface of the first conductive type base region toward the substrate. The first sub-base region and the second sub-base region are independently arranged, and the first conductive type base region between the first sub-base region and the second sub-base region is divided into a third sub-base region. The doping concentrations of the first sub-base region, the second sub-base region, and the third sub-base region are different.

[0025] In one embodiment, the doping concentration of the first sub-base region is less than the doping concentration of the third sub-base region; and the doping concentration of the second sub-base region is greater than the doping concentration of the third sub-base region.

[0026] In one embodiment, before forming the first sub-base region, the method further includes:

[0027] forming a first conductivity type short base region in the first conductivity type base region, wherein a top surface of the first conductivity type short base region is lower than a top surface of the first conductivity type base region;

[0028] The first sub-base region is formed above a first conductive type short base region.

[0029] In one embodiment, the method for manufacturing the power semiconductor device further includes:

[0030] forming a cathode electrode, wherein the cathode electrode is disposed on the second conductive type emitter region, and the cathode electrode is in contact with the second conductive type emitter region;

[0031] A gate electrode is formed, wherein the gate electrode is disposed on the second sub-base region, and the gate electrode is in contact with the second sub-base region.

[0032] In one embodiment, the method for manufacturing the power semiconductor device further includes:

[0033] forming a second conductive type buffer zone, wherein the second conductive type buffer zone is disposed on the second side of the substrate;

[0034] A first conductive type emitter region is formed, wherein the first conductive type emitter region is disposed on a side of the second conductive type buffer region away from the substrate.

[0035] In one embodiment, the method for manufacturing the power semiconductor device further includes:

[0036] An anode electrode is formed. The anode electrode is disposed on a side of the first conductive type emitter region away from the second conductive type buffer region. The anode electrode is in contact with the first conductive type emitter region.

[0037] In one embodiment, forming the second conductive type emitter region further includes the following steps:

[0038] The second conductive type emitter region, the first sub-base region and the first conductive type base region are etched, and the top surface of the second conductive type emitter region after etching is higher than the top surfaces of the first sub-base region and the first conductive type base region, and the top of the second conductive type emitter region is raised relative to the first sub-base region and the first conductive type base region.

[0039] The power semiconductor device and the manufacturing method thereof of the present invention provide a first sub-base region and a second sub-base region separated in the first conductive type base region, decouple the coupling relationship that the breakdown voltage of the gate commutated thyristor unit requires that the concentration of the first conductive type base region cannot be too high but the commutation capability requires that the concentration of the first conductive type base region cannot be too low, thereby improving the anti-triggering capability of the gate commutated thyristor unit during commutation, thereby improving the turn-off current of the gate commutated thyristor unit;

[0040] The power semiconductor device and the manufacturing method thereof of the present invention adopt the second sub-base region to adjust the resistance between the gate contact ring and the gate electrode of the gate commutation thyristor unit, so as to compensate for the difference in the voltage drop of the gate electrode caused by the different distances between the cathode ring and the gate contact ring, thereby improving the consistency of the voltage actually applied to the gate commutation thyristor unit of each cathode ring, improving the uniformity of commutation, and improving the turn-off capability of the overall device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 A top view of the GCT chip in the related scheme.

[0043] Figure 2 for Figure 1 Longitudinal cross-section of the GCT chip along line AA.

[0044] Figure 3 Schematic diagram of the transmission of electrical signals from the gate contact ring to the gate electrode in the relevant scheme.

[0045] Figure 4 Schematic diagram of the transmission of electrical signals between the gate electrode and the cathode electrode in the related scheme.

[0046] Figure 5 Schematic diagram of the carrier flow when the GCT chip is turned off in the relevant scheme.

[0047] Figure 6 is a longitudinal cross-sectional view of a gate-commutated thyristor unit in an exemplary embodiment.

[0048] Figure 7 is a longitudinal cross-sectional view of a gate-commutated thyristor unit in an exemplary embodiment.

[0049] Figure 8 is a longitudinal cross-sectional view of a gate-commutated thyristor unit in an exemplary embodiment.

[0050] Fig. 9 is a longitudinal cross-sectional view of a gate-commutated thyristor unit in an exemplary embodiment.

[0051] Fig.10 FIG. 4 is a top view of the second sub-base region in an exemplary embodiment.

[0052] Fig.11 is a flow chart of a method for manufacturing a power semiconductor device in an exemplary embodiment.

[0053] Description of reference numerals:

[0054] 1. First conductive type emitter region; 2. Second conductive type buffer region; 3. Second conductive type drift region; 5. First conductive type short base region; 6. First conductive type base region; 61. First sub-base region; 62. Second sub-base region; 63. Third sub-base region; 7. Second conductive type emitter region; 10. Insulating layer; 11. Passivation layer; 13. Anode electrode; 14. Cathode electrode; 15. Gate electrode; 100. Gate contact ring; a1. Cathode comb region. DETAILED DESCRIPTION

[0055] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0057] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0058] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0059] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0060] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0061] The present application provides a power semiconductor device, which decouples the coupling relationship that the doping concentration of the first conductive type base region cannot be too high when the gate-commutated thyristor unit is turned off, but the doping concentration of the first conductive type base region cannot be too low when the gate-commutated thyristor unit is turned off, and a first sub-base region and a second sub-base region are arranged in the first conductive type base region, the first sub-base region surrounds and covers the surface of the second conductive type emitter region extending in the first conductive type base region, the second conductive type emitter region and the first conductive type base region are separated by the first sub-base region, the first sub-base region increases the reverse bias voltage between the gate electrode and the cathode electrode of the gate-commutated thyristor unit, thereby increasing the turn-off current of the gate-commutated thyristor unit, the second sub-base region is arranged below the gate electrode, the second sub-base region extends from the top surface of the first conductive type base region in the direction of the first conductive type short base region, the gate electrode and the second sub-base region are in contact and connected, the second sub-base region reduces the resistance of the area below the gate electrode, avoids triggering the PN junction of the gate-commutated thyristor unit to turn on during the process of holes moving toward the gate electrode during commutation, and improves the anti-triggering ability of the gate-commutated thyristor unit.

[0062] According to an exemplary embodiment, this embodiment provides a power semiconductor device, the power semiconductor device includes at least one gate-commutated thyristor unit, such as Figure 6As shown, the gate-commutated thyristor unit includes a first conductive type emitter region 1, a second conductive type buffer region 2, a second conductive type drift region 3 and a first conductive type base region 6 which are stacked in sequence, the first conductive type base region 6 includes a first sub-base region 61, a second sub-base region 62 and a third sub-base region 63 with different doping concentrations, the first sub-base region 61 and the second sub-base region 62 are independently arranged and separated by the third sub-base region 63; the gate-commutated thyristor unit also includes a second conductive type emitter region 7, a cathode electrode and a gate electrode, the second conductive type emitter region 7 is arranged on the first sub-base region 61, the first sub-base region 61 covers the side and bottom surfaces of the second conductive type emitter region 7, the cathode electrode 14 is arranged on the second conductive type emitter region 7, and the gate electrode 15 is arranged on the second sub-base region 62. The gate-commutated thyristor unit also includes an anode electrode 13, which is arranged below the first conductive type emitter region 1. An insulating layer 10 is disposed between the cathode electrode 14 and the gate electrode 15 to electrically isolate the cathode electrode 14 from the gate electrode 15 .

[0063] The first conductivity type and the second conductivity type are opposite, the first conductivity type is P-type conductivity type or N-type conductivity type, and the second conductivity type is N-type conductivity type or P-type conductivity type. The first conductivity type emitter region 1 and the second conductivity type buffer region 2 of the gate-commutated thyristor unit form a PN junction J1, the second conductivity type drift region 3 and the first conductivity type base region 6 form a PN junction J2, and the first conductivity type base region 6 and the second conductivity type emitter region 7 form a PN junction J3.

[0064] In some embodiments, the doping concentration of the first sub-base region 61 is less than the doping concentration of the third sub-base region 63 ; and the doping concentration of the second sub-base region 62 is greater than the doping concentration of the third sub-base region 63 .

[0065] In this embodiment, the doping concentration of the first sub-base region 61 is less than the doping concentration of the third sub-base region 63, which means that in the same lateral direction, the doping concentration of the first conductive type ions in the first sub-base region 61 is less than the doping concentration of the first conductive type ions in the third sub-base region 63. The first sub-base region 61 surrounds and covers the bottom and side surfaces of the second conductive type emitter region 7, and the first sub-base region 61 separates the second conductive type emitter region 7 from the first conductive type base region 6. In this way, the first sub-base region 61 further reduces the doping concentration of the first conductive type ions in the PN junction J3, increases the reverse breakdown voltage of the PN junction J3, increases the reverse bias voltage between the gate electrode 15 and the cathode electrode 14 of the gate-commutated thyristor unit, increases the turn-off current of the gate-commutated thyristor unit, and increases the turn-off capability of the gate-commutated thyristor unit.

[0066] Similarly, the doping concentration of the second sub-base region 62 is greater than the doping concentration of the third sub-base region 63, which means that in the same lateral direction, the doping concentration of the second sub-base region 62 is greater than the doping concentration of the first conductive type base region 6. It can be understood that the greater the doping concentration of the conductive ions in the semiconductor material, the better its conductivity and the smaller its resistance. That is, the resistance of the second sub-base region 62 is smaller than the resistance of the first conductive type base region 6 in the same lateral direction. In this way, the gate electrode 15 is arranged on the second sub-base region 62 and is ohmically connected to the second sub-base region 62. When the gate-commutated thyristor unit is commutated or avalanche, the holes flow to the gate electrode 15. The second sub-base region 62 reduces the resistance of the holes flowing through the second conductive type emitter region 7, and reduces the risk of the PN junction J3 being triggered, thereby avoiding the latch failure of the gate-commutated thyristor unit. At the same time, the second sub-base region 62 can reduce the voltage drop applied to the gate electrode 15 when turned off, increase the voltage actually applied to the gate electrode 15, and improve the turn-off capability of the gate-commutated thyristor unit.

[0067] In the power semiconductor device of the present embodiment, the first sub-base region 61 surrounds and covers the surface of the second conductive type emitter region 7 extending in the first conductive type base region 6, which meets the requirement of the gate-commutated thyristor unit for low doping concentration and improves the turn-off current of the gate-commutated thyristor unit; the second sub-base region 62 with a higher doping concentration is set according to the requirement of the gate-commutated thyristor unit for commutation, and the second sub-base region 62 reduces the commutation resistance of the gate-commutated thyristor unit and reduces the risk of the PN junction J3 being triggered; the power semiconductor device of the present embodiment, by modulating the first conductive type base region 6, divides the first conductive type base region 6 into the first sub-base region 61, the second sub-base region 62 and the third sub-base region 63 with different doping concentrations, overcomes the problem of the conflict between the turn-off and commutation requirements of the gate-commutated thyristor unit on the doping concentration of the first conductive type base region 6, and the power semiconductor device of the present embodiment improves the turn-off capability of the gate-commutated thyristor unit and improves the anti-triggering capability of the gate-commutated thyristor unit during commutation.

[0068] In some embodiments, Figure 6 , Figure 7 or Figure 8 As shown, the bottom of the second conductive type emitter region 7 is buried in the first sub-base region 61, and the top of the second conductive type emitter region 7 is raised relative to the first sub-base region 61. The top surface of the second conductive type emitter region 7 in this embodiment is higher than the top surface of the first sub-base region 61.

[0069] In some embodiments, Fig. 9 As shown, the top surface of the second conductive type emitter region 7 is flush with the top surface of the first sub-base region 61 .

[0070] In some embodiments, a first conductive type short base region 5 is further provided in the first conductive type base region 6 , the top surface of the first conductive type short base region 5 is lower than the top surface of the first conductive type base region 6 , and the first conductive type short base region 5 is located below the first sub-base region 61 .

[0071] In some embodiments, Figure 6 , Figure 7 , Figure 8 , Fig. 9 As shown, the bottom surface of the first sub-base region 61 is higher than a preset distance above the first conductive type short base region 5 .

[0072] In some embodiments, Figure 7 As shown, the depth of the second sub-base region 62 extending in the first conductive type base region 6 is less than or equal to the depth of the first sub-base region 61 extending in the first conductive type base region 6. The bottom surface of the second sub-base region 62 can be flush with the bottom surface of the first sub-base region 61 or higher than the bottom surface of the first sub-base region 61. Specifically, the doping depth of the second sub-base region 62 and the doping depth of the first sub-base region 61 can be set according to the actual process level and product requirements.

[0073] In some embodiments, Figure 6 , Figure 8 or Fig. 9 As shown, the depth of the second sub-base region 62 extending in the first conductive type base region 6 is greater than the depth of the first sub-base region 61 extending in the first conductive type base region 6. That is, the bottom surface of the second sub-base region 62 is lower than the bottom surface of the first sub-base region 61.

[0074] In some embodiments, Figure 8 As shown, the second sub-base region 62 extends into the first conductive type short base region 5 .

[0075] In some embodiments, Figure 6 , Figure 7 , Figure 8 , Fig. 9 As shown, the top surface of the gate electrode 15 is covered by a passivation layer 11, and the material of the passivation layer 11 may include at least one of polyimide (PI), amorphous hydrogenated carbon (aC:H, also known as diamond-like carbon DLC) or an inorganic-organic composite material, polyparaxylene, and a phenolic resin containing polymer particles.

[0076] In some embodiments, reference Fig.10 Combined with Figure 1The power semiconductor device includes at least one gate contact ring 100 and a plurality of concentric cathode rings (not numbered in the figure), each cathode ring includes a plurality of cathode comb strip regions a1 arranged along the radial direction of the cathode ring, a second conductive type emitter region 7 is arranged in the cathode comb strip region a1, a second sub-base region 62 is arranged between adjacent second conductive type emitter regions 7 of the cathode ring, and the second sub-base region 62 is connected to the gate contact ring 100 through the first conductive type base region 6.

[0077] The power semiconductor device in this embodiment may be a gate-commutated thyristor (IGCT), for example, the power semiconductor device may be an asymmetric IGCT, a reverse-conducting IGCT or a symmetric IGCT; or, the power semiconductor device in this embodiment may be other power devices with a radial or annular distribution of the cathode region.

[0078] The power semiconductor device of this embodiment includes a substrate, which is a semiconductor substrate of a first conductivity type or a second conductivity type. The material of the substrate may include silicon, or may be a third-generation semiconductor material such as silicon carbide or gallium nitride. The substrate includes an anode side and a cathode side that are arranged opposite to each other. A gate contact ring 100 and a plurality of concentric cathode rings are arranged on the cathode side of the substrate. The gate contact ring 100 may be arranged at the center of a plurality of cathode rings, or the gate contact ring 100 may be arranged between a plurality of cathode rings, or the gate contact ring 100 may be arranged at the outermost periphery of a plurality of cathode rings.

[0079] Reference Fig.10 Combined with Figure 1 At least one gate-commutated thyristor unit is arranged in the substrate, and at least one gate-commutated thyristor unit is connected in parallel. The second conductive type emitter region 7 of the gate-commutated thyristor unit is arranged in the cathode comb region a1, the cathode electrode 14 of the gate-commutated thyristor unit is arranged on the second conductive type emitter region 7, the gate electrode 15 of the gate-commutated thyristor unit is arranged on the cathode ring adjacent to the cathode comb region a1, the gate electrode 15 is connected to the gate contact ring 100 through the first conductive type base region 6, and when the gate-commutated thyristor unit is turned off, the gate contact ring 100 applies a negative bias to the gate electrode 15 through the first conductive type base region 6.

[0080] In some embodiments, reference Fig.10 Combined with Figure 1, with the direction perpendicular to the radial direction of the cathode ring as the lateral direction, the width of the second sub-base region 62 in the lateral direction is positively correlated with the distance between the second sub-base region 62 and the gate contact ring 100. For example, the width of the second sub-base region 62 of the gate-commutated thyristor unit on the first cathode ring arranged in the direction away from the gate contact ring 100 is wi, and the width of the second sub-base region 62 of the gate-commutated thyristor unit on the second cathode ring arranged in the direction away from the gate contact ring 100 is wi+1, and wi+1 is greater than wi.

[0081] In the power semiconductor device of this embodiment, the width of the second sub-base region 62 is set according to the distance between the gate-commutated thyristor unit and the gate contact ring 100. The farther the second sub-base region 62 of the gate-commutated thyristor unit is from the gate contact ring 100, the wider it is, and the smaller the resistance of the area below the gate electrode 15 of the gate-commutated thyristor unit. In this way, when the gate-commutated thyristor unit is turned off, the gate contact ring 100 applies a negative voltage to the gate electrode 15 of each cathode ring of the gate-commutated thyristor unit, and the farther the second sub-base region 62 of the gate-commutated thyristor unit is from the gate contact ring 100, the smaller the voltage drop generated, so as to compensate for the voltage drop generated by the increased distance between the gate-commutated thyristor unit and the gate contact ring 100.

[0082] In other words, in this embodiment, the gate contact ring 100 applies a negative bias voltage to the gate electrode 15 of the gate commutated thyristor unit through the second sub-base region 62 of the gate commutated thyristor unit to perform resistance compensation. The second sub-base region 62 of the gate commutated thyristor unit close to the gate contact ring 100 has a small width and a relatively large resistance, while the second sub-base region 62 of the gate commutated thyristor unit far from the gate contact ring 100 has a large width and a relatively small resistance, so that the resistance through which the gate contact ring 100 applies a negative bias voltage to the gate electrode 15 of each gate commutated thyristor unit in the substrate is closer. The gate contact ring 100 is arranged close to the gate electrode 15 of each gate-commutated thyristor unit in the substrate so that the voltage drop generated by the gate contact ring 100 to the gate electrode 15 of each gate-commutated thyristor unit in the substrate is equal, thereby improving the uniformity of the voltage actually applied between the gate electrode 15 and the cathode electrode 14 of each gate-commutated thyristor unit, improving the uniformity of the commutation of the cathode electrode 14 of the gate-commutated thyristor unit, thereby improving the turn-off uniformity of the gate-commutated thyristor unit in the power semiconductor device, and avoiding the problem that the gate-commutated thyristor unit far from the gate contact ring 100 is in the on state for a long time and overload occurs, resulting in damage to the power semiconductor device.

[0083] In this embodiment, the doping depths of the gate-commutated thyristor units of each gate-commutated thyristor unit of the power semiconductor device are the same, so that the process difficulty in the manufacturing process can be reduced and the process efficiency can be improved.

[0084] According to an exemplary embodiment, a power semiconductor device is provided, and the power semiconductor device includes a gate-commutated thyristor unit. In this embodiment, the gate-commutated thyristor unit includes a P+ emitter region, an N buffer region, an N-drift region, a P base region, and an N+ emitter region, which are stacked in sequence. The N+ emitter region extends into the P base region, and a P+ short base region is also arranged in the P base region. The top surface of the P+ short base region is lower than the top surface of the P base region. The P base region above the P+ short base region includes a first sub-base region, a second sub-base region, and a third sub-base region. The doping concentrations of the first sub-base region, the second sub-base region, and the third sub-base region are different, wherein the first sub-base region is a P-voltage-resistant region, the second sub-base region is a P+ low-resistance region, the P-voltage-resistant region and the P+ low-resistance region are independently arranged, and the third sub-base region is a P base region arranged between the first sub-base region and the second sub-base region. The P-voltage-resistant region is arranged below the N+ emitter region, the P-voltage-resistant region surrounds and covers the surface of the N+ emitter region extending in the P base region, and the P+ low resistance region extends from the top surface of the P base region to the direction of the P+ short base region. The gate-commutated thyristor unit also includes an anode electrode 13 arranged on one side of the P+ emitter region, a cathode electrode 14 and a gate electrode 15 arranged on one side of the P base region, the second conductive type emitter region 7 is arranged on the first sub-base region 61, the first sub-base region 61 covers the side and bottom surfaces of the second conductive type emitter region 7, the cathode electrode 14 is arranged on the second conductive type emitter region 7, and the gate electrode 15 is arranged on the second sub-base region 62. The gate-commutated thyristor unit also includes an anode electrode 13, the anode electrode 13 is arranged below the first conductive type emitter region 1, the cathode electrode 14 is arranged on the N+ emitter region, and the gate electrode 15 is arranged on the P+ low resistance region.

[0085] In some embodiments, the doping concentration of the P-voltage-withstanding region is less than the doping concentration of the P-base region; and the doping concentration of the P+ low-resistance region is greater than the doping concentration of the P-base region.

[0086] The top surface of the N+ emitter region may be flush with the top surface of the P-voltage-withstanding region, or the top surface of the N+ emitter region may be higher than the top surface of the P-voltage-withstanding region, and the top surface of the N+ emitter region is raised relative to the P-voltage-withstanding region.

[0087] The doping depth of the P+ low resistance region may be the same as the doping depth of the P- voltage-withstanding region, and the bottom surface of the P+ low resistance region and the bottom surface of the P+ low resistance region are at the same height. Alternatively, the doping depth of the P+ low resistance region may be less than the doping depth of the P- voltage-withstanding region, and the bottom surface of the P+ low resistance region is higher than the bottom surface of the P+ low resistance region. Alternatively, the doping depth of the P+ low resistance region may be greater than the doping depth of the P- voltage-withstanding region, and the bottom surface of the P+ low resistance region is lower than the bottom surface of the P+ low resistance region.

[0088] In some embodiments, the P+ low resistance region may extend into the P+ short base region.

[0089] In an exemplary embodiment of the present disclosure, a method for manufacturing a power semiconductor device is provided, such as Fig.11 As shown, Fig.11 A flow chart of a method for manufacturing a power semiconductor device provided according to an exemplary embodiment of the present disclosure is shown. This embodiment does not limit the power semiconductor device. The power semiconductor device will be introduced below as an integrated gate-commutated thyristor (IGCT) as an example, but this embodiment is not limited to this. The power semiconductor device in this embodiment can also be of other structures.

[0090] like Fig.11 As shown, a method for manufacturing a power semiconductor device provided by an exemplary embodiment of the present disclosure includes the following steps:

[0091] Step S11: providing a substrate, wherein the substrate has a second conductivity type and comprises a first side and a second side that are opposite to each other.

[0092] Step S12: forming a first conductivity type base region, wherein the first conductivity type base region is disposed on the first side of the substrate.

[0093] Step S13: forming a first sub-base region, wherein the first sub-base region extends from the top surface of the first conductive type base region toward the substrate.

[0094] Step S14: forming a second conductive type emitter region, wherein the second conductive type emitter region is formed in the first sub-base region, the side and top surfaces of the second conductive type emitter region are covered by the first sub-base region, and the first sub-base region is arranged between the second conductive type emitter region and the first conductive type base region.

[0095] Step S15: forming a second sub-base region, the second sub-base region extending from the top surface of the first conductive type base region toward the substrate, the first sub-base region and the second sub-base region are independently arranged, and the first conductive type base region between the first sub-base region and the second sub-base region is divided into a third sub-base region, and the doping concentrations of the first sub-base region, the second sub-base region and the third sub-base region are different.

[0096] In step S11, refer to Fig.10 The material of the substrate may include silicon, or a third generation semiconductor material such as silicon carbide or gallium nitride, and the second conductivity type is an N-type conductivity type or a P-type conductivity type. In this embodiment, the substrate is a silicon substrate.

[0097] In this embodiment, after step S11 and before step S12, the following steps are further performed:

[0098] Step S111: forming a second conductive type buffer zone, where the second conductive type buffer zone is disposed on the second side of the substrate.

[0099] Reference Figure 6 , Figure 7 , Figure 8 , Fig. 9A second conductive type buffer zone 2 can be formed on the second side of the substrate by epitaxy or doping diffusion, and the doping concentration of the second conductive type ions in the second conductive type buffer zone 2 is greater than the doping concentration of the second conductive type ions in the substrate.

[0100] In step S12, refer to Figure 6 , Figure 7 , Figure 8 , Fig. 9 A first conductive type base region 6 can be formed on the first side of the substrate by epitaxy or doping diffusion, and the first conductive type is a P-type conductive type or an N-type conductive type.

[0101] In this embodiment, after step S12 and before step S13, the following steps are further performed:

[0102] Reference Figure 6 , Figure 7 , Figure 8 , Fig. 9 , first conductivity type ions are injected into the first conductivity type base region 6 from the first side of the substrate, and a first conductivity type short base region 5 is formed inside the first conductivity type base region 6. The top surface of the first conductivity type short base region 5 is lower than the top surface of the first conductivity type short base region 5. After the first conductivity type short base region 5 is formed, the first conductivity type short base region 5 divides the first conductivity type base region 6 into two parts respectively arranged on the upper and lower sides of the first conductivity type short base region 5. The doping concentration of the first conductivity type ions in the first conductivity type short base region 5 is greater than the doping concentration of the first conductivity type ions in the first conductivity type base region 6.

[0103] In step S13, refer to Figure 6 , Figure 7 , Figure 8 , Fig. 9 A mask is formed on the top surface of the first conductive type base region 6, and the mask is etched using a photolithography process to define a window of the first sub-base region 61 on the mask. The window of the first sub-base region 61 exposes a portion of the surface of the first conductive type base region 6, and ions with the second conductive type are injected into the first conductive type base region 6 from the first side of the substrate to form the first sub-base region 61.

[0104] In step S14, a second conductive type emitter region is formed, and the following implementation methods may be adopted:

[0105] Reference Figure 6 , Figure 7 , Figure 8 , Fig. 9A mask is formed on the top surface of the first conductive type base region 6, and the mask is etched by photolithography to define a window of the second conductive type emitter region 7 on the mask. Based on the window of the second conductive type emitter region 7, ions of the second conductive type are injected into the first sub-base region 61, and the substrate is heat-treated to diffuse the ions of the second conductive type to form the second conductive type emitter region 7. The doping depth of the second conductive type emitter region 7 is less than the doping depth of the first sub-base region 61, and the bottom and side surfaces of the second conductive type emitter region 7 are covered by the first sub-base region 61. In this embodiment, the distance between the bottom surface of the second conductive type emitter region 7 and the bottom surface of the first sub-base region 61 is 2μm-10μm.

[0106] In step S15, refer to Figure 6 , Figure 7 , Figure 8 , Fig. 9 A mask is formed on the top surface of the first conductive type base region 6, and the mask is etched using a photolithography process to define a window of the second sub-base region 62 on the mask. Based on the window of the second sub-base region 62, ions of the first conductive type are injected into the first conductive type base region 6 to form a second sub-base region 62 in the first conductive type base region 6.

[0107] The first sub-base region 61 and the second sub-base region 62 are independently arranged, and the first conductive type base region 6 between the first sub-base region 61 and the second sub-base region 62 is divided into a third sub-base region 63 . The doping concentrations of the first sub-base region 61 , the second sub-base region 62 and the third sub-base region 63 are different.

[0108] In some embodiments, in the same lateral direction, the concentration of the first conductivity type ions in the first sub-base region 61 is lower than the concentration of the first conductivity type ions in the first conductivity type base region 6, and the concentration of the first conductivity type ions in the second sub-base region 62 is higher than the concentration of the first conductivity type ions in the first conductivity type base region 6. Preferably, in the same lateral direction, the ratio of the concentration of the first conductivity type ions in the first sub-base region 61 to the concentration of the first conductivity type ions in the first conductivity type base region 6 is 0.1-0.5:1.

[0109] In this embodiment, after step S15, the following steps are further performed:

[0110] Step S112: forming a first conductive type emitter region, wherein the first conductive type emitter region is arranged on a side of the second conductive type buffer region away from the substrate.

[0111] Reference Figure 6 , Figure 7 , Figure 8 , Fig. 9, first conductive type ions are injected into the bottom surface of the second conductive type buffer zone 2 from the second side of the substrate to form a first conductive type emitter region 1, and the first conductive type emitter region 1 is located at the bottom of the second conductive type buffer zone 2.

[0112] Reference Figure 6 , Figure 7 , Figure 8 , Fig. 9 After performing the above steps, the longitudinal cross-section of the substrate is as shown in the figure, and the substrate includes a first conductive type emitter region 1, a second conductive type buffer region 2, a second conductive type drift region 3 (as shown in the longitudinal direction of the figure, the second conductive type drift region 3 is formed by an undoped area in the middle of the substrate), a first conductive type base region 6 and a second conductive type emitter region 7 arranged in sequence from the second side to the first side. A first conductive type short base region 5 is also arranged in the first conductive type base region 6. The first conductive type base region 6 above the first conductive type short base region 5 includes a first sub-base region 61, a second sub-base region 62 and a third sub-base region 63. The first sub-base region 61 and the second sub-base region 62 are independently arranged. The third sub-base region 63 is arranged between the first sub-base region 61 and the second sub-base region 62. The first sub-base region 61 is arranged below the second conductive type emitter region 7. The first sub-base region 61 covers the bottom and side surfaces of the second conductive type emitter region 7. The second sub-base region 62 extends from the top surface of the first conductive type base region 6 to the direction of the first conductive type short base region 5. The doping concentration of the first sub-base region 61 is less than the doping concentration of the third sub-base region 63, and the doping concentration of the second sub-base region 62 is greater than the doping concentration of the third sub-base region 63.

[0113] In this embodiment, after step S112, the following steps are further performed:

[0114] Step S113: forming a cathode electrode, wherein the cathode electrode is disposed on the second conductive type emitter region, and the cathode electrode is in contact with the second conductive type emitter region.

[0115] Step S114: forming a gate electrode, wherein the gate electrode is disposed on the second sub-base region, and the gate electrode is in contact with the second sub-base region.

[0116] In this embodiment, the cathode electrode 14 and the gate electrode 15 can be formed in the same process step, and specifically the following implementation methods can be adopted:

[0117] Reference Figure 6 , Figure 7 , Figure 8 , Fig. 9First, a chemical vapor deposition (CVD) process can be used to deposit an oxide layer on the first side of the substrate, and the oxide layer covers the top surface of the first sub-base region 61, the top surface of the second sub-base region 62, and the top surface of the third sub-base region 63 of the second conductive type emitter region 7.

[0118] Then, a portion of the oxide layer is etched away to form a gate window and a cathode window on the first side of the substrate, wherein the gate window exposes a portion of the top surface of the second sub-base region 62 , and the cathode window exposes the top surface of the second conductive type emitter region 7 . The retained oxide layer is etched to form an insulating layer 10 .

[0119] Next, a first metal layer is deposited by evaporation or sputtering to cover the top surface of the second sub-base region 62 exposed by the gate window, the top surface of the second conductive type emitter region 7 exposed by the cathode window, and the top surface of the insulating layer 10 .

[0120] Next, the first metal layer on the top surface of the insulating layer 10 is etched away, the first metal layer covering the top surface of the second sub-base region 62 is formed as a gate electrode 15, and the first metal layer covering the top surface of the second conductive type emitter region 7 is formed as a cathode electrode 14.

[0121] The materials of the gate electrode 15 and the cathode electrode 14 may include aluminum (Al) or a composite material of aluminum and other materials. In this embodiment, the materials of the gate electrode 15 and the cathode electrode 14 include aluminum.

[0122] Step S115: forming an anode electrode 13, wherein the anode electrode 13 is disposed on a side of the first conductive type emitter region away from the second conductive type buffer region, and the anode electrode 13 is in contact with the first conductive type emitter region.

[0123] In this embodiment, the anode electrode 13 may be formed by the following implementations:

[0124] Reference Figure 6 , Figure 7 , Figure 8 , Fig. 9 , an anode electrode 13 is deposited on the second side of the substrate by evaporation or sputtering, and the anode electrode 13 covers the bottom surface of the first conductive type emitter region 1 and is in contact with the first conductive type emitter region 1. The material of the anode electrode 13 may include aluminum or a composite material of aluminum and other materials. In this embodiment, the material of the anode electrode 13 includes aluminum.

[0125] In this embodiment, after forming the anode electrode 13, the following steps are further performed: Figure 6 , Figure 7 , Figure 8 , Fig. 9A passivation layer 11 is formed on the first side of the substrate, the passivation layer 11 covers the top surface of the gate electrode 15 and the insulating layer 10, and the passivation layer 11 exposes the top surface of the cathode electrode 14. The material of the passivation layer 11 may include at least one of polyimide, amorphous hydrogenated carbon or inorganic-organic composite material, polyparaxylene, and phenolic resin containing polymer particles. Then, the power semiconductor device is subjected to subsequent processing (such as shape processing, packaging, etc.).

[0126] The power semiconductor device formed in this embodiment forms a first sub-base region 61 with a lower doping concentration and a second sub-base region 62 with a higher doping concentration in the first conductive type base region 6, thereby improving the turn-off current of the gate-commutated thyristor unit, reducing the commutation resistance, reducing the risk of the gate-commutated thyristor unit being triggered during avalanche or commutation, improving the turn-off capability of the gate-commutated thyristor unit, and at the same time improving the anti-triggering capability of the gate-commutated thyristor unit during commutation.

[0127] According to an exemplary embodiment, this embodiment does not constitute a limitation on the above embodiment. This embodiment is a further description of the above embodiment. This embodiment includes all the steps of the above embodiment. The difference between this embodiment and the above embodiment is that, in this embodiment, the second conductive type emitter region 7 is formed, and the following implementation method is adopted:

[0128] First, the entire surface of the first surface of the substrate is implanted with ions of the second conductivity type, and then the substrate is subjected to a first heat treatment to pre-diffuse the ions of the second conductivity type to a first depth to form a second conductivity type emitter region 7 .

[0129] Then, the second conductive type emitter region 7, the first sub-base region 61 and the first conductive type base region 6 are etched. After etching, the top surface of the second conductive type emitter region 7 is higher than the top surfaces of the first sub-base region 61 and the first conductive type base region 6, and the top of the second conductive type emitter region 7 is raised relative to the first sub-base region 61 and the first conductive type base region 6.

[0130] Next, the substrate is subjected to a second heat treatment to diffuse the ions of the second conductivity type to a second depth.

[0131] According to an exemplary embodiment, this embodiment includes all the steps of the above embodiment, and the difference between this embodiment and the above embodiment is that:

[0132] Reference Figure 1 , Fig.10The side surface of the first side of the substrate of this embodiment includes a gate contact ring 100 and a plurality of concentric cathode rings. The gate contact ring 100 can be arranged at the center of the plurality of cathode rings, or the gate contact ring 100 can be arranged between the plurality of cathode rings, or the gate contact ring 100 can be arranged at the outermost periphery of the plurality of cathode rings. After the second conductive type emitter region 7 is formed, each cathode ring includes a plurality of cathode comb strip regions a1 arranged along the radial direction of the cathode ring, and the second conductive type emitter region 7 is arranged in the cathode comb strip region a1.

[0133] In this embodiment, refer to Figure 1 , Fig.10 A second sub-base region 62 is formed between adjacent second conductive type emitter regions 7 of the cathode ring. In the process of forming the second sub-base region 62, the direction perpendicular to the radial direction of the cathode ring is taken as the lateral direction. The width of the second sub-base region 62 in the lateral direction is defined according to the distance between the cathode ring and the gate contact ring 100. The farther the cathode ring is from the gate contact ring 100, the wider the second sub-base region 62 is.

[0134] In this way, the farther the gate-commutated thyristor unit formed in the present embodiment is from the gate contact ring 100, the smaller the resistance of the area below the gate electrode 15. When the gate-commutated thyristor unit is turned off, the gate contact ring 100 applies a negative bias to the gate electrode 15 of each cathode ring of the gate-commutated thyristor unit. The voltage drop generated by the second sub-base region 62 of the gate-commutated thyristor unit that is farther from the gate contact ring 100 is smaller, so as to compensate for the voltage drop generated by the increased distance between the gate-commutated thyristor unit and the gate contact ring 100, so as to improve the turn-off uniformity of the gate-commutated thyristor unit in the power semiconductor device, and avoid the problem of overload caused by the gate-commutated thyristor unit that is far from the gate contact ring 100 being in the on state for a long time, thereby causing damage to the power semiconductor device.

[0135] According to an exemplary embodiment, a method for manufacturing a power semiconductor device is provided in this exemplary embodiment. This embodiment is described by taking the first conductivity type as P type and the second conductivity type as N type. The method for manufacturing a power semiconductor device in this embodiment includes the following steps:

[0136] First, a substrate is provided, the substrate is an N-type substrate, and the concentration of N-type conductive ions in the substrate is greater than the N-doping concentration in the range of 5E11cm -3 -1E14cm -3 The thickness of the substrate is 200 μm-1400 μm. The substrate includes a first side and a second side that are oppositely disposed.

[0137] A second conductive buffer zone 2 is formed on the second side of the substrate by epitaxial growth or ion implantation followed by thermal diffusion. The second conductive buffer zone 2 is an N buffer zone. The concentration of N-type conductive ions in the N buffer zone is greater than the concentration of N-type conductive ions in the N-type substrate. The concentration range of N-type conductive ions in the N buffer zone is 1E15cm -3 -5E16cm -3 , the depth of the N buffer is 10μm-50μm.

[0138] The first conductive type base region 6 is formed on the first side of the substrate by epitaxial growth, or the first conductive type ions (such as aluminum ions) are injected into the substrate from the first side of the substrate and then the substrate is heat treated to diffuse the first conductive type ions in the substrate to form the first conductive type base region 6. The first conductive type base region 6 is a P base region, and the concentration range of the P type conductive ions in the P base region is 5E14cm -3 -5E16cm -3 , the depth of the P base region is 40μm-150μm.

[0139] After the substrate is heat-treated, the first conductive type ions (such as aluminum ions) are injected into the first conductive type base region 6 from the first side of the substrate to form the first conductive type short base region 5. The concentration of the first conductive type ions in the first conductive type short base region 5 is greater than the concentration of the first conductive type ions in the first conductive type base region 6. In this embodiment, the first conductive type short base region 5 is a P+ short base region, and the concentration range of the P-type conductive ions in the P+ short base region is 1E16cm -3 -1E20cm -3 , the depth of the P+ short base region is 10-100um.

[0140] Ions of the second conductivity type are injected into the first conductivity type base region 6 at the first side of the substrate, and after thermal diffusion, a first sub-base region 61 is formed. In this embodiment, the first sub-base region 61 is a P-voltage-resistant region. In this embodiment, phosphorus ions are injected into the P base region from the window of the first sub-base region 61, and then the substrate is heat-treated to diffuse the phosphorus ions to form a P-voltage-resistant region. The concentration of P-type conductive ions in the P-voltage-resistant region is lower than the concentration of P-type conductive ions in the P base region in the same lateral direction. In this embodiment, the concentration of P-type conductive ions in the P-voltage-resistant region is 0.1-0.5 times the concentration of P-type conductive ions in the P base region in the same lateral direction.

[0141] Ions of the second conductivity type are injected from the first side of the substrate, and then the ions of the second conductivity type are pre-diffused to form a second conductivity type emitter region 7. In this embodiment, the second conductivity type emitter region 7 is an N+ emitter region, and the depth of the N+ emitter region after pre-diffusion is 5μm-10μm. The surface of the first side of the substrate is etched using a dry process, a wet process, or a mixed process of dry and wet processes, so that the top surface of the etched N+ emitter region is raised relative to the P-voltage-withstand region and the P base region. The N+ emitter region is then thermally diffused to diffuse the depth of the N+ emitter region to 10μm-30μm. Among them, the distance between the bottom surface of the N+ emitter region and the bottom surface of the P base region is 2μm-10μm.

[0142] The first conductive type ions are injected into the first conductive type base region 6 from the window of the second sub-base region 62 to form the second sub-base region 62. In this embodiment, the second sub-base region 62 is a P+ low resistance region, and the concentration range of the P+ low resistance region is 1E17cm -3 -5E18cm -3 The depth of the P+ low resistance region is 20 μm-50 μm. The first conductive type base region 6 between the first sub-base region 61 and the second sub-base region 62 forms a third sub-base region 63 .

[0143] Ions of the first conductivity type (such as boron ions) are injected into the second conductivity type buffer region 2 from the second side of the substrate, and after thermal diffusion, a first conductivity type emitter region 1 is formed. In this embodiment, the first conductivity type emitter region 1 is a P+ emitter region, and the concentration range of the P-type conductive ions in the P+ emitter region is 5E16cm -3 -1E20cm -3 , the depth of the P+ emitter region is 1μm-20μm.

[0144] Then, an oxide layer is formed on the first side of the substrate, and the oxide layer is etched to form a gate window and a cathode window, and the remaining oxide layer forms an insulating layer 10 .

[0145] Metal aluminum is deposited by evaporation or sputtering to form a gate electrode 15 on the P+ low resistance region and a cathode electrode 14 on the N+ emitter region.

[0146] Metal aluminum is deposited by evaporation or sputtering to form an anode electrode 13 on the bottom surface of the P+ emitter region.

[0147] Reference Figure 6 , Figure 7 or Figure 8As shown, the power semiconductor device formed in this embodiment, the gate-commutated thyristor unit includes a P+ emitter region, an N buffer region, an N-drift region, a P base region and an N+ emitter region which are stacked in sequence, the top surface of the N+ emitter region can be higher than the top surface of the P base region, and the N+ emitter region is raised relative to the P base region. A P+ short base region is arranged in the P base region, and the P+ short base region divides the P base region into two parts, a P base region located above the P+ short base region and a P base region located below the P+ short base region. A P- withstand voltage region and a P+ low resistance region are arranged in the P base region located above the P+ short base region, the P- withstand voltage region is arranged below the N+ emitter region, the P- withstand voltage region surrounds and covers the surface of the N+ emitter region extending in the P base region, the cathode electrode 14 is arranged on the N+ emitter region, and the gate electrode 15 is arranged on the P+ low resistance region and is in contact with and connected to the P+ low resistance region.

[0148] According to an exemplary embodiment, a method for manufacturing a power semiconductor device is provided in this exemplary embodiment. This embodiment is described by taking the first conductivity type as P type and the second conductivity type as N type. The method for manufacturing a power semiconductor device in this embodiment includes the following steps:

[0149] Provide a substrate. The substrate provided in this embodiment is the same as that in the above embodiment. The substrate is N-doped with a concentration in the range of 5E11cm -3 -1E14cm -3 The N-type substrate has a thickness of 200 μm-1400 μm.

[0150] An N buffer zone is formed on the second side of the substrate by epitaxial growth or ion implantation followed by thermal diffusion. The concentration of N-type conductive ions in the N buffer zone is greater than that in the N-type substrate. The concentration of N-type conductive ions in the N buffer zone is in the range of 1E15cm -3 -5E16cm -3 , the depth of the N buffer is 10μm-50μm.

[0151] A P-base region is formed on the first side of the substrate by epitaxial growth, and the concentration of P-type conductive ions in the P-base region is in the range of 5E14cm -3 -5E16cm -3 , the depth of the P base region is 40μm-150μm.

[0152] After P-type conductive ions are injected into the P-base region from the first side of the substrate, the substrate is heat treated to form a P+ short base region in the P-base region. The concentration range of the P-type conductive ions in the P+ short base region is 1E16cm -3 -1E20cm -3 , the depth of the P+ short base region is 10-100um.

[0153] After phosphorus ions are injected into the P-base region on the first side of the substrate, the substrate is heat treated to diffuse the ions to form a P-voltage-resistant region. The concentration of P-type conductive ions in the P-voltage-resistant region is lower than the concentration of P-type conductive ions in the P-base region in the same lateral direction. In this embodiment, the concentration of P-type conductive ions in the P-voltage-resistant region is 0.1-0.5 times the concentration of P-type conductive ions in the P-base region in the same lateral direction.

[0154] Phosphorus ions are injected into the window of the N+ emitter region from the first side of the substrate. After thermal diffusion, the N+ emitter region is formed. The concentration of N-type conductive ions in the N+ emitter region is 1E18cm -3 -1E21cm -3 , the depth of the N+ emitter region is 10 μm-30 μm, wherein the distance between the bottom surface of the N+ emitter region and the bottom surface of the P base region is 2 μm-10 μm.

[0155] Aluminum ions are injected into the P base region from the window of the P+ low resistance region, and the P+ low resistance region is formed after thermal diffusion. The concentration range of the P+ low resistance region is 1E17cm -3 -5E18cm -3 , the depth of the P+ low resistance region is 20μm-50μm.

[0156] Boron ions are injected into the N buffer from the second side of the substrate, and a P+ emitter region is formed after thermal diffusion. The concentration of P-type conductive ions in the P+ emitter region is in the range of 5E16cm -3 -1E20cm -3 , the depth of the P+ emitter region is 1μm-20μm.

[0157] Then, a gate electrode 15 is formed on the P+ low resistance region, a cathode electrode 14 is formed on the N+ emitter region, and an anode electrode 13 is formed on the bottom surface of the P+ emitter region. In this embodiment, the gate electrode 15, the cathode electrode 14 and the anode electrode 13 are formed in the same manner as in the above embodiment, and will not be described in detail herein.

[0158] Reference Fig. 9 As shown, in the power semiconductor device formed in this embodiment, the top surface of the second conductivity type emitter region 7 of the gate-commutated thyristor unit is flush with the top surface of the first conductivity type base region 6 .

[0159] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0160] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A power semiconductor device comprising at least one gate-commutated thyristor unit, characterized in that: The gate-commutated thyristor unit comprises a first conductive type base region, the first conductive type base region comprises a first sub-base region, a second sub-base region and a third sub-base region with different doping concentrations, the first sub-base region and the second sub-base region are independently arranged and separated by the third sub-base region; The gate-commutated thyristor unit further includes a second conductive type emitter region, a cathode electrode and a gate electrode, the second conductive type emitter region is arranged on the first sub-base region, the first sub-base region covers the side surface and the bottom surface of the second conductive type emitter region, the cathode electrode is arranged on the second conductive type emitter region, and the gate electrode is arranged on the second sub-base region; The doping concentration of the first sub-base region is less than the doping concentration of the third sub-base region; and the doping concentration of the second sub-base region is greater than the doping concentration of the third sub-base region.

2. The power semiconductor device according to claim 1, characterized in that: The bottom of the second conductive type emitter region is buried in the first sub-base region, the top of the second conductive type emitter region is raised relative to the first sub-base region, or the top surface of the second conductive type emitter region is flush with the top surface of the first sub-base region.

3. The power semiconductor device according to claim 1, characterized in that: A first conductivity type short base region is also provided in the first conductivity type base region, and the first conductivity type short base region is located below the first sub-base region.

4. The power semiconductor device according to claim 3, characterized in that: A depth to which the second sub-base region extends in the first conductive type base region is less than or equal to a depth to which the first sub-base region extends in the first conductive type base region.

5. The power semiconductor device according to claim 3, characterized in that: A depth to which the second sub-base region extends in the first conductive type base region is greater than a depth to which the first sub-base region extends in the first conductive type base region.

6. The power semiconductor device according to claim 5, characterized in that: The second sub-base region extends into the first conductive type short base region.

7. The power semiconductor device according to any one of claims 1 to 6, characterized in that: The power semiconductor device includes at least one gate contact ring and a plurality of concentric cathode rings, each of the cathode rings includes a plurality of cathode comb strip regions arranged along the radial direction of the cathode ring, the second conductive type emitter region is arranged in the cathode comb strip region, the second sub-base region is arranged between adjacent second conductive type emitter regions of the cathode ring, and the second sub-base region is connected to the gate contact ring through the first conductive type base region.

8. The power semiconductor device according to claim 7, characterized in that: Taking the direction perpendicular to the radial direction of the cathode ring as the lateral direction, the width of the second sub-base region in the lateral direction is positively correlated with the distance between the second sub-base region and the gate contact ring.

9. A method for manufacturing a power semiconductor device, characterized in that: The following steps are involved: Providing a substrate, the substrate having a second conductivity type, the substrate comprising a first side and a second side disposed opposite to each other; forming a first conductive type base region, wherein the first conductive type base region is disposed on the first side of the substrate; forming a first sub-base region, wherein the first sub-base region extends from a top surface of the first conductive type base region toward the substrate; forming a second conductive type emitter region, wherein the second conductive type emitter region is formed in the first sub-base region, the side surface and the top surface of the second conductive type emitter region are covered by the first sub-base region, and the first sub-base region is arranged between the second conductive type emitter region and the first conductive type base region; forming a second sub-base region, wherein the second sub-base region extends from the top surface of the first conductive type base region in the direction of the substrate, the first sub-base region and the second sub-base region are independently arranged, and the first conductive type base region between the first sub-base region and the second sub-base region is divided into a third sub-base region, and the first sub-base region, the second sub-base region, and the third sub-base region have different doping concentrations; The doping concentration of the first sub-base region is less than the doping concentration of the third sub-base region; and the doping concentration of the second sub-base region is greater than the doping concentration of the third sub-base region.

10. The method for manufacturing a power semiconductor device according to claim 9, characterized in that: Before forming the first subbase region, the method further includes: forming a first conductivity type short base region in the first conductivity type base region, wherein a top surface of the first conductivity type short base region is lower than a top surface of the first conductivity type base region; The first sub-base region is formed above a first conductive type short base region.

11. The method for manufacturing a power semiconductor device according to claim 9, characterized in that: The method for manufacturing the power semiconductor device further includes: forming a cathode electrode, wherein the cathode electrode is disposed on the second conductive type emitter region, and the cathode electrode is in contact with the second conductive type emitter region; A gate electrode is formed, wherein the gate electrode is disposed on the second sub-base region, and the gate electrode is in contact with the second sub-base region.

12. The method for manufacturing a power semiconductor device according to claim 9, characterized in that: The method for manufacturing the power semiconductor device further includes: forming a second conductive type buffer zone, wherein the second conductive type buffer zone is disposed on the second side of the substrate; A first conductive type emitter region is formed, wherein the first conductive type emitter region is disposed on a side of the second conductive type buffer region away from the substrate.

13. The method for manufacturing a power semiconductor device according to claim 12, characterized in that: The method for manufacturing the power semiconductor device further includes: An anode electrode is formed. The anode electrode is disposed on a side of the first conductive type emitter region away from the second conductive type buffer region. The anode electrode is in contact with the first conductive type emitter region.

14. The method for manufacturing a power semiconductor device according to claim 9, characterized in that: The forming of the second conductive type emitter region further includes the following steps: The second conductive type emitter region, the first sub-base region and the first conductive type base region are etched, and the top surface of the second conductive type emitter region after etching is higher than the top surfaces of the first sub-base region and the first conductive type base region, and the top of the second conductive type emitter region is raised relative to the first sub-base region and the first conductive type base region.

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