Pixel cell readout circuit and method of operation thereof

Abstract

A dual gain column structure for column power area efficiency is disclosed. A pixel cell readout circuit includes a comparator having a current mirror with first and second current paths, a first input transistor coupled to the first current path, a low conversion gain (LCG) second input transistor selectively coupled to the second current path, and a high conversion gain (HCG) second input transistor selectively coupled to the second current path. The pixel cell readout circuit further includes a gain network coupled between a gate node of the first input transistor and a ramp generator output, where the gain network is configured to provide a variable comparator gain to the comparator, an LCG auto-zero switch coupled between a drain node and a gate node of the LCG second input transistor, and an HCG auto-zero switch coupled between a drain node and a gate node of the HCG second input transistor.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to image sensors, and in particular, but not exclusively, to high dynamic range (HDR) complementary metal-oxide-semiconductor (CMOS) image sensors. BACKGROUND

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cell phones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design as well as image acquisition processing. The technology used to manufacture image sensors continues to rapidly evolve. For example, the demand for higher resolution and lower power consumption has already prompted further miniaturization and integration of these devices.

[0003] A typical image sensor operates in response to image light from an external scene incident on the image sensor. The image sensor includes an array of pixels having light-sensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charges after absorbing the image light. The image charges photo-generated by the pixels can be measured as an analog output image signal on a column bitline, which varies with the incident image light. In other words, the amount of image charges generated is proportional to the intensity of the image light, which is read out as an analog image signal from the column bitline and converted to a digital value to produce a digital image (e.g., image data) representing the external scene. The analog image signal on the bitline is coupled to a readout circuit, which includes an input stage having an analog-to-digital (ADC) circuit to convert the analog image signal from the pixel array to a digital image signal. SUMMARY

[0004] According to an aspect of the disclosure, a pixel cell readout circuit is provided. The pixel cell readout circuit includes a comparator including a current mirror having a first current path and a second current path, a first input transistor coupled to the first current path of the current mirror, a low conversion gain (LCG) second input transistor selectively coupled to the second current path of the current mirror, and a high conversion gain (HCG) second input transistor selectively coupled to the second current path of the current mirror, and a gain network coupled between a gate node of the first input transistor and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator, an LCG auto-zero switch coupled between a drain node and a gate node of the LCG second input transistor, and an HCG auto-zero switch coupled between a drain node and a gate node of the HCG second input transistor, wherein the gate node of the LCG second input transistor and the gate node of the HCG second input transistor are each selectively coupled to a bit line, wherein the LCG auto-zero switch is configured to turn on and off prior to an LCG reset period, and wherein the HCG auto-zero switch is configured to turn on and off prior to an HCG reset period.

[0005] According to another aspect of the disclosure, a method of operating a pixel cell readout circuit is provided. The method includes selectively coupling each of a low conversion gain (LCG) second input transistor and a high conversion gain (HCG) second input transistor of a comparator to a current mirror of the comparator, coupling a gain network between a gate node of a first input transistor of the comparator and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator, coupling an LCG auto-zero switch between a drain node and a gate node of the LCG second input transistor, wherein the gate node of the LCG second input transistor is further selectively coupled to a bit line, coupling an HCG auto-zero switch between a drain node and a gate node of the HCG second input transistor, wherein the gate node of the HCG second input transistor is further selectively coupled to the bit line, prior to an LCG reset period— turning on and off the LCG auto-zero switch, and prior to an HCG reset period— turning on and off the HCG auto-zero switch.

[0006] According to yet another aspect of the disclosure, a pixel cell readout circuit is provided. The pixel cell readout circuit includes a comparator having a first input comparator and a second input comparator, a gain network coupled between a gate node of the first input transistor and a slope generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator, a first capacitor coupled between a gate node of the second input transistor and a bit line, and a second capacitor coupled between the gate node of the second input transistor and an auto-zero voltage source, wherein the auto-zero voltage source is configured to be at a low level during a low conversion gain (LCG) reset period and a LCG signal readout period, and wherein the auto-zero voltage source is configured to be at a high level during a high conversion gain (HCG) reset period and a HCG signal readout period.

[0007] According to still another aspect of the disclosure, a method of operating a pixel cell readout circuit is provided. The method includes coupling a gain network between a gate node of a first input transistor of a comparator and a slope generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator, coupling a first capacitor between a gate node of a second input transistor of the comparator and a bit line, coupling a second capacitor between the gate node of the second input transistor and an auto-zero voltage source, configuring the auto-zero voltage source to be at a low level during a low conversion gain (LCG) reset period, configuring the auto-zero voltage source to be at a high level during a high conversion gain (HCG) reset period, configuring the auto-zero voltage source to be at the high level during a HCG signal readout period, and configuring the auto-zero voltage source at the low level during a LCG signal readout period. BRIEF DESCRIPTION OF DRAWINGS

[0008] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views. For the purposes of the present disclosure, the terms "coupled" and "connected," along with their derivatives, can be used. It should be understood that these terms are not intended as synonyms for each other. Rather, particular intent is intended for the terms "coupled" and "connected." For example, connected can be used to indicate that two or more elements are in direct physical contact or that the elements have some other direct or indirect communication between them. Coupled can mean that two or more elements are in direct physical contact. However, coupled can also mean that two or more elements are not in direct contact with each other, but yet still co-operate or "communicate" with each other.

[0009] Figure 1 One example of an imaging system including a pixel array in accordance with the teachings of the present disclosure is described.

[0010] Figure 2 A schematic diagram of one example of a readout circuit including a comparator in accordance with the teachings of the present disclosure is described.

[0011] Figure 3A And 3BA readout cycle timing diagram for a comparator in an example readout circuit according to the teachings of this disclosure is illustrated, where one auto-zero cycle has insufficient HCG reset value and HCG signal value ramp-up time and has sufficient HCG reset value and HCG signal value ramp-up time.

[0012] Figure 4 A readout cycle timing diagram for a comparator in an example readout circuit according to the teachings of this disclosure is illustrated, where one auto-zero cycle has insufficient HCG reset value and HCG signal value ramp-up time and has sufficient HCG reset value and HCG signal value ramp-up time.

[0013] Figure 5 A schematic diagram of one example of a readout circuit including a comparator according to the teachings of this disclosure is illustrated.

[0014] Figure 6 A readout cycle timing diagram for a comparator in an example readout circuit according to the teachings of this disclosure is illustrated, where one auto-zero cycle has insufficient HCG reset value and HCG signal value ramp-up time and has sufficient HCG reset value and HCG signal value ramp-up time.

[0015] Corresponding reference characters indicate corresponding components throughout the several views of the drawings. It will be understood that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures can be exaggerated relative to other elements to help to improve understanding of various embodiments of the present disclosure. Also, common but well-known elements that are useful not in making a mental disclosure of these various embodiments are often not depicted in order to convey certain aspects of the present disclosure more clearly. DETAILED DESCRIPTION

[0016] Described herein relate to an example of a pixel cell readout circuit having improved comparator range and reduced column area. In the following description, numerous specific details are set forth to provide a thorough understanding of the example. One skilled in the relevant art will recognize, however, that the technology described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the example.

[0017] Reference throughout this specification to "one example" or "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present disclosure. Thus, the appearances of the phrases "in one example" or "in one embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more examples.

[0018] For purposes of this description, spatially relative terms (for example, "beneath," "below," "lower," "above," "upper," "top," "bottom," "left," "right," "center," "intermediate," and the like) can be used to describe an element's or feature's relationship to another element or feature as illustrated in the figures. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" or "under" can encompass both an orientation of above and below. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will also be understood that when an element is referred to as being "between" two other elements, it can be the only element between the two other elements or one or more intervening elements can also be present.

[0019] In this specification, several technical terms are used. Such terms have their ordinary meaning in the art unless specifically defined herein or the context of their use clearly dictates otherwise. It is noted that element names and symbols can be used interchangeably in this document (e.g., Si and silicon); however, both have the same meaning.

[0020] As will be discussed, various examples of imaging systems having readout circuits that provide improved comparator range and reduced column area are disclosed. In various examples, a comparator is configured to auto-zero twice: a first instance before a low conversion gain (LCG) reset period; and a second instance before a high conversion gain (HCG) reset period. In various examples, the comparator is selectively coupled to an auto-zero voltage source.

[0021] Image sensors can implement dual conversion gain to obtain a high dynamic range. The high dynamic range can be obtained by reading from a pixel at a low gain, then at a high gain, and then combining the two reads. However, if a comparator is reset only once (e.g., before a readout period), there can be a significant auto-zero voltage difference between the LCG reset value and the HCG reset value. Adding the auto-zero voltage difference to the HCG reset value results in a reduction of the comparator range and an increase in the need for post-processing (e.g., counter code).

[0022] In various examples of the disclosure, the LCG / HCG auto-zero voltage difference is reduced by auto-zeroing a comparator twice. In various examples, the LCG / HCG auto-zero low voltage difference is compensated for by adjusting an auto-zero voltage source that is selectively coupled to the comparator.

[0023] To illustrate, Figure 1An example of an imaging system 100 having a readout circuit 106 that provides dual analog gain (DAG) is shown in accordance with the teachings of this disclosure. In particular, Figure 1 The depicted example illustrates an imaging system 100 that includes a pixel array 102, bit lines 112, control circuit 110, readout circuit 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array that includes a plurality of pixel circuits 104 (e.g., PI, P2,..., Pn) arranged in rows (e.g., Rl to Ry) and columns (e.g., CI to Cx) to acquire image data of a person, location, object, etc., which can then be used to present an image of the person, location, or object, etc.

[0024] In various examples, the readout circuit 106 can be configured to read out image signals over the column bit lines 112. As will be discussed, in various examples, the readout circuit 106 can include an analog-to-digital converter (ADC) having DAG in accordance with the teachings of this disclosure. In various examples, the ADC includes a ramp generator 114 and a comparator circuit 116. The ramp generator 114 has a ramp generator output from which a ramp signal 120 is provided to the comparator circuit 116. In an example, digital image data values generated by the comparator circuit 116 can then be received by the functional logic 108. The functional logic 108 can simply store the digital image data or even manipulate the digital image data by applying post-image effects (e.g., cropping, rotating, red-eye removal, adjusting brightness, adjusting contrast, or others).

[0025] In one example, the control circuit 110 is coupled to the pixel array 102 to control operation of the plurality of photodiodes in the pixel array 102. For example, the control circuit 110 can generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with a light emitting effect (e.g., a flash).

[0026] In one example, the imaging system 100 can be included in a digital camera phone, a laptop computer, an endoscope, a security camera, or an imaging device of an automobile, or the like. Additionally, the imaging system 100 can be coupled to other hardware pieces, such as a processor (general purpose or otherwise), memory elements, an output (USB port, wireless transmitter, HDMI port, etc.), a light / flash, an electrical input (keyboard, touch display, trackpad, mouse, microphone, etc.), and / or a display. The other hardware pieces can deliver instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate image data supplied by the imaging system 100.

[0027] Figure 2 A schematic diagram illustrating one example of a readout circuit 206 in accordance with the teachings of this disclosure is shown. It should be appreciated that, Figure 2 The readout circuit 206 can be included in an imaging system 200 that includes a pixel array 202, bit lines 212, control circuit 210, and functional logic 208. In one example, the pixel array 202 is a two-dimensional (2D) array that includes a plurality of pixel circuits 204 (e.g., PI, P2,..., Pn) arranged in rows (e.g., Rl to Ry) and columns (e.g., CI to Cx) to acquire image data of a person, location, object, etc., which can then be used to present an image of the person, location, or object, etc.Figure 1 The example of readout circuit 106 in imaging system 100 shown in FIG. 1 is shown in FIG. 2, and the similarly named and numbered elements described above are similarly coupled and function below.

[0028] Readout circuit 206 includes a comparator 216 having a first input coupled to a ramp gain network 228 and two alternative second inputs each selectively coupled to a bit line 212. In the depicted example, it will be appreciated that the first input of comparator 216 is the gate of transistor 244, and the two alternative second inputs of comparator 216 are the gates of transistors 242L and 242H. In various examples, transistor 242L is used for low conversion gain (LCG) readout, and transistor 242H is used for high conversion gain (HCG) readout. As shown, comparator 216 includes a transistor 240 on a first current path and a transistor 238 on a second current path, which are coupled as a current mirror. First input transistor 244 is coupled to transistor 240, and the two second input transistors 242L and 242H are each selectively coupled to transistor 238 via switches 224L and 224H, respectively. A tail current source 252 is coupled to transistors 242L, 242H, and 244, as shown.

[0029] According to the teachings of this disclosure, the ramp gain network 228 is configured to provide a variable comparator gain by controlling the slope of the ramp signal generated by the ramp generator output VRAMP 214. The variable comparator gain becomes higher as the slope of the ramp signal becomes lower. In the illustrated example, the ramp gain network 228 includes a first gain capacitor 234 and a second gain capacitor 236. The first gain capacitor 234 can be coupled between the first input of the comparator 216 and the ramp generator output VRAMP 214. The second gain capacitor 236 can be selectively coupled between the first input of the comparator 216 and the ramp generator output VRAMP 214 via a switch 230 or between the first input of the comparator 216 and ground via a switch 232. Only one of the switches 230 and 232 is on at a time, allowing the first gain capacitor 234 and the second gain capacitor 236 to act as voltage dividers when it is desired to reduce the slope of the ramp signal. In various examples, it should be appreciated that other examples of the ramp gain network 228 can have different components and / or configurations that provide a variable comparator gain according to the teachings of this disclosure. For example, the number of gain capacitors in the ramp gain network 228 can depend on the number of desired comparator gain settings. For example, in various examples, the ramp gain network 228 can each include one first gain capacitor 234 and one or more second gain capacitors 236 with one or more sets of corresponding switches 230 and 232 that selectively couple the respective second gain capacitors 236 between the first input of the comparator 216 and the ramp generator output VRAMP 214 via the switches 230 or between the first input of the comparator 216 and ground via the switches 232, as depicted in the example of FIG. 2B. Figure 2

[0030] In the illustrated example, the LCG capacitor 250L is selectively coupled between the bit line 212 (via the switch 226L) and the gate of the transistor 242L, and the HCG capacitor 250H is selectively coupled between the bit line 212 (via the switch 226H) and the gate of the transistor 242H. The LCG capacitor 250L is further selectively coupled to the drain node of the transistor 242L via the LCG auto-zero switch AZL 246L, and the HCG capacitor 250H is further selectively coupled to the drain node of the transistor 242H via the HCG auto-zero switch AZH 246H. In addition, the ramp gain network 228 is selectively coupled to the drain node of the transistor 244 via the ramp auto-zero switch AZR 248.

[0031] ​Comparator 216 has an output voltage VOUT 254 from a node between the drain of transistor 238 and the drains of transistors 242L and 242H. A node between a first input of comparator 216 and slope gain network 228 has a voltage V in,p 245. A node between LCG capacitor 250L and the gate of transistor 242L has a voltage V in,L 243L. A node between HCG capacitor 250H and the gate of transistor 242H has a voltage V in,H 243H.

[0032] Figure 3A and 3B A readout cycle timing diagram for a comparator in an example readout circuit according to the teachings of this disclosure is illustrated, where one auto-zero cycle has insufficient HCG reset value and HCG signal value ramp-up time and has sufficient HCG reset value and HCG signal value ramp-up time. In the illustrated example, the readout cycle includes an LCG reset cycle, an HCG reset cycle, an HCG signal readout cycle, and an LCG signal readout cycle. It will be appreciated that, Figures 3A to 3B An example readout cycle timing diagram for comparator 216 illustrated in Figure 2 may be illustrated, and similarly named and numbered elements described above similarly couple and function below.

[0033] Referring to Figure 3A and 3B Both, prior to the LCG reset cycle, LCG auto-zero switch AZL 346L, HCG auto-zero switch AZH 346H, and slope auto-zero switch AZR 348 are each pulsed to auto-zero the comparator. As shown in the depicted example, switches 346L, 346H, and 348 are each only pulsed once simultaneously during the readout cycle of a given frame such that the comparator has only one auto-zero cycle. A node between a first input of the comparator and the slope gain network has a voltage V in,p 345. The value of V in,p 345 is offset in response to a comparator voltage digital number (CVDN) offset relative to a maximum voltage value of the slope generator output. The CVDN is a register setting used to adjust the offset from the slope generator output voltage. The CVDN offset prior to the LCG reset cycle is represented by CVDN offset 362. In various examples, V in,p 345 is not always a constant value due to kT / C noise 360. Thus, the CVDN offset can represent an average offset value.

[0034] A node between the LCG capacitor and the gate of the LCG second input transistor has a voltage V in,L 343L. A node between the HCG capacitor and the gate of the HCG second input transistor has a voltage Vin,H 343H. Before the LCG reset cycle, V in,L 343L can be equal to or substantially similar to V in,H 343H.

[0035] During the LCG reset cycle, V in,p 345 first changes its value in response to the CVDN offset of 364, then decreases with a downward slope. The angle of the slope is determined by the variable comparator gain provided by the ramp gain network. In the illustrated example, V in,p 345 intersects with the LCG reset value (“rstL”) derived from the bit line voltage value 312. V in,L 343L and V in,H Both 343H and V decreased to the rstL value. in,p 345 then increases to the same value as before in response to the CVDN offset of 364, because the comparator is not automatically zeroed again.

[0036] During the HCG reset cycle, V in,p 345 again decreases with a downward slope, but the angle of the slope differs from that of the LCG reset period (e.g., less steep and indicating higher comparator gain). However, there is a difference between the rstL value and the HCG reset value (“rstH”), as shown in bit line voltage value 312. Both the reset values ​​rstL and rstH are measured based on CVDN offset 362, with rstH being greater than rstL and the HCG slope being less steep. Figure 3A This illustrates an example where the rise time of rstH is insufficient. Therefore, as... Figure 3A The text explains that V in,p 345 failed to intersect with rstH, resulting in an error in the ADC output digital code. V in,L 343L and V in,H 343H diverges because V in,L 343L remained at the rstL value, while V in,H 343H drops to the rstH value. V in,p 345 then increases to the same value as before in response to CVDN offset 364.

[0037] like Figure 3B The instructions state that V must be ensured. in,p One approach to intersecting 345 with rstH is to increase or extend the rstH ramp time by adding an extra rstH ramp period of 363. However, this method increases both the required counter code and line cycle. Given the maximum ramp voltage swing, this method also consumes the ADC range of HCG reset.

[0038] During the HCG signal readout period, Vin,p 345 again decreases with the same downward slope as in the HCG reset period. Figure 3A An example where the sigH ramp-up time is insufficient is also illustrated. Thus, as Figure 3A illustrated in FIG. 2B, V in,p 345 also fails to cross the HCG signal value ("sigH"), again resulting in an error in the ADC output digital code. As shown, the sigH value is measured according to a CVDN offset 362. V in,L 343L remains at the rstL value, while V in,H 343H falls to the sigH value. V in,p 345 then increases to the same value as before in response to a CVDN offset 364.

[0039] As Figure 3B illustrated in FIG. 2B, V in,p 345 one way to ensure that V

[0040] During the LCG signal readout period, V in,p 345 again decreases with the same downward slope as in the LCG reset period. In the illustrated example, V in,p 345 crosses the LCG signal value ("sigL"), indicating that the comparator range decrease is more important for HCG readout than for LCG readout. V in,L 343L falls to the sigL value, while V in,H 343H remains at the sigH value. V in,p 345 then returns to the value before the readout period in response to a CVDN offset 362. After the LCG signal readout period, the comparator moves to the readout value corresponding to the next frame, repeating the timing diagram illustrated and described above.

[0041] Figure 4 An example readout period timing diagram for a comparator in a readout circuit having two auto-zero periods according to the teachings of this disclosure is illustrated. In the illustrated example, the readout period includes an LCG reset period, an HCG reset period, an HCG signal readout period, and an LCG signal readout period. It will be appreciated that, Figure 4 may be Figure 2 the example readout period timing diagram for the comparator 216 illustrated in FIG. 2B, and the similarly named and numbered elements described above are similarly coupled and function below.

[0042] As shown in the depicted example, prior to the LCG reset period, the LCG auto-zero switch AZL 446L and the ramp auto-zero switch AZR 448 are each pulsed at the same time to auto-zero the comparator for the first time. In various examples, the HCG auto-zero switch AZH 446H is not pulsed, but remains open until the end of the LCG reset period. In various examples, the HCG auto-zero switch AZH 446H is turned on at the same time as AZL 446L and AZR 448, and remains on until the end of the LCG reset period. The node between the first input of the comparator and the ramp gain network has a voltage V in,p 445 prior to the LCG reset period. The CVDN offset prior to the LCG reset period is represented by CVDN offset 462. In various examples, V in,p 445 is not always a constant value due to kT / C noise 460. Thus, the CVDN offset can represent an average offset value.

[0043] The node between the LCG capacitor and the gate of the LCG second input transistor has a voltage V in,L 443L. The node between the HCG capacitor and the gate of the HCG second input transistor has a voltage V in,H 443H. Prior to the LCG reset period, V in,L 443L can be equal to or substantially similar to V in,H 443H.

[0044] During the LCG reset period, between tl and t2, V in,p 445 first changes value in response to CVDN offset 464, then decreases with a downward slope. The angle of the slope is determined by the variable comparator gain provided by the ramp gain network. In the illustrated example, V in,p 445 intersects with the rstL value derived from the bit line voltage value 412. AZR 448 is then pulsed again to auto-zero the comparator for the second time. In various examples, AZH 446H is pulsed at the same time as AZR 448. In various examples, AZH 446H is turned on at the same time as AZL 446L and AZR 448 are pulsed prior to the LCG reset period, and is turned off at the end of the LCG reset period with AZR 448. In examples where AZH 446H is pulsed, V in,L 443L falls to the rstL value, while V in,H 443H remains at the initial value until AZH 446H is pulsed. V in,p 445 then increases in response to CVDN offset 466, as the comparator is auto-zeroed for the second time.

[0045] In various instances, CVDN offset 466 is equal to or substantially similar to CVDN offset 462. This allows for a reduction in the LCG signal offset relative to the auto-zero voltage difference, which has the advantages described further below. In various instances, V in,p 445 exhibits behavior again in response to the kT / C noise 460 after the second auto-zeroing cycle, resulting in increased noise and thus a decrease in signal-to-noise ratio (SNR) at the inflection point.

[0046] During the HCG reset cycle, between t2 and t3, V in,p 445 increases again to CVDN offset 468, then decreases with a downward slope, but the angle of the slope is different from that of the LCG reset period (e.g., less steep and indicating higher comparator gain). Although the magnitude of the rstH value is greater than the magnitude of the rstL value, as seen in the bit line voltage value 412, rstH is determined according to the second auto-zero V. in,p The value is 445 (i.e., CVDN offset 466) instead of the first auto-zero V. in,p The value is 445 (i.e., CVDN offset 462) for measurement. Therefore, V in,p 445 intersects with the rstH value, thus avoiding Figure 3A The problem of reduced comparator range described in the text. V in,L 443L remains at the rstL value, while V in,H 443H drops to the rstH value measured according to different reference voltage values, such as Figure 4 Displayed in V. in,p 445 then returns to CVDN offset 468.

[0047] During the HCG signal readout period, between times t3 and t4, V in,p 445 decreases again with the same downward slope as during the HCG reset cycle. V in,p 445 intersects with the sigH value, thus avoiding [further issues]. Figure 3A The issue of reduced comparator range is described in the diagram. As shown, the sigH value is measured with a CVDN offset of 466. V in,L 443L remains at the rstL value, while V in,H 443H drops to the sigH value measured according to the same reference voltage value as rstH. V in,p 445 then responds to the CVDN offset 464 and increases back to the same high value during the LCG reset cycle.

[0048] During the LCG signal readout period, starting from time t4, V in,p445is again decreased with the same downward slope as in the LCG reset period. In the illustrated example, V in,p 445intersects with the sigL value measured according to the CVDN offset 466. While this sigL value represents the actual LCG rollover point, the desired LCG rollover point is the sigL value measured according to the CVDN offset 462, as Figure 4 demonstrated in FIG. 5. The difference between the actual sigL and the desired sigL is the LCG extra noise 470. Thus, the advantages of auto-zeroing the comparator twice (i.e., improved comparator range and reduced column area) should be offset by the LCG extra noise. V in,L 443L falls to a sigL value measured according to a reference voltage value that is the same as the reference voltage value according to which rstL is measured, while V in,H 443H remains at a sigH value. After the LCG signal readout period, the comparator moves to the readout value corresponding to the next frame, repeating the timing diagram illustrated and described above.

[0049] Figure 5 A schematic diagram illustrating one example of a readout circuit 506 according to the teachings of this disclosure is illustrated. It should be appreciated that, Figure 5 the readout circuit 506 can be an example of the readout circuit 106 included in the imaging system 100 shown in Figure 1 FIG. 1, and the similarly named and numbered elements described above similarly couple and function below.

[0050] The readout circuit 506 includes a comparator 516 having a first input coupled to a slope gain network 528 and a second input coupled to a bitline 512. In the depicted example, it should be appreciated that the first input of the comparator 516 is the gate of a transistor 544 and the second input of the comparator 516 is the gate of a transistor 542. As shown, the comparator 516 includes a transistor 540 on a first current path and a transistor 538 on a second current path, which are coupled as a current mirror. The first input transistor 544 is coupled to the transistor 540 and the second input transistor 542 is coupled to the transistor 538. A tail current source 552 is coupled to the transistors 542 and 544, as shown.

[0051] According to the teachings of this disclosure, the ramp gain network 528 is configured to provide a variable comparator gain by controlling the slope of the ramp signal generated by the ramp generator output VRAMP 514. The variable comparator gain becomes higher as the slope of the ramp signal is changed lower. In the illustrated example, the ramp gain network 528 includes a first gain capacitor 534 and a second gain capacitor 536. The first gain capacitor 534 can be coupled between the first input of the comparator 516 and the ramp generator output VRAMP 514. The second gain capacitor 536 can be selectively coupled between the first input of the comparator 516 and the ramp generator output VRAMP 514 via a switch 530 or between the first input of the comparator 516 and ground via a switch 532. Only one of the switches 530 and 532 is on at a time, allowing the first gain capacitor 534 and the second gain capacitor 536 to act as voltage dividers when it is desired to reduce the slope of the ramp signal. In various examples, it should be appreciated that other examples of the ramp gain network 528 can have different components and / or configurations that provide a variable comparator gain according to the teachings of this disclosure. For example, the number of gain capacitors in the ramp gain network 528 can depend on the number of desired comparator gain settings. For example, in various examples, the ramp gain network 528 can each include one first gain capacitor 534 and one or more second gain capacitors 536 with one or more sets of corresponding switches 530 and 532 that selectively couple the respective second gain capacitors 536 between the first input of the comparator 516 and the ramp generator output VRAMP 514 via the switches 530 or between the first input of the comparator 516 and ground via the switches 532, as depicted in the example of FIG. 5B. Figure 5

[0052] In the illustrated example, the bit line capacitor 550B is coupled between the bit line 512 and the gate of the transistor 542. The comparator 516 has an output voltage VOUT 554 from a node between the drain of the transistor 538 and the drain of the transistor 542. The node between the drain of the transistor 538 and the drain of the transistor 542 is further selectively coupled to an auto-zero voltage source V AZ 513 and the gate of the transistor 542 via an auto-zero switch AZ 546. An auto-zero capacitor 550Z is coupled between the auto-zero voltage source V AZ 513 and the auto-zero switch AZ 546. The auto-zero capacitor 550Z is further coupled between the auto-zero voltage source V AZ 513 and the gate of the transistor 542. A node between the first input of the comparator 516 and the ramp gain network 528 has a voltage V in,p ​545. The ramp gain network 528 is further selectively coupled to the drain of the transistor 544 via a ramp auto-zero switch AZR 548.

[0053] In various examples, the bit line capacitor 550B and the auto-zero capacitor 550Z have the same capacitance. In various examples, the bit line capacitor 550B has a different capacitance than the auto-zero capacitor 550Z (e.g., the bit line capacitor 550B has a capacitance that is six, eight, or ten times greater than the capacitance of the auto-zero capacitor 550Z). In various examples, the auto-zero voltage source V AZ 513 has a voltage value between 0.8 V and 1.6 V.

[0054] Figure 6 A readout cycle timing diagram for a comparator in an example readout circuit having an auto-zero voltage source according to the teachings of this disclosure is illustrated. In the illustrated example, the readout cycle includes an LCG reset cycle, an HCG reset cycle, an HCG signal readout cycle, and an LCG signal readout cycle. It will be appreciated that, Figure 6 may be Figure 5 An example readout cycle timing diagram for the comparator 516 illustrated in FIG. 6B, and similarly named and numbered elements described above, are similarly coupled and function below.

[0055] Prior to the LCG reset cycle, the auto-zero switch AZ 646 is pulsed to auto-zero the comparator. During the LCG reset cycle, the auto-zero voltage source V AZ 613 is configured to change to a high value and remain at the high value during the HCG reset cycle and the HCG signal readout cycle. As the readout circuit moves to the LCG reset cycle, the auto-zero voltage source V AZ 613 is configured to change to a high value and remain at the high value during the HCG reset cycle and the HCG signal readout cycle. As the readout circuit moves to the LCG reset cycle, the auto-zero voltage source V AZ 613 is configured to change back to a low value.

[0056] The auto-zero voltage source V AZ 613 is configured to adjust to compensate for a difference between the LCG reset level and the HCG reset level, as shown in the bit line voltage value 612. In various examples, the difference between the LCG reset level and the HCG reset level ranges between 100 mV and 200 mV. In various examples, the auto-zero voltage source V AZ 613 is configured to auto-calibrate based on frame and analog gain.

[0057] However, the advantage of adjusting the auto-zero voltage source V AZ 613 to compensate for the difference between the LCG reset level and the HCG reset level should be offset by the auto-zero voltage source V AZ613 Random noise generated. Coupling to auto-zero voltage source V AZ 613 Capacitor between comparator (e.g. Figure 5 Auto-zero capacitor 550Z in) is an additional source of column gain error. Buffer noise from auto-zero voltage source V AZ 613 is proportionally added to the readout signal row by row through the coupling capacitor (e.g. Figure 5 Auto-zero capacitor 550Z in). In addition, there can be random noise from the capacitor divider configuration. In various examples, the effective signal gain is less than 1. There can also be a stable H-band from auto-zero voltage source V AZ 613. In various examples, it should be appreciated that a global or local buffer can be coupled to auto-zero voltage source V AZ 613 to provide additional power and reduce the settling time.

[0058] The above description of the disclosed examples, including that in the Summary of the Disclosure, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific examples of the disclosure are described herein for illustrative purposes, various modifications are possible within the scope of the disclosure, as will be recognized by those skilled in the relevant art.

[0059] These modifications can be made in light of the above detailed description of the disclosure. The terms used in the following claims should not be construed to limit the disclosure to the specific examples disclosed in the specification. Rather, the scope of the disclosure will be determined by the following claims, applicable statutes, and the principles of claim interpretation set forth in the statutes.

Claims

1. A pixel cell readout circuit, comprising: a comparator, comprising: a current mirror having a first current path and a second current path; a first input transistor coupled to the first current path of the current mirror; a low conversion gain (LCG) second input transistor selectively coupled to the second current path of the current mirror; and a high conversion gain (HCG) second input transistor selectively coupled to the second current path of the current mirror; and a gain network coupled between a gate node of the first input transistor and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator; an LCG auto-zero switch coupled between a drain node and a gate node of the LCG second input transistor; and an HCG auto-zero switch coupled between a drain node and a gate node of the HCG second input transistor, wherein the gate node of the LCG second input transistor and the gate node of the HCG second input transistor are each selectively coupled to a bit line, wherein the LCG auto-zero switch is configured to turn on and off prior to an LCG reset period, and wherein the HCG auto-zero switch is configured to turn on and off prior to an HCG reset period.

2. The pixel cell readout circuit of claim 1, further comprising a ramp auto-zero switch coupled between a drain node and the gate node of the first input transistor, wherein the ramp auto-zero switch is configured to turn on and off prior to the LCG reset period, and wherein the ramp auto-zero switch is further configured to turn on and off prior to the HCG reset period.

3. The pixel cell readout circuit of claim 1, further comprising: an LCG capacitor selectively coupled between the gate node of the LCG second input transistor and the bit line; and an HCG capacitor selectively coupled between the gate node of the HCG second input transistor and the bit line. a tail current source coupled between a reference voltage and source nodes of the first input transistor, the LCG second input transistor, and the HCG second input transistor.

4. The pixel cell readout circuit of claim 1, further comprising:

5. The pixel cell readout circuit of claim 1, wherein a voltage value at the gate node of the first input transistor is configured to be less than a maximum voltage value of the ramp generator output in response to a comparator voltage digital number (CVDN) offset.

6. The pixel cell readout circuit of claim 5, wherein the CVDN offset during the LCG reset period is configured to be less than the CVDN offset during the HCG reset period.

7. The pixel cell readout circuit of claim 5, wherein the CVDN offset when the LCG auto-zero switch is on is configured to be greater than the CVDN offset when the HCG auto-zero switch is on. ​ 8. The pixel cell readout circuit of claim 5, wherein the CVDN offset when the LCG auto-zero switch is on is configured to be substantially similar to the CVDN offset when the HCG auto-zero switch is on.

9. A method of operating a pixel cell readout circuit, comprising: selectively coupling each of a low conversion gain (LCG) second input transistor and a high conversion gain (HCG) second input transistor of a comparator to a current mirror of the comparator; coupling a gain network between a gate node of a first input transistor of the comparator and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator; coupling an LCG auto-zero switch between a drain node and a gate node of the LCG second input transistor, wherein the gate node of the LCG second input transistor is further selectively coupled to a bit line; coupling an HCG auto-zero switch between a drain node and a gate node of the HCG second input transistor, wherein the gate node of the HCG second input transistor is further selectively coupled to the bit line; prior to an LCG reset period, turning on and off the LCG auto-zero switch; and prior to an HCG reset period, turning on and off the HCG auto-zero switch.

10. The method of claim 9, further comprising: coupling a ramp auto-zero switch between a drain node and the gate node of the first input transistor; prior to the LCG reset period, turning on and off the ramp auto-zero switch; and prior to the HCG reset period, turning on and off the ramp auto-zero switch.

11. The method of claim 9, wherein the gate node of the LCG second input transistor is further selectively capacitively coupled to the bit line through an LCG capacitor, and wherein the gate node of the HCG second input transistor is further selectively capacitively coupled to the bit line through an HCG capacitor.

12. The method of claim 9, wherein a voltage value at the gate node of the first input transistor is configured to be less than a maximum voltage value of the ramp generator output in response to a comparator voltage digital number (CVDN) offset.

13. The method of claim 12, wherein the CVDN offset during the LCG reset period is configured to be less than the CVDN offset during the HCG reset period.

14. The method of claim 12, wherein the CVDN offset when the LCG auto-zero switch is on is configured to be greater than a CVDN offset when the HCG auto-zero switch is on.

15. The method of claim 12, wherein the CVDN offset when the LCG auto-zero switch is on is configured to be substantially similar to a CVDN offset when the HCG auto-zero switch is on.

16. A pixel cell readout circuit, comprising: a comparator having a first input transistor and a second input transistor; a gain network coupled between a gate node of the first input transistor and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator; a first capacitor coupled between a gate node of the second input transistor and a bit line; and a second capacitor coupled between the gate node of the second input transistor and an auto-zero voltage source, wherein the auto-zero voltage source is configured to be at a low level during a low conversion gain, LCG, reset period and a LCG signal readout period, and wherein the auto-zero voltage source is configured to be at a high level during a high conversion gain, HCG, reset period and a HCG signal readout period.

17. The pixel cell readout circuit of claim 16, further comprising a first auto-zero switch coupled between a drain node and the gate node of the first input transistor.

18. The pixel cell readout circuit of claim 16, further comprising a second auto-zero switch coupled between a drain node and the gate node of the second input transistor, wherein the second auto-zero switch is configured to turn on and off before the LCG reset period, wherein the second auto-zero switch is further configured to remain off during the HCG reset period, the HCG signal readout period, and the LCG signal readout period.

19. The pixel cell readout circuit of claim 16, wherein a capacitance of the first capacitor is between six times and ten times a capacitance of the second capacitor.

20. A method of operating a pixel cell readout circuit, comprising: coupling a gain network between a gate node of a first input transistor of a comparator and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator; coupling a first capacitor between a gate node of a second input transistor of the comparator and a bit line; coupling a second capacitor between the gate node of the second input transistor and an auto-zero voltage source; during a low conversion gain, LCG, reset period, configuring the auto-zero voltage source to be at a low level; during a high conversion gain, HCG, reset period, configuring the auto-zero voltage source to be at a high level; during a HCG signal readout period, configuring the auto-zero voltage source to be at the high level; and during a LCG signal readout period, configuring the auto-zero voltage source at the low level.

21. The method of claim 20, further comprising coupling a first auto-zero switch between a drain node and a source node of the first input transistor.

22. The method of claim 20, further comprising: coupling a second auto-zero switch between a drain node and the gate node of the second input transistor; before the LCG reset period, turning on and off the second auto-zero switch; during the LCG reset period, the HCG reset period, the HCG signal readout period, and the LCG signal readout period, keeping the second auto-zero switch open.

23. The method of claim 20, wherein a capacitance of the first capacitor is between six times and ten times a capacitance of the second capacitor.

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