Signal delay processing method and device, electronic device and storage medium

Abstract

The present application relates to a method and device for processing signal delay, an electronic device and a storage medium, wherein the method comprises: reading a digital signal from an external memory according to a frame delay based on T1, and caching the read digital data into a processor; wherein the external memory is used to store the digital signal received by the processor from the front-end module; T1 is an integer multiple of the frame data duration; based on T2, the digital signal in the cache is subjected to delayed output processing to obtain a digital signal after delayed output; wherein T2 is associated with the sampling clock of the processor; based on T3, the digital signal after delayed output is subjected to delayed output processing again, and the digital signal after delayed processing is output, wherein T3 is associated with the delay filter of the processor; the sum of T1, T2 and T3 is equal to the preset total delay. Through the present application, the problem that the delay of the signal in the prior art is difficult to meet the high-precision and large-range delay requirements is solved.

Description

Technical Field

[0001] The present application relates to the field of signal processing, and in particular to a method and device for processing signal delay, an electronic device and a storage medium. Background Art

[0002] With the development of electronic technology, electronic systems have put forward higher requirements for signal delay, especially for signal delay accuracy, delay range and delay response speed. At present, the mainstream method for realizing signal delay is delay line technology, that is, using digital programmable delay chips to realize signal delay. The delay step of small-step delay line chips can reach 10ps, but the delay range is generally in the order of 10ns, which is difficult to meet the needs of large-range delay. In other improvement schemes, such as using multiple delay chips for cascading to achieve the purpose of expanding the maximum delay range, to a certain extent, the problem of incompatibility between fine-step and large-range indicators of delay chips is solved, but there are also certain limitations, and the complexity of the system is increased, especially for multi-channel delay application systems, it is difficult to ensure the consistency between channels; such as using fine-step delay chips, combined with FPGA (Field Programmable Gate Array) internal resources to achieve both fine-step and large-range requirements, but limited by the limitation of FPGA resources, the delay range is limited, and it is difficult to meet the application scenarios of multi-channel and large-range delay. At the same time, the delay line has some obvious disadvantages, such as large size, high power consumption, high price, and susceptibility to external environmental influences such as temperature. It is difficult to fully meet the requirements of high precision, large range, and multi-channel in current electronic systems. Summary of the invention

[0003] The present application provides a signal delay processing method and device, an electronic device and a storage medium to solve the problem in the prior art that signal delay is difficult to meet the requirements of high-precision and large-range delay.

[0004] In the first aspect, the present application provides a signal delay processing method, which is applied to a processor, and the method includes: reading a digital signal from an external memory according to a frame delay based on T1, and caching the read digital data into the processor; wherein the external memory is used to store the digital signal received by the processor from the front-end module; T1 is an integer multiple of the frame data duration; based on T2, the digital signal in the cache is delayed output processed to obtain a digital signal after delayed output; wherein T2 is associated with the sampling clock of the processor; based on T3, the digital signal after delayed output is delayed output processed again, and the digital signal after delayed processing is output, wherein T3 is associated with the delay filter of the processor; the sum of T1, T2 and T3 is equal to the preset total delay.

[0005] In a second aspect, the present application provides a signal delay processing device, the method comprising: a first processing module, used to read a digital signal from an external memory according to a frame delay based on T1, and cache the read digital data inside the processor; wherein the external memory is used to store the digital signal received by the processor from the front-end module; the T1 is an integer multiple of the frame data duration; a second processing module, used to perform delayed output processing on the digital signal in the cache based on T2 to obtain a digital signal after delayed output; wherein the T2 is associated with the sampling clock of the processor; a third processing module, used to perform delayed output processing on the digital signal after delayed output again based on T3, and output the digital signal after delayed processing, wherein the T3 is associated with the delay filter of the processor; the sum of T1, T2 and T3 is equal to the preset total delay.

[0006] In a third aspect, the present application provides an electronic device comprising: at least one communication interface; at least one bus connected to the at least one communication interface; at least one processor connected to the at least one bus; and at least one memory connected to the at least one bus, wherein the processor is configured to execute the signal delay processing method described in the first aspect of the present application.

[0007] In a fourth aspect, the present application further provides a computer storage medium storing computer executable instructions, wherein the computer executable instructions are used to execute the signal delay processing method described in the first aspect of the present application.

[0008] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art: three-level delay is performed through the above-mentioned T1, T2 and T3; in this regard, when delay reading is performed based on T1, since the external memory is operated by frame, T1 is an integer multiple of the frame data duration, so the delay is large in the T1 stage. In the T2 stage, since T2 is related to the sampling clock of the processor, it is related to the cache size of each channel of the processor when delay processing is performed, so the T2 stage can be called a coarse delay. In the T3 stage, since T3 is associated with the delay filter of the processor, T3 can be called a fine delay. It can be seen that in the embodiment of the present application, the first level of data delay by frame, the second level of data delay by clock, and the third level of delay filter are used to achieve fractional data delay, thereby achieving high-precision and wide-range signal delay for the received signal, solving the problem that the delay of the signal in the prior art is difficult to meet the high-precision and wide-range delay requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0011] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0012] Figure 1 A flowchart of a signal delay processing method provided in an embodiment of the present application;

[0013] Figure 2 The external memory read and write control flow chart provided in the embodiment of the present application;

[0014] Figure 3 A schematic diagram of external memory address allocation provided in an embodiment of the present application;

[0015] Figure 4 This is a schematic diagram of the structure of a multi-channel, large-range signal delay device provided in a specific implementation manner of the present application;

[0016] Figure 5 A schematic diagram of the structure of a signal delay processing device provided in an embodiment of the present application;

[0017] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0019] The disclosure below provides many different embodiments or examples to implement different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0020] Figure 1 A flowchart of a signal delay processing method provided in an embodiment of the present application, the method is applied to a processor, such as Figure 1 As shown, the steps of the method include:

[0021] Step 101, based on T1, read the digital signal from the external memory according to the frame delay, and cache the read digital data into the processor; wherein the external memory is used to store the digital signal received by the processor from the front-end module; T1 is an integer multiple of the frame data duration;

[0022] It can be seen that in the embodiment of the present application, an external memory is added to cache the received data. The external cache capacity is usually relatively large, such as 1GB of DDR3, while the internal cache of the processor is usually relatively small, such as tens of MB of FPGA internal capacity, and the size of the capacity directly determines the amount of data that can be cached, which directly determines the maximum delay range of the signal.

[0023] Step 102, performing delayed output processing on the digital signal in the cache based on T2 to obtain a delayed output digital signal; wherein T2 is associated with a sampling clock of the processor;

[0024] Step 103, based on T3, the delayed output digital signal is subjected to delayed output processing again, and the delayed digital signal is output, wherein T3 is associated with the delay filter of the processor; and the sum of T1, T2 and T3 is equal to the preset total delay.

[0025] It can be known from the above steps 101 to 103 that three levels of delay are performed through the above T1, T2 and T3; in this regard, when delay reading is performed based on T1, since the external memory is operated by frame, T1 is an integer multiple of the frame data duration, so the T1 stage is a large delay. In the T2 stage, since T2 is related to the sampling clock of the processor, it is related to the cache size of each channel of the processor when delay processing is performed, so the T2 stage can be called a coarse delay. In the T3 stage, since T3 is associated with the delay filter of the processor, T3 can be called a fine delay. It can be seen that in the embodiment of the present application, the first level of data delay by frame, the second level of data delay by clock, and the third level of delay filter are used to achieve fractional data delay, thereby achieving high-precision and wide-range signal delay for the received signal, solving the problem that the delay of the signal in the prior art is difficult to meet the high-precision and wide-range delay requirements in the prior art.

[0026] In an optional implementation manner of the embodiment of the present application, before reading the digital signal from the external memory according to the frame delay based on T1, the method of the embodiment of the present application may further include:

[0027] Step 11, receiving a multi-channel navigation signal transmitted wirelessly, wherein the navigation signal is an analog signal;

[0028] Step 12, converting the multi-channel navigation signals into multi-channel digital signals, and performing signal framing on the multi-channel digital signals;

[0029] Step 13, cache the digital signal after signal framing in the processor, and write the cached digital signal into the external memory after the full frame data is cached.

[0030] It can be seen that the digital signal in the embodiment of the present application is converted from the analog navigation signal. In a specific example, for the navigation signal channel simulation device, it is necessary to perform different delay forwarding on the received multi-channel single-star signals. The specific number of channels is related to the equipment and system requirements. According to the navigation positioning principle, the receiver needs at least 4 stars to participate in positioning, so the processing in the embodiment of the present application receives at least 4 analog navigation signals.

[0031] Furthermore, the conversion between analog signals and digital signals can be realized by an analog-to-digital converter. Since the wirelessly transmitted navigation signal is an analog signal, the received multi-channel analog signals are converted into multi-channel digital signals after passing through multiple analog-to-digital converters. The digital signal in the processor can come from the digital signal output by the front-end analog-to-digital converter, or it can be received from other modules through a high-speed interface (such as optical fiber).

[0032] In the embodiment of the present application, in order to increase the read and write rate of the external memory, the data can be read and written in a frame-by-frame operation mode. In addition, in the embodiment of the present application, the signal framing mode is relatively flexible, and the frame size can be customized. The received framed digital signal is cached, and a write operation to the external memory is initiated after the full frame data is cached. In this regard, in the specific example such as Figure 2 As shown, the sampling frequency of the input digital signal is 50M, the I and Q bit widths of the sampling data are both 16 bits, the input signal channel N=4, and the output signal of each channel is framed separately. Calculated based on the length of each frame being 1024 points, the data size of each frame is 4KB, and the time to complete the reception of a frame of data is T_Frame=20ns×1024=20480ns. After each frame of data is received, a write memory operation is started.

[0033] In the embodiment of the present application, the method of reading the digital signal from the external memory according to the frame delay based on T1 involved in the above step 101 may further include:

[0034] Step 21, determining a first duration required to read a frame of data based on a sampling clock of a processor and a data frame size;

[0035] Step 22, obtaining a storage space of each channel of the memory, and determining a second duration of the data stored in each channel based on the storage space and the first duration;

[0036] Step 23, determining T1 based on the first duration and the second duration, and reading the digital signal from the external memory according to frame delay based on T1.

[0037] The above steps 21 to 23 are the first level delay in the embodiment of the present application. Since the external memory is operated on a frame basis, all delay amounts are integer multiples of the frame data length, and the maximum delay amount is related to the size of the available space allocated to the channel.

[0038] In this regard, in a specific example, the time required to cache a frame of data can be calculated based on the processing sampling clock and data frame size. For example, the input digital signal sampling frequency is 50M, the sampling data I and Q bit widths are both 16 bits, and the input signal channel N=4, the output signal of each channel is framed separately, and each frame of data is written separately. Calculated based on the length of each frame being 1024 points, the data size of each frame is 4KB, and the time to complete receiving a frame of data is 20ns×1024=20480ns. At this time, the minimum delay of the first-level delay is 0ns, and the minimum step is 20480ns.

[0039] The framing signal is written to the external memory in a sequential and cyclic manner, and the position of the data frame to be read is determined according to the value of the first-level delay T1 and the position of the currently written frame, and the data is read into the processor, thereby achieving the first-level T1 delay of the data.

[0040] For example, if the data currently being written is the i-th frame, and the first-level delay T1 is 0, then the i-th frame data is read. If the data currently being written is the i-th frame, and the first-level delay T1 is 20480ns, then the i-1-th frame data is read. If the data currently being written is the i-th frame, and the first-level delay T1 is 40960ns, then the i-2-th frame data is read. The position of the data frame read will change with the change of T1, that is, the device can be flexibly controlled to achieve variable delay.

[0041] Furthermore, in a specific example of an embodiment of the present application, for the value of T1, if DDR3 is sampled as the memory, the capacity of DDR3 is 1GB, the number of channels is 4, the storage space corresponding to each channel is 256MB, the number of frames that can be stored in each channel is 65536 frames, and each channel can store T_total=65536×T_Frame=1.34s of data.

[0042] The address of the read data is calculated based on the delay required by the system and the write data address, and the integer frame delay of the data is completed. The minimum unit of delay is 1 frame T_Frame. Assuming that the processor requires the total signal delay to be completed to be T, the delay that can be completed in the processor is: T1 = T_Frame × floor (T / T_Frame), floor means rounding down.

[0043] In another optional implementation of the embodiment of the present application, the method of performing delayed output processing on the digital signal in the buffer based on T2 to obtain the delayed output digital signal involved in the above step 102 may further include:

[0044] Step 31, determining T2 based on a sampling clock of a processor, a first duration, and a second duration;

[0045] Step 32, performing delayed output processing on the digital signal in the buffer based on T2 to obtain a delayed output digital signal.

[0046] It should be noted that the above T2 is the second-level delay in the embodiment of the present application. The size of the second-level delay is related to the cache size allocated to each channel inside the processor, but it must be guaranteed to be greater than one frame of data storage space. The minimum delay amount of the coarse delay is related to the system working clock, and the delay step is 1 sampling working clock. Therefore, for the above steps 31 and 32, in a specific example, the dual-port BRAM in the FPGA is used to realize the delay of the signal in the second-level delay, and the input data is written to the A port of the BRAM. According to the delay requirements of the coarse delay module, the B port data read address of the BRAM is controlled to realize the delay of the input and output data. The processor working time is a sampling clock of 50M, and the delay resolution is 1 clock cycle, that is, 20ns, then T2 = floor ((T% T_Frame) / 20), % represents the remainder.

[0047] In an optional implementation of the embodiment of the present application, the method of performing delayed output processing on the delayed output digital signal again based on T3 and outputting the delayed processed digital signal involved in the above step 103 may further include:

[0048] Step 41, determining T3 based on the order of the delay filter of the processor, the first duration and the second duration;

[0049] Step 42, performing delayed output processing again on the delayed output digital signal based on T3, and outputting the delayed processed digital signal.

[0050] It should be noted that T3 is the third level of delay in the embodiment of the present application. The third level of delay is called precision delay. The maximum delay that can be achieved at this level is 1 sampling working clock. The delay step is related to the delay filter used. Therefore, for the above steps 41 and 42, in the specific example, the accuracy of the delay is related to the order of the delay filter. When the order of the delay filter is N, the resolution of the signal delay that can be achieved is 20 / N (ns). The order of the delay filter used in this device is 128, so the delay resolution that can be controlled is 20 / 128=156.25ps, then T3=floor((T%T_Frame) / 156.25).

[0051] Combine the following Figure 3 The specific implementation of the embodiment of the present application is explained and described. The specific implementation provides a multi-channel large-range signal delay processing method, and the steps of the method include:

[0052] Step 51, the device receives multiple digital signals and frames them;

[0053] Step 52, writing the framed multiplexed signals into an external memory in sequence;

[0054] In this regard, there are multiple input channels in parallel in the device, which can simultaneously receive multiple digital signals input by the front-end module. After the processor receives the multiple digital signals, it frames the digital signals. The sampling frequency of the input digital signal is 50M, the I and Q bit widths of the sampling data are both 16bit, the input signal channel N=4, and each channel output signal is framed separately. Calculated based on the length of each frame being 1024 points, the data size of each frame is 4KB, and the time to complete receiving a frame of data is T_Frame=20ns×1024=20480ns. After the data framing module receives a frame of data, it controls the write module to start a write memory operation.

[0055] Step 53, according to the set total delay T, read the digital signal from the external memory frame by frame to complete the first level delay T1 of the signal;

[0056] In this regard, in the memory, according to the number of channels N, the memory is divided into N storage spaces, and each channel data is continuously allocated an address space, such as Figure 4 The external memory address allocation diagram shown in the figure shows that after receiving the framed data, the channel data is cyclically written into the corresponding storage space, and the address of the write data is recorded. The size of the storage space is related to the number of channels and the capacity of the memory. In the embodiment of the present application, DDR3 is used as the memory, the DDR3 capacity is 1GB, the number of channels is 4, and the storage space corresponding to each channel is 256MB. The number of frames that can be stored in each channel is 65536 frames, and each channel can store T_total = 65536 × T_Frame = 1.34s of data.

[0057] At the data read control end, the address of the read data is calculated according to the delay required by the system and the write data address, and the integer frame delay of the data is completed. The minimum unit of delay is 1 frame T_Frame. Assuming that the system requires the signal delay to be T, the delay that can be completed in the processor is: T1 = T_Frame × floor (T / T_Frame), floor means rounding down.

[0058] Step 54, the read digital signal is framed and written into the internal cache of the processor, and the second level delay T2 of the signal is completed according to the total delay T;

[0059] In this regard, the read data is deframed and output to the coarse delay module, and the T2 delay is completed in the coarse delay module. In the delay device of the present invention, the coarse delay module uses the dual-port BRAM in the FPGA to realize the delay of the signal, writes the input data into the A port of the BRAM, and controls the data read address of the B port of the BRAM according to the delay requirement of the coarse delay module to realize the delay of the input and output data. The system working time is the sampling clock 50M, and the delay resolution is 1 clock cycle, that is, 20ns. The delay completed in the module is: T2 = floor ((T% T_Frame) / 20), then T3 = floor ((T% T_Frame) / 156.25).

[0060] Step 55, input the data output from the internal cache into the precision delay module, and complete the third level signal delay T3 according to the total delay amount T;

[0061] In this regard, the data output by the coarse delay is input into the precise delay, and the T3 delay is completed in the precise delay. The precise delay is implemented by sampling the delay filter. The accuracy of the delay is related to the order of the delay filter. When the order of the delay filter is N, the resolution of the signal delay can be 20 / N (ns). The device uses a delay filter with an order of 128, so the delay resolution can be controlled to be 20 / 128=156.25ps.

[0062] Step 56, output the precisely delayed signal.

[0063] Through the above steps 51 to 56, under the joint action of the delay amounts T1, T2, and T3, the total delay amount T is accurately completed, and the delay accuracy of the input signal is below 200ps, and the delay range is above 100ms, and the wide range of precision delay of the input multi-channel signals is completed. In other words, through the first stage of data delay by frame, the second stage of data delay by clock, and the third stage of delay filter to achieve fractional data delay, high-precision and wide range of signal delay of the received signal is achieved.

[0064] Corresponding to the above Figure 1 The present application also provides a signal delay processing device, such as Figure 5 As shown, the device comprises:

[0065] The first processing module 502 is used to read the digital signal from the external memory according to the frame delay based on T1, and cache the read digital data into the processor; wherein the external memory is used to store the digital signal received by the processor from the front-end module; T1 is an integer multiple of the frame data duration;

[0066] The second processing module 504 is used to perform delayed output processing on the digital signal in the cache based on T2 to obtain a digital signal after delayed output; wherein T2 is associated with the sampling clock of the processor;

[0067] The third processing module 506 is used to perform delayed output processing on the delayed output digital signal again based on T3, and output the delayed digital signal, wherein T3 is associated with the delay filter of the processor; and the sum of T1, T2 and T3 is equal to the preset total delay.

[0068] Optionally, the device in the embodiment of the present application may also include: a receiving module, used to receive a multi-channel navigation signal transmitted wirelessly before reading the digital signal from the external memory with frame delay based on T1, wherein the navigation signal is an analog signal; a fourth processing module, used to convert the multi-channel navigation signal into a multi-channel digital signal, and perform signal framing on the multi-channel digital signal; a fifth processing module, used to cache the digital signal after signal framing in the processor, and write the cached digital signal to the external memory after caching the full frame data.

[0069] Optionally, the first processing module in the embodiment of the present application may include: a reading unit, used to determine a first duration required to read a frame of data based on a sampling clock and a data frame size of a processor; a first processing unit, used to obtain a storage space of each channel of a memory, and determine a second duration of data stored in each channel based on the storage space and the first duration; a second processing unit, used to determine T1 based on the first duration and the second duration, and read a digital signal from an external memory with a frame delay based on T1.

[0070] Optionally, the second processing module in the embodiment of the present application may further include: a first determination unit, used to determine T2 based on the sampling clock of the processor, the first duration and the second duration; a third processing unit, used to perform delayed output processing on the digital signal in the cache based on T2 to obtain a digital signal after delayed output.

[0071] Optionally, the third processing module in the embodiment of the present application may further include: a second determination unit, used to determine T3 based on the order of the delay filter of the processor, the first time length and the second time length; a fourth processing unit, used to perform delayed output processing on the digital signal after delayed output again based on T3, and output the digital signal after delayed processing.

[0072] like Figure 6 As shown, an embodiment of the present application provides an electronic device, including a processor 611, a communication interface 612, a memory 613 and a communication bus 614, wherein the processor 611, the communication interface 612, and the memory 613 communicate with each other through the communication bus 614.

[0073] Memory 613, used for storing computer programs;

[0074] In one embodiment of the present application, the processor 611 is used to execute the program stored in the memory 613 to implement the signal delay processing method provided by any of the aforementioned method embodiments, and its role is similar and will not be repeated here.

[0075] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the signal delay processing method provided in any of the aforementioned method embodiments are implemented.

[0076] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0077] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0078] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0079] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for processing signal delay, characterized in that: Applied to a processor, the method comprises: Based on T1, a digital signal is read from an external memory according to a frame delay, and the read digital data is cached inside the processor; wherein the external memory is used to store the digital signal received by the processor from the front-end module; and T1 is an integer multiple of the frame data duration; Performing delayed output processing on the digital signal in the cache based on T2 to obtain a digital signal after delayed output; wherein T2 is associated with a sampling clock of the processor; Based on T3, the digital signal after delayed output is subjected to delayed output processing again, and the digital signal after delayed processing is output, wherein T3 is associated with the delay filter of the processor; and the sum of T1, T2 and T3 is equal to the preset total delay; Among them, reading the digital signal with frame delay from the external memory based on T1 includes: determining a first time length required for reading a frame of data based on the sampling clock and data frame size of the processor; acquiring the storage space of each channel of the memory, and determining a second time length of the data stored in each channel based on the storage space and the first time length; determining T1 based on the first time length and the second time length, and reading the digital signal with frame delay from the external memory based on T1.

2. The method according to claim 1, characterized in that: Before reading the digital signal from the external memory according to the frame delay based on T1, the method further includes: receiving a multi-channel navigation signal transmitted wirelessly, wherein the navigation signal is an analog signal; Converting the multi-channel navigation signals into multi-channel digital signals, and performing signal framing on the multi-channel digital signals; The digital signal after signal framing is cached in the processor, and the cached digital signal is written into the external memory after a full frame of data is cached.

3. The method according to claim 1, characterized in that Based on T2, the digital signal in the cache is subjected to delayed output processing, and the digital signal after delayed output is obtained includes: Determine T2 based on a sampling clock of the processor, the first duration, and the second duration; Based on T2, delayed output processing is performed on the digital signal in the cache to obtain a digital signal after delayed output.

4. The method according to claim 1, characterized in that Based on T3, the delayed output digital signal is subjected to delayed output processing again, and the output delayed digital signal includes: Determine T3 based on the order of the delay filter of the processor, the first duration, and the second duration; Based on T3, the delayed output digital signal is subjected to delayed output processing again, and the delayed processed digital signal is output.

5. A signal delay processing device, characterized in that: The device comprises: A first processing module is used to read digital signals from an external memory according to frame delay based on T1, and cache the read digital data into the processor; wherein the external memory is used to store the digital signals received by the processor from the front-end module; and T1 is an integer multiple of the frame data duration; A second processing module, configured to perform delayed output processing on the digital signal in the cache based on T2 to obtain a digital signal after delayed output; wherein T2 is associated with a sampling clock of the processor; A third processing module is used to perform delayed output processing on the delayed output digital signal again based on T3, and output the delayed digital signal, wherein T3 is associated with the delay filter of the processor; and the sum of T1, T2 and T3 is equal to the preset total delay; Among them, the first processing module includes: a reading unit, used to determine the first duration required to read a frame of data based on the sampling clock and data frame size of the processor; a first processing unit, used to obtain the storage space of each channel of the memory, and determine the second duration of the data stored in each channel based on the storage space and the first duration; a second processing unit, used to determine T1 based on the first duration and the second duration, and read the digital signal from the external memory with frame delay based on T1.

6. The device according to claim 5, characterized in that The device also includes: A receiving module, used for receiving a wirelessly transmitted multi-channel navigation signal before reading a digital signal from an external memory according to a frame delay based on T1, wherein the navigation signal is an analog signal; A fourth processing module, used for converting the multi-channel navigation signals into multi-channel digital signals, and performing signal framing on the multi-channel digital signals; The fifth processing module is used to cache the digital signal after signal framing in the processor, and write the cached digital signal into the external memory after caching a full frame of data.

7. An electronic device comprising: at least one communication interface; at least one bus connected to the at least one communication interface; at least one processor coupled to the at least one bus; At least one memory connected to the at least one bus, wherein the processor is configured to execute the signal delay processing method described in any one of claims 1 to 4 of the present application.

8. A computer storage medium storing computer executable instructions, wherein the computer executable instructions are used to execute the signal delay processing method described in any one of claims 1 to 4 of the present application.

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