Physics accelerator and physics acceleration system

Abstract

The present application provides a physical accelerator and a physical acceleration system, which includes: multiple hardware acceleration cards; wherein the hardware acceleration cards are synchronized through inter-board synchronization signals; any hardware acceleration card includes a master node chip, at least one slave node chip and at least one external high-speed interface; the chips are interconnected through at least one interface and synchronized through internal synchronization control signals; the physical accelerator is interconnected with the digital space through an external high-speed interface and an external synchronization control signal; the digital space performs synchronization control between the digital space and the hardware acceleration card through an external synchronization control signal. The physical accelerator provided by the present application can realize the system synchronization between the digital space and the physical device during the data acquisition and processing of large-scale systems in the field of digital twins, and synchronize the digital end and the physical end in the system at the microsecond level while ensuring the accuracy and authenticity of the data. In addition, the universalization of the interface can improve the universality.

Description

Technical Field

[0001] The present application relates to the field of simulation technology, and in particular to a physical accelerator and a physical acceleration system. Background Art

[0002] As a cutting-edge technology, digital twins are playing an increasingly important role in today's wave of digital transformation. They bridge the physical and digital worlds, simulating the operating status of physical systems in real time. Through sensors and other devices, they synchronize information with the real world, enabling accurate monitoring of real-world systems. This enables ongoing optimization and adjustments of real-world systems, thereby improving production efficiency and resource utilization. However, existing technologies have the following shortcomings and bottlenecks.

[0003] 1. Data collection and processing

[0004] Digital twins require large amounts of data to support simulation and prediction, but data collection and processing remain a challenge, especially for complex systems, where data acquisition and processing can be cumbersome.

[0005] 2. Accuracy and authenticity

[0006] The accuracy and authenticity of digital twins directly impact their practical value. When building a digital twin model, it is necessary to restore the characteristics of the real system as closely as possible to ensure the accuracy of the simulation results.

[0007] 3. Simulation speed and real-time performance

[0008] Digital space simulation is limited by factors such as the digital system communication method and the complexity of simulation calculations, resulting in slow simulation speed. There is an urgent need to improve the simulation speed. Summary of the Invention

[0009] In order to solve one of the above technical defects, the present application provides a physical accelerator and a physical acceleration system.

[0010] In a first aspect, the present application provides a physical accelerator, the physical accelerator comprising: a plurality of hardware acceleration cards;

[0011] Among them, multiple hardware accelerator cards are synchronized through inter-board synchronization signals;

[0012] Any hardware accelerator card includes a master node chip, at least one slave node chip and at least one external high-speed interface;

[0013] The master and slave node chips of any hardware accelerator card are interconnected via at least one input / output interface and / or at least one internal high-speed serial interface, and synchronization between the master and slave node chips is achieved via an internal synchronization control signal line.

[0014] The physical accelerator is interconnected with the digital space through an external high-speed interface and an external synchronous control signal;

[0015] The digital space performs synchronization control between the digital space and the hardware acceleration card through external synchronization control signals.

[0016] Optionally, the master node chip of any hardware accelerator card is used for bus decoding, input and output control, and high-speed serial interface control; the slave node chip of any board card is used to run user-specific functional logic;

[0017] The chips on any board exchange data through the internal high-speed serial interface.

[0018] Optionally, a universal interface is reserved on the slave node chip of any hardware accelerator card;

[0019] General interface, used to obtain user-specific functional logic;

[0020] The master node chip of any hardware accelerator card is used to interact with the digital space through an external high-speed interface to analyze the results, and then re-analyze the results from the digital space and send them to the corresponding slave node chip; the analysis results are the result of the digital space analyzing the data sent by the external simulation software;

[0021] The slave node chip of any hardware acceleration card is used to run user-specific functional logic, accelerate the re-analysis results sent by the master node chip, and then feed back the processing results to the digital space, so that the digital space can feed back the processing results to the external simulation software.

[0022] Optionally, the external high-speed interface is a high-speed serial computer expansion bus standard interface; the external high-speed interface has a maximum rate of 5GT / s and supports high-throughput data interaction of multiple hardware acceleration cards;

[0023] The internal high-speed serial interface is a G-bit transceiver interface and / or an interconnection system interface based on data packet switching; the minimum rate of the internal high-speed serial interface is 5GT / s;

[0024] The input and output interfaces include one or more of the following: external memory interface, flash memory interface;

[0025] The synchronization error between the hardware acceleration cards is less than 10 nanoseconds.

[0026] Optionally, the digital space includes: digital space control and parsing software, a synchronous communication component, and a communication interface component;

[0027] Digital space, used for interface display, data interaction, data display, data storage, data playback, and data synchronization;

[0028] Among them, the interface display is implemented based on the DuiLib library, and the user interface and processing logic are separated;

[0029] Data interaction, including data interaction with external simulation software and data interaction with the physical accelerator; wherein, data interaction with external simulation software includes: data acquisition and analysis by the external simulation software, obtaining analysis results, and feeding back the processing results of the physical accelerator to the external simulation software; data interaction with the physical accelerator includes: sending the analysis results to the physical accelerator and receiving the processing results fed back by the physical accelerator;

[0030] Data display, including data display of external simulation software and display of processing results of physical accelerator feedback;

[0031] Data storage, including classified storage of data from external simulation software and classified storage of processing results fed back by physical accelerators;

[0032] Data playback, including retrieval and playback of stored data;

[0033] Data synchronization, including data synchronization between digital space and physical accelerator, is achieved through synchronization control signals.

[0034] In a second aspect of the present application, a physical acceleration system is provided, the system comprising: external simulation software, a digital space, and a physical accelerator;

[0035] The physical accelerator is the physical accelerator shown in the first aspect above.

[0036] Optionally, the digital space includes: digital space control and analysis software, a synchronous communication component and a communication interface component.

[0037] Optionally, the external simulation software is used to send data to the digital space control analysis software via the communication interface component and the synchronous communication component;

[0038] Digital space control analysis software, used to analyze the data sent by the external simulation software and send the analysis results to the physical accelerator through the communication interface component;

[0039] The physical accelerator is used to perform acceleration processing based on the analysis results and then feed back the processing results to the external simulation software through the communication interface component and the synchronous communication component.

[0040] Optionally, the analysis result includes the address, data, and signal of the external simulation software.

[0041] Optionally, the synchronous communication component is further used to synchronize signals and data inside and outside the system when the physical accelerator performs acceleration processing based on the analysis results.

[0042] The present application provides a physical accelerator and a physical acceleration system, which includes: multiple hardware acceleration cards; wherein the multiple hardware acceleration cards are synchronized through inter-board synchronization signals; any hardware acceleration card includes a master node chip, at least one slave node chip and at least one external high-speed interface; the master and slave node chips of any hardware acceleration card are interconnected through at least one input and output interface and / or at least one internal high-speed serial interface, and the master and slave node chips of the hardware acceleration card are synchronized through the internal synchronization control signal line; the physical accelerator is interconnected with the digital space through the external high-speed interface and the external synchronization control signal; the digital space performs synchronization control between the digital space and the hardware acceleration card through the external synchronization control signal. The physical accelerator provided by the present application can realize the system synchronization between the digital space and the physical device in the data acquisition and processing process of large-scale systems in the field of digital twins, and synchronize the digital end and the physical end in the system at the microsecond level while ensuring the accuracy and authenticity of the data. In addition, the universalization of the interface can improve the universality. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0044] Figure 1 A schematic structural diagram of a physical accelerator provided in an embodiment of the present application;

[0045] Figure 2 A schematic structural diagram of another physical accelerator provided in an embodiment of the present application;

[0046] Figure 3 A block diagram of the data space function module provided in an embodiment of the present application;

[0047] Figure 4 A case diagram of a physical acceleration system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the technical solutions and advantages of the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, and are not an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless they conflict.

[0049] During the development of this application, the inventors discovered that digital twins, as a cutting-edge technology, are playing an increasingly important role in today's wave of digital transformation. They serve as a bridge that seamlessly connects the physical and digital worlds, enabling real-time simulation of the operating status of physical systems. Through sensors and other devices, they synchronize with the real world in real time, enabling accurate monitoring of real-world systems. This enables optimization and adjustment of real-world systems during operation, thereby improving production efficiency and resource utilization. However, existing technologies have the following shortcomings and bottlenecks: 1) Digital twins require large amounts of data to support simulation and prediction, but data collection and processing remain a challenge. Data acquisition and processing can be particularly cumbersome, especially for complex systems. 2) The accuracy and authenticity of digital twins directly impact their practical value. When building digital twin models, it is necessary to replicate the characteristics of the real system as closely as possible to ensure the accuracy of simulation results. 3) Simulation speed and real-time performance. Digital space simulation is limited by factors such as digital system communication methods and the complexity of simulation computations, resulting in slow simulation speeds. Improving simulation speed is urgently needed.

[0050] In response to the above problems, a physical accelerator and a physical acceleration system are provided in an embodiment of the present application, and the physical accelerator includes: multiple hardware acceleration cards; wherein the multiple hardware acceleration cards are synchronized through inter-board synchronization signals; any hardware acceleration card includes a master node chip, at least one slave node chip and at least one external high-speed interface; the master and slave node chips of any hardware acceleration card are interconnected through at least one input and output interface and / or at least one internal high-speed serial interface, and the master and slave node chips of the hardware acceleration card are synchronized through the internal synchronization control signal line; the physical accelerator is interconnected with the digital space through the external high-speed interface and the external synchronization control signal; the digital space performs synchronization control between the digital space and the hardware acceleration card through the external synchronization control signal. The physical accelerator provided in this application can realize the system synchronization between the digital space and the physical device in the data acquisition and processing process of large-scale systems in the field of digital twins, and synchronize the digital end and the physical end in the system at the microsecond level while ensuring the accuracy and authenticity of the data. In addition, the universalization of the interface can improve the universality.

[0051] See also Figure 1 This embodiment provides a physical accelerator, which includes: multiple hardware acceleration cards.

[0052] Among them, any hardware acceleration card includes a master node chip, at least one slave node chip and at least one external high-speed interface.

[0053] The master and slave node chips of any hardware accelerator card are interconnected through at least one input / output (IO) interface and / or at least one internal high-speed serial interface, and synchronization between the master and slave node chips is achieved through the internal synchronization control signal line.

[0054] The input and output (IO) interfaces include, but are not limited to, switch interfaces and flash interfaces.

[0055] The internal high-speed serial interface is a Gigabyte Transceiver (GT) transceiver interface and / or a RapidIO interface. The minimum internal high-speed serial interface rate is 5 GT / s and can be used for AXI (Advanced eXtensible Interface) data transmission.

[0056] The physical accelerator is interconnected with the digital space through an external high-speed interface and an external synchronous control signal.

[0057] The digital space performs synchronization control between the digital space and the hardware acceleration card through external synchronization control signals.

[0058] in, Figure 1 Only one slave node chip, one external high-speed interface, one input / output interface, and one internal high-speed serial interface are shown. In actual application, there may be multiple slave node chips, multiple external high-speed interfaces, multiple input / output interfaces, and multiple internal high-speed serial interfaces.

[0059] The master node chip of any hardware accelerator card is used for bus decoding, input and output control, and high-speed serial interface control, while the slave node chip of any board is used to run user-specific functional logic.

[0060] The synchronization control signal between the digital space and the hardware acceleration card only exists between the digital space and one of the designated hardware acceleration cards ( Figure 1 and Figure 2 Taking the first hardware accelerator card as the designated hardware accelerator card as an example, in actual application, any hardware accelerator card may be designated), and the direction is unidirectional, sent from the digital space and received by the first hardware accelerator card.

[0061] Thereafter, the synchronization signal is distributed backward by the master node in one of the designated hardware acceleration cards to the master nodes of other hardware acceleration cards and the slave node of the first hardware acceleration card itself.

[0062] Figure 2 It shows the physical accelerator structure for internal high-speed serial interfaces such as GTX interfaces.

[0063] The chips on any board exchange data through the internal high-speed serial interface.

[0064] Among them, a universal interface is reserved in the slave node chip of any hardware acceleration card.

[0065] A general interface for obtaining user-specific functional logic.

[0066] The master node chip of any hardware accelerator card is used to exchange analysis results with the digital space through an external high-speed interface, re-analyzing the analysis results from the digital space and sending them to the corresponding slave node chip. The analysis results are the result of the digital space parsing the data sent by the external simulation software.

[0067] The slave node chip of any hardware acceleration card is used to run user-specific functional logic, accelerate the re-analysis results sent by the master node chip, and then feed back the processing results to the digital space, so that the digital space can feed back the processing results to the external simulation software.

[0068] The external high-speed interface is a Peripheral Component Interconnect Express (PCIE) interface with a maximum speed of 5 Gigabit per second (GT / s), supporting high-throughput data exchange between multiple hardware accelerator cards.

[0069] The input and output interfaces include one or more of the following: external memory interface (EMIF), flash memory interface.

[0070] The synchronization error between the hardware accelerator cards is less than 10ns (nanoseconds).

[0071] In addition, the digital space includes: digital space control and analysis software, synchronous communication components and communication interface components.

[0072] Digital space is used for interface display, data interaction, data display, data storage, data playback, and data synchronization. Figure 3 The principle block diagram of the digital space functional module is shown. The digital space is used to integrate the display and distribution of data sent by the front-stage data acquisition module or various circuit simulation software and the back-stage physical accelerator. The following are the modules of the digital space.

[0073] The interface display is implemented based on the DuiLib library, and the user interface and processing logic are separated. For example, the interface display uses the DuiLib library for drawing and display, which can completely separate the user interface and processing logic, and can run on all systems from Windows XP to Windows 10.

[0074] Data interaction includes data interaction with external simulation software and data interaction with physical accelerators. Specifically, data interaction with external simulation software includes: data acquisition and analysis by external simulation software, obtaining analysis results, and feeding back the processing results of the physical accelerator to the external simulation software. Data interaction with the physical accelerator includes: sending the analysis results to the physical accelerator and receiving the processing results fed back by the physical accelerator. Therefore, through data interaction, the storage, analysis, and display of various upper-level simulation and computing software data can be completed, and support can be provided for passing data to the various boards in the hardware accelerator cluster for system simulation. At the same time, it also completes the function of monitoring, displaying, and packaging the data returned by each board in the hardware accelerator cluster and returning it to the upper-level simulation software.

[0075] Data display includes data from external simulation software and processing results from the physical accelerator. This allows for real-time visualization of the interaction between the hardware accelerator cluster and upper-layer software, allowing for data interpretation. Key parameters in the test data can be highlighted, and various display formats are supported, including data lists, curves, bar charts, and pie charts.

[0076] Data storage includes categorized storage of data from external simulation software and categorized storage of processing results from the physical accelerator. Therefore, data storage allows for categorized storage of data exchanged between the hardware accelerator cluster and upper-layer software. Data is stored in a standardized format based on the system simulation step size, making it easy for users to view. The data storage function operates independently and does not affect other software functions.

[0077] Data playback, including the retrieval and playback of stored data. Data playback allows you to select locally stored data sources and supports data retrieval and data playback.

[0078] Data synchronization, including between the digital space and the physical accelerator, is achieved through external synchronization control signals. The digital space and the physical accelerator can achieve data synchronization for system simulation through independently developed synchronization communication components.

[0079] The physical accelerator provided in this embodiment connects to a virtual domain, embedded with digital space analysis software. It can connect to multi-terminal simulation software, exchange data via synchronous communication components, and provide an external communication interface. The physical accelerator provided in this embodiment is a physical physical system that primarily provides data computing power for the digital domain, enabling hardware acceleration. A high-speed bus bridges communication between the two, enabling data exchange from the virtual domain to the physical domain.

[0080] See also Figure 2The physics accelerator provided in this embodiment is composed of multiple hardware accelerator cards. Each accelerator card has at least two processors, which are interconnected via input / output (IO) interfaces and internal high-speed serial interfaces. The cards also have multiple external high-speed interfaces. The physics accelerator is primarily used for simulation acceleration, exchanging data with the digital space via high-speed interfaces.

[0081] The hardware of the physical accelerator provided in this embodiment is configured with multiple hardware acceleration cards; it supports high-speed parallel buses, multiple high-speed serial interfaces, and multiple external electrical interfaces; and it supports multiple high-speed serial ports and multiple ordinary IO interfaces between dual-node chips.

[0082] Regarding the software / driver aspects of the physical accelerator provided in this embodiment, each board in the hardware accelerator cluster has a master node chip and a slave node chip. The master node is used to exchange data with the digital space, while the slave node runs user-specific logic function programs. The master node parses and distributes data packets transmitted from the digital space to the slave nodes. After running the user logic in the slave node, the data is returned to the master node, and then back to the software digital space. In this way, the master node of the digital space and the hardware accelerator cluster board acts as a bridge for data exchange simulation acceleration between the digital space and the physical accelerator. The slave nodes of the hardware accelerator card leave a common interface for the user logic to use for system function simulation.

[0083] Regarding the interface of the physical accelerator provided in this embodiment, the external high-speed interface between the digital space and the physical accelerator utilizes a high-speed parallel bus PCIE interface, achieving an interface rate of 5GT / s, capable of simultaneously supporting high-throughput data exchange between multiple accelerator cards in the physical accelerator. Synchronous control lines synchronize the digital space and the various boards in the physical accelerator. The internal high-speed serial interface utilizes a Gigabyte Transceiver (GT) transceiver interface and / or a RAPIDIO interface based on data packet switching. The minimum internal high-speed serial interface rate is 5GT / s. Synchronous control signal lines between boards are used to synchronize all boards in the physical accelerator, with a synchronization error of less than 10ns. Multiple internal IO ports provide data exchange between processors, enabling real-time simulation of various data interfaces.

[0084] The physical accelerator provided in this embodiment can form a large data envelope from the data collected and processed in the system through the digital space. At the same time, the interface display, data storage, synchronization, playback and other functions of the digital space can solve the cumbersome problem of data acquisition and processing in complex data twin systems. In addition, the digital space of the physical accelerator provided in this embodiment and the single-board interface rate of the physical accelerator can reach 5GT / s. Connecting the digital end and the physical end through a high-speed parallel bus interface can greatly improve the accuracy and real-time performance of the digital twin system data. The overall design of the physical accelerator provided in this embodiment adopts a universal digital space envelope and data interaction mechanism, which can save technical and personnel investment for subsequent development and application.

[0085] The physical accelerator provided by this embodiment can increase the system simulation rate by 400-800 times; it can achieve system synchronization between digital space and physical devices, and can synchronize the digital end and physical end within the system at the microsecond level; it can monitor the real data of each node in the system in real time, and restore the characteristics of the real system as much as possible to ensure the accuracy of the simulation results; it can quickly and accurately locate problems in complex system simulations, facilitating early product problem troubleshooting.

[0086] The present embodiment provides a physical accelerator, which includes: multiple hardware acceleration cards; wherein the multiple hardware acceleration cards are synchronized through inter-board synchronization signals; any hardware acceleration card includes a master node chip, at least one slave node chip and at least one external high-speed interface; the master and slave node chips of any hardware acceleration card are interconnected through at least one input and output interface and / or at least one internal high-speed serial interface, and the master and slave node chips of the hardware acceleration card are synchronized through the internal synchronization control signal line; the physical accelerator is interconnected with the digital space through the external high-speed interface and the external synchronization control signal; the digital space performs synchronization control between the digital space and the hardware acceleration card through the external synchronization control signal. The physical accelerator provided in this embodiment can realize the system synchronization of the digital space and the physical device in the data acquisition and processing process of large-scale systems in the field of digital twins, and synchronize the digital end and the physical end in the system at the microsecond level while ensuring the accuracy and authenticity of the data. In addition, the universalization of the interface can improve the universality.

[0087] based on Figure 1 The physical accelerator shown in this embodiment provides a physical acceleration system, which includes: external simulation software, digital space and a physical accelerator.

[0088] 1. External simulation software

[0089] The external simulation software is used to send data to the digital space control analysis software through the communication interface component and the synchronous communication component.

[0090] Among them, there can be multiple external simulation software.

[0091] 2. Digital Space

[0092] The digital space includes: digital space control and analysis software, synchronous communication components and communication interface components.

[0093] Digital space control analysis software is used to analyze the data sent by external simulation software and send the analysis results to the physical accelerator through the communication interface component.

[0094] Among them, the synchronous communication component is also used to control the synchronization of signals and data outside, inside and between boards of the system when the physical accelerator performs acceleration processing based on the analysis results.

[0095] Figure 3 The block diagram of the Digital Space functional module shows the functional principles. It consists of six main components: interface display, data interaction, data display, data storage, data playback, and data synchronization. The Digital Space integrates the display and distribution of data sent from the preceding data acquisition module or various circuit simulation software, as well as the subsequent physical accelerator. The following is an overview of each module in the Digital Space.

[0096] The interface display is implemented based on the DuiLib library, and the user interface and processing logic are separated. For example, the interface display uses the DuiLib library for drawing and display, which can completely separate the user interface and processing logic, and can run on all systems from Windows XP to Windows 10.

[0097] Data interaction includes data interaction with external simulation software and data interaction with physical accelerators. Specifically, data interaction with external simulation software includes: data acquisition and analysis by external simulation software, obtaining analysis results, and feeding back the processing results of the physical accelerator to the external simulation software. Data interaction with the physical accelerator includes: sending the analysis results to the physical accelerator and receiving the processing results fed back by the physical accelerator. Therefore, through data interaction, the storage, analysis, and display of various upper-level simulation and computing software data can be completed, and support can be provided for passing data to the various boards in the hardware accelerator cluster for system simulation. At the same time, it also completes the function of monitoring, displaying, and packaging the data returned by each board in the hardware accelerator cluster and returning it to the upper-level simulation software.

[0098] Data display includes data from external simulation software and processing results from the physical accelerator. This allows for real-time visualization of the interaction between the hardware accelerator cluster and upper-layer software, allowing for data interpretation. Key parameters in the test data can be highlighted, and various display formats are supported, including data lists, curves, bar charts, and pie charts.

[0099] Data storage includes categorized storage of data from external simulation software and categorized storage of processing results from the physical accelerator. Therefore, data storage allows for categorized storage of data exchanged between the hardware accelerator cluster and upper-layer software. Data is stored in a standardized format based on the system simulation step size, making it easy for users to view. The data storage function operates independently and does not affect other software functions.

[0100] Data playback, including the retrieval and playback of stored data. Data playback allows you to select locally stored data sources and supports data retrieval and data playback.

[0101] Data synchronization, including between the digital space and the physical accelerator, is achieved through external synchronization control signals. Through data synchronization, the digital space and the physical accelerator can achieve data synchronization for system simulation through independently developed synchronization communication components.

[0102] 3. Physical Accelerator

[0103] Physical accelerator is Figure 1 The physical accelerator shown.

[0104] The physical accelerator is used to perform acceleration processing based on the analysis results and then feed back the processing results to the external simulation software through the communication interface component and the synchronous communication component.

[0105] The analysis results include the address, data, and signals of the external simulation software.

[0106] See also Figure 2 The physics accelerator provided in this embodiment is composed of multiple hardware accelerator cards. Each accelerator card has at least two processors, which are interconnected via input / output (IO) interfaces and internal high-speed serial interfaces. The cards also have multiple external high-speed interfaces. The physics accelerator is primarily used for simulation acceleration, exchanging data with the digital space via high-speed interfaces.

[0107] The hardware of the physical accelerator provided in this embodiment is configured with multiple hardware acceleration cards; it supports high-speed parallel buses, multiple high-speed serial interfaces, and multiple external electrical interfaces; and it supports multiple high-speed serial ports and multiple ordinary IO interfaces between dual-node chips.

[0108] Regarding the software / driver aspects of the physical accelerator provided in this embodiment, each board in the hardware accelerator cluster has a master node chip and a slave node chip. The master node is used to exchange data with the digital space, while the slave node runs user-specific logic function programs. The master node parses and distributes data packets transmitted from the digital space to the slave nodes. After running the user logic in the slave node, the data is returned to the master node, and then back to the software digital space. In this way, the master node of the digital space and the hardware accelerator cluster board acts as a bridge for data exchange simulation acceleration between the digital space and the physical accelerator. The slave nodes of the hardware accelerator card leave a common interface for the user logic to use for system function simulation.

[0109] Regarding the interface of the physical accelerator provided in this embodiment, since the external high-speed interface between the digital space and the physical accelerator uses a high-speed parallel bus PCIE interface, the interface rate can reach 5GT / s, which can simultaneously support high-throughput data exchange between multiple accelerator cards in the physical accelerator; the external synchronization control signal is used for synchronous control of the digital space and each board of the physical accelerator. The internal high-speed serial interface is a Gigabyte Transceiver (GT) transceiver interface and / or a RAPIDIO interface based on data packet exchange. The minimum rate of the internal high-speed serial interface is 5GT / s; the synchronization control signal line between the boards is used to synchronize the operation of all boards in the physical accelerator, with a synchronization error of less than 10ns. The board has multiple IO ports for data exchange between processors, which can be used to simulate various data interfaces in real time.

[0110] The physical acceleration system provided in this embodiment can form a large data envelope from the data collected and processed in the system through the digital space. At the same time, the interface display, data storage, synchronization, playback and other functions of the digital space can solve the cumbersome problem of data acquisition and processing in complex data twin systems. In addition, the digital space of the physical accelerator provided in this embodiment and the single-board interface rate of the physical accelerator can reach 5GT / s. Connecting the digital end and the physical end through a high-speed parallel bus interface can greatly improve the accuracy and real-time performance of the digital twin system data. The overall design of the physical accelerator provided in this embodiment adopts a universal digital space envelope and data interaction mechanism, which can save technical and personnel investment for subsequent development and application.

[0111] The physical system provided by this embodiment can increase the simulation rate by 400-800 times; it can achieve system synchronization between digital space and physical equipment, and can synchronize the digital end and the physical end within the system at the microsecond level; it can monitor the real data of each node in the system in real time, and restore the characteristics of the real system as much as possible to ensure the accuracy of the simulation results; it can quickly and accurately locate problems in complex system simulations, facilitating early product problem troubleshooting.

[0112] The digital space in the physics acceleration system provided in this embodiment is a virtual domain, embedded with digital space analysis software. It can connect to multi-terminal simulation software, exchange data through synchronous communication components, and provide an external communication interface. The physical accelerator in the physics acceleration system provided in this embodiment is a physical system that primarily provides data computing power for the digital space, enabling hardware acceleration. A high-speed bus bridges communication between the two, enabling data exchange from the virtual domain to the physical domain.

[0113] Figure 4 The example illustrates a physics acceleration system provided by this embodiment. The system consists of multiple external simulation software programs, a digital space (including a synchronous communication component and digital space control and analysis software), and a physics accelerator. The external simulation software programs and the digital space control and analysis software transmit data via the synchronous communication component. The digital space interprets the addresses, data, and signals from the external simulation software programs and sends them to a cluster of hardware accelerator cards according to the protocol. After the hardware accelerator cards perform data calculations, they return instructions and data via the synchronous communication component. The synchronous communication component synchronizes internal and external signals and data at each calculation step, enabling synchronized simulation across the entire hardware and software system.

[0114] The physics acceleration system provided in this embodiment is applicable to simulation technologies that improve simulation efficiency. By integrating computer simulation loops into physical objects, the simulations are closer to reality while leveraging hardware acceleration to achieve orders of magnitude improvements in system simulation speed. The physics acceleration system provided in this embodiment is a digital mirror of a physical entity or process. It is a simulation model built using digital twin technology that can be updated in real time and boasts exponentially faster computational speeds. It is used to support decision-making across various activities in the physical product lifecycle.

[0115] The physical acceleration system provided in this embodiment can achieve system synchronization between digital space and physical devices during data collection and processing of large-scale systems in the field of digital twins, and synchronize the digital end and physical end within the system at the microsecond level while ensuring the accuracy and authenticity of the data. In addition, the universalization of the interface can improve versatility.

[0116] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of a fully hardware embodiment, a fully software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present application may be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0117] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0118] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0119] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0120] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0121] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A physical accelerator, characterized in that: The physical accelerator includes: a plurality of hardware acceleration cards; Among them, multiple hardware accelerator cards are synchronized through inter-board synchronization signals; Any hardware accelerator card includes a master node chip, at least one slave node chip and at least one external high-speed interface; The master and slave node chips of any hardware accelerator card are interconnected via at least one input / output interface and / or at least one internal high-speed serial interface, and synchronization between the master and slave node chips is achieved via an internal synchronization control signal line. The physical accelerator is interconnected with the digital space via an external high-speed interface and an external synchronous control signal; The digital space performs synchronization control between the digital space and the hardware acceleration card through the external synchronization control signal; The digital space includes: digital space control and analysis software, synchronous communication components and communication interface components; The digital space is used for interface display, data interaction, data display, data storage, data playback, and data synchronization; The interface display is implemented based on the DuiLib library, and the user interface and processing logic are separated; The data interaction includes data interaction with external simulation software and data interaction with the physical accelerator; wherein the data interaction with the external simulation software includes: data acquisition and analysis by the external simulation software, obtaining analysis results, and feeding back the processing results of the physical accelerator to the external simulation software; the data interaction with the physical accelerator includes: sending the analysis results to the physical accelerator and receiving the processing results fed back by the physical accelerator; The data display includes the display of data from the external simulation software and the display of the processing results fed back by the physical accelerator; The data storage includes classified storage of data from external simulation software and classified storage of processing results fed back by the physical accelerator; The data playback includes retrieval and playback of stored data; The data synchronization includes data synchronization between the digital space and the physical accelerator through a synchronization control signal.

2. The physical accelerator according to claim 1, characterized in that: The master node chip of any hardware accelerator card is used for bus decoding, input and output control, and high-speed serial interface control; the slave node chip of any hardware accelerator card is used to run user-specific functional logic; The chips of any of the hardware acceleration cards exchange data via an internal high-speed serial interface.

3. The physical accelerator according to claim 1, characterized in that: A universal interface is reserved in the slave node chip of any hardware accelerator card; The general interface is used to obtain user-specific functional logic; The master node chip of any of the hardware accelerator cards is configured to interact with the digital space through an external high-speed interface to perform analysis results, and to further analyze the analysis results from the digital space and send them to the corresponding slave node chip; wherein the analysis results are the result of the digital space analyzing the data sent by the external simulation software; The slave node chip of any hardware acceleration card is used to run user-specific functional logic, accelerate the processing of the re-analysis results sent by the master node chip, and then feed back the processing results to the digital space, so that the digital space feeds back the processing results to the external simulation software.

4. The physical accelerator according to claim 1, characterized in that: The external high-speed interface is a high-speed serial computer expansion bus standard interface; the maximum speed of the external high-speed interface is 5GT / s, and it supports high-throughput data interaction of multiple hardware acceleration cards at the same time; The internal high-speed serial interface is a G-bit transceiver interface and / or an interconnection system interface based on data packet switching; the minimum rate of the internal high-speed serial interface is 5GT / s; The input and output interfaces include one or more of the following: an external memory interface, a flash memory interface; The synchronization error between the hardware acceleration cards is less than 10 nanoseconds.

5. A physical acceleration system, characterized in that: The system includes: external simulation software, digital space and physical accelerator; Wherein, the physical accelerator is the physical accelerator shown in any one of claims 1 to 4.

6. The system according to claim 5, characterized in that The digital space includes: digital space control and analysis software, synchronous communication components and communication interface components.

7. The system according to claim 6, characterized in that The external simulation software is used to send data to the digital space control analysis software through the communication interface component and the synchronous communication component; The digital space control analysis software is used to analyze the data sent by the external simulation software and send the analysis results to the physical accelerator through the communication interface component; The physical accelerator is used to perform acceleration processing based on the analysis result and then feed back the processing result to the external simulation software through the communication interface component and the synchronous communication component.

8. The system according to claim 7, characterized in that The analysis results include the address, data, and signals of the external simulation software.

9. The system according to claim 7, wherein: The synchronous communication component is further used to control the synchronization of signals and data inside and outside the system when the physical accelerator performs acceleration processing based on the analysis result.

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