FPGA lookup table fault identification method, device, equipment and storage medium

Abstract

The present invention relates to the field of FPGA technology, and discloses a method, device, equipment and storage medium for identifying faults of an FPGA lookup table, wherein the method comprises: obtaining a lookup table on a to-be-tested FPGA, dividing the lookup table into a plurality of lookup table groups, connecting the plurality of lookup table groups in series in sequence, inputting a test input signal into a first-level lookup table group, and obtaining a test output signal, and performing fault judgment of a lookup table in each lookup table group according to a comparison result between a test output signal of each level of the lookup table group and a test expected output signal. The present invention reduces the number of configuration times of mass production tests by designing a lookup table group, and by serially cascading the lookup table, the mass production test is not limited by chip scale and routing resources, thereby improving the fault detection efficiency of the lookup table on the FPGA.

Description

Technical Field

[0001] The present invention relates to the field of FPGA technology, and in particular to a fault identification method, device, equipment and storage medium of an FPGA lookup table. Background Art

[0002] As a programmable hardware platform, field programmable gate array (FPGA) is versatile, flexible, reconfigurable and parallel computing, and is widely used in many important fields such as national defense, medical treatment, computing acceleration and communication signal processing. Its unique feature is that it can reconfigure hardware logic circuits through programming to adapt them to different application scenarios and realize specific digital logic functions.

[0003] After the FPGA chip leaves the factory, it must undergo CP (Circuit Probe) mass production test and FT (Final test) mass production test. CP is a wafer-level test of the chip before packaging. FT is a test after packaging is completed, and it is also the test closest to actual usage. Whether it is CP mass production test or FT mass production test, detailed fault coverage test of the most critical resources of FPGA is required. The most distributed logic resource in FPGA chip is the lookup table. How to efficiently achieve full coverage of the lookup table resources is very important for mass production design.

[0004] The traditional solution is to connect the stimulus signal of TPG (Test Pattern Generator) with the input signal of each LUT under test, and TPG applies stimulus to the LUT under test. TPG is connected to the INPUT PIN of all LUTs in the chip, and this connection requires high routing resources. Especially when the device scale is large, the routing resources are not sufficient. At this time, a certain physical segmentation is required, and the number of configurations needs to be increased to meet the coverage test of all LUTs. Increasing the number of configurations will extend the test time and increase the test cost. Summary of the invention

[0005] In view of this, the present invention provides a method, device, equipment and storage medium for fault identification of an FPGA lookup table to solve the problems of large number of mass production test configuration times, high dependence on routing resources and low detection efficiency of traditional lookup table resources.

[0006] In a first aspect, the present invention provides a method for identifying a fault of an FPGA lookup table, the method comprising:

[0007] Get the lookup table on the FPGA to be tested;

[0008] Dividing the lookup table into a plurality of lookup table groups, each lookup table group includes a preset number of lookup tables, and the number of outputs of all the lookup tables in the lookup table group is greater than or equal to the preset number;

[0009] Connecting multiple lookup table groups in series, the input of the next level lookup table group is determined based on part or all of the output of the previous level lookup table group;

[0010] Inputting a test input signal into a first-level lookup table group, and obtaining a test output signal, wherein the test output signal includes a test output signal of each level of the lookup table group;

[0011] According to the comparison result between the test output signal of each level of the lookup table group and the corresponding test expected output signal, the fault judgment of the lookup table in each lookup table group is performed.

[0012] The FPGA lookup table fault identification method provided in the embodiment of the present invention reduces the number of configuration times by designing the lookup table group, and through the serial cascading of the lookup table, the test process does not need to rely on routing resources, so as to solve the problem that the full coverage mass production test of traditional lookup table resources has a large number of configuration times and a high dependence on routing resources, resulting in low detection efficiency.

[0013] In an optional embodiment, each lookup table group includes a preset number of triggers, and the triggers are connected to the output ends of the corresponding lookup tables, and the triggers are used to output the test output signals of each level of the lookup table group in sequence at the output end of the last level of the lookup table group.

[0014] The fault identification method of the FPGA lookup table provided in the embodiment of the present invention adds a trigger so that the output end of the last level lookup table group outputs the output signal of each level lookup table group in sequence according to the serial order of the lookup table group, so that the output signal of each beat has a one-to-one correspondence with each lookup table group.

[0015] In an optional implementation, before inputting the test input signal into the first-stage lookup table group and obtaining the test output signal, the method further includes:

[0016] The truth table of each lookup table in the lookup table group is configured. The truth table is determined according to the connection relationship between two adjacent lookup table groups, so that the test expected output signal of each level of the lookup table group is the same as or complementary to the test input signal.

[0017] The FPGA lookup table fault identification method provided by the embodiment of the present invention designs the truth table of the lookup table group so that the input and output results are predictable, easy to observe and compare, and the efficiency of fault testing and positioning is improved.

[0018] In an optional implementation, the test input signal is input into the first-stage lookup table group, and the test output signal is obtained, further comprising:

[0019] The truth table of the lookup table in the lookup table group is updated so that each bit of the truth table of the lookup table group has 0 or 1;

[0020] The test input signal is input to the first stage lookup table group again, and the test output signal is obtained.

[0021] The FPGA lookup table fault identification method provided in an embodiment of the present invention designs the lookup table so that each bit of the lookup table traverses and outputs 0 or 1, and inputs the test input signal into the first-level lookup table group again, and obtains the test output signal to ensure full coverage of fault detection of each bit.

[0022] In an optional implementation, updating the truth table of a lookup table in the lookup table group includes:

[0023] The truth tables of different lookup tables in the lookup table group are exchanged in a preset order or the values ​​of preset bits in the truth tables of the lookup tables in the lookup table group are complemented.

[0024] The FPGA lookup table fault identification method provided in the embodiment of the present invention can ensure that the output of each bit in the truth table covers 0 and 1 by exchanging the truth tables of each lookup table in each lookup table group in a specific order and directly selecting specific bits for de-complementation operation.

[0025] In an optional implementation, according to the comparison result between the test output signal of each level of the lookup table group and the corresponding test expected output signal, the fault judgment of the lookup table in each lookup table group is performed, including:

[0026] If the test output signal of each level of the lookup table group is consistent with the expected test output signal, it indicates that there is no fault in the FPGA under test;

[0027] If the test output signal of any lookup table group is inconsistent with the expected test output signal, it indicates that the FPGA to be tested has a fault.

[0028] The FPGA lookup table fault identification method provided in the embodiment of the present invention compares each level of the test output signal of the lookup table group with the expected output signal. If there is any test output signal of the first-level lookup table group that is inconsistent with the expected output signal, it indicates that the FPGA has a fault. By designing an expected output signal that is easy to observe, fault judgment is made more efficient.

[0029] In an optional implementation, according to the comparison result between the test output signal of each level of the lookup table group and the corresponding test expected output signal, the fault judgment of the lookup table in each lookup table group is performed, which also includes:

[0030] Acquire a test output signal of the lookup table group that is inconsistent with the test expected output signal;

[0031] Obtaining a target bit position in a test output signal that is inconsistent with a test expected output signal;

[0032] It is determined that in the lookup table group, a lookup table corresponding to the target bit has a fault.

[0033] The FPGA lookup table fault identification method provided in the embodiment of the present invention locates the fault lookup table group according to the inconsistent first-level test output signal, determines the fault lookup table in the lookup table group according to the abnormal target bit in the inconsistent first-level output signal, and can directly locate the fault lookup table according to the beat number of the test output signal and the specific output value, so that the fault location is efficient and more accurate.

[0034] In a second aspect, the present invention provides a fault identification device for an FPGA lookup table, the device comprising:

[0035] An acquisition module is used to obtain a lookup table on the FPGA to be tested;

[0036] A grouping module, used for dividing the lookup table into a plurality of lookup table groups, each lookup table group includes a preset number of lookup tables, and the number of outputs of all the lookup tables in the lookup table group is greater than or equal to the preset number;

[0037] A connection module, used to connect the multiple lookup table groups in series, and the input of the next level lookup table group is determined based on part or all of the output of the previous level lookup table group;

[0038] A test module, used to input a test input signal into the first level lookup table group and obtain a test output signal, wherein the test output signal includes a test output signal of each level lookup table group;

[0039] The comparison module is used to perform fault judgment of the lookup tables in each lookup table group according to the comparison result between the test output signal of each level of the lookup table group and the test expected output signal.

[0040] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the FPGA lookup table fault identification method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0041] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the FPGA lookup table fault identification method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 is a flow chart of a method for identifying a fault of an FPGA lookup table according to an embodiment of the present invention;

[0044] Figure 2 is a schematic diagram of a lookup table group according to an embodiment of the present invention;

[0045] Figure 3 is a schematic diagram of another lookup table group according to an embodiment of the present invention;

[0046] Figure 4 is a structural block diagram of a fault identification device for an FPGA lookup table according to an embodiment of the present invention;

[0047] Figure 5 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0049] Before leaving the factory, FPGA chips must go through a series of rigorous testing processes, including CP (Circuit Probe) mass production testing and FT (Final Test) mass production testing. CP testing is mainly performed at the wafer level before packaging, while FT testing is performed on chips after packaging, which is closer to actual usage. In these two stages of testing, it is crucial to conduct detailed fault coverage testing on the most critical resources of FPGA. The time efficiency of these mass production tests directly affects the cost of the chip, because the longer the test time, the higher the cost.

[0050] The most distributed logic resource in FPGA chips is the lookup table. Efficiently achieving full coverage of the lookup table resources is a very important part of FPGA mass production testing. The traditional solution requires half of the lookup tables to be used as the circuit under test, and the other half to be used as the detection circuit, and then exchanged and tested again. This detection method has a high dependence on routing resources, especially when the device scale is large, the routing resources cannot be met, and the number of configurations needs to be increased to meet the coverage test of all lookup tables, resulting in the bitstream loading occupying most of the test time, making the overall test efficiency low.

[0051] According to an embodiment of the present invention, an embodiment of a fault identification method for an FPGA lookup table is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0052] In this embodiment, a method for identifying faults of an FPGA lookup table is provided. Figure 1 is a flow chart of a method for identifying a fault in an FPGA lookup table according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0053] Step S101, obtaining a lookup table on the FPGA to be tested.

[0054] Specifically, the type and quantity of the lookup tables on the FPGA to be tested are obtained.

[0055] Step S102: divide the lookup table into a plurality of lookup table groups, each lookup table group including a preset number of lookup tables.

[0056] Specifically, the lookup table is divided into a plurality of lookup table groups, and each lookup table group includes an equal number of lookup tables.

[0057] Further, the number of outputs of all the lookup tables in the lookup table group is greater than or equal to the number of the lookup tables in the lookup table group.

[0058] Furthermore, if the number of outputs of the lookup table group is greater than the number of inputs of the lookup table group, a number of output terminals equal to the number of input terminals of the lookup table group are selected to be connected to the input terminals of the next level lookup table.

[0059] Step S103, connecting the multiple lookup table groups in series.

[0060] Specifically, each lookup table group is identified as a first-level lookup table group, and multiple levels of lookup table groups are connected in series.

[0061] Further, the input of the next level lookup table group is determined based on part or all of the output of the previous level lookup table group. Specifically, the outputs of the lookup tables in the previous level lookup table group are combined as the input of the lookup tables in the next level lookup table group; or the outputs of some lookup tables in the previous level lookup table group are combined as the input of the lookup tables in the next level lookup table group.

[0062] Furthermore, the inputs of the lookup tables in the next level lookup table group are the same.

[0063] Step S104: input the test input signal to the first-stage lookup table group, and obtain the test output signal.

[0064] Specifically, the input of the first-level lookup table group is connected to the input pin of the FPGA, and the output of the last-level lookup table is connected to the output pin of the FPGA chip.

[0065] Furthermore, the test input signal is input to the FPGA input pin, and the test output signal of the FPGA output pin is recorded and observed.

[0066] Further, the test output signal includes a test output signal of each stage of the lookup table group.

[0067] In other optional specific implementations, for each level of lookup table group, the test output signal of the lookup table group can be directly obtained from the output pins of each lookup table in the lookup table group.

[0068] In addition, for a lookup table in a lookup table group, it can be divided into a tested lookup table and a lookup table serving as an ORA (Output Response Analyzer). After the tested lookup table group completes the test, the exchange configuration is performed. Specifically, the ORA is converted into the tested lookup table, and the tested lookup table is converted into the ORA, and the ORA converted into the tested lookup table is tested.

[0069] Step S105 , performing fault judgment on the lookup tables in each lookup table group according to the comparison result between the test output signal of each level of the lookup table group and the corresponding test expected output signal.

[0070] Specifically, the expected signal is obtained based on the test input signal combined with the truth table of the lookup table group.

[0071] Furthermore, the test output signal of each level of the lookup table group is compared with the expected output signal to obtain a comparison result.

[0072] By obtaining the type and number of lookup tables on the FPGA to be tested, each lookup table is divided into several lookup table groups. Each lookup table group contains the same number of lookup tables. The lookup table groups are connected in series. The input of the next level lookup table group is determined based on part or all of the output of the previous level lookup table group. For example, Figure 2 As shown, the lookup table group can be composed of 4 lookup tables with 4 inputs and 1 output. The lookup table groups at all levels in the chip are connected in series, and the input of the lookup table group at the next level is determined by part or all of the output of the lookup table at the previous level. In addition, by designing the lookup table group, the number of configurations is reduced, and the serial cascade solves the problem of high dependence on routing resources in mass production testing of traditional lookup tables, so as to achieve efficient mass production coverage testing and fault judgment of all lookup tables in the FPGA chip.

[0073] In some optional embodiments, each lookup table group includes a preset number of triggers, and the triggers are connected to the output ends of the corresponding lookup tables, and the triggers are used to output the test output signals of each level of the lookup table group in sequence at the output end of the last level of the lookup table group.

[0074] The length of time for these mass production tests is often an important factor affecting chip costs. During the execution of FPGA mass production tests, the most time is spent on bitstream loading time, so the most important consideration for mass production design is to test the bitstream configuration as few times as possible to cover as many faults as possible.

[0075] The most distributed logic resource in FPGA chips is the lookup table. How to efficiently achieve full coverage of the lookup table resources is very important for mass production design. The traditional solution requires half of the lookup tables to be used as the circuit under test, and the other half to be used as the detection circuit, and the detection is exchanged, which increases the number of configurations, and the TPG is connected to the input of each lookup table. Therefore, the routing resources are relatively high. Especially when the device scale is large, the routing resources cannot be met, and it is difficult to meet the needs of coverage testing of all lookup tables.

[0076] like Figure 3 As shown, taking a lookup table group consisting of 4 lookup tables with 4 inputs and 1 output as an example, a trigger is connected to the output end of each lookup table. The lookup table group has a total of 4 output ends, and therefore includes 4 triggers. The function of the trigger is to make the test output signal of each level of the lookup table group be output at the output end of the last level of the lookup table in sequence according to the order of the levels.

[0077] In some optional implementations, before inputting the test input signal into the first-stage lookup table group and obtaining the test output signal, the method further includes:

[0078] The truth table of each lookup table in the lookup table group is configured. The truth table is determined according to the connection relationship between two adjacent lookup table groups, so that the test expected output signal of each level of the lookup table group is the same as or complementary to the test input signal.

[0079] By designing the truth table of the lookup table, the test output signal is easy to observe based on the test input signal. The design idea here is to make the test output signal consistent with the test input signal or complement each other, so as to make the fault judgment and fault location of the FPGA lookup table under test more efficient and convenient. By designing the truth table of the lookup table group, the situation where the test input signal is consistent with the test output signal is shown in Table 1; by designing the truth table of the lookup table group, the situation where the test input signal and the test output signal are complement each other is shown in Table 5.

[0080] In some optional implementations, inputting the test input signal into the first-stage lookup table group and obtaining the test output signal further includes:

[0081] The truth table of the lookup table in the lookup table group is updated so that each bit of the truth table of the lookup table group has 0 or 1;

[0082] The test input signal is input to the first stage lookup table group again, and the test output signal is obtained.

[0083] By designing the truth table of each lookup table in the lookup table group, the lookup table can complete full coverage detection of each bit according to the truth table, that is, each bit is traversed and outputs 0 or 1. If only one lookup table is tested to see whether it can output 0, there will be a fault omission that cannot correctly output 1. By designing the lookup table, each bit appears 0 or 1, achieving full coverage of fault detection.

[0084] In some optional implementations, updating the truth table of a lookup table in the lookup table group includes:

[0085] The truth tables of different lookup tables in the lookup table group are exchanged in a preset order or the values ​​of preset bits in the truth tables of the lookup tables in the lookup table group are complemented.

[0086] like Figure 2As shown, taking the lookup table group including 4 lookup tables with 4 inputs and 1 output as an example, the original truth table of the lookup table group can be designed as shown in Table 1, so that the test output signal of the lookup table group is consistent with the test input signal. In order to make each bit in the truth table of the lookup table group appear 0 or 1, several bit stream configurations are performed to change the truth table. Specifically, the truth tables of the four lookup tables can be exchanged in sequence, and the exchange order is: the first configuration: LUT-1->LUT-2->LUT-3->LUT-0, as shown in Table 2, the second exchange configuration: LUT-2->LUT-3->LUT-0->LUT-1 as shown in Table 3, and the third exchange configuration: LUT-3->LUT-0->LUT-1->LUT-2 as shown in Table 4. After configuration, in order to ensure that the test input signal is still consistent with the test output signal, the input connection order of the lookup table group needs to be correspondingly exchanged according to the truth table.

[0087] After the above four configurations, the output values ​​of the 0th bit and the 15th bit are always 0 or 1, so it is necessary to perform a de-complementation operation on the specific bit, as shown in Table 5. The test output signal and the test input signal here are complements of each other. After an even number of cascades, the test output signal is consistent with the test input signal.

[0088] Table 1: Original lookup table group truth table

[0089]

[0090]

[0091] Table 2: Truth table after first configuration

[0092] Lookup table address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lookup Table B 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Lookup Table C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Lookup Table D 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Lookup Table A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

[0093] Table 3: Truth table after the second configuration

[0094] Lookup table address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lookup Table C 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Lookup Table D 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Lookup Table A 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Lookup Table B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

[0095] Table 4: Truth table after the third configuration

[0096] Lookup table address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lookup Table D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Lookup Table A 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Lookup Table B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Lookup Table C 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

[0097] Table 5: Truth table after taking the complement code

[0098] Lookup table address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lookup Table C 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Lookup Table D 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Lookup Table A 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Lookup Table B 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

[0099] In some optional implementations, according to the comparison result between the test output signal of each level of the lookup table group and the corresponding test expected output signal, the fault judgment of the lookup table in each lookup table group is performed, including:

[0100] If the test output signal of each level of the lookup table group is consistent with the expected test output signal, it indicates that there is no fault in the FPGA under test;

[0101] If the test output signal of any lookup table group is inconsistent with the expected test output signal, it indicates that the FPGA to be tested has a fault.

[0102] like Figure 2 As shown, taking the lookup table group containing 4 lookup tables with 4 inputs and 1 output, and a total of 4 levels of lookup table groups as an example, assuming that the test input signal is 0001, the test input signal of the first-level lookup table group is 0001. If the test output signal of the last-level lookup table group is four beats of 0001, specifically, the test output signal is: 0001000100010001, then it indicates that there is no fault in the lookup table on the FPGA. If one beat of the test output signal does not match the test input signal, for example, it is 0001000000010001, the second beat should be 0001, and the actual second-level test output signal is 0000, then it indicates that there is a fault in the lookup table on the FPGA.

[0103] In some optional implementations, according to the comparison result between the test output signal of each level of the lookup table group and the corresponding test expected output signal, the fault judgment of the lookup table in each lookup table group is performed, which further includes:

[0104] Acquire a test output signal of the lookup table group that is inconsistent with the test expected output signal;

[0105] Obtaining a target bit position in a test output signal that is inconsistent with a test expected output signal;

[0106] It is determined that in the lookup table group, a lookup table corresponding to the target bit has a fault.

[0107] like Figure 2 As shown, taking a lookup table group including 4 lookup tables with 4 inputs and 1 output, and a total of 4 levels of lookup table groups as an example, assuming that the test input signal is 0001, the input signal of the first level lookup table group is 0001. If all the lookup tables are normal and there is no fault, the output signal of the last level lookup table group should be four beats 0001, that is, 0001000100010001. If at this time, one of the beats of the test output signal does not match the test input signal, for example, 0001000000010001, the second beat should be 0001, and the actual second-level test output signal is 0000. Then, it is determined that the target bit is the fourth bit of the second beat, and the second-level lookup table group corresponding to the second beat is faulty. Then, according to the target bit, it is determined that the fourth lookup table in the lookup table group is a faulty lookup table.

[0108] In this embodiment, a fault identification device for an FPGA lookup table is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0109] This embodiment provides a fault identification device for an FPGA lookup table, such as Figure 4 As shown, the device comprises:

[0110] An acquisition module 501 is used to acquire a lookup table on the FPGA to be tested;

[0111] A grouping module 502, configured to divide the lookup table into a plurality of lookup table groups, each lookup table group comprising a preset number of lookup tables, and the number of outputs of all the lookup tables in the lookup table group being greater than or equal to the preset number;

[0112] A connection module 503 is used to connect the multiple lookup table groups in series, and the input of the next level lookup table group is determined based on part or all of the output of the previous level lookup table group;

[0113] A test module 504, configured to input a test input signal into the first level lookup table group, and obtain a test output signal, wherein the test output signal includes a test output signal of each level lookup table group;

[0114] The comparison module 505 is used to perform fault judgment of the lookup tables in each lookup table group according to the comparison result between the test output signal and the test expected output signal of each level of the lookup table group.

[0115] In some optional embodiments, the device further comprises:

[0116] The trigger module is used to add a preset number of triggers in each lookup table group, and the trigger is connected to the output end of the corresponding lookup table. The trigger is used to make the test output signal of each level of lookup table group output in sequence at the output end of the last level of lookup table group.

[0117] In some optional embodiments, the device further comprises:

[0118] The truth table configuration module is used to configure the truth table of each lookup table in the lookup table group. The truth table is determined based on the connection relationship between two adjacent lookup table groups so that the test expected output signal of each level of lookup table group is the same as or complementary to the test input signal.

[0119] In some optional implementations, the testing module 504 includes:

[0120] The updating submodule is used to update the truth table of the lookup table in the lookup table group so that each bit of the truth table of the lookup table group has 0 or 1.

[0121] The retest submodule is used to input the test input signal into the first-level lookup table group again and obtain the test output signal.

[0122] In some optional implementations, the updating submodule includes:

[0123] The exchange configuration unit is used to exchange the truth tables of different lookup tables in the lookup table group in a preset order or to complement the values ​​of preset bits in the truth tables of each lookup table in the lookup table group.

[0124] In some optional embodiments, the comparison module 505 includes:

[0125] The fault determination submodule is used to determine that the FPGA to be tested has a fault when the test output signal of any lookup table group is inconsistent with the test expected output signal.

[0126] In some optional implementations, the comparison module 505 further includes:

[0127] The signal acquisition submodule is used to acquire the test output signal of the lookup table group that is inconsistent with the expected test output signal.

[0128] The bit position acquisition submodule is used to acquire the target bit position in the test output signal that is inconsistent with the test expected output signal.

[0129] The fault finding submodule is used to determine whether a fault exists in the lookup table corresponding to the target bit in the lookup table group.

[0130] The fault identification device of the FPGA lookup table in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0131] The embodiment of the present invention also provides a computer device having the above Figure 4 The fault identification device of the FPGA lookup table is shown.

[0132] See also Figure 5 , Figure 5 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 5As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 5 A processor 10 is taken as an example.

[0133] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0134] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0135] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0136] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0137] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 5 The example of connecting through bus is taken in the following.

[0138] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0139] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0140] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for identifying faults in an FPGA lookup table, characterized in that: The method comprises: Get the lookup table on the FPGA to be tested; Dividing the lookup table into a plurality of lookup table groups, each of the lookup table groups comprising a preset number of lookup tables, and the number of outputs of all the lookup tables in the lookup table group being greater than or equal to the preset number; Connecting the plurality of lookup table groups in series, wherein the input of the lookup table group at the next level is determined based on part or all of the output of the lookup table group at the previous level; Configuring a truth table of each of the lookup tables in the lookup table group, wherein the truth table is determined according to a connection relationship between two adjacent lookup table groups, so that a test expected output signal of each level of the lookup table group is identical to or complementary to a test input signal; Inputting a test input signal into the first-stage lookup table group, and obtaining a test output signal, wherein the test output signal includes a test output signal of each stage of the lookup table group; The truth tables of different lookup tables in the lookup table group are exchanged in a preset order or the values ​​of preset bits in the truth tables of the lookup tables in the lookup table group are complemented, so that each bit in the truth table of the lookup table group appears 0 or 1; Inputting the test input signal to the first-stage lookup table group again, and obtaining the test output signal; According to the comparison result between the test output signal of each level of the lookup table group and the corresponding test expected output signal, the fault judgment of the lookup table in each lookup table group is performed; The step of performing fault judgment of the lookup table in each lookup table group according to a comparison result between the test output signal of each level of the lookup table group and the corresponding test expected output signal comprises: If the test output signal of the lookup table group at each level is consistent with the expected test output signal, it indicates that there is no fault in the FPGA to be tested; If the test output signal of any of the lookup table groups is inconsistent with the expected test output signal, it indicates that the FPGA to be tested has a fault.

2. The method according to claim 1, characterized in that Each of the lookup table groups includes a preset number of triggers, and the triggers are connected to the output ends of the corresponding lookup tables, and the triggers are used to make the test output signals of each level of the lookup table group be output in sequence at the output end of the last level of the lookup table group.

3. The method according to claim 1, characterized in that The method of performing fault judgment of the lookup table in each lookup table group according to the comparison result between the test output signal of each level of the lookup table group and the corresponding test expected output signal also includes: Acquire a test output signal of the lookup table group that is inconsistent with a test expected output signal; Acquire a target bit position in the test output signal that is inconsistent with the test expected output signal; It is determined that in the lookup table group, a lookup table corresponding to the target bit position has a fault.

4. A fault identification device for an FPGA lookup table, characterized in that: The device comprises: An acquisition module is used to obtain a lookup table on the FPGA to be tested; A grouping module, used for dividing the lookup table into a plurality of lookup table groups, each of the lookup table groups comprising a preset number of lookup tables, and the number of outputs of all the lookup tables in the lookup table group being greater than or equal to the preset number; A truth table configuration module is used to configure the truth table of each of the lookup tables in the lookup table group, wherein the truth table is determined according to the connection relationship between two adjacent lookup table groups, so that the test expected output signal of each level of the lookup table group is the same as or complementary to the test input signal; A connection module, used to connect the plurality of the lookup table groups in series, wherein the input of the lookup table group at the next level is determined based on part or all of the output of the lookup table group at the previous level; A test module, used for inputting a test input signal into the first level of the lookup table group, and obtaining a test output signal, wherein the test output signal includes a test output signal of each level of the lookup table group; The test module comprises: an updating submodule, which is used to exchange the truth tables of different lookup tables in the lookup table group in a preset order or to complement the values ​​of preset bits in the truth tables of the lookup tables in the lookup table group, so that each bit of the truth table of the lookup table group appears 0 or 1; A retest submodule, used for inputting the test input signal into the first-stage lookup table group again, and obtaining the test output signal; A comparison module, used for performing fault judgment of the lookup table in each lookup table group according to a comparison result between a test output signal of the lookup table group at each level and a test expected output signal; The comparison module further includes: a fault determination submodule, which is used to indicate that there is no fault in the FPGA to be tested if the test output signal of the lookup table group at each level is consistent with the test expected output signal; If the test output signal of any of the lookup table groups is inconsistent with the expected test output signal, it indicates that the FPGA to be tested has a fault.

5. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method according to any one of claims 1 to 3 by executing the computer instructions.

6. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 3.

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