Driving method of pixel circuit and display panel

Abstract

The application discloses a driving method of a pixel circuit and a display panel. The pixel circuit comprises a data writing module, a driving module and a first reset module; the data writing module is connected with the driving module, and the first reset module is connected with a control end of the driving module; in one display frame, the driving method of the pixel circuit comprises the following steps: in a first reset stage, controlling the first reset module to reset the control end of the driving module at least once; in a second reset stage, controlling the first reset module to reset the control end of the driving module at least once; and in a first data writing stage, controlling the data writing module to write a first data voltage into the control end of the driving module at least once. The technical scheme of the application improves the display effect of the display panel.

Description

[0001] The present application claims priority of application No. 202311434931.8 (the filing date of the prior application is October 31, 2023, and the invention name is pixel driving circuit and driving method). TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a driving method of a pixel circuit and a display panel. BACKGROUND

[0003] The flat display device of the organic light emitting diode (OLED) is widely used in mobile phones, televisions, notebook computers, desktop computers and other electronic products due to its high image quality, power saving, thin body and wide application range.

[0004] However, the display effect of the current display product needs to be improved, that is, the display product has the problem of poor display effect. SUMMARY

[0005] The present application provides a driving method of a pixel circuit and a display panel to solve the problem of poor display effect of the display product.

[0006] According to an aspect of the present application, a driving method of a pixel circuit is provided, the pixel circuit comprising a data writing module, a driving module and a first reset module; the data writing module is connected with the driving module, and the control end of the driving module is connected with the first reset module; in one display frame, the method comprises:

[0007] In the first reset stage, the first reset module is controlled to reset the control end of the driving module at least once;

[0008] In the second reset stage, the first reset module is controlled to reset the control end of the driving module at least once;

[0009] In the first data writing stage, the data writing module is controlled to write the first data voltage to the control end of the driving module at least once.

[0010] Optionally, the method further comprises: performing a second data writing stage between the first reset stage and the second reset stage;

[0011] In the second data writing stage, the data writing module writes the second data voltage to the control end of the driving module at least once;

[0012] Preferably, in the second data writing stage, the data writing module writes a second data voltage to the control terminal of the driving module at least twice.

[0013] Preferably, the pixel circuit further comprises a light emitting module, and the driving module is connected with the light emitting module; the method further comprises:

[0014] In the light emitting stage, the driving module generates a driving current to make the light emitting module emit light in response to the driving current.

[0015] Optionally, the pixel circuit further comprises a storage module, a first terminal of the storage module is connected with a direct current signal, and a second terminal of the storage module is connected with the control terminal of the driving module; between the first reset stage and the second data writing stage, the method further comprises:

[0016] In the reset maintaining stage, the first reset module and the data writing module are controlled to be turned off, so that the storage module maintains the potential of the control terminal of the driving module;

[0017] Alternatively, in part of the reset maintaining stage, the first reset module is controlled to reset the control terminal of the driving module at least once, and in another part of the reset maintaining stage, the first reset module and the data writing module are controlled to be turned off; wherein the another part of the reset maintaining stage is a time period between the end of the last time that the first reset module resets the control terminal of the driving module in the reset maintaining stage and the beginning of the second data writing stage.

[0018] Preferably, the first data writing stage can also be located before the first reset stage; in the first data writing stage, the data writing module writes a second data voltage to the control terminal of the driving module at least once; in the second data writing stage, the data writing module writes a first data voltage to the control terminal of the driving module at least once; wherein the second reset stage is located before the first data writing stage.

[0019] Optionally, before the reset maintaining stage, the method further comprises:

[0020] determining the length of the reset maintaining stage according to a test parameter value of a display panel in which the pixel circuit is located; wherein the test parameter value at least comprises a residual image value of the display panel.

[0021] Optionally, between the second reset stage and the first data writing stage, the method further comprises:

[0022] in the transition stage, the data writing module and the first reset module are controlled to be turned off;

[0023] The length of the reset maintaining stage is greater than the length of the transition stage.

[0024] Preferably, the length of the other part of the period is greater than the length of the transition stage.

[0025] Optionally, between the first reset stage and the reset maintaining stage, the method further comprises performing at least one first reset stage.

[0026] Alternatively, between the reset maintaining stage and the second data writing stage, the method further comprises performing at least one first reset stage and at least one reset maintaining stage.

[0027] Preferably, the pixel circuit further comprises a second reset module, the second reset module being connected with the light emitting module; the method further comprises:

[0028] In the first reset stage, the second reset module is controlled to reset the light emitting module at least once.

[0029] In the second reset stage, the second reset module is controlled to reset the light emitting module at least once.

[0030] Optionally, the single effective pulse width of the control signal of the first reset module is the same.

[0031] The single effective pulse width of the control signal of the first reset module is n times of the single effective pulse width of the control signal of the data writing module.

[0032] Preferably, n is an integer greater than or equal to 1.

[0033] Preferably, n is 1 or 2.

[0034] According to another aspect of the present application, a driving method of a pixel circuit is provided, the pixel circuit comprising a data writing module, a driving module and a first reset module; the data writing module is connected with the driving module, and the first reset module is connected with the control end of the driving module; in one display frame, the method comprises:

[0035] In the first reset stage, the first reset module is controlled to reset the control end of the driving module at least once.

[0036] In the second data writing stage, the data writing module is controlled to write a second data voltage to the control end of the driving module at least once.

[0037] In the first data writing stage, the data writing module is controlled to write a first data voltage to the control end of the driving module at least once.

[0038] Optionally, the pixel circuit further comprises a storage module, a first end of the storage module is connected to a direct current signal, and a second end of the storage module is connected to a control end of the driving module; the method further comprises:

[0039] in the reset maintaining stage, the first reset module and the data writing module are controlled to be turned off, so that the storage module maintains the potential of the control end of the driving module;

[0040] Alternatively, in part of the reset maintaining stage, the first reset module is controlled to reset the control end of the driving module at least once, and in another part of the reset maintaining stage, the first reset module and the data writing module are controlled to be turned off; wherein the another part of the reset maintaining stage is a period between the end of the last reset of the control end of the driving module by the first reset module in the reset maintaining stage and the beginning of the second data writing stage.

[0041] Optionally, between the second data writing stage and the first data writing stage, the method further comprises:

[0042] in the second reset stage, the first reset module is controlled to reset the control end of the driving module at least once;

[0043] Preferably, in the second data writing stage, the data writing module writes the second data voltage to the control end of the driving module at least twice;

[0044] Preferably, the first data writing stage can also be located before the first reset stage; in the first data writing stage, the data writing module writes the second data voltage to the control end of the driving module at least once; in the second data writing stage, the data writing module writes the first data voltage to the control end of the driving module at least once; wherein the second reset stage is located before the first data writing stage;

[0045] Preferably, the pixel circuit further comprises a light emitting module, and the driving module is connected to the light emitting module; the method further comprises:

[0046] in the light emitting stage, the driving module generates a driving current, so that the light emitting module emits light in response to the driving current;

[0047] Preferably, the pixel circuit further comprises a second reset module, and the second reset module is connected to the light emitting module; the method further comprises:

[0048] In the first reset stage, the second reset module is controlled to reset the light-emitting module at least once.

[0049] In the second reset stage, the second reset module is controlled to reset the light-emitting module at least once.

[0050] Optionally, between the second reset stage and the first data write stage, the method further comprises:

[0051] In the transition stage, the data write module and the first reset module are controlled to be turned off.

[0052] Preferably, the length of the reset maintenance stage is greater than the length of the transition stage.

[0053] Preferably, the length of the other part of the period is greater than the length of the transition stage.

[0054] Optionally, before the reset maintenance stage, the method further comprises:

[0055] The length of the reset maintenance stage is determined according to a test parameter value of a display panel in which the pixel circuit is located; wherein the test parameter value at least includes a residual image value of the display panel.

[0056] Optionally, between the first reset stage and the reset maintenance stage, the method further comprises executing at least one first reset stage.

[0057] Alternatively, between the reset maintenance stage and the second data write stage, the method further comprises executing at least one first reset stage and at least one reset maintenance stage.

[0058] Optionally, the single effective pulse width of the control signal of the first reset module is the same.

[0059] The single effective pulse width of the control signal of the first reset module is n times the single effective pulse width of the control signal of the data write module.

[0060] Preferably, n is an integer greater than or equal to 1.

[0061] Preferably, n is 1 or 2.

[0062] According to another aspect of the present application, a driving method of a pixel circuit is provided, the pixel circuit comprising a data writing module, a driving module, a first reset module and a storage module; the data writing module is connected with the driving module, the first reset module is connected with a control terminal of the driving module; a first terminal of the storage module is connected with a direct current signal, a second terminal of the storage module is connected with the control terminal of the driving module; in one display frame, the method comprises:

[0063] in the first reset stage, the first reset module is controlled to reset the control terminal of the driving module at least once;

[0064] in the reset maintaining stage, the first reset module and the data writing module are controlled to be turned off, so that the storage module maintains the potential of the control terminal of the driving module; or, in part of the reset maintaining stage, the first reset module is controlled to reset the control terminal of the driving module at least once, and in another part of the reset maintaining stage, the first reset module and the data writing module are controlled to be turned off;

[0065] in the first data writing stage, the data writing module is controlled to write a first data voltage to the control terminal of the driving module at least once;

[0066] wherein the another part of the time period is a time period between the end of the last reset of the control terminal of the driving module by the first reset module in the reset maintaining stage and the beginning of the first data writing stage.

[0067] Optionally, between the reset maintaining stage and the first data writing stage, the method further comprises:

[0068] in the second data writing stage, the data writing module is controlled to write a second data voltage to the control terminal of the driving module at least once; wherein the another part of the time period is a time period between the end of the last reset of the control terminal of the driving module by the first reset module in the reset maintaining stage and the beginning of the second data writing stage;

[0069] in the second reset stage, the first reset module is controlled to reset the control terminal of the driving module at least once;

[0070] Preferably, the first data writing stage can also be located before the first reset stage; in the first data writing stage, the data writing module writes a second data voltage to the control terminal of the driving module at least once; in the second data writing stage, the data writing module writes a first data voltage to the control terminal of the driving module at least once; wherein the second reset stage is located before the first data writing stage.

[0071] Preferably, in the second data writing stage, the data writing module writes the second data voltage to the control terminal of the driving module at least twice.

[0072] Preferably, the pixel circuit further comprises a light emitting module, and the driving module is connected with the light emitting module; the method further comprises:

[0073] In the light emitting stage, the driving module generates a driving current to make the light emitting module emit light in response to the driving current.

[0074] Optionally, before the reset maintaining stage, the method further comprises:

[0075] The length of the reset maintaining stage is determined according to a test parameter value of a display panel in which the pixel circuit is located; wherein the test parameter value at least comprises a residual image value of the display panel.

[0076] Optionally, between the second reset stage and the first data writing stage, the method further comprises:

[0077] In the transition stage, the data writing module and the first reset module are controlled to be turned off;

[0078] The length of the reset maintaining stage is greater than the length of the transition stage.

[0079] Preferably, the length of the other part of the period is greater than the length of the transition stage.

[0080] Optionally, between the first reset stage and the reset maintaining stage, the method further comprises performing at least one first reset stage;

[0081] Or, between the reset maintaining stage and the second data writing stage, the method further comprises performing at least one first reset stage and at least one reset maintaining stage.

[0082] Preferably, the pixel circuit further comprises a second reset module, and the second reset module is connected with the light emitting module; the method further comprises:

[0083] In the first reset stage, the second reset module is controlled to reset the light emitting module at least once;

[0084] In the second reset stage, the second reset module is controlled to reset the light emitting module at least once.

[0085] Optionally, the single effective pulse width of the control signal of the first reset module is the same.

[0086] The single effective pulse width of the control signal of the first reset module is n times of the single effective pulse width of the data writing module.

[0087] Preferably, the n is an integer greater than or equal to 1.

[0088] Preferably, the n is 1 or 2.

[0089] According to another aspect of the present application, a display panel is provided, which comprises a plurality of first gate driving circuits, a plurality of second gate driving circuits and a plurality of pixel circuits; the pixel circuit comprises a data writing module, a driving module and a first reset module; the data writing module is connected with the driving module, and the first reset module is connected with the control end of the driving module.

[0090] One of the first gate driving circuits is connected with the first reset modules of k rows of the pixel circuits, and the first gate driving circuit is used for transmitting a first gate driving signal to the first reset modules of the k rows of the pixel circuits.

[0091] One of the second gate driving circuits is connected with the data writing modules of one row of the pixel circuits, and the second gate driving circuit is used for transmitting a second gate driving signal to the data writing modules of one row of the pixel circuits.

[0092] The single effective pulse width of the first gate driving signal is n times of the single effective pulse width of the second gate driving signal.

[0093] Optionally, the k is an integer greater than or equal to 1, and the n is an integer greater than or equal to 1.

[0094] Preferably, the k is equal to the n.

[0095] Preferably, k = n = 2.

[0096] Preferably, k = n = 1.

[0097] The technical scheme of the embodiment of the present application controls the first reset module to reset the control end of the driving module at least once in the first reset stage, and controls the second reset module to reset the control end of the driving module at least once in the second reset stage. Thus, the control end of the driving module is reset at least twice, the time length and the number of times of applying the reverse voltage stress to the driving module are increased, the driving module with a large characteristic shift can be well restored in characteristics, each driving module can be well restored in characteristics, the driving currents generated by different driving modules tend to be consistent under the same gray scale, the luminance of different light emitting modules tends to be consistent, the display uniformity of the display panel can be improved, residual images can be avoided, and the display effect of the display panel is improved.

[0098] It is to be understood that the details set forth herein do not limit the scope of the embodiments of the application to the specific embodiments described. The foregoing detailed description has been presented for purposes of clarity and description. It is not intended to be exhaustive or to limit the application to the precise form described. BRIEF DESCRIPTION OF DRAWINGS

[0099] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort based on these drawings.

[0100] Figure 1 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0101] Figure 2 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the present application;

[0102] Figure 3 is a driving timing diagram of a pixel circuit provided by an embodiment of the present application;

[0103] Figure 4 is a flowchart of a driving method of a pixel circuit provided by another embodiment of the present application;

[0104] Figure 5 is a driving timing diagram of a pixel circuit provided by another embodiment of the present application;

[0105] Figure 6 is a driving timing diagram of a pixel circuit provided by another embodiment of the present application;

[0106] Figure 7 is a structural schematic diagram of a pixel circuit provided by another embodiment of the present application;

[0107] Figure 8 is a flowchart of a driving method of a pixel circuit provided by another embodiment of the present application;

[0108] Figure 9 is a driving timing diagram of a pixel circuit provided by another embodiment of the present application;

[0109] Figure 10 is a flowchart of a driving method of a pixel circuit provided by another embodiment of the present application;

[0110] Figure 11 is a driving timing diagram of a pixel circuit provided by another embodiment of the present application;

[0111] Figure 12is a driving timing diagram of another pixel circuit provided by an embodiment of the application;

[0112] Figure 13 is a driving timing diagram of another pixel circuit provided by an embodiment of the application;

[0113] Figure 14 is a driving timing diagram of another pixel circuit provided by an embodiment of the application;

[0114] Figure 15 is a flowchart of a driving method of another pixel circuit provided by an embodiment of the application;

[0115] Figure 16 is a driving timing diagram of another pixel circuit provided by an embodiment of the application;

[0116] Figure 17 is a flowchart of a driving method of another pixel circuit provided by an embodiment of the application;

[0117] Figure 18 is a driving timing diagram of another pixel circuit provided by an embodiment of the application;

[0118] Figure 19 is a flowchart of a driving method of another pixel circuit provided by an embodiment of the application;

[0119] Figure 20 is a driving timing diagram of another pixel circuit provided by an embodiment of the application;

[0120] Figure 21 is a flowchart of a driving method of another pixel circuit provided by an embodiment of the application;

[0121] Figure 22 is a driving timing diagram of another pixel circuit provided by an embodiment of the application;

[0122] Figure 23 is a flowchart of a driving method of another pixel circuit provided by an embodiment of the application;

[0123] Figure 24 is a driving timing diagram of another pixel circuit provided by an embodiment of the application;

[0124] Figure 25 is a driving timing diagram of another pixel circuit provided by an embodiment of the application;

[0125] Figure 26 is a structural schematic diagram of a display panel provided by an embodiment of the application;

[0126] Figure 27 is a structural schematic diagram of another display panel provided by an embodiment of the application;

[0127] Figure 28 is a structure diagram of still another pixel circuit provided by the embodiment of the present application. DETAILED DESCRIPTION

[0128] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work should belong to the protection scope of the present application.

[0129] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0130] As mentioned in the background, the existing display product has the problem of poor display effect. The inventor has found that the cause of this problem is that the organic light-emitting diode display panel is driven by current to emit light. The display panel includes a plurality of pixel circuits and organic light-emitting diodes, and the plurality of pixel circuits can be arranged in an array. The pixel circuit includes a driving transistor, and the driving transistor is connected to the organic light-emitting diode. The driving transistor in the pixel circuit can generate a driving current according to a data voltage, so that the organic light-emitting diode emits light in response to the driving current. However, when displaying a picture, the driving transistor is turned on, and the driving transistor is subjected to a forward voltage stress. The driving transistor is subjected to a forward voltage stress for a long time, which can cause the characteristics of the driving transistor to deviate. When switching to the next display gray scale, a brightness deviation can occur. When displaying a picture, the target brightness of the organic light-emitting diode at different positions is different, and the target data voltage received by different driving transistors is different, so that the forward voltage stress received by different driving transistors is different. The characteristics of different driving transistors change differently, so that the driving current generated by different driving transistors is different at the same gray scale, thereby causing the display brightness of different organic light-emitting diodes to be different. Therefore, when switching from a display picture of different gray scales to a display picture of the same gray scale, the brightness of the organic light-emitting diode corresponding to each driving transistor is different, which causes a residual image, resulting in poor display uniformity of the display panel and affecting the display effect of the display panel.

[0131] To solve the above problems, the embodiment of the present application provides a driving method of a pixel circuit. Figure 1 is a structural schematic diagram of a pixel circuit provided by the embodiment of the present application, referring to Figure 1 The pixel circuit includes a data writing module 11, a driving module 12 and a first reset module 13. The data writing module 11 is connected to the driving module 12, and the control end of the driving module 12 is connected to the first reset module 13.

[0132] The data writing module 11 can be connected to the control end of the driving module 12. The data writing module 11 is connected to the data line Data, and transmits the data voltage on the data line Data to the control end of the driving module 12. The data writing module 11 can also be connected to the first end of the driving module 12, and writes the data voltage from the first end of the driving module 12 to the control end of the driving module 12. Figure 1 The data writing module 11 is connected to the control end of the driving module 12, but is not limited thereto.

[0133] The first reset module 13 is connected with the control end of the driving module 12. The first reset module 13 is connected with the first reset voltage Vref1, so that the first reset module 13 can transmit the first reset voltage Vref1 to the control end of the driving module 12 to reset the control end of the driving module 12. The first end of the driving module 12 can be connected with the first power supply VDD. The pixel circuit can further include a light emitting module 14. The second end of the driving module 12 can be connected with the first end of the light emitting module 14, and the second end of the light emitting module 14 is connected with the second power supply VSS. The voltage of the first power supply VDD can be a positive voltage, and the voltage of the second power supply VSS can be zero or a negative voltage. In this way, a current loop can be formed between the first power supply VDD, the driving module 12, the light emitting module 14 and the second power supply VSS. The driving module 12 can generate a driving current according to the data voltage, and the light emitting module 14 can emit light in response to the driving current.

[0134] The pixel circuit can be connected with a gate driving circuit. The gate driving circuit provides a gate driving signal for the pixel circuit. The gate driving signal can control whether the first reset module 13 is turned on or not, and can also control whether the data writing module 11 is turned on or not. The gate driving signals written to the first reset module 13 and the data writing module 11 are different. For example, the control end of the first reset module 13 is connected with a first gate driving line S1. The first gate driving line S1 provides a first gate driving signal for the first reset module 13. The control end of the data writing module 11 is connected with a second gate driving line S2. The second gate driving line S2 can provide a second gate driving signal for the data writing module 11.

[0135] Figure 2 is a flowchart of a driving method of a pixel circuit provided by an embodiment of the present application. Referring to Figure 2 In one display frame, the driving method of the pixel circuit includes:

[0136] S101, in the first reset stage, the control end of the driving module is reset at least once by the first reset module.

[0137] Specifically, an exemplary, Figure 3 is a driving timing diagram of a pixel circuit provided by an embodiment of the present application, as Figure 1 and Figure 3As shown, in the first reset stage t01, the first gate driving signal Scan1 transmitted by the first gate driving line S1 is at an effective level, and the first reset module 13 is controlled to conduct at least once, so that the first reset module 13 transmits the first reset voltage Vref1 to the control end of the driving module 12 at least once to reset the control end of the driving module 12 at least once. In this way, the residual charge of the last frame can be cleared, and the driving module 12 can be applied with a reverse voltage stress (opposite to the voltage stress when the driving module 12 is turned on), thereby reducing the characteristic deviation degree caused by long-time conduction of the driving module 12, improving the characteristics of the driving module 12, avoiding the residual image problem caused by the change of the characteristics of the driving module 12 when it is turned on in the last frame, and being beneficial to improving the display effect of the display panel where the pixel circuit is located.

[0138] In addition, in the first reset stage, the first reset module 13 can reset the control end of the driving module 12 multiple times, so that the driving module 12 can be applied with a reverse voltage stress multiple times, and the characteristics of the driving module 12 can be better improved. Even if the driving module 12 has a large characteristic deviation, the characteristics of the driving module 12 can also be well restored, so that each driving module 12 can better restore the characteristics before generating the driving current. The upper limit of the number of times that the first reset module 13 is turned on in the first reset stage can be determined according to actual conditions, for example, according to the proportion of the non-emitting stage in a driving cycle, and the present embodiment is not limited in this regard.

[0139] In the first reset stage, the first reset module 13 can reset the control end of the driving module 12 multiple times, so that the driving module 12 can be applied with a reverse voltage stress multiple times, and the characteristics of the driving module 12 can be better improved. Even if the driving module 12 has a large characteristic deviation, the characteristics of the driving module 12 can also be well restored, so that each driving module 12 can better restore the characteristics before generating the driving current. The upper limit of the number of times that the first reset module 13 is turned on in the first reset stage can be determined according to actual conditions, for example, according to the proportion of the non-emitting stage in a driving cycle, and the present embodiment is not limited in this regard.

[0140] S102, in the second reset stage, the first reset module is controlled to reset the control end of the driving module at least once.

[0141] Specifically, as Figure 1 and Figure 3As shown, in the second reset stage t02, the first gate drive signal Scan1 transmitted by the first gate drive line S1 is at an effective level, controlling the first reset module 13 to be turned on at least once. This allows the first reset module 13 to transmit the first reset voltage Vref1 to the control terminal of the drive module 12 at least once, resetting the control terminal of the drive module 12 at least once. This allows for continued resetting of the control terminal of the drive module 12, increasing the number and duration of reverse voltage stress applied to the drive module 12, thereby further improving the characteristics of the drive module 12 and providing time for it to recover its characteristics. This ensures good characteristic recovery when the drive module 12 generates drive current. Therefore, even drive modules 12 with large characteristic deviations can recover their characteristics well, ensuring that the characteristics of each drive module 12 are well recovered. This makes the drive current generated by the drive module 12 tend to be consistent at the same grayscale, resulting in consistent luminous brightness of different light-emitting modules 14. This improves the display uniformity and overall display effect of the display panel. Furthermore, it can avoid the problem of color shift caused by the failure of the drive module 12 to recover its characteristics after switching screens, which would result in different drive currents generated by different drive modules 12 when the first frame is displayed, and large differences in the luminous efficiency of light-emitting modules 14 with different luminous colors, thus avoiding the ghosting phenomenon.

[0142] In this embodiment, when the first reset module 13 resets the control terminal of the drive module 12 multiple times during the second reset phase, it can perform multiple resets continuously or intermittently.

[0143] S103. In the first data writing stage, the control data writing module writes the first data voltage to the control terminal of the drive module at least once.

[0144] Specifically, such as Figure 1 As shown, in the first data writing stage t03, the second gate drive signal Scan2 on the second gate drive line S2 is at an active level, controlling the data writing module 11 to be turned on. This allows the data writing module 11 to transmit the first data voltage on the data line Data to the control terminal of the drive module 12, so that the drive module 12 can generate a drive current according to the first data voltage, and the light-emitting module 14 responds to the drive current to emit light. The first data voltage is the data voltage corresponding to the current row pixel circuit.

[0145] And, in the related art, the second gate driving signal corresponding to the data writing module 11 is the first gate driving signal corresponding to the first reset module 13, that is, the second gate driving signal is the next stage signal of the first gate driving signal. In the technical solution of the embodiment, the first gate driving signal is irrelevant to the second gate driving signal, and the number and length of the effective level of the first gate driving signal can be adjusted according to actual needs (for example, the degree of residual image), so that the first gate driving signal can be adjusted for different working states (for example, the display panel displays different pictures), and the characteristics of the driving module 12 can be better restored.

[0146] It should be noted that the above effective level can be a high level or a low level, that is, the data writing module 11 and the first reset module 13 can be turned on in response to a high level or a low level. Figure 3 The effective level is low in the above embodiment, but it is not limited thereto.

[0147] The technical solution of the embodiment controls the first reset module to reset the control end of the driving module at least once in the first reset stage, and controls the second reset module to reset the control end of the driving module at least once in the second reset stage. Thus, the control end of the driving module is reset at least twice, the length and number of the reverse voltage stress applied to the driving module can be increased, the characteristics of the driving module with large characteristic deviation can be well restored, the characteristics of each driving module can be well restored, the driving currents generated by different driving modules under the same gray scale tend to be consistent, the luminance of different light emitting modules tends to be consistent, the display uniformity of the display panel can be improved, the residual image can be avoided, and the display effect of the display panel is improved.

[0148] On the basis of the above technical solution, the following describes the stages that the driving method can further include, but is not limited to the present application.

[0149] Figure 4 is a flowchart of another driving method of a pixel circuit provided by the embodiment of the present application. Optionally, refer to Figure 4 In one display frame, the driving method of the pixel circuit includes:

[0150] S201, in the first reset stage, control the first reset module to reset the control end of the driving module at least once. For example, Figure 5 is another driving timing diagram of a pixel circuit provided by the embodiment of the present application, as shown in Figure 5 In the first reset stage t11, the first gate driving signal Scan1 on the first gate driving line S1 is an effective level, and the first reset module 13 resets the control end of the driving module 12.

[0151] S202, performing a second data writing stage; wherein in the second data writing stage, the data writing module writes the second data voltage to the control terminal of the driving module at least once.

[0152] The second data voltage is a first data voltage corresponding to a pixel circuit in a plurality of preceding rows of the current row, for example, the current row is the a-th row, and the preceding rows are the a-b rows, and b can be a positive integer greater than or equal to 1. Because the preceding rows have performed or are performing the first data writing stage when the current row performs the second data writing stage, the second data writing stage can write the first data voltage of the preceding rows to perform data pre-charging. When the to-be-displayed picture is a solid color picture, the first data voltage is equal to the second data voltage, that is, the data voltage corresponding to the preceding rows is the same as the data voltage corresponding to the current row. When the to-be-displayed picture is a non-solid color picture, the first data voltage is different from the second data voltage.

[0153] Specifically, as shown in Figure 1 and Figure 5 In the second data writing stage t12, the second gate driving signal Scan2 on the second gate driving line S2 is at least once at an effective level, and the data writing module 11 is controlled to be turned on at least once, so that the data writing module 11 transmits the second data voltage to the control terminal of the driving module 12 at least once. The voltage at the first end of the driving module 12 is a first power voltage, which can be a positive voltage, and the second data voltage can be a negative voltage. Therefore, the current stress can be applied to the driving module 12, so that all the driving modules 12 are unified in the state of inputting the first data voltage in advance, thereby avoiding a large difference in driving current generated by the driving module 12 at the same gray scale, and improving display uniformity. By applying current stress to the driving module 12, the characteristics of the driving module 12 are improved, and the difference between the driving current generated by the driving module 12 and the driving current corresponding to the target brightness after switching the picture is large, thereby avoiding a large difference between the first frame brightness and the target brightness after switching the picture, and further improving the display effect of the display panel.

[0154] Figure 5 In the second data writing stage t12, the data writing module 11 is turned on once, but it is not limited thereto.

[0155] S203, in the second reset stage, controlling the first reset module to reset the control terminal of the driving module at least once.

[0156] For example, as shown in Figure 5 In the second reset stage t13, the first gate driving signal Scan1 on the first gate driving line S1 is at an effective level, and the first reset module 13 is controlled to reset the control terminal of the driving module 12.

[0157] S204. In the first data writing stage, the control data writing module writes the first data voltage to the control terminal of the drive module at least once.

[0158] For example, such as Figure 5 As shown, during the first data writing stage t14, the second gate drive signal Scan2 on the second gate drive line S2 is at an effective level, controlling the data writing module 11 to be turned on, so that the data writing module 11 transmits the first data voltage on the data line Data to the control terminal of the drive module 12.

[0159] Furthermore, by executing the second reset phase and the first data writing phase, the charge can be cleared after the data pre-charge (second data writing phase). When the first data voltage is written in the first data writing phase, that is, when the characteristics of the drive module 12 are restored, the first data voltage can be written, which can ensure that the drive module 12 generates the drive current better according to the written first data voltage.

[0160] In some implementations, optionally, during the second data writing stage, the data writing module writes the second data voltage to the control terminal of the drive module at least twice.

[0161] Figure 6 This is another driving timing diagram of a pixel circuit provided in an embodiment of the present invention, such as... Figure 6 As shown, during the second data writing stage t12, the second gate drive signal Scan2 on the second gate drive line S2 has two valid levels, controlling the data writing module 11 to be turned on twice, so that the data writing module 11 transmits the second data voltage to the control terminal of the drive module 12 twice. This increases the duration and frequency of applying current stress to the drive module 12, which can better improve the characteristics of the drive module 12, further reduce the difference between the drive current generated by the drive module 12 and the drive current corresponding to the target brightness, avoid a large difference between the brightness of the first frame and the target brightness after screen switching, and further improve the display effect of the display panel.

[0162] It should be noted that in some other embodiments, the data writing module 11 can also be controlled to be turned on multiple times during the second data writing stage t12, further increasing the duration and frequency of applying current stress to the driving module 12, which can better improve the characteristics of the driving module 12. This embodiment does not limit the number of effective levels in the second data writing stage t12.

[0163] The technical scheme of the embodiment can not only apply current stress to the driving module, but also unify the states of the driving modules in advance, so that the driving current generated by all the driving modules in the first frame after the picture switching is close to the current corresponding to the target brightness, and thus the brightness of the display panel in the first frame after the picture switching is close to the target brightness.

[0164] On the basis of the above technical scheme, the following describes the stages that the driving method can further include, but does not limit the present application.

[0165] Figure 7 is another structure schematic diagram of a pixel circuit provided by the embodiment of the present application. Figure 7 The pixel circuit further includes a light emitting module 14, and the driving module 12 is connected with the light emitting module 14.

[0166] Optionally, as shown in Figure 7 The pixel circuit further includes a light emitting control module 15, the light emitting control module 15 is connected between the first power supply VDD and the light emitting module 14, the control end of the light emitting control module 15 is connected with the third gate driving line Em, and the third gate driving signal EM provided by the third gate driving line Em is used to control the turn-on and turn-off of the light emitting control module 15.

[0167] Optionally, in one display frame, the driving method of the pixel circuit further includes:

[0168] In the light emitting stage, the driving module generates a driving current to make the light emitting module emit light in response to the driving current.

[0169] As shown in Figure 6 In the light emitting stage t15, the third gate signal EM is at an effective level, the light emitting control module 15 is controlled to be turned on, so that the first power supply VDD, the driving module 12, the light emitting control module 15, the light emitting module 14 and the second power supply VSS form a current loop, the driving module 12 generates a driving current, and the light emitting module 14 emits light in response to the driving current.

[0170] Optionally, as shown in Figure 7 The pixel circuit further includes a threshold compensation module 16, the control end of the threshold compensation module 16 is connected with the second gate driving line S2, and the threshold compensation module 16 is connected between the second end of the driving module 12 and the control end of the driving module 12.

[0171] Figure 7The first end of the data writing module 11 is connected with the driving module 12, as shown in the figure. When the second gate driving signal Scan2 provided by the second gate driving line S2 is at an effective level, the data writing module 11 and the threshold compensation module 16 are turned on, the data writing module 11 transmits the data voltage (the first data voltage or the second data voltage) to the control end of the driving module 12 through the driving module 12 and the threshold compensation module 16, so as to write the data voltage (the first data voltage or the second data voltage) to the control end of the driving module 12.

[0172] Optionally, as shown in the figure, the pixel circuit further comprises a storage module 17, the first end of the storage module 17 is connected with a direct current signal, and the second end of the storage module 17 is connected with the control end of the driving module 12. For example, the first end of the storage module 17 is connected with the first power supply VDD. The potential of the first end of the storage module 17 is constant, so that the potential of the control end of the driving module 12 can be maintained. Figure 7

[0173] Figure 8 is a flow chart of another driving method of the pixel circuit provided by the embodiment of the present application. Optionally, referring to Figure 8 In one display frame, the driving method of the pixel circuit comprises the following steps.

[0174] S301, in the first reset stage, the control end of the driving module is reset at least once by the first reset module.

[0175] Figure 9 is a driving timing diagram of another pixel circuit provided by the embodiment of the present application. As shown in the figure, in the first reset stage t21, the first gate driving signal Scan1 on the first gate driving line S1 is at an effective level, the first reset module 13 is turned on, and the control end of the driving module 12 is reset. Figure 9

[0176] S302, in the reset maintaining stage, the first reset module and the data writing module are turned off, so that the storage module maintains the potential of the control end of the driving module.

[0177] Specifically, as shown in the figure, in the reset maintaining stage t22, the first reset module 13 and the data writing module 11 are turned off, so that the storage module 17 maintains the potential of the control end of the driving module 12. Figure 9 ​​As shown, in the reset maintaining stage t22, the first gate drive signal Scan1 and the second gate drive signal Scan2 are both invalid level, and the first reset module 13 and the data writing module 11 are turned off. Because the first reset voltage is written to the control end of the drive module 12 in the first reset stage t21, the storage module 17 can maintain the potential of the control end of the drive module 12, so as to continuously apply a forward voltage stress to the drive module 12, and the drive module 12 can better recover the characteristics, that is, even if the characteristics of the drive module 12 are greatly deviated, the drive module 12 can also well recover the characteristics, so as to facilitate the drive current generated by the drive module 12 to be close to or equal to the current corresponding to the target brightness, thereby improving the display effect of the display panel.

[0178] In addition, the length of the reset maintaining stage can be adjusted according to actual needs, for example, according to the residual image degree of the display panel or the characteristic deviation degree of the drive module 12, so as to be applicable to different working states, thereby improving the applicability of the driving method of the pixel circuit.

[0179] S303, a second data writing stage is performed; in the second data writing stage, the data writing module writes a second data voltage to the control end of the drive module at least once.

[0180] As shown in FIG. 3, the second data writing stage t23 is performed after the reset maintaining stage t22. Figure 9 As shown, in the second data writing stage t23, the second gate drive signal Scan2 on the second gate drive line S2 has two valid levels, the data writing module 11 is turned on twice, and the data writing module 11 transmits the second data voltage to the control end of the drive module 12 twice.

[0181] S304, in a second reset stage, the first reset module is controlled to reset the control end of the drive module at least once.

[0182] As shown in FIG. 3, the second reset stage t24 is performed after the second data writing stage t23. Figure 9 As shown, in the second reset stage t24, the first gate drive signal Scan1 on the first gate drive line S1 is valid level, the first reset module 13 is turned on, and the control end of the drive module 12 is reset.

[0183] S305, in a first data writing stage, the data writing module is controlled to write a first data voltage to the control end of the drive module at least once.

[0184] As shown in FIG. 3, the first data writing stage t25 is performed after the second reset stage t24. Figure 9 As shown, in the first data writing stage t25, the second gate drive signal Scan2 on the second gate drive line S2 is valid level, the data writing module 11 is turned on, and the data writing module 11 transmits the first data voltage on the data line Data to the control end of the drive module 12.

[0185] ​​​​​​​​S306、In the light emitting stage, the driving module generates a driving current to make the light emitting module emit light in response to the driving current.

[0186] As Figure 9 shown, in the light emitting stage t26, the third gate signal EM is at an effective level, controlling the light emitting control module 15 to turn on, so that the first power supply VDD, the driving module 12, the light emitting control module 15, the light emitting module 14 and the second power supply VSS form a current loop, the driving module 12 generates a driving current according to the first data voltage, and the light emitting module 14 emits light in response to the driving current.

[0187] In another embodiment, Figure 10 is a flowchart of another driving method of the pixel circuit provided by the embodiment of the present application. Optionally, refer to Figure 10 In one display frame, the driving method of the pixel circuit comprises:

[0188] S401、In the first reset stage, the first reset module is controlled to reset the control end of the driving module at least once.

[0189] S402、In part of the reset maintenance stage, the first reset module is controlled to reset the control end of the driving module at least once, and in another part of the reset maintenance stage, the first reset module and the data writing module are controlled to turn off; wherein the other part of the time period is the time period between the end of the last reset of the control end of the driving module by the first reset module in the reset maintenance stage and the beginning of the second data writing stage.

[0190] Specifically, by controlling the first reset module 13 to reset the control end of the driving module 12 at least once in part of the reset maintenance stage, the number of times of applying reverse voltage stress to the driving module 12 can be increased, and the problem that the storage module 17 cannot well maintain the potential of the control end of the driving module 12, resulting in poor characteristic recovery, can be avoided. Moreover, when the gate driving circuit cannot output an invalid level for a long time period, the length of the reset maintenance stage can be ensured, and the characteristics of all driving modules 12 can be recovered.

[0191] Exemplarily, Figure 11 is a driving timing diagram of another pixel circuit provided by the embodiment of the present application, as Figure 11 shown, Figure 11 and Figure 9 the difference lies in that, in Figure 11In some embodiments, in the partial time period t221 of the reset maintaining stage t22, the first gate drive signal Scan1 is at an active level, and the first reset module 13 is controlled to reset the control terminal of the drive module 12 at least once; in the remaining time period of the reset stage t22, the first gate drive signal Scan1 and the second gate drive signal Scan2 are both at an inactive level, and the first reset module 13 and the data write module 11 are turned off. The other partial time period t222 is the time period between the partial time period t221 and the second data write stage t23. It should be noted that the time period in which the first gate drive signal Scan1 is at the active level in the reset stage t22 can be the beginning of the reset maintaining stage t22, the middle of the reset maintaining stage t22, or the part before the end of the reset maintaining stage t22, and the present embodiment is not limited in this regard.

[0192] S403, performing a second data write stage; in the second data write stage, the data write module writes a second data voltage to the control terminal of the drive module at least once.

[0193] S404, in a second reset stage, controlling the first reset module to reset the control terminal of the drive module at least once.

[0194] S405, in a first data write stage, controlling the data write module to write a first data voltage to the control terminal of the drive module at least once.

[0195] S406, in a light emitting stage, the drive module generates a drive current to make the light emitting module emit light in response to the drive current.

[0196] The technical solution of the present embodiment can increase the time length of applying the reverse voltage stress to the drive module by setting the reset maintaining stage after the first reset stage, and can ensure the characteristics of the drive module to recover. Moreover, the time length of the reset maintaining stage can be adjusted according to the residual image degree of the display panel, thereby improving the applicability of the driving method of the pixel circuit.

[0197] In other embodiments, the stages in the driving timing of the pixel circuit can be executed in other orders, and another possible execution order is described below, but the present application is not limited in this regard.

[0198] Optionally, the first data write stage can also be located before the first reset stage; the second reset stage is located before the first data write stage; in the first data write stage, the data write module writes a second data voltage to the control terminal of the drive module at least once; in the second data write stage, the data write module writes a first data voltage to the control terminal of the drive module at least once. For example, Figure 12 is another driving timing diagram of a pixel circuit provided by the present embodiment, as shown inFigure 12 as shown, Figure 12 different from Figure 9 the difference between the first data write stage t25 is before the first reset stage t21. Figure 12

[0199] Specifically, when the first data write stage t25 is before the first reset stage t21, the execution order of the driving method is the second reset stage t24, the first data write stage t25, the first reset stage t21, the reset maintenance stage t22, the second data write stage t23 and the light emitting stage t26. In this way, the control end of the driving module 12 can be reset in the second reset stage t24, and a reverse voltage stress is applied to the driving module 12 to improve the characteristics of the driving module 12. Then in the first data write stage t25, the second data voltage is transmitted to the control end of the driving module 12, a current stress is applied to the driving module 12, and the characteristics of the driving module 12 are further improved. Further, the first reset stage t21 and the reset maintenance stage t22 are executed to further improve the characteristics of the driving module 12, so that the characteristics of all driving modules 12 can be restored, and in the second data write stage t23, the first data voltage is written to the driving module 12 after the characteristics are restored, so that the driving current generated by the driving module 12 according to the first data voltage can be the same as the current corresponding to the target brightness, thereby improving the display effect of the display panel.

[0200] On the basis of the above technical solutions, optionally, before the reset maintenance stage, the driving method of the pixel circuit further comprises:

[0201] determining the duration of the reset maintenance stage according to the test parameter value of the display panel in which the pixel circuit is located; wherein the test parameter value at least includes the residual image value of the display panel.

[0202] Specifically, by measuring the brightness difference of the display panel before and after switching when the display panel switches from a non-pure color picture to a pure color picture, the residual image value of the display panel can be determined. In the test, the duration of the reset maintenance stage corresponding to the case where the residual image value is improved better can be tested, and the correspondence between the residual image value and the duration of the reset maintenance stage is stored. When driving the pixel circuit, if the display panel switches from a non-pure color picture to a pure color picture, the brightness value of the display panel can be obtained, and then the residual image value of the display panel can be determined. According to the correspondence between the residual image value and the duration of the reset maintenance stage, the duration of the reset maintenance stage can be determined. In this way, the duration of the reset maintenance stage determined according to the residual image value can better improve the characteristics of the driving module, and can reduce the residual image degree to a greater extent under any working condition, so that the first frame brightness can be improved when switching to the next picture, and the first frame brightness is closer to the target brightness.

[0203] ​On the basis of the above technical solutions, the following stages that the driving method can further include are described, but not as a limitation of the present application. Optionally, as shown in Figure 6 、 Figure 9 or Figure 11 Between the second reset stage and the first data writing stage, the driving method of the pixel circuit further includes:

[0204] In the transition stage, the data writing module and the first reset module are controlled to be turned off;

[0205] The length of the reset maintaining stage is greater than the length of the transition stage.

[0206] For example, as shown in Figure 6 、 Figure 9 or Figure 11 In the transition stage ty, the first gate driving signal Scan1 and the second gate driving signal Scan2 are both invalid. Because the driving module 12 has been applied with a reverse voltage stress for a long time in the first reset stage, the reset maintaining stage and the second reset stage, the bias state of the driving module 12 can be improved, and the reset maintaining in the transition stage ty does not need to be performed for a long time, which can avoid a long time of non-emitting stage. Moreover, by setting the length of the reset maintaining stage to be greater than the length of the transition stage, for example, the length of the reset maintaining stage is much greater than the length of the transition stage, that is, the reset maintaining stage lasts for a long time, it is ensured that the reset maintaining stage can improve the characteristics of all the driving modules 12, and the driving modules 12 with a large characteristic shift can also be well recovered.

[0207] Optionally, as shown in Figure 11 The length of the other part of the time period t222 is greater than the length of the transition stage ty. In this way, it is ensured that the reset maintaining stage maintains the reset of the driving module 12 for a long time, and the effect of improving the bias state of the driving module 12 is ensured, and the reset maintaining in the transition stage ty does not need to be performed for a long time, which can avoid a long time of non-emitting stage.

[0208] On the basis of the above technical solutions, in some embodiments, optionally, between the first reset stage and the reset maintaining stage, the method further includes performing at least one first reset stage. In this way, the number and length of times of applying the reverse voltage stress to the driving module 12 can be further increased, the characteristics of the driving module 12 can be further improved, the driving modules 12 with a large characteristic shift can also be well recovered, so that the characteristics of all the driving modules 12 are recovered to be consistent, which is beneficial to improving the display uniformity of the display panel.

[0209] In some embodiments, between the reset maintaining stage and the second data writing stage, the method further comprises performing at least one first reset stage and at least one reset maintaining stage. In this way, the characteristics of the driving module 12 can be improved to a greater extent, so that the driving module 12 with a larger characteristic offset can also better restore the characteristics, thereby making the characteristics of all driving modules 12 consistent, which is beneficial to improving the display uniformity of the display panel.

[0210] On the basis of the above technical solutions, the following stages that the driving method can further include are described, but are not as a limitation of the present application.

[0211] Optionally, as shown in Figure 7 The pixel circuit further includes a second reset module 18, which is connected with the light emitting module 14; for example, the control end of the second reset module 18 is connected with the first gate driving line S1, the first end of the second reset module 18 is connected with the second reset voltage Vref2, and the second end of the second reset module 18 is connected with the first end of the light emitting module 14.

[0212] Optionally, the driving method of the pixel circuit further includes:

[0213] In the first reset stage, the second reset module is controlled to reset the light emitting module at least once;

[0214] In the second reset stage, the second reset module is controlled to reset the light emitting module at least once.

[0215] Specifically, in the first reset stage, the first gate driving signal Scan1 is at an effective level, the second reset module 18 is controlled to be turned on, and the second reset module 18 transmits the second reset voltage Vref2 to the first end of the light emitting module 14 to reset the light emitting module 14 at least once. In the second reset stage, the first gate driving signal Scan1 is at an effective level, the second reset module 18 is controlled to be turned on, and the second reset module 18 resets the light emitting module 14 at least once. In this way, the residual charge at the first end of the light emitting module 14 can be cleared, so that the light emitting module 14 can display the target brightness more accurately.

[0216] The voltage difference between the second reset voltage Vref2 and the voltage at the second end of the light emitting module 14 (the voltage of the second power supply VSS) is less than the turn-on voltage of the light emitting module 14.

[0217] On the basis of the above technical solutions, optionally, the single effective pulse width of the control signal of the first reset module is the same;

[0218] The single effective pulse width of the control signal of the first reset module is n times the single effective pulse width of the control signal of the data writing module.

[0219] The control signal of the first reset module 13 is a first gate driving signal. The control signals of the first reset module are the same control signal, and the single effective pulse width of the same control signal is the same. The control signal of the data writing module 11 is a second gate driving signal.

[0220] Specifically, in the first reset stage and the second reset stage, the first reset module responds to the first gate driving signal, so the single effective pulse width of the first reset stage and the second reset stage is the same. Because multiple pixel circuit arrays are arranged, when data is written, it is written row by row, so the single effective pulse width of the control signal of the data writing module 11 is at most a row time, that is, the single effective pulse width of the control signal of the data writing module 11 is less than or equal to a row time. When the control end of the driving module 12 is reset, it can be reset row by row, or at least two rows can be reset at the same time, that is, the single effective pulse width of the control signal (the first gate driving signal) of the first reset module can be a row time, or two row times, or multiple row times. Therefore, the single effective pulse width of the control signal of the first reset module 13 is n times the single effective pulse width of the control signal of the data writing module 11. When the single effective pulse width of the control signal of the data writing module 11 is equal to a row time, n is an integer. When the single effective pulse width of the control signal of the data writing module 11 is less than a row time, n can not be an integer. In this way, the number of first gate driving signals can be reduced, the number of gate driving circuits can be reduced, and the space can be reduced.

[0221] Optionally, n is an integer greater than or equal to 1. At this time, the single effective pulse width of the control signal of the data writing module 11 is equal to a row time, which can realize sufficient data writing and ensure that the data voltage (the first data voltage or the second data voltage) is completely written to the driving module 12.

[0222] Optionally, n is 1 or 2.

[0223] In an embodiment, Figure 13 is another driving timing diagram of a pixel circuit provided by an embodiment of the present application, as shown in Figure 13 The single effective pulse width of the control signal (the first gate driving signal Scan1) of the first reset module 13 is the same as the single effective pulse width of the control signal (the second gate driving signal Scan2) of the data writing module 11, that is, the single effective pulse width of the control signal (the first gate driving signal Scan1) of the first reset module 13 is 1 times the single effective pulse width of the control signal (the second gate driving signal Scan2) of the data writing module 11.

[0224] In another embodiment,Figure 14 is a driving timing diagram of another pixel circuit provided by an embodiment of the present application, as shown in Figure 14 The single effective pulse width of the control signal (first gate drive signal Scan1) of the first reset module 13 is twice the single effective pulse width of the control signal (second gate drive signal Scan2) of the data writing module 11, so that the first gate drive signal Scan1 can simultaneously drive the first reset module 13 in two rows of pixel circuits to be turned on, which can reduce the number of gate drive circuits and save space.

[0225] In other embodiments, n can also be an integer greater than or equal to 3, and the first gate drive signal can simultaneously drive the first reset module in multiple rows of pixel circuits to be turned on, further reducing the number of gate drive circuits.

[0226] As shown in Figure 14 When n is 2, one first gate drive signal Scan1 corresponds to two rows of pixel circuits, and one second gate drive signal Scan2 corresponds to one row of pixel circuits, then the 2m-1th row of pixel circuits and the 2mth row of pixel circuits correspond to the mth first gate drive signal Scan1(m), the 2m-1th row of pixel circuits corresponds to the 2m-1th second gate drive signal Scan2(2m-1), and the 2mth row of pixel circuits corresponds to the 2mth second gate drive signal Scan2(2m). In the first data writing stage t24, the 2m-1th second gate drive signal Scan2(2m-1) and the 2mth second gate drive signal Scan2(2m) output effective levels in turn. In the second data writing stage t23, if the second data voltage is written to the control end of the drive module only once, then the 2m-1th second gate drive signal Scan2(2m-1) and the 2mth second gate drive signal Scan2(2m) output effective levels in turn. In the second data writing stage t23, if the second data voltage is written to the control end of the drive module at least twice, then the 2m-1th second gate drive signal Scan2(2m-1) and the 2mth second gate drive signal Scan2(2m) output effective levels alternately. That is, when the data voltage (first data voltage or second data voltage) is written at least twice, the data voltage (first data voltage or second data voltage) is alternately written to the adjacent two rows of pixel circuits, and data writing to the adjacent two rows of pixel circuits is realized. Wherein, m is an integer greater than or equal to 1.

[0227] In another embodiment, Figure 15 is a flow chart of another driving method of a pixel circuit provided by an embodiment of the present application, referring to Figure 15 In one display frame, the driving method of the pixel circuit comprises:

[0228] S501、in the first reset stage, control the first reset module to reset the control end of the driving module at least once.

[0229] Exemplary, Figure 16 is another driving timing diagram of a pixel circuit provided by the embodiment of the application, as Figure 16 As shown in the first reset stage t31, the first gate drive signal Scan1 on the first gate drive line S1 is at an effective level, and the first reset module 13 is controlled to conduct at least once, so that the first reset module 13 transmits the first reset voltage Vref1 to the control end of the driving module 12 at least once to reset the control end of the driving module 12 at least once. In this way, the residual charge of the last frame can be cleared, and a reverse voltage stress (opposite to the voltage stress when the driving module 12 is turned on) can be applied to the driving module 12, thereby improving the characteristics of the driving module 12, avoiding the residual image problem caused by the change of the characteristics of the driving module 12 when it is turned on in the last frame, and being beneficial to improving the display effect of the display panel where the pixel circuit is located. Moreover, the first reset module 13 can reset the control end of the driving module 12 multiple times in the first reset stage, so that the reverse voltage stress can be applied to the driving module 12 multiple times, and the characteristics of the driving module 12 can be better improved. Even the driving module 12 with a large characteristic offset can also be well restored, so that each driving module 12 can better restore the characteristics before generating the driving current.

[0230] S502、in the second data write stage, control the data write module to write the second data voltage to the control end of the driving module at least once.

[0231] Specifically, as Figure 16 shown in the second data write stage t32, the second gate drive signal Scan2 on the second gate drive line S2 is at an effective level at least once, and the data write module 11 is controlled to conduct at least once, so that the data write module 11 transmits the second data voltage to the control end of the driving module 12 at least once. The voltage at the first end of the driving module 12 is the first power voltage, which can be a positive voltage, and the second data voltage is a negative voltage, so that the current stress can be applied to the driving module 12, so that all the driving modules 12 are unified in the state under the first data voltage, and the difference between the driving currents generated by the driving modules 12 under the same gray scale is small, and the display uniformity can be improved. By applying the current stress to the driving module 12, the characteristics of the driving module 12 can be improved, and the difference between the driving current generated by the driving module 12 and the target brightness in the first frame after switching the picture can be avoided, and the difference between the brightness and the target brightness in the first frame after switching the picture can be avoided, and the display effect of the display panel can be further improved.

[0232] S503, In the first data writing stage, the control data writing module writes the first data voltage to the control terminal of the drive module at least once.

[0233] Specifically, such as Figure 16 As shown, during the first data writing stage t33, the second gate drive signal Scan2 on the second gate drive line S2 is at an effective level, controlling the data writing module 11 to be turned on, so that the data writing module 11 transmits the first data voltage on the data line Data to the control terminal of the drive module 12, so that the drive module 12 generates a drive current according to the first data voltage, and the light-emitting module 14 responds to the drive current to emit light.

[0234] The technical solution of this embodiment, by setting a first data writing stage and a second data writing stage, can not only apply current stress to the driving module, but also unify the state of each driving module in advance, so that the driving current generated by all driving modules in the first frame after the screen switch is close to the current corresponding to the target brightness, thereby making the brightness of the display panel in the first frame after the screen switch close to the target brightness.

[0235] Based on the above technical solutions, Figure 17 This is a flowchart of another pixel circuit driving method provided in an embodiment of the present invention. Optionally, refer to... Figure 17 Within a display frame, the driving methods for pixel circuits include:

[0236] S601. In the first reset phase, the first reset module is controlled to reset the control terminal of the drive module.

[0237] Figure 18 This is another driving timing diagram of a pixel circuit provided in an embodiment of the present invention, such as... Figure 18 As shown, in the first reset stage t41, the first gate drive signal Scan1 on the first gate drive line S1 is at an effective level, controlling the first reset module 13 to be turned on at least once, so that the first reset module 13 transmits the first reset voltage Vref1 to the control terminal of the drive module 12 at least once, and performs a reset on the control terminal of the drive module 12 at least once.

[0238] S602. During the reset maintenance phase, the first reset module and the data writing module are turned off so that the storage module maintains the potential of the control terminal of the drive module.

[0239] Specifically, such as Figure 18As shown, during the reset maintenance phase t42, both the first gate drive signal Scan1 and the second gate drive signal Scan2 are at invalid levels, and the first reset module 13 and the data writing module 11 are turned off. Because the first reset voltage is written to the control terminal of the drive module 12 during the first reset phase t41, the storage module 17 can maintain the potential of the control terminal of the drive module 12, thereby continuously applying positive voltage stress to the drive module 12. The drive module 12 can better recover its characteristics, and even if the characteristic deviation of the drive module 12 is large, it can still recover its characteristics well. This makes it easier for the drive current generated by the drive module 12 to be close to or equal to the current corresponding to the target brightness, thereby improving the display effect of the display panel.

[0240] Furthermore, the duration of the reset holding phase can be adjusted according to actual needs, such as the degree of image retention on the display panel or the degree of offset of the driving module 12, so as to be applicable to different working states and improve the applicability of the pixel circuit driving method.

[0241] S603. In the second data writing stage, the control data writing module writes the second data voltage to the control terminal of the drive module at least once.

[0242] Specifically, such as Figure 18 As shown, during the second data writing stage t43, the second gate drive signal Scan2 on the second gate drive line S2 has two valid levels, which controls the data writing module 11 to be turned on twice, so that the data writing module 11 transmits the second data voltage to the control terminal of the drive module 12 twice.

[0243] S604. In the first data writing stage, the control data writing module writes the first data voltage to the control terminal of the drive module at least once.

[0244] Specifically, such as Figure 18 As shown, during the first data writing stage t44, the second gate drive signal Scan2 on the second gate drive line S2 is at an effective level, controlling the data writing module 11 to be turned on, so that the data writing module 11 transmits the first data voltage on the data line Data to the control terminal of the drive module 12.

[0245] The technical solution of this embodiment, by setting a reset sustaining phase after the first reset phase, can increase the duration of applying reverse voltage stress to the driving module, thereby ensuring the recovery of the driving module's characteristics. Furthermore, the duration of the reset sustaining phase can be adjusted according to the degree of image retention on the display panel, thus improving the applicability of the pixel circuit driving method.

[0246] In another implementation, Figure 19 This is a flowchart of another pixel circuit driving method provided in an embodiment of the present invention. Optionally, refer to...Figure 19 In one display frame, the driving method of the pixel circuit comprises:

[0247] S701, in the first reset stage, the first reset module is controlled to reset the control end of the driving module.

[0248] S702, in a part of the reset maintenance stage, the first reset module is controlled to reset the control end of the driving module at least once, and in another part of the reset maintenance stage, the first reset module and the data writing module are controlled to be turned off; wherein the other part of the time period is the time period between the end of the last reset of the control end of the driving module by the first reset module in the reset maintenance stage and the beginning of the second data writing stage.

[0249] Exemplarily, Figure 20 is another driving timing diagram of a pixel circuit provided by the embodiment of the present application, as shown in Figure 20 , the difference between Figure 20 and Figure 18 is that, in Figure 20 , in a part of the reset maintenance stage t42, the first gate driving signal Scan1 is at an effective level, and the first reset module 13 is controlled to reset the control end of the driving module 12 at least once; in the remaining time period of the reset stage t42, the first gate driving signal Scan1 and the second gate driving signal Scan2 are both at an ineffective level, and the first reset module 13 and the data writing module 11 are turned off. The other part of the time period t422 is the time period between the part of the time period t421 and the second data writing stage t43. It should be noted that the time period in which the first gate driving signal Scan1 is at the effective level in the reset stage t42 can be the beginning part of the reset maintenance stage t42, can be the middle part of the reset maintenance stage t42, or can be the part before the end of the reset maintenance stage t42, and the embodiment is not limited thereto.

[0250] In this way, the number of times of applying reverse voltage stress to the driving module 12 can be increased, and the problem that the storage module 17 cannot well maintain the potential of the control end of the driving module 12, resulting in poor characteristic recovery, can be avoided. Moreover, when the gate driving circuit cannot output an ineffective level for a long time period, the length of the reset maintenance stage can be ensured, and the characteristics of all the driving modules 12 can be recovered.

[0251] S703, in the second data writing stage, the data writing module is controlled to write the second data voltage to the control end of the driving module at least once.

[0252] S704, in the first data writing stage, the data writing module is controlled to write the first data voltage to the control end of the driving module at least once.

[0253] In another embodiment,Figure 21 is a flowchart of another driving method of the pixel circuit provided by an embodiment of the present application, referring to Figure 21 In one display frame, the driving method of the pixel circuit comprises:

[0254] S801, in the first reset stage, the first reset module is controlled to reset the control end of the driving module.

[0255] Figure 22 is a driving timing diagram of another pixel circuit provided by an embodiment of the present application, as Figure 12 shown, in the first reset stage t51, the first gate drive signal Scan1 on the first gate drive line S1 is at an effective level, the first reset module 13 is controlled to conduct at least once, so that the first reset module 13 transmits the first reset voltage Vref1 to the control end of the driving module 12 at least once, and the control end of the driving module 12 is reset at least once.

[0256] S802, in the reset maintenance stage, the first reset module and the data writing module are controlled to be turned off, so that the storage module maintains the potential of the control end of the driving module.

[0257] Specifically, as Figure 22 shown, in the reset maintenance stage t52, the first gate drive signal Scan1 and the second gate drive signal Scan2 are both at an ineffective level, and the first reset module 13 and the data writing module 11 are turned off. Because the first reset voltage is written to the control end of the driving module 12 in the first reset stage t51, the storage module 17 can maintain the potential of the control end of the driving module 12, so as to continuously apply a forward voltage stress to the driving module 12, and the driving module 12 can better recover the characteristics. Even if the driving module 12 has a large characteristic offset, the driving module 12 can also well recover the characteristics, so that the driving current generated by the driving module 12 is close to or equal to the current corresponding to the target brightness, thereby improving the display effect of the display panel.

[0258] Moreover, the length of the reset maintenance stage can be adjusted according to actual needs, for example, according to the residual image degree of the display panel or the offset degree of the driving module 12, so as to be applicable to different working states, thereby improving the applicability of the driving method of the pixel circuit.

[0259] S803, in the first data writing stage, the data writing module is controlled to write the first data voltage to the control end of the driving module at least once.

[0260] As Figure 22As shown, during the first data writing stage t53, the second gate drive signal Scan2 on the second gate drive line S2 is at an effective level, controlling the data writing module 11 to be turned on, so that the data writing module 11 transmits the first data voltage on the data line Data to the control terminal of the drive module 12.

[0261] In another implementation, Figure 23 This is a flowchart of another pixel circuit driving method provided in an embodiment of the present invention, see reference. Figure 23 Within a display frame, the driving methods for pixel circuits include:

[0262] S901. In the first reset phase, the first reset module is controlled to reset the control terminal of the drive module.

[0263] S902. During a portion of the reset maintenance phase, the first reset module is controlled to reset the control terminal of the drive module at least once. During another portion of the reset maintenance phase, the first reset module and the data writing module are controlled to shut down. The other portion of the time is the period between the end of the last reset of the control terminal of the drive module by the first reset module during the reset maintenance phase and the start of the first data writing phase.

[0264] For example, Figure 24 This is another driving timing diagram of a pixel circuit provided in an embodiment of the present invention, such as... Figure 24 As shown, Figure 24 and Figure 22 The difference is that, in Figure 24 In the reset sustain phase t52, during a portion of time t521, the first gate drive signal Scan1 is active, controlling the first reset module 13 to reset the control terminal of the drive module 12 at least once. During the remaining time of reset phase t52, both the first gate drive signal Scan1 and the second gate drive signal Scan2 are inactive, and the first reset module 13 and the data writing module 11 are turned off. Another portion of time t522 is the period between the portion of time t521 and the first data writing phase t53. It should be noted that the period during reset phase t52 when the first gate drive signal Scan1 is active can be the beginning of reset sustain phase t52, the middle of reset sustain phase t52, or the period before the end of reset sustain phase t52; this embodiment does not impose any limitation on this.

[0265] This increases the number of times reverse voltage stress is applied to the drive module 12, preventing the storage module 17 from failing to maintain the potential of the control terminal of the drive module 12, which would result in poor characteristic recovery. Furthermore, when the gate drive circuit cannot output an invalid level for a prolonged period, the duration of the reset maintenance phase can be guaranteed, ensuring that the characteristics of all drive modules 12 are restored.

[0266] S903、in the first data write stage, the control data write module writes the first data voltage to the control end of the driving module at least once.

[0267] In some embodiments, Figure 25 is another driving timing diagram of a pixel circuit provided by the embodiments of the present application, as Figure 25 As shown, the single effective pulse width of the first gate driving signal Scan1 is the same as the single effective pulse width of the second gate driving signal Scan2. As Figure 25 As shown, the driving timing of the pixel circuit in one display frame includes the following stages.

[0268] In the first reset stage t61, the first gate driving signal Scan1 transmits three effective levels to the first reset module 13, controlling the first reset module 13 to reset the control end of the driving module 12 three times.

[0269] In the reset maintenance stage t62, the first gate driving signal Scan1 and the second gate driving signal Scan2 are both invalid levels, controlling the first reset module 13 and the data write module 11 to turn off.

[0270] In the second reset stage t63, the first gate driving signal Scan1 transmits three effective levels to the first reset module 13, controlling the first reset module 13 to reset the control end of the driving module 12 three times.

[0271] In the first data write stage t64, the second gate driving signal Scan2 transmits three effective levels to the data write module 11, controlling the data write module 11 to write the first data voltage to the control end of the driving module 12 three times. When the second reset stage t63 and the first data write stage t64 both include multiple effective levels, the second reset stage t63 and the first data write stage t64 can be alternately performed, that is, in the second reset stage t63 and the first data write stage t64, the first gate driving signal Scan1 and the second gate driving signal Scan2 alternately output effective levels.

[0272] In the light emitting stage t65, the third gate signal EM is an effective level, controlling the light emitting control module 15 to turn on, so that the first power supply VDD, the driving module 12, the light emitting control module 15, the light emitting module 14 and the second power supply VSS form a current loop, the driving module 12 generates a driving current, and the light emitting module 14 emits light in response to the driving current.

[0273] Thus, the control end of the driving module 12 is reset multiple times in the first reset stage t61 and the second reset stage t63, and the electrical stress applied to the driving module 12 is maintained in the reset maintaining stage t62, so that the control end of the driving module 12 is subjected to the negative gate bias stress (NBS) for a long time, the influence of the positive gate bias stress (PBS) caused by the long-time conduction of the driving module 12 in the previous frame display process is reduced, the characteristics of the driving module 12 can be restored before the light emitting stage, and thus the display effect of the display panel is improved. Moreover, the reset process of the control end of the driving module 12 is separated from the data writing process, so that the invalid reset condition is avoided.

[0274] It should be noted that in the timing diagrams provided in the embodiments of the present application, the active level is low and the invalid level is high, but this is not limited, in some other embodiments, the active level can also be high and the invalid level can also be low.

[0275] The embodiment of the present application also provides a display panel, which comprises a plurality of first gate driving circuits 21, a plurality of second gate driving circuits 22 and a plurality of pixel circuits 10; the pixel circuit 10 comprises a data writing module 11, a driving module 12 and a first reset module 13; the data writing module 11 is connected with the driving module 12, and the first reset module 13 is connected with the control end of the driving module 12.

[0276] Figure 26 is a structural schematic diagram of a display panel provided by the embodiment of the present application, referring to Figure 26 A first gate driving circuit 21 is connected with the first reset module 13 of k rows of pixel circuits 10, and the first gate driving circuit 21 is used for transmitting a first gate driving signal Scan1 to the first reset module 13 of the corresponding k rows of pixel circuits 10.

[0277] A second gate driving circuit 22 is connected with the data writing module 11 of a row of pixel circuits 10, and the second gate driving circuit 22 is used for transmitting a second gate driving signal Scan2 to the data writing module 11 of the corresponding row of pixel circuits 10.

[0278] The single active pulse width of the first gate driving signal Scan1 is n times of the single active pulse width of the second gate driving signal Scan2.

[0279] Specifically, a second gate drive circuit 22 is connected with the data writing module 11 of a row of pixel circuits 10, so that the second gate drive signal output by the second gate drive circuit 22 drives the data writing module 11 in a row of pixel circuits 10, and realizes the row-by-row writing of the data voltage (first data voltage or second data voltage). The first gate drive circuit 21 is connected with the first reset module 13 of k rows of pixel circuits 10, can simultaneously transmit the first gate drive signal Scan1 to k rows of pixel circuits 10, can reduce the number of first gate drive signals Scan1, reduce the number of first gate drive circuits 21, and is beneficial to reduce the occupied area. The second gate drive circuit 22 is connected with the data writing module 11 of a row of pixel circuits 10, and the second gate drive signal Scan2 can be the same as one row of time, or can be less than one row of time, that is, the single effective pulse width of the second gate drive signal Scan2 is less than or equal to one row of time. And the single effective pulse width of the first gate drive signal Scan1 is k times of one row of time, so when the single effective pulse width of the second gate drive signal Scan2 is equal to one row of time, n is the same as k. When the single effective pulse width of the second gate drive signal Scan2 is less than one row of time, n is greater than k, and n is not an integer.

[0280] In an embodiment, optionally, k = n = 2. As shown in Figure 14 the single effective pulse width of the first gate drive signal Scan1 is twice the single effective pulse width of the second gate drive signal Scan2, so that the first gate drive signal can simultaneously drive the first reset module in two rows of pixel circuits to be turned on, can reduce the number of gate drive circuits, and save space. And k = n, that is, the single effective pulse width of the second gate drive signal Scan2 is equal to one row of time, can sufficiently write the data voltage (first data voltage or second data voltage), and ensure the integrity of the writing of the data voltage (first data voltage or second data voltage).

[0281] In another embodiment, optionally, k = n = 1. Figure 27 is another structure schematic diagram of a display panel provided by an embodiment of the application, referring to Figure 27 a first gate drive circuit 21 is connected with the first reset module of a row of pixel circuits 10, and the first gate drive circuit 21 is used for transmitting the first gate drive signal Scan1 to the first reset module 13 corresponding to a row of pixel circuits 10;

[0282] a second gate drive circuit 22 is connected with the data writing module 11 of a row of pixel circuits 10, and the second gate drive circuit 22 is used for transmitting the second gate drive signal Scan2 to the data writing module 11 corresponding to a row of pixel circuits 10;

[0283] The single effective pulse width of the first gate drive signal Scan1 is the same as the single effective pulse width of the second gate drive signal Scan2.

[0284] Specifically, the single effective pulse width of the first gate drive signal is the same as the single effective pulse width of the second gate drive signal, i.e., the single effective pulse width of the first gate drive signal is 1 times the single effective pulse width of the second gate drive signal. In this way, the row-by-row reset drive module can be realized, and the data voltage (the first data voltage or the second data voltage) can be written to the control end of the drive module row by row, facilitating row-by-row control. Moreover, k = n, i.e., the single effective pulse width of the second gate drive signal Scan2 is equal to the row time, and the data voltage (the first data voltage or the second data voltage) can be fully written, ensuring the integrity of the data voltage (the first data voltage or the second data voltage) written.

[0285] Optionally, as shown in Figure 26 and Figure 27 , the display panel further includes a third gate drive circuit 23, which is connected with the light-emitting control modules 15 of the two rows of pixel circuits 10 and provides light-emitting control signals for the light-emitting control modules 15. In this way, the number of third gate drive circuits 23 can be reduced, further saving space. In other embodiments, one third gate drive circuit 23 can also be connected with one row of pixel circuits 10, and the present embodiment is not limited in this regard.

[0286] Optionally, as shown in Figure 26 and Figure 27 , the pixel circuit 10 can be located in the display area AA of the display panel, and the first gate circuit 21, the second gate circuit 22, and the third electrode circuit 23 can be the non-display area NA of the display panel. Figure 26 and Figure 27 In order to illustrate the first gate circuit 21, the second gate circuit 22, and the third electrode circuit 23, the non-display NA is drawn to be larger, but the size of the non-display area NA is not limited, and the proportional relationship between the size of the display area AA and the size of the non-display area NA is not limited.

[0287] It should be noted that, due to limited space, Figure 26 and Figure 27 , only the first reset module 13, the data writing module 11, and the light-emitting control module 15 of the pixel circuit 10 are shown, and other modules and the connection relationship between the modules are not shown. The specific structure of the pixel circuit 10 can refer to Figure 1 or Figure 7 . The structure of the pixel circuit 10 that can be included in each module in Figure 7 will be described below, but this is not a limitation on the present application.

[0288] Figure 28 is another structure diagram of a pixel circuit provided by an embodiment of the present application, as shown in the figure, the data writing module 11 includes a data writing transistor T1, the control electrode of the data writing transistor T1 is connected with the second gate driving line S2, the first electrode of the data writing transistor T1 is connected with the data line Data, and the second electrode of the data writing transistor T1 is connected with the first end of the driving module 12. Figure 28

[0289] The driving module 12 includes a driving transistor T2.

[0290] The first reset module 13 includes a first reset transistor T3, the control electrode of the first reset transistor T3 is connected with the first gate driving line S1, the first electrode of the first reset transistor T3 is connected with the first reset voltage Vref1, and the second electrode of the first reset transistor T3 is connected with the control electrode of the driving transistor T2; the first reset transistor T3 can be a double-gate transistor.

[0291] The light emitting module 14 includes a light emitting diode D1.

[0292] The light emitting control module 15 includes a first light emitting control transistor T4 and a second light emitting control transistor T5, the first light emitting control transistor T4 is connected between the first power supply VDD and the first electrode of the driving transistor T2, and the second light emitting control transistor T5 is connected between the second electrode of the driving transistor T2 and the first electrode of the light emitting diode D1; the control electrodes of the first light emitting control transistor T4 and the second light emitting control transistor T5 are connected with the third gate driving line Em; and the second electrode of the light emitting diode D1 is connected with the second power supply VSS.

[0293] The threshold compensation module 16 includes a threshold compensation transistor T6, the threshold compensation transistor T6 is connected between the first electrode of the driving transistor T2 and the control electrode of the driving transistor T2, and the control electrode of the threshold compensation transistor T6 is connected with the second gate driving line S2; the threshold compensation transistor T6 can be a double-gate transistor.

[0294] The storage module 17 includes a storage capacitor C1, the first electrode of the storage capacitor C1 is connected with the first power supply VDD, and the second electrode of the storage capacitor C1 is connected with the control electrode of the driving transistor T2.

[0295] The second reset module 18 includes a second reset transistor T7, the control electrode of the second reset transistor T7 is connected with the first gate driving line S1, the first electrode of the second reset transistor T7 is connected with the second reset voltage Vref2, and the second electrode of the second reset transistor T7 is connected with the first electrode of the light emitting diode D1.

[0296] ​Specifically, in the first reset stage, the first gate drive signal provided by the first gate drive line S1 is at least one active level, so as to control the first reset transistor T1 to be conductive at least once, and control the second reset transistor T7 to be conductive at least once, so that the first reset transistor T1 resets the control electrode of the drive transistor T2 at least once, and the second reset transistor T7 resets the first electrode of the light emitting diode D1 at least once. In the second reset stage, the first gate drive signal provided by the first gate drive line S1 is at least one active level, so as to control the first reset transistor T1 to be conductive at least once, and control the second reset transistor T7 to be conductive at least once, so that the first reset transistor T1 resets the control electrode of the drive transistor T2 at least once, and the second reset transistor T7 resets the first electrode of the light emitting diode D1 at least once. Thus, the control electrode of the drive transistor T2 is reset at least twice, the time length and the number of times of applying the reverse voltage stress to the drive transistor T2 can be increased, even the drive transistor T2 with large characteristic shift can also be well restored in characteristics, so that each drive transistor T2 can be well restored in characteristics, the drive currents generated by different drive transistors T2 under the same gray scale tend to be consistent, the luminance of different light emitting diodes D1 tends to be consistent, the display uniformity of the display panel can be improved, the residual image can be avoided, and the display effect of the display panel is improved.

[0297] In the first data writing stage, the second gate drive signal provided by the second gate drive line S2 is at least one active level, so as to control the data writing transistor T1 and the threshold compensation transistor T6 to be conductive at least once, so that the data writing transistor T1 transmits the data voltage (the first data voltage or the second data voltage) on the data line Data to the control electrode of the drive transistor T2 through the drive transistor T2 and the threshold compensation transistor T6 at least once.

[0298] In the light emitting stage, the third gate drive signal provided by the third gate drive line Em is an active level, the first light emitting control transistor T4 and the second light emitting control transistor T5 are conductive, so that the drive transistor T2 generates a drive current, and the light emitting diode D1 emits light in response to the drive transistor T2.

[0299] It should be noted that, Figure 28 All the transistors are P-type transistors in the above-mentioned embodiments, but are not limited thereto. In some other embodiments, all the transistors of the pixel circuit can be N-type transistors, or part of the transistors can be N-type transistors and the other part can be P-type transistors.

[0300] It should be understood that the various forms of flow shown above can be used to reorder, add, or remove steps. For example, the steps recited in the present application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0301] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A driving method of a pixel circuit, characterized by, The pixel circuit comprises a data writing module, a driving module and a first reset module; the data writing module is connected with the driving module, and the first reset module is connected with a control end of the driving module; In one display frame, the method comprises: In a first reset stage, the first reset module is controlled to reset the control end of the driving module at least once; In a second reset stage, the first reset module is controlled to reset the control end of the driving module at least once; In a first data writing stage, the data writing module is controlled to write a first data voltage to the control end of the driving module at least once; The method further comprises: between the first reset stage and the second reset stage, a second data writing stage is performed; The pixel circuit further comprises a storage module, a first end of the storage module is connected with a direct current signal, and a second end of the storage module is connected with the control end of the driving module; between the first reset stage and the second data writing stage, the method further comprises: In a reset maintaining stage, the first reset module and the data writing module are controlled to be turned off, so that the storage module maintains the potential of the control end of the driving module; Or, in part of the reset maintaining stage, the first reset module is controlled to reset the control end of the driving module at least once, and in another part of the reset maintaining stage, the first reset module and the data writing module are controlled to be turned off; wherein the other part of the time period is the time period between the end of the last reset of the control end of the driving module by the first reset module in the reset maintaining stage and the beginning of the second data writing stage; Before the reset maintaining stage, the method further comprises: The length of the reset maintaining stage is determined according to a test parameter value of a display panel in which the pixel circuit is located; wherein the test parameter value at least comprises a residual image value of the display panel.

2. The method of claim 1, wherein, In the second data writing stage, the data writing module writes a second data voltage to the control end of the driving module at least once; The pixel circuit further comprises a light emitting module, the driving module is connected with the light emitting module; the method further comprises: In a light emitting stage, the driving module generates a driving current, so that the light emitting module emits light in response to the driving current.

3. The method of claim 2, wherein, In the second data writing stage, the data writing module writes a second data voltage to the control end of the driving module at least twice.

4. The method of claim 1, wherein, The first data writing stage can also be located before the first reset stage; in the first data writing stage, the data writing module writes a second data voltage to the control end of the driving module at least once; in the second data writing stage, the data writing module writes a first data voltage to the control end of the driving module at least once; wherein the second reset stage is located before the first data writing stage.

5. The method of claim 1, wherein, Between the second reset stage and the first data write stage, the method further comprises: In the transition stage, the data write module and the first reset module are controlled to be turned off; The duration of the reset maintenance stage is greater than the duration of the transition stage.

6. The method of claim 5, wherein, The duration of the other part of the period is greater than the duration of the transition stage.

7. The method of claim 1, wherein, Between the first reset stage and the reset maintenance stage, the method further comprises performing at least one first reset stage; Or, between the reset maintenance stage and the second data write stage, the method further comprises performing at least one first reset stage and at least one reset maintenance stage.

8. The method of claim 1, wherein, The pixel circuit further comprises a second reset module connected with the light-emitting module; the method further comprises: In the first reset stage, the second reset module is controlled to reset the light-emitting module at least once; In the second reset stage, the second reset module is controlled to reset the light-emitting module at least once.

9. The method of claim 1, wherein, The single effective pulse width of the control signal of the first reset module is the same; The single effective pulse width of the control signal of the first reset module is n times the single effective pulse width of the control signal of the data write module; The n is an integer greater than or equal to 1.

10. The method of claim 9, wherein, The n is 1 or 2.

11. A driving method of a pixel circuit, characterized by, The pixel circuit comprises a data write module, a driving module and a first reset module; the data write module is connected with the driving module, and the first reset module is connected with the control end of the driving module; In one display frame, the method comprises: In the first reset stage, the first reset module is controlled to reset the control end of the driving module at least once; In the second data write stage, the data write module is controlled to write a second data voltage to the control end of the driving module at least once; In the first data write stage, the data write module is controlled to write a first data voltage to the control end of the driving module at least once; Between the second data write stage and the first data write stage, the method further comprises: In the second reset stage, the first reset module is controlled to reset the control end of the driving module at least once; In the second data write stage, the data write module writes a second data voltage to the control end of the driving module at least twice; The first data write stage can also be located before the first reset stage; in the first data write stage, the data write module writes a second data voltage to the control end of the driving module at least once; in the second data write stage, the data write module writes a first data voltage to the control end of the driving module at least once; wherein, the second reset stage is located before the first data write stage; The pixel circuit further comprises a second reset module connected with the light-emitting module; the method further comprises: In the first reset stage, the second reset module is controlled to reset the light-emitting module at least once; In the second reset stage, the second reset module is controlled to reset the light-emitting module at least once. In the second reset stage, the second reset module is controlled to reset the light emitting module at least once.

12. The method of claim 11, wherein, The pixel circuit further comprises a storage module, a first end of the storage module is connected to a direct current signal, and a second end of the storage module is connected to the control end of the driving module; between the first reset stage and the second data writing stage, the method further comprises: In the reset maintaining stage, the first reset module and the data writing module are controlled to be turned off, so that the storage module maintains the potential of the control end of the driving module; Alternatively, in part of the reset maintaining stage, the first reset module is controlled to reset the control end of the driving module at least once, and in another part of the reset maintaining stage, the first reset module and the data writing module are controlled to be turned off; wherein the other part of the time period is the time period between the end of the last reset of the control end of the driving module by the first reset module in the reset maintaining stage and the beginning of the second data writing stage.

13. The method of claim 11, wherein, The pixel circuit further comprises a light emitting module, and the driving module is connected to the light emitting module; the method further comprises: In the light emitting stage, the driving module generates a driving current, so that the light emitting module emits light in response to the driving current.

14. The method of claim 12, wherein, Between the second reset stage and the first data writing stage, the method further comprises: In the transition stage, the data writing module and the first reset module are controlled to be turned off; The length of the reset maintaining stage is greater than the length of the transition stage.

15. The method of claim 14, wherein, The length of the other part of the time period is greater than the length of the transition stage.

16. The method of claim 12, wherein, Before the reset maintaining stage, the method further comprises: The length of the reset maintaining stage is determined according to a test parameter value of a display panel in which the pixel circuit is located; wherein the test parameter value at least comprises a residual image value of the display panel.

17. The method of claim 12, wherein, Between the first reset stage and the reset maintaining stage, the method further comprises executing at least one first reset stage; Alternatively, between the reset maintaining stage and the second data writing stage, the method further comprises executing at least one first reset stage and at least one reset maintaining stage.

18. The method of claim 11, wherein, The single effective pulse width of the control signal of the first reset module is the same; The single effective pulse width of the control signal of the first reset module is n times the single effective pulse width of the control signal of the data writing module; The n is an integer greater than or equal to 1.

19. The method of claim 18, wherein, The n is 1 or 2.

20. A driving method of a pixel circuit, characterized by, The pixel circuit comprises a data writing module, a driving module, a first reset module and a storage module; the data writing module is connected to the driving module, and the first reset module is connected to the control end of the driving module; A first end of the storage module is connected to a direct current signal, and a second end of the storage module is connected to the control end of the driving module; In one display frame, the method comprises: In the first reset stage, the first reset module is controlled to reset the control end of the driving module at least once; In the reset maintaining stage, the first reset module and the data writing module are controlled to be turned off, so that the storage module maintains the potential of the control terminal of the driving module; or, in a part of the reset maintaining stage, the first reset module is controlled to reset the control terminal of the driving module at least once, and in another part of the reset maintaining stage, the first reset module and the data writing module are controlled to be turned off; In the first data writing stage, the data writing module is controlled to write a first data voltage to the control terminal of the driving module at least once; The other part of the time period is a time period between the end of the last reset of the control terminal of the driving module by the first reset module in the reset maintaining stage and the start of the first data writing stage. Between the reset maintaining stage and the first data writing stage, the method further comprises: In the second reset stage, the first reset module is controlled to reset the control terminal of the driving module at least once; Between the second reset stage and the first data writing stage, the method further comprises: In the transition stage, the data writing module and the first reset module are controlled to be turned off; The length of the reset maintaining stage is greater than the length of the transition stage; The length of the other part of the time period is greater than the length of the transition stage.

21. The method of claim 20, wherein, Between the reset maintaining stage and the first data writing stage, the method further comprises: In the second data writing stage, the data writing module is controlled to write a second data voltage to the control terminal of the driving module at least once; the other part of the time period is a time period between the end of the last reset of the control terminal of the driving module by the first reset module in the reset maintaining stage and the start of the second data writing stage.

22. The method of claim 20, wherein, The first data writing stage can also be located before the first reset stage; in the first data writing stage, the data writing module writes a second data voltage to the control terminal of the driving module at least once; in the second data writing stage, the data writing module writes a first data voltage to the control terminal of the driving module at least once; the second reset stage is located before the first data writing stage.

23. The method of claim 22, wherein, In the second data writing stage, the data writing module writes a second data voltage to the control terminal of the driving module at least twice; The pixel circuit further comprises a light emitting module, the driving module is connected with the light emitting module; the method further comprises: In the light emitting stage, the driving module generates a driving current, so that the light emitting module emits light in response to the driving current.

24. The method of claim 20, wherein, Before the reset maintaining stage, the method further comprises: The length of the reset maintaining stage is determined according to a test parameter value of a display panel in which the pixel circuit is located; the test parameter value at least comprises a residual image value of the display panel.

25. The method of claim 21, wherein, Between the first reset stage and the reset maintaining stage, the method further comprises executing at least one first reset stage; Or, between the reset maintenance stage and the second data write stage, the method further comprises performing at least one first reset stage and at least one reset maintenance stage.

26. The method of claim 20, wherein, The pixel circuit further comprises a second reset module connected with the light-emitting module; the method further comprises: In the first reset stage, controlling the second reset module to reset the light-emitting module at least once; In the second reset stage, controlling the second reset module to reset the light-emitting module at least once.

27. The method of claim 20, wherein, The single effective pulse width of the control signal of the first reset module is the same; The single effective pulse width of the control signal of the first reset module is n times of the single effective pulse width of the control signal of the data write module; The n is an integer greater than or equal to 1.

28. The method of claim 27, wherein, The n is 1 or 2.

29. A display panel, comprising: The pixel circuit comprises a data write module, a driving module and a first reset module; the data write module is connected with the driving module, and the first reset module is connected with the control end of the driving module; the pixel circuit is driven by the driving method of the pixel circuit according to any one of claims 1-28; One first gate drive circuit is connected with the first reset module of k rows of pixel circuits, and the first gate drive circuit is used for transmitting a first gate drive signal to the first reset module of the corresponding k rows of pixel circuits; One second gate drive circuit is connected with the data write module of one row of pixel circuits, and the second gate drive circuit is used for transmitting a second gate drive signal to the data write module of the corresponding one row of pixel circuits; The single effective pulse width of the first gate drive signal is n times of the single effective pulse width of the second gate drive signal.

30. The display panel of claim 29, wherein, The k is an integer greater than or equal to 1, and the n is an integer greater than or equal to 1.

31. The display panel of claim 29, wherein, The k is equal to the n.

32. The display panel of claim 29, wherein, k=n=2.

33. The display panel of claim 29, wherein, k=n=1.

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