Filter circuit, voltage filter control circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of electronic circuits, in particular to a filter circuit, a voltage filter control circuit, a chip and electronic equipment. The filter circuit comprises a counter, a first data selector, a digital operation circuit and a register, the counter is used for receiving the counting enable signal, outputting a counting mark value to the first data selector, determining a corresponding current logic operation mode according to the current counting mark value, and performing logic operation on the intermediate input parameter according to the current logic operation mode to obtain a first voltage error value after filtering processing; by adopting the filter circuit provided by the invention, required logical operation can be completed by virtue of the first data selector and the digital operation circuit, so that the first voltage error value is output, and the filtered voltage signal is adjusted according to the first voltage error value, so that the set frequency component in the output voltage signal is filtered out; in this way, complex filter coefficients do not need to be configured, a processor with higher computing power does not need to be used, and hardware cost is saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, and in particular to a filter circuit, a voltage filter control circuit, a chip and an electronic device. BACKGROUND

[0002] In the application fields such as PFC (Power Factor Correction Controller, PFC for short) controllers, it is usually required to filter out the 50Hz or 60Hz power frequency components contained in the signals in the loop control. Since the power frequency is low, the low-pass filter characteristic (LPF) of the traditional proportional-integral (PI) controller cannot realize the function of filtering out the low-frequency components, and therefore a bandstop filter (BSF) is usually used to realize the filtering of the specific frequency components in the signals.

[0003] In the related art, in order to filter out the 50Hz or 60Hz power frequency components contained in the power signals, a processor is mainly used, and then two sets of different filter coefficients are calculated by using a software method, which results in a relatively cumbersome filter coefficient configuration process and requires a large amount of information processing resources and memory in the processor, thereby affecting the processing efficiency of the processor on other data information. If a processor with higher computing power is used to realize this, the hardware cost of the processor is relatively high. Therefore, the filtering method for specific frequencies in the power in the related art is difficult to meet most application scenarios. SUMMARY

[0004] The present application provides a filter circuit, a voltage filter control circuit, a chip and an electronic device to solve the technical problems of a relatively cumbersome process and a relatively high hardware cost when a processor is used to configure filter coefficients by using a software method in the related art.

[0005] In a first aspect, the present application provides a filter circuit, which is used in a power factor correction controller and is used to filter out one or more set frequency components in an output voltage signal. The filter circuit comprises a counter, a first data selector, a digital operation circuit and a register. The counter is configured to receive a count enable signal and output a set of count flag values to the first data selector in sequence under the triggering of the count enable signal, wherein one current count flag value is output to the first data selector in each operation iteration period. The first data selector is configured to receive initial input data and the current count flag value, select at least two data information in the initial input data as intermediate input parameters of the current operation iteration period according to the current count flag value, and output the intermediate input parameters to the digital operation circuit; The digital operation circuit is configured to receive the intermediate input parameters, determine a corresponding current logic operation mode according to the current count flag value, perform logic operation on the intermediate input parameters according to the current logic operation mode to obtain intermediate output parameters, and output the intermediate output parameters to the register. The digital operation circuit is further configured to, when the current count flag value is the last one in the group of count flag values, take a result of the current logic operation as a first voltage error value after filtering processing; and the first voltage error value is used as a control compensation amount to adjust a filtered voltage signal, so as to filter out the set frequency component in the output voltage signal.

[0006] In a possible design, the digital operation circuit includes a multiplier, a second data selector, and an adder. The first data selector includes a first data output end, a second data output end, a third data output end, and a fourth data output end. The first data output end is connected with a first input end of the adder; the second data output end is connected with a first signal channel of the second data selector; the third data output end and the fourth data output end are respectively connected with a first input end and a second input end of the multiplier; a data output end of the multiplier is connected with a second signal channel of the second data selector; and a data output end of the second data selector is connected with a second input end of the adder. The second data selector is configured to receive the current count flag value, determine a mode selection signal corresponding to the current operation iteration period according to the current count flag value, and determine the first signal channel or the second signal channel to work according to the mode selection signal, so as to output the second data output end or an output result of the multiplier to the adder. The adder is configured to perform addition processing on the first data output end and an output signal of the second data selector; and an output end of the adder is configured to output the intermediate output parameters or the first voltage error value.

[0007] In a possible design, the digital operation circuit further includes a limiting judgment module, and an output terminal of the adder is connected to an input terminal of the limiting judgment module. The limiting judgment module is configured to perform limiting judgment on an intermediate output parameter output by the adder in each operation iteration period, to determine whether the intermediate output parameter is less than a preset upper limit value and greater than a preset lower limit value, and if yes, output the intermediate output parameter; if no, further determine whether the intermediate output parameter is greater than or equal to the preset upper limit value, and if yes, determine the preset upper limit value as the intermediate output parameter, and if no, determine the preset lower limit value as the intermediate output parameter.

[0008] In a possible design, the initial input data includes an initial voltage error value, and the initial voltage error value is a voltage difference between a current output voltage signal of the power factor correction controller and a preset reference voltage. The first voltage error value is a voltage error value obtained by filtering the initial voltage error value to remove a specified frequency component.

[0009] In a possible design, the data includes first and second setting parameters set for filtering the specified frequency component, and the first and second setting parameters are determined according to a frequency value of the output voltage signal, a frequency value of the specified frequency component, and an angular frequency of the specified frequency component. The initial input data further includes a plurality of intermediate input parameters generated according to the first and second setting parameters.

[0010] In a possible design, a transfer function of a filter is generated according to a frequency value of the output voltage signal, a frequency value of the specified frequency component, and an angular frequency of the specified frequency component. The first and second setting parameters of the transfer function are set for the specified frequency component, and the first and second setting parameters are substituted into the transfer function to obtain a corresponding difference equation. A logic operation table is generated according to a logic to be processed of the difference equation, and the logic operation table includes a plurality of groups of intermediate input parameters, wherein each group of intermediate input parameters corresponds to a count flag value and a mode selection signal. According to the count flag value and the mode selection signal, the digital operation circuit is controlled to perform multiple iteration operations to obtain the first voltage error value.

[0011] In a possible design, the digital operation circuit is further configured to: obtain the intermediate output parameter output by the adder in the current operation iteration period or the truncated data in the low storage position of the first voltage error value, and perform summation processing on the truncated data in the current period and the truncated data in the previous period to determine whether a carry will be generated from the summation result; if a carry will be generated, perform carry processing on the intermediate output parameter output in the current period or the first voltage error value; if not, do not perform carry processing on the intermediate output parameter output in the current period or the first voltage error value; and register the truncated data in the current period and the truncated data in the previous period.

[0012] In a second aspect, the present application also provides a voltage filtering control circuit, which comprises a voltage sampling circuit, a subtraction operation module, a filtering circuit, a PI control operation module, a frequency control module, and a current mode control module; the filtering circuit is the filtering circuit in any of the preceding items; The output end of the voltage sampling circuit is connected with the input ends of the subtraction operation module and the frequency control module respectively, the output end of the subtraction operation module is connected with the input end of the filtering circuit, the output end of the filtering circuit is connected with the input end of the PI control operation module, and the output end of the PI control operation module is connected with the input end of the current mode control module; the output end of the frequency control module is connected with the input ends of the filtering circuit and the current mode control module respectively; The voltage sampling circuit is configured to sample an input analog voltage signal to obtain an output voltage signal; the subtraction operation module is configured to subtract the voltage value of the output voltage signal from a preset reference voltage to obtain an initial voltage error value; the filtering circuit is configured to filter a specified frequency component in the initial voltage error value to obtain a first voltage error value; and the PI control operation module is configured to generate a corresponding PI compensation amount according to the first voltage error value. The frequency control module is configured to rectify the output voltage signal, delay the rectified voltage to obtain a delayed voltage, and obtain the peak position of the analog voltage signal according to the delayed voltage and the output voltage signal; and obtain the original frequency of the analog voltage signal, compare the original frequency with a preset reference frequency to obtain the frequency value of the output voltage signal. The current mode control module is configured to determine the peak current and the off-time control amount of the analog voltage signal in each period according to the PI compensation amount, the peak position, and the frequency value of the output voltage signal; and the peak current and the off-time control amount are used to control the conversion of the analog voltage signal into a corresponding direct-current voltage signal.

[0013] In a possible design, the voltage filtering control circuit further includes an analog control module, and an output terminal of the current mode control module is connected to an input terminal of the analog control module. The analog control module is configured to convert the analog voltage signal into a corresponding direct current voltage signal according to a peak value control quantity and an off time control quantity of the analog voltage signal in each period.

[0014] In a third aspect, the present application also provides a chip, which includes the filtering circuit according to any one of the preceding aspects, or which includes the voltage filtering control circuit according to the preceding aspect.

[0015] In a fourth aspect, the present application also provides an electronic device, which includes the filtering circuit according to any one of the preceding aspects, or which includes the voltage filtering control circuit according to the preceding aspect.

[0016] The filter circuit provided by the first aspect is used in a power factor correction controller, and is used to filter one or more set frequency components in an output voltage signal. The filter circuit comprises a counter, a first data selector, a digital operation circuit and a register. The counter is configured to receive a counting enable signal, and sequentially output a set of counting mark values to the first data selector under the triggering of the counting enable signal, wherein one current counting mark value is output to the first data selector in each operation iteration period. The first data selector is configured to receive initial input data and the current counting mark value, and select at least two data information in the initial input data as intermediate input parameters in the current operation iteration period according to the current counting mark value, and output the intermediate input parameters to the digital operation circuit. The digital operation circuit is configured to receive the intermediate input parameters, determine a corresponding current logic operation mode according to the current counting mark value, perform logic operation on the intermediate input parameters according to the current logic operation mode to obtain intermediate output parameters, and output the intermediate output parameters to the register. The register is configured to register the intermediate output parameters, and add the current intermediate output parameters to the initial input data. The initial input data further comprises a plurality of set parameters configured to filter the set frequency components. The digital operation circuit is further configured to, when the current counting mark value is the last one in the set of counting mark values, take the result of the current logic operation as a first voltage error value after filtering. The first voltage error value is used as a control compensation amount to adjust the filtered voltage signal, so as to filter the set frequency components in the output voltage signal. It can be seen that, by means of the first data selector and the digital operation circuit, the required logic operation can be completed by controlling the digital operation circuit to perform cyclic multiplexing, so as to output the first voltage error value. According to the first voltage error value as the control compensation amount, the filtered voltage signal can be adjusted, so as to filter the set frequency components in the output voltage signal. In this way, it is not necessary to configure complex filter coefficients, and it is not necessary to use a processor with stronger computing power, thereby saving hardware cost.

[0017] The beneficial effects provided by the other aspects and the possible designs of the other aspects can be referred to the beneficial effects brought by the first aspect and the possible designs of the first aspect, which will not be described herein. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 An amplitude-frequency characteristic curve diagram when a notch filter is used to filter a specific frequency signal in the related art; Figure 2 A filter circuit structure schematic diagram provided by an embodiment of the present application; Figure 3 A processing principle schematic diagram of a digital operation circuit provided by an embodiment of the present application; Figure 4 A structure diagram of a digital operation circuit provided by an embodiment of the present application is shown in FIG. 1. Figure 5 A curve diagram of amplitude-frequency and phase-frequency characteristics of the filter circuit provided by the embodiment of the present application when the commercial power is 50Hz is shown in FIG. 2. Figure 6 A curve diagram of amplitude-frequency and phase-frequency characteristics of the filter circuit provided by the embodiment of the present application when the commercial power is 60Hz is shown in FIG. 3. Figure 7 A structure diagram of a voltage filter control circuit provided by the embodiment of the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0019] In the present application, “at least one” means one or more, and “multiple” means two or more. “And / or” describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character “ / ” generally represents an “or” relationship between the front and rear associated objects. “At least one of the following” or similar expressions means any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b or c alone can mean a, b, c alone, combination of a and b, combination of a and c, combination of b and c, or combination of a, b and c, where a, b and c can be single or multiple. In addition, the terms “first” and “second” are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0020] The terms “center”, “longitudinal”, “transverse”, “upper”, “lower”, “left”, “right”, “front”, “back” and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0021] The terms “connected” and “connected” should be broadly understood, for example, the “connected” or “connected” of the circuit structure can mean not only physical connection, but also electrical connection or signal connection, for example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, it can also be the internal connection of two elements; In addition to signal connection through the circuit, signal connection through media medium, such as radio waves, can also be referred to. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0022] In application fields such as PFC controllers, it is usually required to filter out the 50Hz or 60Hz power frequency component contained in the signal in loop control. Because the power frequency is low, the low-pass filtering characteristic of the traditional proportional-integral controller cannot realize the function of filtering out the low-frequency component, and therefore a band-stop filter is usually used to filter out the specific frequency component in the signal. The PFC controller is based on the feedback control principle, calculates the real-time power factor by detecting the voltage and current signals of the power grid, and controls the switching of the compensation capacitor, so that the power factor of the circuit approaches 1. The PFC controller in the related art usually uses a digital signal processor (Digital Signal Processor, abbreviated as DSP) or a microcontroller (Microcontroller Unit, abbreviated as MCU) to realize high-precision control, and supports multiple communication protocols (such as Modbus, CAN) to facilitate system integration.

[0023] In the related art, in order to filter out the 50Hz or 60Hz power frequency component contained in the power signal, a band-stop filter with a very small stop band range, i.e. a notch filter, is used at the output end of the phase detection module of the phase-locked loop circuit in the controller. The filter is mainly realized by software and can filter out the twice power frequency component well. The coefficients of the filter can be adjusted in real time at the software level according to the change of the power frequency. Since there are usually only two power frequencies, and this implementation method needs to calculate two different sets of filter coefficients, the data processing process is relatively complicated and requires a large amount of processor resources.

[0024] Figure 1 For the amplitude-frequency characteristic curve of the notch filter used in the related art to filter out the specific frequency signal, please refer to the amplitude-frequency characteristic curve and the phase-frequency characteristic curve of the notch filter at the twice power frequency (i.e. 100Hz and 120Hz) shown in Figure 1 Figure 1 The expression of the transfer function of the filter in the z domain is as follows: Formula (1) In the above formula (1), the period T is taken as , , , the current signal in the nth period is taken as , z represents the z domain, and represents the transfer function.

[0025] By Figure 1 ​It can be seen that the notch filter can realize the amplitude attenuation of the signal components at 100Hz and 120Hz frequencies; however, since the power grid frequency is usually only two kinds, and the way of updating the filter coefficients in real time at the software level needs to calculate two different sets of filter coefficients, the implementation process is more cumbersome, and for related applications of customized hardware circuit, this implementation method needs to configure more parameters according to different frequencies, thereby occupying more hardware resources, resulting in larger circuit area overhead, which is difficult to meet more general application scenarios.

[0026] In order to overcome the deficiencies in the related art, the present application aims to provide a customized and lightweight PFC voltage loop digital filter circuit adaptive to 50Hz or 60Hz mains frequency, which can be applied to PFC controller and other application fields. The filter circuit can adaptively filter out the twice mains frequency AC component in the input voltage signal, and can realize optimal filtering function by configuring only two control parameters according to different requirements. Specifically, the filter circuit provided by the present application comprises a counter, a first data selector, a digital operation circuit and a register. The counter is used to receive a counting enable signal and output a set of counting flag values to the first data selector in turn under the triggering of the counting enable signal, wherein one current counting flag value is output to the first data selector in each operation iteration period. The first data selector is used to receive initial input data and a current counting flag value; and select at least two data information in the initial input data as intermediate input parameters of the current operation iteration period according to the current counting flag value, and output the intermediate input parameters to the digital operation circuit. The digital operation circuit is used to receive the intermediate input parameters, determine the corresponding current logic operation mode according to the current counting flag value, perform logic operation on the intermediate input parameters according to the current logic operation mode to obtain intermediate output parameters, and output the intermediate output parameters to the register. The register is used to register the intermediate output parameters, and add the current intermediate output parameters to the initial input data. The initial input data also includes a plurality of set parameters set for filtering out the set frequency component. The digital operation circuit is also used to take the result of the current logic operation as a first voltage error value after filtering when the current counting flag value is the last one in the set of counting flag values. The first voltage error value is used as a control compensation amount to adjust the filtered voltage signal, so as to filter out the set frequency component in the output voltage signal.

[0027] It can be seen that, by adopting the filtering circuit provided in the application, the first data selector and the digital operation circuit are used to complete the required logical operation by controlling the digital operation circuit to perform cyclic time-sharing multiplexing, so as to output the first voltage error value, and the first voltage error value is used as a control compensation amount to adjust the filtered voltage signal, thereby filtering out the set frequency component in the output voltage signal. In this way, a complex filter coefficient does not need to be configured, the work efficiency is improved, and a processor with stronger computing power does not need to be used, thereby saving the hardware cost.

[0028] Figure 2 A filtering circuit structure diagram provided by the embodiment of the application is shown in FIG. 2. Figure 2 As shown in FIG. 2, the filtering circuit 200 provided by the embodiment includes a counter 201, a first data selector 202, a digital operation circuit 203, and a register 204. The output end of the counter 201 is connected with the input end of the first data selector 202, the output end of the first data selector 202 is connected with the input end of the digital operation circuit 203, the output end of the digital operation circuit 203 is connected with the input end of the register 204, and the output end of the register 204 is connected with the input end of the first data selector 202.

[0029] The counter 201 is configured to receive a count enable signal and sequentially output a group of count flag values to the first data selector under the triggering of the count enable signal, wherein one current count flag value is output to the first data selector in each operation iteration period. The first data selector 202 is configured to receive initial input data and a current count flag value, the initial input data including a plurality of set parameters set for filtering out the set frequency component, and select at least two data information in the initial input data as intermediate input parameters of the current operation iteration period according to the current count flag value, and output the intermediate input parameters to the digital operation circuit 203. The digital operation circuit 203 is configured to receive the intermediate input parameters output by the first data selector 202 in the current period, determine a corresponding current logical operation mode according to the current count flag value, perform logical operation on the intermediate input parameters according to the current logical operation mode to obtain intermediate output parameters, and output the intermediate output parameters to the register 204. The register 204 is configured to register the intermediate output parameters and add the current intermediate output parameters to the initial input data. The digital operation circuit 203 is further configured to, when the current count flag value is the last one in the group of count flag values, take the result of the current logical operation as a first voltage error value after filtering processing. The first voltage error value is used as a control compensation amount to adjust the filtered voltage signal, thereby filtering out the set frequency component in the output voltage signal.

[0030] In an embodiment of the present application, the digital operation circuit 203 needs to be iterated multiple times to obtain the final operation result for a difference equation, and the intermediate output data obtained by the previous operation can be used as the intermediate input data for the next iteration operation.

[0031] In an embodiment of the present application, according to the operation sequence and the operation logic, the operation logic of a difference equation can be set to multiple iteration operations, and a count flag value is set for each iteration operation, which corresponds to a set of intermediate input parameters of the current iteration period. Thus, a set of count flag values can be set to complete multiple iteration operations, such as a set of count flag values [0, 1, 2, 3, 4, 5, 6, 7]. Each count flag value corresponds to a set of intermediate input data. For example, when the count flag value output by the counter 201 to the first data selector 202 is 1, the first data selector 202 selects a set of intermediate input data [a1, a2, a3, a4] at this time. The first data selector 202 inputs [a1, a2, a3, a4] to the digital operation circuit 203. The digital operation circuit 203 determines the logic operation mode of the current iteration operation according to the count flag value 1. The logic operation mode specifically refers to the control of the operation sequence of the multiple operation devices in the digital operation circuit 203. After the digital operation circuit 203 determines the logic operation mode of the current iteration operation according to the count flag value 1, the digital operation circuit 203 can be controlled to operate according to the logic operation mode of the current iteration operation to operate on the intermediate input data [a1, a2, a3, a4] to output the operation result of the current iteration operation.

[0032] In an embodiment of the present application, the transfer function of the filter can be generated according to the frequency value of the output voltage signal, the frequency value of the set frequency component, and the angular frequency of the set frequency component. The first set parameter and the second set parameter of the transfer function are set for the set frequency component, and the first set parameter and the second set parameter are substituted into the transfer function to obtain the corresponding difference equation. The logic operation table is generated according to the logic to be processed of the difference equation, and the logic operation table includes multiple sets of intermediate input parameters. Each set of intermediate input parameters corresponds to a count flag value and a mode selection signal. According to the count flag value and the mode selection signal, the digital operation circuit is controlled to perform multiple iteration operations to obtain a first voltage error value, which is the voltage error value after the specified frequency component is filtered from the initial voltage error value.

[0033] In one embodiment of this application, the processor is configured to generate a transfer function for a filter based on the frequency value of the output voltage signal, the frequency value of a set frequency component, and the angular frequency of the set frequency component; set a first set parameter and a second set parameter for the transfer function for the set frequency component, and substitute the first set parameter and the second set parameter into the transfer function to obtain the corresponding difference equation; generate a logic operation table based on the logic to be processed according to the difference equation, the logic operation table including multiple sets of intermediate input parameters; wherein each set of intermediate input parameters corresponds to a count flag value and a mode selection signal; and control the digital operation circuit to perform multiple iterative operations based on the count flag value and the mode selection signal to obtain a first voltage error value.

[0034] In one embodiment of this application, to reduce hardware resource consumption and latency while simplifying the system transfer function, this embodiment proposes a digital notch filter circuit that adapts to 50Hz or 60Hz mains frequency, based on the basic form of a second-order infinite impulse response (IIR) filter. This notch filter can adaptively filter out AC components at twice the mains frequency in the input voltage signal, and can achieve optimal filtering functionality by configuring only two control parameters according to different needs.

[0035] The basic form of the s-domain transfer function of a second-order IIR notch filter is as follows: Formula (2) In the above formula (2), The center frequency of the notch filter (in rad / s). For quality factors, Substituting the s-domain transfer function yields the amplitude-frequency response, and combining this with the stopband definition allows us to calculate the stopband width. At the notch center frequency Under fixed conditions, quality factor The higher the quality factor, the narrower the stopband; conversely, the lower the quality factor, the narrower the stopband. The lower the value, the wider the stopband.

[0036] In this embodiment, the bilinear transformation method is used to replace the differential operator s with a discrete difference form as follows: Formula (3) In the above formula (3), T To represent the sampling period, substitute formula (3) into formula (2). From the expression, the discretized z-domain transfer function can be derived as follows: Formula (4) in, TFor the sampling period, analyzing the above expression can know that the numerator coefficient and denominator coefficient of the transfer function H(z) both exist division operation, in the actual hardware circuit needs to use the divider, and the divider occupies a larger area in the hardware circuit. Since the numerator coefficient and denominator coefficient mainly involve two variables, therefore, two parameters can be defined as follows: Equation (5) When the mains frequency is 50Hz, the AC component frequency (i.e. notch frequency) to be filtered out is 100Hz, corresponding to the angular frequency , in the embodiment, the sampling time is taken as ; when the mains frequency is 60Hz, the AC component frequency to be filtered out is 120Hz, corresponding to the angular frequency , in the embodiment, the sampling time is taken as .When the quality factor takes the same value, under the condition of different mains frequencies, the values of the parameters A and B are the same, so that the filter can be self-adaptive to two mains frequencies.

[0037] Thus, the z-domain transfer function can be rewritten as follows: Equation (6) Neglecting the small amount of quadratic term and , the expression can be obtained by normalizing the coefficient of the highest order term in the denominator as follows: Equation (7) Wherein, , , , , .

[0038] According to the normalized expression, the corresponding difference equation can be obtained as follows: Equation (8) In the embodiment, in order to facilitate the implementation of digital circuit, the accumulation amount and are introduced, and the difference equation is rewritten as follows:

[0039]

[0040] Equation (9) As can be seen from the above analysis of this embodiment, in order to adapt to the filtering requirements of 50Hz or 60Hz mains frequency, the AC component of twice the mains frequency in the input voltage signal is adaptively filtered out. In the final difference equation, only two setting parameters A and B as shown in formula (5) are required. For example, A is the first setting parameter and B is the second setting parameter. Then, through the method provided in this embodiment, the above can be expressed based on the two parameters A and B. Then, the difference equation shown in formula (9) above is obtained. It can be seen from the difference equation shown in formula (9) that the expression of the difference equation in this embodiment only involves multiplication and addition processing logic, and there is no division calculation. In related technologies, for digital filters for two mains frequencies, if the transfer function and its coefficients are not simplified, a divider is usually required to calculate the coefficients, and two sets of parameters are required to implement the function. Each set contains five 16-bit parameters, and theoretically, configuring the parameters alone involves 160 bits of data. The circuit designed in this embodiment does not need to use a divider to calculate the coefficients, and only two 8-bit control parameters need to be configured to realize the digital filtering function according to the user's actual needs, reducing the register resource consumption of the digital circuit and thus saving chip area.

[0041] Figure 3 For a schematic diagram of the processing principle of the digital arithmetic circuit provided in the embodiments of this application, please refer to [link / reference]. Figure 3 As shown, based on the filter difference equation form described in the principle, the following can be derived: Figure 3 The diagram shows the internal processing logic structure of the filter circuit 200. In each operation cycle, the filter circuit 200 first combines the initial input voltage error value Verror with the accumulated value SUM1 from the previous cycle to calculate the output for the current cycle. Next, first-order noise shaping is performed to obtain the carry signal. The carry signal is then superimposed on the original output, and after amplitude limiting, the final filter output bsf_res is output. Then, according to the operational relationship shown in the difference equation, the filter circuit updates the accumulated SUM1 data in two steps, and then updates the accumulated SUM2 data in two steps, thus preparing for the calculation of the next cycle.

[0042] Specifically, in this embodiment, the first data selector 202 can be a first multiplexer. When the filtering function is enabled, the counter 201 will start counting each time a counting start signal is received. In each cycle, the counter 201 counts upward from its initial value of zero, and the counting flag value is output to the first data selector 202 in real time. When the target value is reached, the counter 201 will be cleared and wait for the next counting start signal. The first data selector 202 selects the logic operation mode and the data input terminal based on the real-time count value input by the counter 201. In each operation cycle, based on the current logic operation mode and the intermediate input parameters selected to participate in the operation, the digital operation circuit 203 will perform corresponding operations and determine whether the operation result of the current cycle needs to be stored in the register 204 according to actual needs. At the same time, based on the counting flag value output by the counter 201, it determines whether to output the operation result of the current cycle as the final result of the digital filter in the current sampling cycle to the subsequent modules.

[0043] To achieve lightweight design, this embodiment incorporates a digital arithmetic circuit 203 for multiplication and addition operations. This circuit is time-division multiplexed during actual operations to perform the multiplication and addition operations involved in filtering and PI control.

[0044] Figure 4 For a schematic diagram of the digital arithmetic circuit provided in the embodiments of this application, please refer to [link / reference]. Figure 4 As shown, the digital arithmetic circuit 203 provided in this embodiment includes a multiplier 401, a second data selector 402, and an adder 403. Specifically, the first data selector 202 in this embodiment includes a first data output terminal, a second data output terminal, a third data output terminal, and a fourth data output terminal. The first data output terminal is connected to the first input terminal of the adder 403. The second data output terminal is connected to the first signal channel of the second data selector 402. The third and fourth data output terminals are respectively connected to the first and second input terminals of the multiplier 401. The data output terminal of the multiplier 401 is connected to the second signal channel of the second data selector 402. The data output terminal of the second data selector 402 is connected to the second input terminal of the adder 403.

[0045] The second data selector 402 is used to receive the current count flag value, determine the mode selection signal corresponding to the current operation iteration cycle based on the current count flag value, and determine the operation of the first signal channel or the second signal channel based on the mode selection signal, so as to output the output result of the second data output terminal or the multiplier 401 to the adder 403; the adder 403 is used to perform addition processing on the output signals of the first data output terminal and the second data selector 402, and the output terminal of the adder 403 is used to output intermediate output parameters or the first voltage error value.

[0046] It is understood that the first data selector 202 includes a first data output terminal, a second data output terminal, a third data output terminal, and a fourth data output terminal. In each operation cycle, the intermediate input parameters output by the four data output ports of the first data selector 202 are different. For ease of understanding, the parameters output by the four data output ports can be defined as c1, c2, m1, and m2. In each operation cycle, the actual values ​​assigned to c1, c2, m1, and m2 are different. In this way, the second data selector 402 can perform relevant calculations based on the actual values ​​of the four input parameters to obtain the intermediate output parameters of the current cycle.

[0047] In one embodiment of this application, the data includes a first setting parameter and a second setting parameter set for filtering out the set frequency component. The first setting parameter and the second setting parameter are determined based on the frequency value of the output voltage signal, the frequency value of the set frequency component, and the angular frequency of the set frequency component. The initial input data also includes a plurality of intermediate input parameters generated based on the first setting parameter A and the second setting parameter B. For example, in different operation cycles, the actual values ​​assigned to c1, c2, m1, and m2 output by the four data output terminals of the first data selector 202 are different, and these multiple different assignments are equivalent to multiple intermediate input parameters generated.

[0048] In one embodiment of this application, in a real digital circuit, this embodiment uses the Q16 format in the fixed-point number format to amplify the values ​​of the first set parameter A and the second set parameter B. The user can configure the first set parameter A and the second set parameter B, that is, configure them as coefficients A and B in Q16 format, both of which have a bit width of 8 bits.

[0049] In one embodiment of this application, the second data selector 402 determines the type of operation to be performed in the current operation cycle based on the value of the mode selection signal mode. When mode=0, the ADD_ONLY operation is performed, that is, only the addition operation is performed, and c1 and c2 are summed. When mode=1, the MUL_ADD operation is performed, that is, the multiplication and addition operation is performed, first the product of m1 and m2 is calculated, and then the product result is summed with c1.

[0050] In one embodiment of the present application, in order to implement the operation logic of the difference equation shown in the above formula (9), a logic operation table shown in Table 1 below is generated according to the operation logic, the logic operation table including a plurality of sets of intermediate input parameters; wherein each set of intermediate input parameters corresponds to a count flag value and a mode selection signal; according to the count flag value and the mode selection signal, the digital operation circuit is controlled to perform a plurality of iteration operations to obtain the first voltage error value.

[0051] Table 1

[0052] Please refer to Table 1, different count flag values (i) correspond to different intermediate input values, different mode selection signals mode, and different results are output each time. In different operation periods, the actual values of c1, c2, m1 and m2 output by the four data output terminals of the first data selector 202 are different, the intermediate input parameters c1 and c2 use 32-bit count bits, the intermediate input parameter m1 uses 18-bit count bits, the intermediate input parameter m2 uses 11-bit count bits, and the output result result uses 32-bit count bits. The operation modes corresponding to the mode selection signals include addition operation (i.e. ADD_ONLY) and multiplication followed by addition (i.e. MUL_ADD). The ADD_ONLY mode means that only the values corresponding to the parameters c1 and c2 are added to obtain the operation result result of the current period. The MUL_ADD mode means that the values corresponding to the parameters m1 and m2 are multiplied first, and then the result of the multiplication is added to the parameter m1 to obtain the operation result result of the current period. For the operation result result output in each period, no update means no output, update means that the output of the current operation period is stored in the register 204, and output means that the calculation result of the current operation period is directly output.

[0053] For example, please refer to Table 1, when the count flag value i = 1, the operation mode corresponding to the mode selection signal at this time is multiplication followed by addition (i.e. MUL_ADD), that is, the values corresponding to the parameters m1 and m2 need to be multiplied first, and then the result of the multiplication is added to the parameter c1. At this time, the actual value corresponding to the parameter c1 is psuml, the actual value corresponding to the parameter m1 is b0, and the actual value corresponding to the parameter m2 is the initial voltage error value Verror. In the current operation period, the multiplier 401 is controlled to multiply b0 and Verror first, and then multiply the result of multiplying b0 and Verror with psuml. Please refer to the first formula in formula (9): , In this process, psuml corresponds to the formula , Verror corresponds to the formula . In addition, when the count flag value i = 3, the calculation result of the current operation period is output, i.e. the current operation period is completed, and the first voltage error value is obtained.

[0054] bsf_buf in Table 1 represents the truncated data required to be registered in the noise shaping operation in each sampling period, bsf_cry represents the carry signal of the noise shaping operation result in each sampling period, bsf_res represents the final output result of the filter in each sampling period; pi_intg represents the compensation of the PI controller integral link; coef_sel represents the proportional coefficient or integral coefficient actually selected by the PI controller; pi_err_sel represents the actual error amount input to the PI controller, i.e. whether to use the filtered error amount can be selected; slow_ki, fast_ki, slow_kp and fast_kp are the related coefficients of the PI control.

[0055] Generally, when the current count flag value is the last one in the set of count flag values, the result of the current logical operation is taken as the filtered first voltage error value; specifically, in the present embodiment, since in the actual working process, the digital operation circuit 203 performs operation according to the operation logic period shown in Table 1, when the count flag value i = 3, it is the last count flag value for each operation period, at this time, the first voltage error value is output. When i = 4-11, the relevant operation behind continues to be performed to prepare for the next period, and the cycle is worked.

[0056] In an embodiment of the present application, please continue to refer to Figure 4As shown, the digital operation circuit 203 further comprises a limiting judgment module 404, an output terminal of the adder 403 is connected with an input terminal of the limiting judgment module 404; the limiting judgment module 404 is used for judging the intermediate output parameter outputted by the adder 403 in each operation iteration period, determining whether the intermediate output parameter is less than a preset upper limit value and greater than a preset lower limit value, if yes, outputting the intermediate output parameter, i.e. without modifying the intermediate output parameter; if no, further determining whether the intermediate output parameter is greater than or equal to the preset upper limit value, if yes, determining the preset upper limit value as the intermediate output parameter and outputting, i.e. if the outputted intermediate output parameter is equal to or greater than the preset upper limit value, taking the preset upper limit value as the intermediate output parameter and outputting, if no, determining the preset lower limit value as the intermediate output parameter, i.e. limiting the minimum intermediate output parameter to be greater than the preset lower limit value. In this way, the limiting processing of the intermediate output parameter can be completed, the intermediate output parameter is limited between the preset lower limit value and the preset upper limit value, the final outputted intermediate output parameter is not deviated too much, and the operation result is more accurate.

[0057] In the embodiment, before outputting the final result in each operation period, the operation result (i.e. the intermediate output parameter) needs to be judged, if the intermediate output parameter exceeds the given preset upper limit value up_limit, the final intermediate output parameter takes the upper limit value; if the intermediate output parameter is lower than the given preset lower limit value dn_limit, the final result takes the lower limit value; if the operation result is within the preset lower limit value dn_limit and the preset upper limit value up_limit, the intermediate output parameter takes the actual operation result. In an embodiment of the present application, before outputting the final result in each operation period, the operation result needs to be judged, if the operation result exceeds the given upper limit value up_limit, the final result takes the upper limit value; if the operation result is lower than the given lower limit value dn_limit, the final result takes the lower limit value; if the operation result is within the upper and lower limits, the final result takes the operation result.

[0058] In an embodiment of the present application, the initial input data comprises an initial voltage error value, the initial voltage error value is a voltage difference value between a current output voltage signal of the power factor correction controller and a preset reference voltage; the first voltage error value outputted from the filter circuit 200 is a voltage error value after filtering out the specified frequency component from the initial voltage error value.

[0059] In an embodiment of the present application, since the filter coefficients are floating-point numbers, the embodiment adopts Q16 format to fix-point process the coefficients, and in the operation process, a 32-bit numerical result is obtained, thus the lower 16 bits of the numerical result need to be truncated and the higher 16 bits are reserved as the actual output result of the current operation period, and the truncation will cause quantization noise in the operation process. To solve the problem, the embodiment introduces a first-order noise shaping link in the filter operation process to reduce the influence of the quantization noise on the filter effect. In the noise shaping link, in each operation period, the system registers the lower 16 bits of the numerical result truncated in the current period, sums the lower 16 bits of the numerical result with the lower 16 bits of the numerical result registered in the last period, and judges whether a carry is generated by the sum of the two numbers. If the carry is generated, the higher 16 bits of the actual output result, i.e. the numerical result, need to be operated by 1, and the carry is cleared; if the carry is not generated, the actual output result is not operated by 1, and the sum of the two numbers is registered.

[0060] The digital operation circuit 203 provided by the embodiment is also used to receive a corresponding count flag value to perform noise shaping processing on the calculation result of the current period, and finally obtain an accurate first voltage error value after noise shaping. Specifically, as shown in Table 1, when the count flag value i=2 and the count flag value i=3, the digital operation circuit 203 performs noise shaping processing on the calculation result of the current period. Specifically, the digital operation circuit 203 acquires the truncated data in the lower storage position of the intermediate output parameter or the first voltage error value output by the adder 403 in the current operation iteration period, sums the truncated data in the current period and the truncated data in the last period, determines whether a carry is generated by the sum result, performs carry processing on the intermediate output parameter or the first voltage error value output this time if the carry is generated, does not perform carry processing on the intermediate output parameter or the first voltage error value output this time if not, and registers the truncated data in the current period and the truncated data in the last period.

[0061] Figure 5 The amplitude-frequency and phase-frequency characteristic curve diagram of the filter circuit provided by the embodiment of the present application when the mains power is 50Hz is shown in Figure 6 The amplitude-frequency and phase-frequency characteristic curve diagram of the filter circuit provided by the embodiment of the present application when the mains power is 60Hz is shown in Figure 5 and Figure 6 Taking the application of the PFC controller as an example, i.e. applying the filter circuit 200 provided by the embodiment to the PFC controller, the quality factor , when , the sampling time ; when , the sampling time ; then the parameter A_Q16 in the Q16 format=238, and the parameter B_Q16=198. FromFigure 5 and Figure 6 It can be seen that the component of double mains frequency is effectively suppressed under both 50Hz and 60Hz mains frequency conditions.

[0062] As can be seen from the above description, according to the filter circuit provided in the embodiment, a user only needs to configure two 8-bit parameters (i.e. the first setting parameter A and the second setting parameter B) on an external interface, and combines the frequency detection function and the step adjustment function, so as to realize the digital filter function facing two mains frequencies. The filter circuit provided in the embodiment uses only one product accumulation circuit module to complete all logical operations of the notch filter and the PI controller, so that the hardware structure is simpler and the hardware cost is lower.

[0063] According to the digital filter circuit provided in the embodiment, the self-adaptation to 50Hz or 60Hz mains frequency can be realized. For the digital filter facing two mains frequencies, if the transfer function and its coefficients are not simplified, a divider is usually needed to calculate the coefficients, and two sets of parameters are needed to realize the function, each set containing 5 16-bit parameters. In theory, only the parameter configuration involves 160 bits of data. The filter circuit designed in the embodiment does not need to use a divider to calculate the coefficients, and only two control parameters with a bit width of 8 bits need to be configured, so that the digital filter function can be realized according to the actual needs of the user, the register resource consumption of the digital circuit is reduced, and the chip area is saved.

[0064] On the basis of the filter circuit provided in the above embodiments, the embodiment further provides a voltage filter control circuit to realize the purpose of filtering and controlling the input mains. The voltage filter control circuit provided in the embodiment will be specifically described below in combination with specific drawings and embodiments.

[0065] The voltage filter control circuit provided in the embodiment is mainly applied to the voltage loop of the PFC controller, and plays a role in filtering the noise caused by the mains frequency component in the input signal Vin.

[0066] Figure 7 For the structure diagram of the voltage filter control circuit provided in the embodiment, please refer to Figure 7 As shown in the figure, the voltage filter control circuit specifically can include a digital control module 800 and an analog control module 900, wherein the digital control module 800 of the filter control circuit specifically includes a subtraction operation module 801, a filter circuit 200, a PI control operation module 803, a frequency control module 805, a voltage sampling circuit 806 and a current mode control module 804; wherein the filter circuit 200 provided in the embodiment can be the filter circuit provided in any one of the above embodiments.

[0067] The output end of the voltage sampling circuit 806 is connected with the input end of the subtraction operation module 801 and the frequency control module 805 respectively, the output end of the subtraction operation module 801 is connected with the input end of the filter circuit 200, the output end of the filter circuit is connected with the input end of the PI control operation module 803, the output end of the PI control operation module 803 is connected with the input end of the current mode control module 804, and the output end of the frequency control module 805 is connected with the input end of the filter circuit 200 and the current mode control module 804 respectively.

[0068] The voltage sampling circuit 806 is used for sampling the input analog voltage signal (i.e. analog sample) to obtain an output voltage signal Vout; the subtraction operation module 801 is used for subtracting the voltage value of the output voltage signal Vout from a preset reference voltage to obtain an initial voltage error value Verror; the filter circuit 200 is used for filtering the specified frequency component in the initial voltage error value Verror to obtain a first voltage error value Vres; the PI control operation module 803 is used for generating a corresponding PI compensation amount Vpi according to the first voltage error value Vres; the frequency control module 805 is used for rectifying the output voltage Vout, delaying the rectified voltage to obtain a delayed voltage, and obtaining the peak position of the analog voltage signal according to the delayed voltage and the output voltage signal; at the same time, the original frequency of the analog voltage signal is obtained, the original frequency is compared with a preset reference frequency to obtain the frequency value of the output voltage; and the current mode control module 804 is used for determining the peak current i peak and the turn-off time control amount t off of the analog voltage signal in each cycle according to the PI compensation amount Vpi, the peak position and the frequency value of the output voltage signal Vout. peak and the turn-off time control amount t off , so as to control the conversion of the analog voltage signal into a corresponding direct current voltage signal.

[0069] The voltage filter control circuit of the embodiment further comprises an analog control module 900, and the output end of the current mode control module 804 is connected with the input end of the analog control module 900; the analog control module 900 is used for converting the analog voltage signal into a corresponding direct current voltage signal according to the peak current i peak and the turn-off time control amount t off of the analog voltage signal in each cycle, so as to achieve the purpose of filtering control on the input commercial power.

[0070] The filter circuit 200 provided in the embodiment can refer to the filter circuit 200 provided in the embodiment of the voltage filter control circuit. Figure 2As shown, the filter circuit 200 comprises a counter 201, a first data selector 202, a digital operation circuit 203 and a register 204; wherein an output terminal of the counter 201 is connected with an input terminal of the first data selector 202, an output terminal of the first data selector 202 is connected with an input terminal of the digital operation circuit 203, and an output terminal of the digital operation circuit 203 is connected with an input terminal of the register 204, and an output terminal of the register 204 is connected with an input terminal of the first data selector 202. Wherein the counter 201 is configured to receive a counting enable signal, and sequentially output a group of counting mark values to the first data selector under the triggering of the counting enable signal, wherein one current counting mark value is output to the first data selector in each operation iteration period; the first data selector 202 is configured to receive initial input data and a current counting mark value, the initial input data comprising a plurality of set parameters set for filtering out set frequency components; and select at least two data information in the initial input data as intermediate input parameters of the current operation iteration period according to the current counting mark value, and output the intermediate input parameters to the digital operation circuit 203; the digital operation circuit 203 is configured to receive the intermediate input parameters output by the first data selector 202 in the current period, and determine a corresponding current logic operation mode according to the current counting mark value, perform logic operation on the intermediate input parameters according to the current logic operation mode to obtain intermediate output parameters, and output the intermediate output parameters to the register 204; the register 204 is configured to register the intermediate output parameters, and add the current intermediate output parameters into the initial input data; the digital operation circuit 203 is further configured to, when the current counting mark value is the last one in the group of counting mark values, take the result of the current logic operation as a first voltage error value after filtering processing, specifically, in the embodiment, when the counting mark value i = 3, it indicates that the current counting mark value is the last one in the group of counting mark values; the first voltage error value is used as a control compensation amount to adjust the filtered voltage signal, so as to filter out the set frequency components in the output voltage signal.

[0071] It can be understood that the specific structure and working principle of the filter circuit and the achieved technical effects can refer to the filter circuits provided in the above embodiments, which will not be described here.

[0072] According to the voltage filter control circuit provided in the embodiment, the user does not need to configure complex filter coefficients, the working efficiency is improved, and a processor with stronger computing power does not need to be used, thereby saving the hardware cost.

[0073] The embodiment of the present application also provides a chip comprising the filter circuit provided in any one of the above embodiments; or the chip comprises the voltage filter control circuit provided in any one of the above embodiments.

[0074] It can be understood that, in order to improve the integration of the circuit and save the space occupied by the circuit, the filter circuit provided in each of the above embodiments can be integrated in a digital control chip, so that the digital control chip has the functions of the filter circuit provided in each of the above embodiments, and the overall volume is smaller, and can be mass-produced, and the internal space occupied when applied to products is also smaller. In another embodiment, in order to improve the integration of the circuit and save the space occupied by the circuit, the voltage filter control circuit provided in each of the above embodiments can also be integrated in a digital control chip, so that the digital control chip has the functions of the voltage filter control circuit provided in each of the above embodiments, and the overall volume is smaller, and can be mass-produced, and the internal space occupied when applied to products is also smaller.

[0075] The embodiment of the present application also provides an electronic device, for example, the electronic device can be a filter, the electronic device includes the filter circuit provided in any one of the above embodiments, or the electronic device includes the digital control chip provided in the above embodiment; the specific structure and working principle of the filter circuit and the technical effects achieved can be referred to the filter circuit provided in each of the above embodiments, and will not be repeated here. According to the electronic device provided in the embodiment, the user does not need to configure complex filter coefficients, the working efficiency is improved, and a processor with stronger computing power is not needed, and the hardware cost is saved.

[0076] In another embodiment, the electronic device includes the voltage filter control circuit provided in any one of the above embodiments, or the electronic device includes the digital control chip provided in the above embodiment, according to the electronic device provided in the embodiment, the user does not need to configure complex filter coefficients, the working efficiency is improved, and a processor with stronger computing power is not needed, and the hardware cost is saved.

[0077] Finally, it should be noted that: the above embodiments are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any change or replacement within the technical scope disclosed in the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A filter circuit for use in a power factor correction controller, the filter circuit being configured to filter out one or more set frequency components in an output voltage signal; characterized in that, The filter circuit comprises a counter, a first data selector, a digital operation circuit and a register; The counter is configured to receive a counting enable signal and sequentially output a group of counting mark values to the first data selector under triggering of the counting enable signal, wherein one current counting mark value is output to the first data selector in each operation iteration period; The first data selector is configured to receive initial input data and the current counting mark value, select at least two data information in the initial input data as intermediate input parameters of the current operation iteration period according to the current counting mark value, and output the intermediate input parameters to the digital operation circuit; The digital operation circuit is configured to receive the intermediate input parameters, determine a corresponding current logic operation mode according to the current counting mark value, perform logic operation on the intermediate input parameters according to the current logic operation mode to obtain intermediate output parameters, and output the intermediate output parameters to the register; the register is configured to register the intermediate output parameters and add the current intermediate output parameters to the initial input data; the initial input data further comprises a plurality of setting parameters set for filtering out the set frequency components; The digital operation circuit is further configured to take the result of the current logic operation as a first voltage error value after the filtering processing when the current counting mark value is the last one in the group of counting mark values; the first voltage error value is used to filter out the set frequency components in the output voltage signal.

2. The filter circuit of claim 1, wherein, The digital operation circuit comprises a multiplier, a second data selector and an adder; The first data selector comprises a first data output end, a second data output end, a third data output end and a fourth data output end; The first data output end is connected with a first input end of the adder; The second data output end is connected with a first signal channel of the second data selector; the third data output end and the fourth data output end are respectively connected with a first input end and a second input end of the multiplier; a data output end of the multiplier is connected with a second signal channel of the second data selector; and a data output end of the second data selector is connected with a second input end of the adder; The second data selector is configured to receive the current counting mark value, determine a mode selection signal corresponding to the current operation iteration period according to the current counting mark value, and determine the first signal channel or the second signal channel to work according to the mode selection signal, so as to output the second data output end or the output result of the multiplier to the adder; The adder is configured to perform addition processing on the first data output end and the output signal of the second data selector; and an output end of the adder is configured to output the intermediate output parameters or the first voltage error value.

3. The filter circuit of claim 2, wherein, The digital operation circuit further comprises a limiting judgment module; and an output end of the adder is connected with an input end of the limiting judgment module. The limiting judgment module is configured to perform limiting judgment on the intermediate output parameter output by the adder in each operation iteration period, determine whether the intermediate output parameter is less than a preset upper limit value and greater than a preset lower limit value, output the intermediate output parameter if yes, further determine whether the intermediate output parameter is greater than or equal to the preset upper limit value if no, determine the preset upper limit value as the intermediate output parameter if yes, and determine the preset lower limit value as the intermediate output parameter if no.

4. The filter circuit of claim 3, wherein, The initial input data includes an initial voltage error value, which is a voltage difference between a current output voltage signal of the power factor correction controller and a preset reference voltage. The first voltage error value is a voltage error value obtained by filtering a specified frequency component from the initial voltage error value.

5. The filter circuit of claim 4, wherein, The data includes first and second setting parameters set for filtering the specified frequency component, which are determined according to a frequency value of the output voltage signal, a frequency value of the specified frequency component, and an angular frequency of the specified frequency component. The initial input data further includes a plurality of intermediate input parameters generated according to the first and second setting parameters.

6. The filter circuit of claim 5, wherein, A transfer function of a filter is generated according to the frequency value of the output voltage signal, the frequency value of the specified frequency component, and the angular frequency of the specified frequency component. The first and second setting parameters of the transfer function are set for the specified frequency component, and the first and second setting parameters are substituted into the transfer function to obtain a corresponding difference equation. A logic operation table is generated according to a logic to be processed of the difference equation, and the logic operation table includes a plurality of groups of intermediate input parameters; each group of intermediate input parameters corresponds to a count flag value and a mode selection signal. The digital operation circuit is configured to obtain a truncated data in a low storage position of the intermediate output parameter output by the adder or the first voltage error value in a current operation iteration period, sum the truncated data in the current period and the truncated data in a previous period, determine whether a carry occurs in a sum result, perform carry processing on the intermediate output parameter output in the current period or the first voltage error value if the carry occurs, perform no carry processing on the intermediate output parameter output in the current period or the first voltage error value if the carry does not occur, and register the truncated data in the current period and the truncated data in the previous period.

7. The filter circuit of claim 5, wherein, The voltage filtering control circuit includes a voltage sampling circuit, a subtraction operation module, a filtering circuit, a PI control operation module, a frequency control module, and a current mode control module; and the filtering circuit is the filtering circuit of any one of claims 1-7.

8. A voltage filter control circuit, characterized by, ​ An output terminal of the voltage sampling circuit is connected with an input terminal of the subtraction operation module and the frequency control module respectively, an output terminal of the subtraction operation module is connected with an input terminal of the filter circuit, an output terminal of the filter circuit is connected with an input terminal of the PI control operation module, and an output terminal of the PI control operation module is connected with an input terminal of the current mode control module; an output terminal of the frequency control module is connected with an input terminal of the filter circuit and the current mode control module respectively. The voltage sampling circuit is configured to sample an input analog voltage signal to obtain an output voltage signal. The subtraction operation module is configured to subtract a voltage value of a preset reference voltage from the output voltage signal to obtain an initial voltage error value. The filter circuit is configured to filter a specified frequency component in the initial voltage error value to obtain a first voltage error value. The PI control operation module is configured to generate a corresponding PI compensation amount according to the first voltage error value. The frequency control module is configured to rectify the output voltage signal, delay the rectified voltage to obtain a delayed voltage, and obtain a peak position of the analog voltage signal according to the delayed voltage and the output voltage signal; and obtain an original frequency of the analog voltage signal, compare the original frequency with a preset reference frequency to obtain a frequency value of the output voltage signal.

9. The voltage filter control circuit of claim 8, wherein, The current mode control module is configured to determine a peak current and an off-time control amount of the analog voltage signal in each cycle according to the PI compensation amount, the peak position, and the frequency value of the output voltage signal; and the peak current and the off-time control amount are used to control conversion of the analog voltage signal into a corresponding direct current voltage signal. The voltage filter control circuit further comprises an analog control module, and an output terminal of the current mode control module is connected with an input terminal of the analog control module.

10. A chip, characterized by The analog control module is configured to convert the analog voltage signal into a corresponding direct current voltage signal according to the peak control amount and the off-time control amount of the analog voltage signal in each cycle.

11. An electronic device, comprising: The chip comprises the filter circuit according to any one of claims 1-7; or the chip comprises the voltage filter control circuit according to claim 8 or 9. The electronic device comprises the filter circuit according to any one of claims 1-7; or the electronic device comprises the voltage filter control circuit according to claim 8 or 9.

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