A display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The pixel circuit in the display panel comprises a driving transistor, a first light-emitting control module and a second light-emitting control module. In the first pixel circuit, the control end of the first light-emitting control module receives a first control signal, and the control end of the second light-emitting control module receives a second control signal. In the second pixel circuit, the control end of the first light-emitting control module and the control end of the second light-emitting control module both receive the first control signal or both receive the second control signal. In the first mode, the first control signal and the second control signal are different control signals. In the working period of the first pixel circuit, the effective pulse period of the first control signal and the effective pulse period of the second control signal partially overlap. The present application can make different light-emitting devices have different light-emitting durations and can compensate for the light-emitting efficiency difference of different light-emitting devices.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Micro LEDs (micro light-emitting diodes) and Mini LEDs (mini light-emitting diodes) boast high luminous efficiency, high brightness, a wide color gamut, and low power consumption, making them a key technology for future display products. Color displays require red, green, and blue LEDs. Due to differences in luminous efficiency between different color LEDs, the pixel circuit structure used to drive the LEDs plays a crucial role in determining the display quality. Summary of the Invention

[0003] Embodiments of the present invention provide a display panel and a display device to solve the technical problem of improving display effects.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, comprising a plurality of pixel circuits and a plurality of light-emitting devices; the pixel circuits comprising a driving transistor, a first light-emitting control module, and a second light-emitting control module; a first electrode of the driving transistor being coupled to a first power supply terminal via the first light-emitting control module, and a second electrode of the driving transistor being coupled to the light-emitting device via the second light-emitting control module;

[0005] The pixel circuit includes a first pixel circuit and a second pixel circuit; the control end of the first light emitting control module in the first pixel circuit receives a first control signal, and the control end of the second light emitting control module receives a second control signal; and the control ends of the first light emitting control module and the second light emitting control module in the second pixel circuit both receive the first control signal or both receive the second control signal;

[0006] The display panel includes a first mode. In the first mode, the first control signal and the second control signal are different control signals. In a working cycle of the first pixel circuit, the effective pulse period of the first control signal and the effective pulse period of the second control signal partially overlap.

[0007] In a second aspect, based on the same inventive concept, an embodiment of the present invention provides a display device, including the display panel provided by any embodiment of the present invention.

[0008] The display panel and display device provided by the embodiments of the present invention have the following beneficial effects: the control end of the first light-emitting control module and the control end of the second light-emitting control module in the first pixel circuit are respectively configured to receive the first control signal and the second control signal, and the control end of the first light-emitting control module and the control end of the second light-emitting control module in the second pixel circuit both receive the first control signal or both receive the second control signal. During the light-emitting phase of the operation of the first pixel circuit, the duration of the driving current provided to it is controlled by at least the first control signal and the second control signal, while during the light-emitting phase of the operation of the second pixel circuit, the duration of the driving current provided to it is controlled by only one of the first control signal and the second control signal. The present invention can achieve different durations of driving current provided by the first pixel circuit and the second pixel circuit during operation in the first mode, so that different light-emitting devices can have different light-emitting durations, thereby compensating for differences in luminous efficiency of different light-emitting devices and improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0010] Figure 1 A schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0011] Figure 2 for Figure 1 A timing diagram of a pixel circuit;

[0012] Figure 3 A schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0013] Figure 4 A signal timing diagram provided by an embodiment of the present invention;

[0014] Figure 5 A schematic diagram of another pixel circuit in a display panel provided by an embodiment of the present invention;

[0015] Figure 6 Another signal timing diagram provided by an embodiment of the present invention;

[0016] Figure 7 Another signal timing diagram provided by an embodiment of the present invention;

[0017] Figure 8 Another signal timing diagram provided by an embodiment of the present invention;

[0018] Figure 9 Another signal timing diagram provided by an embodiment of the present invention;

[0019] Figure 10 Another signal timing diagram provided by an embodiment of the present invention;

[0020] Figure 11 Another signal timing diagram provided by an embodiment of the present invention;

[0021] Figure 12 A schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0022] Figure 13 Another signal timing diagram provided by an embodiment of the present invention;

[0023] Figure 14 A schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0024] Figure 15 Another signal timing diagram provided by an embodiment of the present invention;

[0025] Figure 16 A schematic diagram of a display panel provided by an embodiment of the present invention;

[0026] Figure 17 for Figure 16 Schematic diagram of membrane disassembly;

[0027] Figure 18 A partial schematic diagram of a display panel provided by an embodiment of the present invention;

[0028] Figure 19 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0029] Figure 20 for Figure 18 A schematic cross-sectional view at the midline AA′;

[0030] Figure 21 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0032] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "an", "the" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0033] Different color LEDs require different colors of luminescent materials. This material influence leads to differences in the luminous efficiency of these LEDs. LED luminescent materials are significantly affected by temperature, resulting in different luminous efficiencies at different temperatures. Furthermore, the luminous efficiency of different color LEDs is affected differently by temperature, which can cause color shift in the display. For example, tests have shown that when a display panel is operated at a high temperature (e.g., 85°C) compared to a 25°C operating environment, the luminous efficiency of the red, green, and blue LEDs decreases to varying degrees, resulting in color shift and reduced brightness.

[0034] In order to solve the problems existing in the related technology, an embodiment of the present invention provides a display panel, in which the pixel circuit in the display panel is coupled to the light-emitting device, and the control method of different pixel circuits is designed so that the light-emitting devices driven by different pixel circuits can have different light-emitting durations, thereby compensating for the differences in light-emitting efficiency of different light-emitting devices and improving the display effect of the display panel.

[0035] Figure 1 A schematic diagram of a pixel circuit provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the pixel circuit includes a driving transistor Tm, a first light emitting control module 10, a second light emitting control module 20, a gate reset module 30, an electrode reset module 40 and a data writing module 50. The first electrode of the driving transistor Tm is coupled to the first power supply terminal Pvdd through the first light emitting control module 10, the second electrode of the driving transistor Tm is coupled to one electrode of the light emitting device LD through the second light emitting control module 20, the other electrode of the light emitting device LD is coupled to the second power supply terminal Pvee, one plate of the storage capacitor Cst is coupled to the first power supply terminal Pvdd, and the other plate is coupled to the gate of the driving transistor Tm. Figure 1 It can be seen that the gate reset module 30 is controlled by the first scan signal S1, the data write module 50 and the electrode reset module 40 are controlled by the second scan signal S2, and the first light control module 10 and the second light control module 20 are controlled by the light control signal Emit. The light emitting device LD is an LED device, such as a Micro LED or a Mini LED.

[0036] Figure 2 for Figure 1 A timing diagram of a pixel circuit, such as Figure 2As shown, the working cycle of the pixel circuit includes a gate reset phase t1, a data writing phase t2, and a light-emitting phase t3. In the gate reset phase t1, the gate reset module 30 starts to write the reset signal Ref (with the same reference numeral as its signal terminal) provided by the reset signal terminal Ref into the gate of the driving transistor Tm to reset the gate of the driving transistor Tm; in the data writing phase t2, the data writing module 50 starts to write the data voltage Data into the gate of the driving transistor Tm, and at the same time, the electrode reset module 40 starts to reset the electrode of the light-emitting device LD using the reset signal Ref; in the light-emitting phase t3, the first light-emitting control module 10 and the second light-emitting control module 20 are turned on, the driving transistor Tm is turned on under the control of its gate voltage, the pixel circuit provides a driving current to the light-emitting device LD, and the light-emitting device LD emits light under the control of the light-emitting current.

[0037] Optional, such as Figure 1 As shown, the data writing module 50 includes a data writing transistor T1 and a compensation transistor T2, the gate reset module 30 includes a gate reset transistor T3, the electrode reset module 40 includes an electrode reset transistor T4, the first light emitting control module 10 includes a first light emitting control transistor T5, and the second light emitting control module 20 includes a second light emitting control transistor T6.

[0038] In some implementations, an electrode reset transistor may not be provided in the pixel circuit.

[0039] Figure 1 The pixel circuit is illustrated as if each transistor is a p-type transistor. In other embodiments, each transistor is an n-type transistor. In other embodiments, at least one of the gate reset transistor T3 and the compensation transistor T2 is an n-type transistor, and the other transistors are p-type transistors. When the compensation transistor T2 is an n-type transistor and the data write transistor T1 is a p-type transistor, it can be understood that the two need to be controlled by different signals. In the figures of the following embodiments, only the transistors in the pixel circuit are p-type transistors for schematic illustration.

[0040] Figure 1 The basic structure of the pixel circuit is shown in Figure 1 In this embodiment, the first and second light-emitting control modules 10 and 20 are controlled by the same signal. In this embodiment, the control methods of the first and second light-emitting control modules 10 and 20 in different pixel circuits are designed so that different pixel circuits provide drive current to the light-emitting device LD for different durations during the light-emitting phase. This results in different light-emitting durations for the light-emitting devices LD driven by the different pixel circuits, thereby compensating for differences in the light-emitting efficiency of the light-emitting devices LD and improving the display effect.

[0041] Figure 3A schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present invention is shown. Figure 3 The first pixel circuit 01 and the second pixel circuit 02 in the pixel circuit are shown. The first pixel circuit 01 is coupled to the first light emitting device LD1, and the second pixel circuit 02 is coupled to the second light emitting device LD2. Figure 3 As shown, the control end of the first light emitting control module 10 in the first pixel circuit 01 receives the first control signal Emit1, and the control end of the second light emitting control module 20 receives the second control signal Emit2. The control ends of the first light emitting control module 10 and the second light emitting control module 20 in the second pixel circuit 02 both receive the first control signal Emit1 or both receive the second control signal Emit2. Figure 3 It is illustrated that both receive the first control signal Emit1.

[0042] The display panel is provided with signal lines such as data lines, scan lines, light-emitting control lines, and power lines. The data lines provide a data voltage Data, the first scan lines provide a first scan signal S1, the second scan lines provide a second scan signal S2, the power lines serve as a first power supply terminal Pvdd and provide a first power supply voltage Pvdd (the power supply terminal and the voltage signal it provides use the same reference numerals), and the first control signal Emit1 and the second control signal Emit2 are provided by corresponding light-emitting control lines.

[0043] In order to facilitate the understanding of this solution, some of the terms involved are first explained. The "effective level of the signal" mentioned in the embodiments of the present invention refers to the level required when the module controlled by the signal is in the open state. In some embodiments, the low level is the effective level, and in other embodiments, the high level is the effective level. "The effective pulse of the signal" refers to the pulse signal when the module controlled by the signal is in the open state. For example, the first control signal Emit1 in the first pixel circuit 01 controls the first light-emitting control module 10. The low-level pulse of the first control signal Emit1 controls the first light-emitting control module 10 to turn on. Then the low-level pulse of the first control signal Emit1 is its effective pulse, and the low level is the effective level. The width (or duration) of the effective pulse is the effective pulse width, which can also be called the duration of the effective pulse. "Different control signals" means that the effective pulse widths of the signals are different, that is, the effective pulse durations of the signals are different.

[0044] In the embodiment of the present invention, the first light emitting device LD1 and the second light emitting device LD2 driven by the first pixel circuit 01 and the second pixel circuit 02 respectively may be located in the same pixel row or in different pixel rows.

[0045] It can be understood that when the first pixel circuit 01 and the second pixel circuit 02 drive the light-emitting devices located in the same pixel row, the first scanning signal S1 received by both is at an effective level in the same period, the second scanning signal S2 received by both is at an effective level in the same period, and the first control signal Emit1 received by both is at an effective level in the same period.

[0046] It can be understood that when the first pixel circuit 01 and the second pixel circuit 02 drive light-emitting devices located in different pixel rows, the duration of the first scanning signal S1 received by each of them is equal, but there is a time difference between the start time of the effective level. This is because the display panel typically drives multiple pixel rows row by row, and the cascaded shift registers provide scanning signals to multiple scan lines row by row. Therefore, there is a time difference between the effective level periods of the scanning signals received by the pixel circuits driving different pixel rows. Correspondingly, for the first control signal Emit1, the duration of the first control signal Emit1 received by the first pixel circuit 01 and the second pixel circuit 02 is equal, but there is a time difference between the start time of the effective level.

[0047] Combine Figure 1 The operation of the pixel circuit in the embodiment is described as follows: during light-emitting phase t3, when the first light-emitting control module 10 is turned on, the first electrode of the driving transistor Tm is electrically connected to the first power supply terminal Pvdd; when the second light-emitting control module 20 is turned on, the second electrode of the driving transistor Tm is electrically connected to the light-emitting device LD. When both the first light-emitting control module 10 and the second light-emitting control module 20 are turned on, the driving transistor Tm generates a driving current and supplies it to the light-emitting device LD, thereby causing the light-emitting device LD to emit light. In other words, during light-emitting phase t3, only when the first light-emitting control module 10 and the second light-emitting control module 20 are simultaneously turned on can a light-emitting channel be formed, causing the light-emitting device LD to emit light. The embodiments of the present invention allow for different durations of simultaneous activation of the first light-emitting control module 10 and the second light-emitting control module 20 in different pixel circuits, thereby enabling the light-emitting devices controlled by different pixel circuits to emit light for different durations.

[0048] In an embodiment of the present invention, the display panel includes a first mode. In the first mode, the first control signal Emit1 and the second control signal Emit2 are different control signals; that is, the effective pulse widths of the first control signal Emit1 and the second control signal Emit2 are different. During the operating cycle of the first pixel circuit 01, the effective pulse period of the first control signal Emit1 and the effective pulse period of the second control signal Emit2 partially overlap. This overlap refers to the fact that both control signals are at an active level during a certain period of time. It will be understood that during the operating cycle of the first pixel circuit 01, during the period when the effective pulses of the first control signal Emit1 and the effective pulses of the second control signal Emit2 overlap, the first pixel circuit 01 can provide a drive current to control the first light-emitting device LD1 to emit light.

[0049] In a display panel provided by an embodiment of the present invention, the control terminals of the first light-emitting control module 10 and the second light-emitting control module 20 in the first pixel circuit 01 are configured to receive a first control signal Emit1 and a second control signal Emit2, respectively. In the second pixel circuit 02, the control terminals of the first light-emitting control module 10 and the second light-emitting control module 20 both receive the first control signal Emit1 or the second control signal Emit2. During the light-emitting phase of the first pixel circuit 01, at least the first control signal Emit1 and the second control signal Emit2 control the duration of the driving current provided to the first pixel circuit 01. However, during the light-emitting phase of the second pixel circuit 02, only one of the first control signal Emit1 and the second control signal Emit2 controls the duration of the driving current provided to the second pixel circuit 02. The present invention enables different durations of driving current provided by the first pixel circuit 01 and the second pixel circuit 02 during operation in a first mode, allowing different light-emitting devices to have different light-emitting durations. This compensates for differences in luminous efficiency among the different light-emitting devices and improves the display quality of the display panel.

[0050] In some embodiments, as Figure 3 As shown, the control ends of the first light emitting control module 10 and the second light emitting control module 20 in the second pixel circuit 02 both receive the first control signal Emit1; wherein, in the first mode, the effective pulse width of the first control signal Emit1 is greater than the effective pulse width of the second control signal Emit2. Figure 4 A signal timing diagram provided by an embodiment of the present invention. Figure 4 The provided timing diagram can be applied to Figure 3 The pixel circuit provided in the embodiment. Figure 4 right Figure 3 The working cycle of the pixel circuit can be understood. Figure 4The illustrated timing sequence can be applied to the first pixel circuit 01 and the second pixel circuit 02 to illustrate their respective working cycles, but does not mean that the first pixel circuit 01 and the second pixel circuit 02 must work at the same time.

[0051] Combine Figure 3 and Figure 4 For example, taking a low-level signal as an active pulse signal, the operating cycles of both the first pixel circuit 01 and the second pixel circuit 02 include a gate reset phase t1, a data write phase t2, and a light-emitting phase t3. During the operating cycle of the first pixel circuit 01, the active pulse of the first control signal Emit1 and the active pulse of the second control signal Emit2 coincide during period t31. The period during which the first control signal Emit1 is an active pulse and the second control signal Emit2 is an inactive pulse is t32. During period t31, the first pixel circuit 01 provides a drive current to control the first light-emitting device LD1 to emit light. However, during period t32, the second light-emitting control module 20 is turned off, preventing the first pixel circuit 01 from providing a drive current. During the operating cycle of the second pixel circuit 02, both the first and second light-emitting control modules 10 and 20 are turned on during periods t31 and t32, when the first control signal Emit1 provides an active pulse. Consequently, during periods t31 and t32, the second pixel circuit 02 provides a drive current to control the second light-emitting device LD2 to emit light. This means that the lighting duration of the second light emitting device LD2 is longer than the lighting duration of the first light emitting device LD1.

[0052] In this embodiment, the first pixel circuit 01 is operated in the light-emitting stage t3, and the first control signal Emit1 and the second control signal Emit2 are used to control the duration of the driving current provided thereto. In the light-emitting stage t3, the second pixel circuit 02 is operated in the light-emitting stage t3, and only the first control signal Emit1 is used to control the duration of the driving current provided thereto. This enables the second pixel circuit 02 to provide the driving current for a longer duration than the first pixel circuit 01 in the first mode, so that the light-emitting duration of the second light-emitting device LD2 is longer than the light-emitting duration of the first light-emitting device LD1. This allows compensation for differences in light-emitting efficiency between different light-emitting devices, thereby improving the display effect of the display panel.

[0053] In some embodiments, Figure 3In this embodiment, the emission wavelength of the first light-emitting device LD1 is shorter than that of the second light-emitting device LD2. The different emission wavelengths of the first and second light-emitting devices LD1 and LD2 result in differences in luminous efficiency due to the different luminescent materials. Embodiments of the present invention enable the design of luminous duration based on the emission wavelength, enabling devices with longer emission wavelengths and relatively lower luminous efficiency to have a relatively longer luminous duration. For example, the first light-emitting device LD1 may emit green light, while the second light-emitting device LD2 may emit red light; alternatively, the first light-emitting device LD1 may emit blue light, while the second light-emitting device LD2 may emit red light.

[0054] In one embodiment, the red light emitting device in the display panel adopts Figure 3 The second pixel circuit 02 is driven, and the green light emitting device and the blue light emitting device are respectively Figure 3 The first pixel circuit 01 is driven. This can extend the light-emitting duration of the red light-emitting device, compensating for the low light-emitting efficiency of the red light-emitting device. In applications, it can improve color shift and enhance display effects.

[0055] In some embodiments, Figure 5 A schematic diagram of a pixel circuit in another display panel provided by an embodiment of the present invention is shown. Figure 6 Another signal timing diagram provided by an embodiment of the present invention. Figure 6 The provided timing diagram can be applied to Figure 5 The pixel circuit provided by the embodiment. Figure 5 As shown, the control ends of the first light-emitting control module 10 and the second light-emitting control module 20 in the second pixel circuit 02 both receive the first control signal Emit1; the first pixel circuit 01 also includes a first functional module 60, which is connected between the first electrode of the driving transistor Tm and the first signal terminal D1, and the control end of the first functional module 60 receives the third control signal K3.

[0056] Combine Figure 6 In the first mode, the effective pulse width of the first control signal Emit1 is smaller than the effective pulse width of the second control signal Emit2. The working cycles of the first pixel circuit 01 and the second pixel circuit 02 both include a gate reset phase t1, a data writing phase t2, and a light emitting phase t3.

[0057] Among them, in the working cycle of the first pixel circuit 01: in the t31 period, the effective pulse of the first control signal Emit1 coincides with the effective pulse of the second control signal Emit2, during which the first light-emitting control module 10 and the second light-emitting control module 20 are both turned on, and the first pixel circuit 01 provides a driving current to the first light-emitting device LD1; in at least part of the period during which the first control signal Emit1 is an ineffective pulse and the second control signal Emit2 is an effective pulse, that is, Figure 6 During period t33, the third control signal K3 provides a first active pulse p1 to control the first functional module 60 to turn on and write the first signal V1 provided by the first signal terminal D1 to the first electrode of the driver transistor Tm. The first signal V1 is a constant voltage signal, and its voltage value may or may not be equal to the voltage value of the signal provided by the first power supply terminal Pvdd. During period t33, the first functional module 60 turns on to write the first signal V1 to the first electrode of the driver transistor Tm. The second emission control module 20 also turns on, enabling the driver transistor Tm to generate a drive current. During this period, the first pixel circuit 01 provides a drive current to the first light-emitting device LD1. During periods t31 and t33 of the light-emitting phase t3, the first pixel circuit 01 provides a drive current to the first light-emitting device LD1, controlling its emission. During the operating cycle of the second pixel circuit 02, the first and second emission control modules 10 and 20 are only turned on during period t31, when the first control signal Emit1 provides an active pulse, enabling the second pixel circuit 02 to provide a drive current to control the emission of the second light-emitting device LD2. Then the lighting time of the second light emitting device LD2 is shorter than the lighting time of the first light emitting device LD1.

[0058] In this embodiment, in the first mode, the effective pulse width of the first control signal Emit1 is smaller than the effective pulse width of the second control signal Emit2, and a first functional module 60 is added to the first pixel circuit 01. During the operating cycle of the first pixel circuit 01, during the period when the second control signal Emit2 is an active pulse and the first control signal Emit1 is an active pulse, the first light-emitting control module 10, the driving transistor Tm, and the second light-emitting control module 20 are connected in series to form a light-emitting channel, and the first pixel circuit 01 provides a driving current to the first light-emitting device LD1. During the period when the second control signal Emit2 is an active pulse and the first control signal Emit1 is an inactive pulse, the first functional module 60, the driving transistor Tm, and the second light-emitting control module 20 are connected in series to form another light-emitting channel, and the first pixel circuit 01 provides a driving current to the first light-emitting device LD1. In this embodiment, the duration of the driving current provided during the light-emitting phase t3 of the first pixel circuit 01 is controlled by the first control signal Emit1, the second control signal Emit2, and the third control signal K3. However, during the light-emitting phase t3 of the second pixel circuit 02, the duration of the driving current provided is controlled solely by the first control signal Emit1. This embodiment can achieve that in the first mode, the time duration for the first pixel circuit 01 to provide the driving current is longer than the time duration for the second pixel circuit 02 to provide the driving current, so that the light-emitting time duration of the first light-emitting device LD1 is longer than the light-emitting time duration of the second light-emitting device LD2, thereby compensating for the brightness difference caused by the difference in light-emitting efficiency of different light-emitting devices and improving the display effect of the display panel.

[0059] In some embodiments, as Figure 5 As shown, the first functional module 60 includes a first transistor T7, the gate of which receives the third control signal K3. The first electrode of the first transistor T7 is connected to the first signal terminal D1, and the second electrode of the first transistor T7 is connected to the first electrode of the driving transistor Tm. Optionally, the channel width and channel length of the first transistor T7 are respectively equal to the channel width and channel length of the first light-emitting control transistor T5, that is, the width-to-length ratio of the first transistor T7 is equal to the width-to-length ratio of the first light-emitting control transistor T5. This can make the characteristics of the first transistor T7 substantially the same as those of the first light-emitting control transistor T5, facilitate the design of the high and low levels of the third control signal K3, and simplify the control method of the pixel circuit.

[0060] In some embodiments, as Figure 5 As shown, a first pixel circuit 01 is coupled to a first light-emitting device LD1, and a second pixel circuit 02 is coupled to a second light-emitting device LD2. In the first pixel circuit 01, the control terminal of the first light-emitting control module 10 receives a first control signal Emit1, and the control terminal of the second light-emitting control module 20 receives a second control signal Emit2. In the second pixel circuit 02, the control terminals of both the first light-emitting control module 10 and the second light-emitting control module 20 receive the first control signal Emit1. The first pixel circuit 01 also includes a first functional module 60, which is connected between the first electrode of the driving transistor Tm and the first signal terminal D1. The control terminal of the first functional module 60 receives a third control signal K3. In a first mode, the effective pulse width of the first control signal Emit1 is less than the effective pulse width of the second control signal Emit2. During the operating cycle of the first pixel circuit 01, during at least a portion of the time period when the first control signal Emit1 is an inactive pulse and the second control signal Emit2 is an active pulse, the third control signal K3 provides a first active pulse p1 to control the first functional module 60 to turn on and write the first signal provided by the first signal terminal D1 to the first electrode of the driving transistor Tm. Figure 5 In this embodiment, the emission wavelength of the first light-emitting device LD1 is greater than that of the second light-emitting device LD2. The different emission wavelengths of the first and second light-emitting devices LD1 and LD2 result in differences in luminous efficiency due to the different luminescent materials. This embodiment of the present invention allows for the design of the luminous duration based on the emission wavelength, enabling devices with longer emission wavelengths and relatively lower luminous efficiency to have a relatively longer luminous duration. For example, the first light-emitting device LD1 emits red light, while the second light-emitting device LD2 emits green or blue light.

[0061] In one embodiment, the red light emitting device in the display panel adopts Figure 5The first pixel circuit 01 is driven, and the green light emitting device and the blue light emitting device are respectively Figure 5 The second pixel circuit 02 is driven. This can extend the light-emitting duration of the red light-emitting device, compensating for the low light-emitting efficiency of the red light-emitting device. In applications, it can improve color shift and enhance display effects.

[0062] In some embodiments, as Figure 6 As shown, the falling edge of the first effective pulse p1 is located after the rising edge of the effective pulse (i.e., the low-level signal) of the first control signal Emit1. This configuration ensures that the on-time period of the first functional module 60 and the on-time period of the first light-emitting control module 10 do not overlap, thus avoiding the risk of short circuit caused by the simultaneous on-time of the two modules.

[0063] It should be noted that Figure 6 The figure illustrates an ideal pulse signal. The transitions from high to low and from low to high appear instantaneous. In reality, both transitions require a certain amount of time. The transition from high to low is called a falling edge, and the transition from low to high is called a rising edge. Both rising and falling edges in actual pulse signals have a certain arc. For example, the falling edge is the transition from a high level to a low level. The starting moment of the falling edge is when the high level begins to fall, and the ending moment is when the signal reaches the target low level.

[0064] in addition, Figure 6 The figure shows that the rising edge of the second control signal Emit2 is after the rising edge of the third control signal K3. Optionally, the rising edge of the second control signal Emit2 coincides with the rising edge of the third control signal K3, that is, the second control signal Emit2 and the third control signal K3 have rising edges in the same period. Alternatively, the rising edge of the second control signal Emit2 may also be before the rising edge of the third control signal K3.

[0065] in addition, Figure 6 The figure also illustrates that the falling edge of the second control signal Emit2 coincides with the falling edge of the first control signal Emit1. Optionally, the falling edges of the two signals may be arranged one after the other. For example, the falling edge of the second control signal Emit2 is located after the falling edge of the first control signal Emit1. The following embodiments also illustrate that the falling edge of the second control signal Emit2 coincides with the falling edge of the first control signal Emit1.

[0066] In some embodiments, as Figure 6As shown, during period t33, the third control signal K3 provides a first effective pulse p1. The duration of the first effective pulse p1 is m1, and the interval between the falling edge of the first effective pulse p1 and the rising edge of the effective pulse of the first control signal Emit1 is m2, where m1>m2. That is, in the actual pulse signal, the interval between the end of the rising edge of the effective pulse of the first control signal Emit1 and the start of the falling edge of the first effective pulse p1 is m2. During the operating cycle of the first pixel circuit 01, only the second control signal Emit2 is an effective pulse during the period between the falling edge of the first effective pulse p1 and the rising edge of the effective pulse of the first control signal Emit1, and the first pixel circuit 01 cannot provide a drive current. The duration m1 of the first effective pulse p1 affects the light-emitting duration of the first light-emitting device LD1. During the light-emitting phase t3, the longer the duration m1, the longer the light-emitting duration of the first light-emitting device LD1 compared to the second light-emitting device LD2. In this embodiment, m1>m2 is set, and m2 is set to be smaller during the working cycle of the first pixel circuit 01, so that more time can be used to adjust the light-emitting duration of the first light-emitting device LD1, so that the light-emitting duration modulation has greater freedom.

[0067] In some embodiments, as Figure 6 As shown, the duration of the first effective pulse p1 is m1, and the duration of the effective pulse of the first control signal Emit1 is m3, where m3>m1. The duration of the effective pulse of the first control signal Emit1 can also be understood as the effective pulse width of the first control signal Emit1. In this embodiment, the time during which the second pixel circuit 02 provides the driving current is controlled by the first control signal Emit1, and the effective pulse width of the first control signal Emit1 affects the duration of the light emission of the second light-emitting device LD2. Furthermore, for the first pixel circuit 01, during the t31 period, the first control signal Emit1 is an effective pulse and the second control signal Emit2 is an effective pulse. The period (t31 period) during which the first control signal Emit1 is an effective pulse can be considered the first light-emitting period of the first pixel circuit 01, and the period (t33 period) during which the third control signal K3 is an effective pulse can be considered the second light-emitting period of the first pixel circuit 01. In this embodiment, m3>m1 is set, and the first effective pulse p1 can be used in conjunction with the second control signal Emit2 in the first mode to increase the luminous duration of the first light-emitting device LD1, while also ensuring that the second light-emitting device LD2 driven by the second pixel circuit 02 also has sufficient luminous duration.

[0068] In some embodiments, the display panel includes different operating modes, and adapts to different operating modes to match different pulse widths of control signals, so that the light-emitting device can have different light-emitting durations in different modes.

[0069] In one embodiment, Figure 7 Another signal timing diagram provided by an embodiment of the present invention Figure 7 Only the signal timings of the first control signal Emit1, the second control signal Emit2, and the third control signal K3 are provided Figure 7 Can be applicable to Figure 5 The pixel circuit provided by the embodiment. Combining Figure 5 And Figure 7 It can be seen that the display panel includes a first mode mode1 and a second mode mode2; in the first mode mode1, the first control signal Emit1 and the second control signal Emit2 are different control signals; in the second mode mode2, the first control signal Emit1 and the second control signal Emit2 are different control signals

[0070] From Figure 7 It can be seen that the effective pulse width of the second control signal Emit2 in the first mode mode1 is less than the effective pulse width of the second control signal Emit2 in the second mode mode2, and the pulse width of the first effective pulse p1 of the third control signal K3 in the first mode mode1 is less than the pulse width of the first effective pulse p1 in the second mode mode2. Among them, the coincidence duration of the effective pulse of the second control signal Emit2 and the first effective pulse p1 in the first mode mode1 is m4, and the coincidence duration of the effective pulse of the second control signal Emit2 and the first effective pulse p1 in the second mode mode2 is m5, and m4 < m5. In this embodiment, the "coincidence duration" means that both pulse signals are effective pulses within a certain time period, and the time length of this time period is the coincidence duration of the two pulse signals. The content related to the "coincidence duration" in the following embodiments can also be understood by referring to this part of the description

[0071] It should be noted that Figure 7 It is shown that the rising edge of the second control signal Emit2 is before the rising edge of the third control signal K. Optionally, the rising edge of the second control signal Emit2 is after the rising edge of the third control signal K, or the rising edge of the second control signal Emit2 coincides with the rising edge of the third control signal K. Only one case is shown in the following related drawings. And the "coincidence duration" is defined by the rising edge of the one that is the first rising edge among the two

[0072] During the working cycle of the first pixel circuit 01, the overlapping period of the effective pulse of the second control signal Emit2 and the first effective pulse p1 enables the first pixel circuit 01 to provide drive current to the first light-emitting device LD1. In this embodiment, the pulse widths of the first effective pulse p1 in two modes are different, the effective pulse width of the second control signal Emit2 is different, and m4 < m5 is set. In the same mode, the overlapping duration of the effective pulse of the second control signal Emit2 and the first effective pulse p1 affects the increase in the light-emitting duration of the first light-emitting device LD1 compared to the second light-emitting device LD2, that is, the longer the overlapping duration, the longer the light-emitting duration of the first light-emitting device LD1 and the greater the increase in the light-emitting duration of the first light-emitting device LD1 compared to the second light-emitting device LD1. This embodiment can make the increase in the light-emitting duration of the first light-emitting device LD1 compared to the second light-emitting device LD2 in the second mode mode2 greater than that in the first mode mode1. That is to say, in the second mode mode2, the first light-emitting device LD1 has a longer light-emitting duration to provide more compensation for its brightness to meet the brightness requirements of the first light-emitting device LD1 in different working modes.

[0073] In addition, as Figure 7 shown, the effective pulse width of the first control signal Emit1 in the first mode mode1 is less than that in the second mode mode2. In this way, it can be achieved that the light-emitting duration of the second light-emitting device LD2 in the second mode mode2 is longer than that in the first mode mode1, and it can also make the first light-emitting device LD1 have a longer light-emitting duration in the second mode mode2 compared to that in the first mode mode1. Combining with the design of m4 < m5, it can be achieved that the first light-emitting device LD1 and the second light-emitting device LD2 have different light-emitting durations in different modes, and the increase in the light-emitting duration of the first light-emitting device LD1 is greater in the second mode mode2. Thus, different degrees of brightness compensation can be performed for different-color light-emitting devices in different modes to improve the display effect.

[0074] In some embodiments, the operating temperature in the first mode (mode 1) is lower than the operating temperature in the second mode (mode 2). Optionally, the first mode (mode 1) is a normal temperature operating mode, and the second mode (mode 2) is a high temperature operating mode. Because the luminous efficiency of light-emitting devices is significantly affected by temperature, and the luminous efficiency of different color LEDs is affected differently by temperature, color shift and brightness reduction may occur in high temperature operating modes. The design of the embodiments of the present invention can increase the lighting duration of the first light-emitting device LD1 and the lighting duration of the second light-emitting device LD2 in the second mode (mode 2), thereby compensating for the brightness reduction caused by the decrease in luminous efficiency due to high temperature. Furthermore, the lighting duration of the first light-emitting device LD1 in the second mode (mode 2) can be increased compared to the lighting duration of the second light-emitting device LD2. For example, if the luminous efficiency of the first light-emitting device LD1 is more affected by temperature than that of the second light-emitting device LD2, the brightness of the first light-emitting device LD1 can be further supplemented in the second mode (mode 2). This allows for differentiated compensation based on the decrease in luminous efficiency caused by high temperature for different light-emitting devices, thereby improving display color shift.

[0075] In other embodiments, the brightness of the display panel in the first mode, mode 1, is lower than the brightness of the display panel in the second mode, mode 2. Optionally, the first mode, mode 1, is a low-brightness operating mode, and the second mode, mode 2, is a high-brightness operating mode. The design of the embodiment of the present invention can increase the luminous duration of the first light-emitting device LD1 and the luminous duration of the second light-emitting device LD2 in the second mode, mode 2, and make the luminous duration of the first light-emitting device LD1 longer than the luminous duration of the second light-emitting device LD2. This not only compensates for differences in luminous efficiency between different light-emitting devices, but also meets the brightness requirements of the devices in the high-brightness operating mode.

[0076] In other embodiments, Figure 8 Another signal timing diagram provided by an embodiment of the present invention is: Figure 8 Only the signal timings of the first control signal Emit1 , the second control signal Emit2 , and the third control signal K3 are provided. Figure 8 Applicable Figure 5 The pixel circuit provided in the embodiment. Figure 5 and Figure 8As shown, the display panel includes a first mode mode1 and a second mode mode2; in the first mode mode1, the first control signal Emit1 and the second control signal Emit2 are different control signals; in the second mode mode2, the first control signal Emit1 and the second control signal Emit2 are different control signals. Among them, the effective pulse width of the first control signal Emit1 in the first mode mode1 is equal to its effective pulse width in the second mode mode2; the effective pulse width of the second control signal Emit2 in the first mode mode1 is less than its effective pulse width in the second mode mode2, and the pulse width of the first effective pulse p1 of the third control signal K3 in the first mode mode1 is less than its pulse width in the second mode mode2. In the first mode mode1, the coincidence duration of the effective pulse of the second control signal Emit2 and the first effective pulse p1 is m4, and in the second mode mode2, the coincidence duration of the effective pulse of the second control signal Emit2 and the first effective pulse p1 is m5, and m4 < m5. This embodiment can achieve that the light-emitting duration of the first light-emitting device LD1 is greater than that of the second light-emitting device LD2 in one working mode, the light-emitting durations of the second light-emitting device LD2 in the first mode mode1 and the second mode mode2 are equal, and the light-emitting duration of the first light-emitting device LD1 in the second mode mode2 is greater than its light-emitting duration in the first mode mode1, and the increase in the light-emitting duration of the first light-emitting device LD1 compared to the second light-emitting device LD2 in the second mode mode2 is greater than the increase in the light-emitting duration of the first light-emitting device LD1 compared to the second light-emitting device LD2 in the first mode mode1.

[0077] In another embodiment, Figure 9 This is another signal timing diagram provided by the embodiment of the present invention, Figure 9 Only the signal timings of the first control signal Emit1, the second control signal Emit2, and the third control signal K3 are provided. Figure 9 Can be applied to Figure 5 The pixel circuit provided by the embodiment. Combining Figure 5 and Figure 9As shown, the display panel includes a first mode mode1 and a second mode mode2; in the first mode mode1, the effective pulse width of the second control signal Emit2 is less than that in the second mode mode2, and in the first mode mode1, the pulse width of the first effective pulse p1 is equal to that in the second mode mode2; in the first mode mode1, the coincidence duration of the effective pulse of the second control signal Emit2 and the first effective pulse p1 is m4, and in the second mode mode2, the coincidence duration of the effective pulse of the second control signal Emit2 and the first effective pulse p1 is m5, where m4 < m5. Here, the "coincidence duration" means that both pulse signals are effective pulses within a certain time period, and the time length of this time period is the coincidence duration of the two pulse signals. The parts related to the coincidence duration can be understood by referring to this. This embodiment sets the pulse width of the first effective pulse p1 to be equal in the two modes, and the effective pulse widths of the second control signal Emit2 in the two modes are different. Combining with the setting of m4 < m5, it can be realized that the first light-emitting device LD1 has a longer light-emitting duration in the second mode mode2 than in the first mode mode1. In the second mode mode2, the first light-emitting device LD1 has a longer light-emitting duration to perform more compensation for its brightness, so as to meet the brightness requirements of the first light-emitting device LD1 in different working modes.

[0078] In addition, Figure 9 It also shows that in the first mode mode1, the effective pulse width of the first control signal Emit1 is less than that in the second mode mode2. Such a setting can realize that the first light-emitting device LD1 and the second light-emitting device LD2 have different light-emitting durations in different modes. Moreover, combined with the design of m4 < m5, it can make the increase in the light-emitting duration of the first light-emitting device LD1 larger in the second mode mode2. Thus, different degrees of brightness compensation can be performed for light-emitting devices of different colors in different modes to improve the display effect.

[0079] Figure 9 The signal timing diagram provided by the embodiment can be applied to the scheme where the working temperature in the first mode mode1 is less than that in the second mode mode2, or to the scheme where the brightness of the display panel in the first mode mode1 is less than that in the second mode mode2.

[0080] In another embodiment, Figure 10 This is another signal timing diagram provided by the embodiment of the present invention. Figure 10 Only the signal timings of the first control signal Emit1, the second control signal Emit2, and the third control signal K3 are provided. Figure 10 Can be applied to Figure 5The pixel circuit provided by the embodiment. In combination with Figure 5 and Figure 10 viewed, the display panel includes a first mode mode1 and a second mode mode2; the effective pulse width of the second control signal Emit2 is equal in the first mode mode1 and the second mode mode2, and the pulse width of the first effective pulse p1 in the first mode mode1 is less than the pulse width of the first effective pulse p1 in the second mode mode2; in the first mode mode1, the coincidence duration of the effective pulse of the second control signal Emit2 and the first effective pulse p1 is m4, and in the second mode mode2, the coincidence duration of the effective pulse of the second control signal Emit2 and the first effective pulse p1 is m5, and m4 < m5. This embodiment sets the pulse widths of the first effective pulse p1 in the two modes to be unequal, and the effective pulse widths of the second control signal Emit2 in the two modes to be equal. Combining with the setting of m4 < m5, it can be realized that the first light-emitting device LD1 has a longer light-emitting duration in the second mode mode2 than in the first mode mode1. In the second mode mode2, the first light-emitting device LD1 has a longer light-emitting duration to compensate its brightness more, so as to meet the brightness requirements of the first light-emitting device LD1 in different working modes.

[0081] In addition, Figure 10 also shows that the effective pulse width of the first control signal Emit1 in the first mode mode1 is less than the effective pulse width of the first control signal Emit1 in the second mode mode2. Such a setting can realize that the first light-emitting device LD1 and the second light-emitting device LD2 have different light-emitting durations in different modes. Moreover, combined with the design of m4 < m5, it can make the increase in the light-emitting duration of the first light-emitting device LD1 in the second mode mode2 larger. Therefore, different degrees of brightness compensation can be carried out for different color light-emitting devices in different modes to improve the display effect.

[0082] Figure 10 The signal timing diagram provided by the embodiment can be applied to the scheme where the working temperature in the first mode mode1 is less than the working temperature in the second mode mode2, or can be applied to the scheme where the brightness of the display panel in the first mode mode1 is less than the brightness of the display panel in the second mode mode2.

[0083] In some embodiments, Figure 11 This is another signal timing diagram provided by the embodiment of the present invention. Figure 11 The provided timing diagram can be applied to Figure 5 the pixel circuit provided by the embodiment. In combination with Figure 11 and Figure 5From a holographic perspective, the operating cycle of the first pixel circuit 01 includes a data writing phase t2; data writing phase t2 occurs before the second control signal Emit2 provides an effective pulse. Before data writing phase t2, the third control signal K3 provides a second effective pulse p2 to control the activation of the first functional module 60 and write the first pre-charge signal V2 provided by the first signal terminal D1 to the first electrode of the driver transistor Tm. In this embodiment, the third control signal K3 provides the second effective pulse p2 before data writing phase t2 and the first effective pulse p1 during the light-emitting phase t3, respectively. The first functional module 60 is activated during two separate periods. The first functional module 60 not only cooperates with the second light-emitting control module 20 during the light-emitting phase to form an additional light-emitting channel, thereby increasing the light-emitting duration of the first light-emitting device LD1, but also pre-charges the first electrode of the driver transistor Tm before data writing phase t2. This ensures more complete data writing during data writing phase t2, thereby improving display uniformity.

[0084] In some embodiments, as Figure 11 As shown, at least during the period when the second effective pulse p2 controls the first functional module 60 to be turned on, the first signal terminal D1 provides a first pre-charge signal V2. The first pre-charge signal V2 is a constant voltage signal. This configuration enables the first pixel circuits 01 arranged at different positions in the display panel to be pre-charged using the same voltage signal, thereby simplifying the wiring in the display panel, reducing the number of signal terminals in the display panel, saving space, and correspondingly reducing the manufacturing cost of the display driver chip.

[0085] In some embodiments, the voltage value of the first pre-charge signal V2 is greater than the voltage value of the first signal V1. In this embodiment, the first signal terminal D1 provides a signal at least in two different time periods, and the first pre-charge signal V2 and the first signal V1 provided by the first signal terminal D1 have different functions. The first pre-charge signal V2 is used to pre-charge the first electrode of the driving transistor Tm before the data writing phase t2, thereby ensuring that the data is written more fully in the data writing phase t2. The first signal V1 is used to bias the driving transistor Tm to generate a driving current in the light-emitting phase t3, thereby providing a driving current to the first light-emitting device LD1 to increase the light-emitting duration. Setting the voltage value of the first pre-charge signal V2 to be relatively large can achieve a good pre-charging effect on the first electrode of the driving transistor Tm in a relatively short period of time.

[0086] In some embodiments, the first power terminal Pvdd provides a first power signal Pvdd, and the first power terminal and the first power signal have the same reference numeral. The voltage of the first pre-charge signal V2 is greater than the voltage of the first power signal Pvdd. In conjunction with the operating cycle of the first pixel circuit 01, during the period when the first control signal Emit1 is at an active level, the first power terminal Pvdd and the first electrode of the driver transistor Tm are conductive, writing the first power signal Pvdd to the first electrode of the driver transistor Tm. During period t31, the first control signal Emit1 and the second control signal Emit2 are both at active levels, and the light-emitting channel formed in series by the first light-emitting control module 10, the driver transistor Tm, and the second light-emitting control module 20 operates, providing a drive current to the first light-emitting device LD1. In other words, the first power signal Pvdd is used to bias the driver transistor Tm to generate a drive current during the light-emitting phase t3. The first pre-charge signal V2 is used to pre-charge the first electrode of the driving transistor Tm before the data writing phase t2. Although the first pre-charge signal V2 and the first power supply signal Pvdd are both written to the first electrode of the driving transistor Tm, they have different writing periods and functions. Setting the voltage value of the first pre-charge signal V2 relatively high can effectively pre-charge the first electrode of the driving transistor Tm in a relatively short period of time.

[0087] In some embodiments, the voltage value of the first signal V1 is equal to the voltage value of the first power signal Pvdd.

[0088] In some other embodiments, the voltage value of the first signal V1 is not equal to the voltage value of the first power signal Pvdd.

[0089] In some embodiments, as Figure 5 As shown, the gate reset module 30 in the pixel circuit is connected between the reset signal terminal Ref and the gate of the driving transistor Tm, and the control terminal of the gate reset module 30 receives the first scanning signal S1. Figure 11From the above, in the working cycle of the first pixel circuit 01: in the gate reset phase t1, the first scan signal S1 provides an effective pulse to control the gate reset module 30 to start and write the reset signal Ref to the gate of the driving transistor Tm to reset the gate of the driving transistor Tm; wherein, the period during which the third control signal K3 provides the second effective pulse p2 and the period during which the first scan signal S1 provides the effective pulse at least partially overlap. It can be understood that the duration of the pixel circuit working cycle is related to the refresh rate of the display panel. When the number of pixel rows of the display panel is determined, the higher the refresh rate and the shorter the driving time allocated to each pixel row, the shorter the working cycle of the pixel circuit. In an embodiment of the present invention, the second effective pulse p2 of the third control signal K3 can control the first functional module 60 to start to pre-charge the first electrode of the driving transistor Tm, and the second effective pulse p2 needs to be provided before the data writing phase t2. The gate reset phase t1 is the original working period in the working cycle of the first pixel circuit 01. The period of setting the second effective pulse p2 and the period of providing the effective pulse by the first scanning signal S1 at least partially overlap, which can reduce the impact of setting the second effective pulse p2 on the working cycle length of the first pixel circuit 01, and ensure that the length of the working cycle can match the display refresh rate.

[0090] In some embodiments, as Figure 11 As shown, during the operating cycle of the first pixel circuit 01, the start time of the second effective pulse p2 provided by the third control signal K3 coincides with the start time of the effective pulse provided by the first scanning signal S1, and the end time of the second effective pulse p2 provided by the third control signal K3 coincides with the end time of the effective pulse provided by the first scanning signal S1. In other words, the third control signal K3 provides the second effective pulse p2 during the gate reset phase t3. This configuration does not affect the total duration of the operating cycle of the first pixel circuit 01, but also ensures that the pre-charging time for the first electrode of the driving transistor Tm is sufficiently long.

[0091] In some embodiments, as Figure 11 As shown, the pulse width of the second effective pulse p2 is smaller than the pulse width of the first effective pulse p1. The pulse width of the second effective pulse p2 affects the charging time for precharging the first electrode of the driving transistor Tm, while the pulse width of the first effective pulse p1 affects the luminescence duration of the first light-emitting device LD1. Setting a larger pulse width for the first effective pulse p1 allows for a greater range of control over the luminescence duration during the operating cycle of the first pixel circuit 01.

[0092] In some embodiments, Figure 12 Another pixel circuit diagram provided by an embodiment of the present invention is shown. Figure 13 Another signal timing diagram provided by an embodiment of the present invention. Figure 13 The provided timing diagram can be applied to Figure 12 The pixel circuit provided by the embodiment. Figure 12 As shown, the first pixel circuit 01 includes a first functional module 01, and a second functional module 70 is connected between the first electrode of the driving transistor Tm and the first signal terminal D1. The second pixel circuit 02 includes a second functional module 70, and the second functional module 70 is connected between the first electrode of the driving transistor Tm and the second signal terminal D2. Figure 13 From the working cycle of the second pixel circuit 02, during the period when the first control signal Emit1 is a non-valid pulse, such as period t33, the second functional module 70 starts to write the second signal provided by the second signal terminal D2 into the first electrode of the driving transistor Tm.

[0093] The operating cycle of the second pixel circuit 02 includes a gate reset phase t1, a data write phase t2, and a light-emitting phase t3. During light-emitting phase t3, during the period when the first control signal Emit1 is an active pulse, i.e., period t31, the first light-emitting control module 10 and the second light-emitting control module 20 are both turned on. The first light-emitting control module 10, the driving transistor Tm, and the second light-emitting control module 20 form a light-emitting channel that provides a driving current to the second light-emitting device LD2. In the operating cycle of the first pixel circuit 01, during period t31 of light-emitting phase t3, the first light-emitting control module 10, the driving transistor Tm, and the second light-emitting control module 20 form one light-emitting channel; during period t32, the first functional module 60, the driving transistor Tm, and the second light-emitting control module 20 form another light-emitting channel. This results in the operating duration of the driving transistor Tm in the first pixel circuit 01 being longer than that in the second pixel circuit 02, which may result in a difference in the threshold shift of the two driving transistors Tm. In this embodiment of the present invention, a second functional module 70 is provided in the second pixel circuit 02. This module 70 can be used to write a second signal to the first electrode of the driving transistor Tm during non-luminous periods (i.e., during the portion of time when the first control signal Emit1 is an inactive pulse) to adjust the bias state of the driving transistor Tm. This embodiment can reduce the difference in the bias state of the driving transistor Tm in the first pixel circuit 01 and the second pixel circuit 02, thereby reducing the difference in the characteristics of the driving transistor Tm in the two pixel circuits, thereby improving display uniformity.

[0094] In some embodiments, the second signal terminal D2 and the first signal terminal D1 are configured to provide the same signal. When the second signal terminal D2 and the first signal terminal D1 provide constant voltage signals during the operating cycle of the pixel circuit, signal lines that cross horizontally and vertically and are electrically connected can be configured in the display panel to form a grid-like routing, wherein the grid-like routing includes a first signal line and a second signal line, the first functional module 60 is coupled to the first signal line, and the first signal line serves as the first signal terminal D1, the second functional module 70 is coupled to the second signal line, and the second signal line serves as the second signal terminal D2. Such a configuration can reduce the voltage drop on the signal line and improve the uniformity of the panel signal. When the second signal terminal D2 and the first signal terminal D1 provide different signals in time-sharing during the operating cycle of the pixel circuit, the first pixel circuit 01 and the second pixel circuit 02 located in the same pixel circuit row can be configured to couple to the same signal line, and the signal line serves as the second signal terminal D2 and the first signal terminal D1. Setting the second signal terminal D2 and the first signal terminal D1 to provide the same signal can simplify the wiring of the display panel and save space.

[0095] When the second signal terminal D2 and the first signal terminal D1 provide the same signal, the t33 period during which the first pixel circuit 01 works corresponds to the t33 period during which the second pixel circuit 02 works, and the first signal provided by the first signal terminal D1 and the second signal provided by the second signal terminal D2 have the same voltage value.

[0096] In some embodiments, the first functional module 60 is turned on during the t33 period when the first pixel circuit 01 is working, and the second functional module 70 is turned on during the t33 period when the second pixel circuit 02 is working. The t33 period when the first pixel circuit 01 is working corresponds to the t33 period when the second pixel circuit 02 is working. Figure 12 As shown, the control end of the second functional module 70 and the control end of the first functional module 60 receive the same signal, that is, the control end of the second functional module 70 receives the third control signal K3. This arrangement can simplify the wiring in the display panel and save space.

[0097] In one embodiment, a display panel includes a first drive circuit, a second drive circuit, and a third drive circuit, each of which includes multiple cascaded shift registers. The display panel also includes a first control line, a second control line, and a third control line. The first control line is coupled to the first drive circuit and provides a first control signal, Emit1; the second control line is coupled to the second drive circuit and provides a second control signal, Emit2; and the third control line is coupled to the third drive circuit and provides a third control signal, K3.

[0098] In some embodiments, as Figure 12As shown, the second functional module 70 includes a second transistor T8, a control terminal of the second transistor T8 receives a third control signal K3, a first electrode of the second transistor T8 is connected to the second signal terminal D2, and a second electrode of the second transistor T8 is connected to the first electrode of the driving transistor Tm.

[0099] Optionally, the second transistor T8 and the first transistor T7 have the same channel width and the same channel length.

[0100] In other embodiments, Figure 12 The pixel circuit provided in the embodiment can also adopt Figure 11 Driven by the signal timing in Figure 11 From the above, the working cycle of the second pixel circuit 02 includes a gate reset phase t1, a data writing phase t2, and a light-emitting phase t3. In the working cycle of the second pixel circuit 02: the first control signal Emit1 provides a valid pulse in the light-emitting phase t3, and the data writing phase t2 occurs before the first control signal Emit1 provides a valid pulse; before the data writing phase t2, the third control signal K3 provides a second valid pulse p2 to control the second functional module 70 to turn on and write the second pre-charge signal provided by the second signal terminal D2 to the first electrode of the driving transistor Tm. When the second signal terminal D2 and the first signal terminal D1 provide the same signal, the voltage value of the second pre-charge signal is equal to the voltage value of the first pre-charge signal V2. In this embodiment, the second functional module 70 can write the second signal to the first electrode of the driving transistor Tm during the non-light-emitting period to adjust the bias state of the driving transistor Tm, reduce the difference in the characteristics of the driving transistor Tm in the two pixel circuits, and help improve display uniformity. The second functional module 70 can also pre-charge the first electrode of the driving transistor Tm before the data writing phase t2, which can ensure that the data writing in the data writing phase t2 is more sufficient, and is conducive to improving display uniformity.

[0101] In other embodiments, Figure 14 Another pixel circuit diagram provided by an embodiment of the present invention is shown. Figure 15 Another signal timing diagram provided by an embodiment of the present invention is: Figure 14 Implementation of the provided pixel circuit can employ Figure 15 The signal timing provided in the embodiment is driven. Figure 14As shown, the control terminals of the first emission control module 10 and the second emission control module 20 in the first pixel circuit 01 both receive the first control signal Emit1. The control terminals of the first emission control module 10 and the second emission control module 20 in the second pixel circuit 02 both receive the second control signal Emit2. The first pixel circuit 01 also includes a third functional module 80, which is connected between the second electrode of the driving transistor Tm and the first light-emitting device LD1. The control terminal of the third functional module 80 receives the fourth control signal K4. The third functional module 80 is connected in parallel with the second emission control module 20.

[0102] Combine Figure 15 From the timing diagram, in the first mode, the effective pulse width of the first control signal Emit1 is greater than the effective pulse width of the second control signal Emit2. The working cycle of the first pixel circuit 01 includes a gate reset phase t1, a data writing phase t2, and a light emitting phase t3. In the working cycle of the first pixel circuit 01: at least part of the time period when the first control signal Emit1 is a valid pulse and the second control signal Emit2 is a non-valid pulse, such as Figure 15 During period t34, the fourth control signal K4 provides an active pulse to control the activation of the third functional module 80. During period t34, the first light-emitting control module 10, the driving transistor Tm, and the third functional module 80 form a light-emitting channel. During this period, the first pixel circuit 01 can provide a driving current to the first light-emitting device LD1, causing it to emit light. Furthermore, during period t31, both the first control signal Emit1 and the second control signal Emit2 are active pulses. During this period, the first light-emitting control module 10, the driving transistor Tm, and the second light-emitting control module 20 form a light-emitting channel, causing the first light-emitting device LD1 to emit light. During the operating cycle of the first pixel circuit 01, the first light-emitting device LD1 emits light during periods t31 and t34. For the second pixel circuit 02, both the first light-emitting control module 10 and the second light-emitting control module 20 are controlled by the second control signal Emit2. This means that the light-emitting channel is only formed during period t31, causing the second light-emitting device LD2 to emit light. This embodiment can achieve that in the first mode, the luminous duration of the first light-emitting device LD1 is longer than the luminous duration of the second light-emitting device LD2, thereby compensating for the brightness difference caused by the difference in luminous efficiency of the two light-emitting devices, improving color deviation and enhancing display effects.

[0103] Optional, such as Figure 14 As shown, the third functional module 80 includes a third transistor T9, a control terminal of which receives a fourth control signal K4, a first electrode of the third transistor T9 connected to the second electrode of the driving transistor Tm, and a second electrode of the third transistor T9 connected to the first light-emitting device LD1. The third transistor T9 and the second light-emitting control transistor T6 have the same channel length and channel width.

[0104] In some embodiments, as Figure 15 As shown, in the first mode, the effective pulse width of the fourth control signal K4 is less than the effective pulse width of the second control signal Emit2. That is, the duration of the effective pulse provided by the fourth control signal K4 is less than the duration of the effective pulse provided by the second control signal Emit2. In this embodiment, the time during which the second pixel circuit 02 provides the drive current is controlled by the second control signal Emit2, and the effective pulse width of the second control signal Emit2 affects the duration of light emission of the second light-emitting device LD2. For the first pixel circuit 01, the period (t31) during which the second control signal Emit2 is an effective pulse can be considered the first light-emitting period of the first pixel circuit 01, and the period (t34) during which the fourth control signal K4 is an effective pulse can be considered the second light-emitting period of the first pixel circuit 01. In this embodiment, the effective pulse width of the fourth control signal K4 is set to be less than the effective pulse width of the second control signal Emit2. This allows the fourth control signal K4 to cooperate with the first control signal Emit1 in the first mode to increase the light-emitting period of the first light-emitting device LD1, while also ensuring that the second light-emitting device LD2 driven by the second pixel circuit 02 also has a sufficient light-emitting period.

[0105] In one embodiment, the red light emitting device in the display panel adopts Figure 14 The first pixel circuit 01 is driven, and the green light emitting device and the blue light emitting device are respectively Figure 14 The second pixel circuit 02 is driven. This can extend the light-emitting duration of the red light-emitting device, compensating for the low light-emitting efficiency of the red light-emitting device. In applications, it can improve color shift and enhance display effects.

[0106] In some embodiments, Figure 16 A schematic diagram of a display panel provided by an embodiment of the present invention is shown. Figure 16 It shows the area where a pixel circuit is located. Figure 17 for Figure 16 Schematic diagram of membrane disassembly. Figure 1 The schematic circuit diagram is shown in Figure 2. Figure 16As shown, the display panel is arranged with a first scan line S1, a second scan line S2, an emission control line Emit, and a reset signal line Ref. The first scan line S1 provides a first scan signal S1, the second scan line S2 provides a second scan signal S2, and the emission control line Emit provides an emission control signal Emit. The reset signal line Ref serves as a reset signal terminal Ref, providing a reset signal. The pixel circuit includes a drive transistor Tm, a data write transistor T1, a compensation transistor T2, a gate reset transistor T3, an electrode reset transistor T4, a first emission control transistor T5, a second emission control transistor T6, and a storage capacitor Cst. Figure 16 A first power supply terminal Pvdd is also shown.

[0107] Combine Figure 17 From the perspective of the display panel, the display panel at least includes a semiconductor layer 000, a first metal layer 001, a second metal layer 002, a third metal layer 003 and a fourth metal layer 004 located on the substrate. The semiconductor layer 000, the first metal layer 001, the second metal layer 002, the third metal layer 003 and the fourth metal layer 004 are sequentially arranged away from the substrate. Among them, the active layer of each transistor is located in the semiconductor layer 000, Figure 17 In the figure, the locations of the transistors are marked in the semiconductor layer 000. Figure 17 It can be seen that in this embodiment, the driving transistor Tm is a parallel structure of two transistors. Such a configuration can increase the width-to-length ratio, thereby increasing the driving current.

[0108] The first scan line S1 , the second scan line S2 , and the light emitting control line Emit are located in the first metal layer 001 , and the gates of the transistors are located in the first metal layer 001 . Figure 17 The diagram schematically illustrates the gate Tmg of the driver transistor Tm, which doubles as one plate C1 of the storage capacitor Cst. The other plate C2 of the storage capacitor Cst is located in the second metal layer 002, and the reset signal line Ref is also located in the second metal layer 002. Several connecting lines are arranged in the third metal layer 003, such as a first connecting line X1 connecting the gate reset transistor T3 to the gate Tmg of the driver transistor Tm, a second connecting line X2 connecting the gate reset transistor T3 to the reset signal line Ref, a third connecting line X3 connecting the second emission control transistor T6, and a fourth connecting line X4 connecting the first emission control transistor T5. The third connecting line X3 is electrically connected to the connecting electrode X5 through a first via O1. The connecting electrode X5 is connected to the light-emitting device, and the third connecting line X3 is used to couple the second emission control transistor T6 to the light-emitting device. The fourth connecting line X4 is connected to the first power supply terminal Pvdd through a second via O2. The first power supply terminal Pvdd and the connecting electrode X5 are located in the fourth metal layer 004.

[0109] In one embodiment, Figure 18 A partial schematic diagram of a display panel provided by an embodiment of the present invention, Figure 18 A pixel unit area is shown, and a pixel unit includes two first pixel circuits 01 and one second pixel circuit 02. The structures of the first pixel circuit 01 and the second pixel circuit 02 can be combined Figure 16 and Figure 17 Understand. Figure 3 The pixel circuit shown in the embodiment can be applied to Figure 18 In the display panel provided in the embodiment. Figure 18 As shown, the control terminal (i.e., gate) of the first emission control transistor T5 and the control terminal of the second emission control transistor T6 in the second pixel circuit 02 are both connected to the first control line Emit1, which provides a first control signal Emit1. The control terminal of the first emission control transistor T5 in the first pixel circuit 01 is connected to the first control line Emit1, and the control terminal of the second emission control transistor T6 is connected to the second control line Emit2, which provides a second control signal Emit2. The second pixel circuit 02 is coupled to a red light-emitting device, and one of the two first pixel circuits 01 is coupled to a green light-emitting device, and the other is coupled to a blue light-emitting device. Figure 18 The data line Data is also schematically shown in FIG. 4 . The data line Data provides a data signal and is located in the third metal layer 003 .

[0110] In another embodiment, Figure 19 A partial schematic diagram of another display panel provided by an embodiment of the present invention, Figure 19 A pixel unit area is shown, and a pixel unit includes a first pixel circuit 01 and two second pixel circuits 02. The positions of the transistors in the first pixel circuit 01 and the second pixel circuit 02 can be combined Figure 16 and Figure 17 Understand. Figure 12 The pixel circuit shown in the embodiment can be applied to Figure 19 In the display panel provided in the embodiment. Figure 19As shown, the first pixel circuit 01 includes a first functional module 60, which includes a first transistor T7. The second pixel circuit 02 includes a second functional module 70, which includes a second transistor T8. The control terminal of the first emission control transistor T5 and the control terminal of the second emission control transistor T6 in the second pixel circuit 02 are both connected to the first control line Emit1, which provides a first control signal Emit1. The control terminal of the first emission control transistor T5 in the first pixel circuit 01 is connected to the first control line Emit1, and the control terminal of the second emission control transistor T6 is connected to the second control line Emit2, which provides a second control signal Emit2. The control terminal of the first functional module 60 and the control terminal of the second functional module 70 are both connected to the third control line K3, which provides a third control signal K3. Figure 19 The first power supply terminal Pvdd and the first signal terminal D1 are also shown. The first pixel circuit 01 is coupled to a red light emitting device, and one of the two second pixel circuits 02 is coupled to a green light emitting device and the other is coupled to a blue light emitting device. Figure 19 The third control line K3 is located in the first metal layer 001, and the first power supply terminal Pvdd and the first signal terminal D1 are located in the same layer.

[0111] Figure 20 for Figure 18 A schematic diagram of a cross section at the mid-tangent line AA′. Figure 20 1 shows a driving transistor Tm, a first light emitting control transistor T5, a second light emitting control transistor T6, a storage capacitor Cst, and also shows a first control line Emit1, a second control line Emit2, a data line Data and a first power supply terminal Pvdd. Figure 17 From the above, we can see that the active layer of the transistor is located in the semiconductor layer 000, the first control line Emit1 and the second control line Emit2 are located in the first metal layer 001, the storage capacitor Cst has a plate and the second metal layer 002, the data line Data is located in the third metal layer 003, and the first power supply terminal Pvdd is located in the fourth metal layer 004.

[0112] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Figure 21 A schematic diagram of a display device provided by an embodiment of the present invention, such as Figure 21 As shown, the display device includes a display panel 100 provided by any embodiment of the present invention. The structure of the display panel has been described in the above embodiments and will not be repeated here. The display device provided by the embodiment of the present invention can be, for example, an electronic device such as a mobile phone, a computer, a tablet, a television, a transparent display device, etc.

[0113] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of pixel circuits and a plurality of light-emitting devices; the pixel circuit includes a driving transistor, a first light-emitting control module, and a second light-emitting control module; a first electrode of the driving transistor is coupled to a first power supply terminal through the first light-emitting control module, and a second electrode of the driving transistor is coupled to the light-emitting device through the second light-emitting control module; The pixel circuit includes a first pixel circuit and a second pixel circuit; The control end of the first light emitting control module in the first pixel circuit receives a first control signal, and the control end of the second light emitting control module receives a second control signal. The control ends of the first light emitting control module and the second light emitting control module in the second pixel circuit both receive the first control signal or both receive the second control signal. The display panel includes a first mode, in which the first control signal and the second control signal are different control signals; in a working cycle of the first pixel circuit, an effective pulse period of the first control signal and an effective pulse period of the second control signal partially overlap.

2. The display panel according to claim 1, wherein: Control terminals of the first light emitting control module and the second light emitting control module in the second pixel circuit both receive the first control signal; In the first mode, the effective pulse width of the first control signal is smaller than the effective pulse width of the second control signal; The first pixel circuit further includes a first functional module, the first functional module is connected between the first electrode and the first signal terminal of the driving transistor, and the control terminal of the first functional module receives a third control signal; In the working cycle of the first pixel circuit: in at least part of the time period when the first control signal is an ineffective pulse and the second control signal is a effective pulse, the third control signal provides a first effective pulse to control the first functional module to turn on and write the first signal provided by the first signal terminal into the first electrode of the driving transistor.

3. The display panel according to claim 2, wherein: The light emitting device includes a first light emitting device and a second light emitting device, the first light emitting device is coupled to the first pixel circuit, and the second light emitting device is coupled to the second pixel circuit; The light emission wavelength of the first light emitting device is greater than the light emission wavelength of the second light emitting device.

4. The display panel according to claim 2, wherein: The falling edge of the first valid pulse is located after the rising edge of the valid pulse of the first control signal.

5. The display panel according to claim 4, wherein: The duration of the first effective pulse is m1, and the interval between the falling edge of the first effective pulse and the rising edge of the first control signal effective pulse is m2, where m1>m2.

6. The display panel according to claim 2, wherein: The duration of the first effective pulse is m1, the duration of the effective pulse of the first control signal is m3, and m3>m1.

7. The display panel according to claim 2, wherein: The display panel further includes a second mode; in the second mode, the first control signal and the second control signal are different control signals; wherein, The effective pulse width of the second control signal in the first mode is less than the effective pulse width of the second control signal in the second mode, and the pulse width of the first effective pulse in the first mode is less than or equal to the pulse width of the first effective pulse in the second mode; In the first mode, the overlap time of the effective pulse of the second control signal and the first effective pulse is m4. In the second mode, the overlap time of the effective pulse of the second control signal and the first effective pulse is m5, m4. <m5。 8. The display panel according to claim 2, wherein: The display panel further includes a second mode; in the second mode, the first control signal and the second control signal are different control signals; wherein, The effective pulse widths of the second control signal are equal in the first mode and the second mode, and the pulse width of the first effective pulse in the first mode is smaller than the pulse width of the first effective pulse in the second mode; In the first mode, the overlap time of the effective pulse of the second control signal and the first effective pulse is m4. In the second mode, the overlap time of the effective pulse of the second control signal and the first effective pulse is m5, m4. <m5。 9. The display panel according to claim 2, wherein: The second pixel circuit includes a second functional module connected between the first electrode and the second signal terminal of the driving transistor; In a working cycle of the second pixel circuit: during a partial period in which the first control signal is an ineffective pulse, the second functional module is turned on to write the second signal provided by the second signal terminal into the first electrode of the driving transistor.

10. The display panel according to claim 9, wherein: The second signal terminal and the first signal terminal provide the same signal.

11. The display panel according to claim 9, wherein The control end of the second functional module and the control end of the first functional module receive the same signal.

12. The display panel according to claim 11, wherein: The working cycle of the second pixel circuit includes a data writing phase; In the working cycle of the second pixel circuit: the data writing phase is before the first control signal provides a valid pulse; before the data writing phase, the third control signal provides a second valid pulse to control the second functional module to start and write the second pre-charge signal provided by the second signal terminal into the first electrode of the driving transistor.

13. The display panel according to claim 2, wherein: The working cycle of the first pixel circuit includes a data writing phase; In the working cycle of the first pixel circuit: the data writing phase is before the second control signal provides a valid pulse; before the data writing phase, the third control signal provides a second valid pulse to control the first functional module to start and write the first pre-charge signal provided by the first signal terminal into the first electrode of the driving transistor.

14. The display panel according to claim 13, wherein: The first pre-charge signal is a constant voltage signal.

15. The display panel according to claim 14, wherein: A voltage value of the first precharge signal is greater than a voltage value of the first signal.

16. The display panel according to claim 13, wherein: The first power supply terminal provides a first power supply signal; A voltage value of the first pre-charge signal is greater than a voltage value of the first power supply signal.

17. The display panel according to claim 13, wherein: The pixel circuit further includes a gate reset module, the gate reset module is connected between the reset signal terminal and the gate of the driving transistor, and the control terminal of the gate reset module receives the first scanning signal; During a working cycle of the first pixel circuit: the first scanning signal provides an effective pulse to control the gate reset module to start and write the reset signal into the gate of the driving transistor; A period during which the third control signal provides the second effective pulse and a period during which the first scan signal provides the effective pulse at least partially overlap.

18. The display panel according to claim 17, wherein: In the working cycle of the first pixel circuit: the starting moment of the second effective pulse provided by the third control signal coincides with the starting moment of the effective pulse provided by the first scanning signal, and the ending moment of the second effective pulse provided by the third control signal coincides with the ending moment of the effective pulse provided by the first scanning signal.

19. The display panel according to claim 13, wherein: The pulse width of the second effective pulse is smaller than the pulse width of the first effective pulse.

20. The display panel according to claim 1, wherein The control ends of the first light emitting control module and the second light emitting control module in the second pixel circuit both receive the second control signal; In the first mode, the effective pulse width of the first control signal is greater than the effective pulse width of the second control signal; The first pixel circuit further includes a third functional module, the third functional module is connected between the second electrode of the driving transistor and the light emitting device, and the control terminal of the third functional module receives a fourth control signal; In a working cycle of the first pixel circuit: during at least a portion of a period when the first control signal is a valid pulse and the second control signal is an ineffective pulse, the fourth control signal provides a valid pulse to control the third functional module to start.

21. The display panel according to claim 20, wherein: In the first mode, the effective pulse width of the fourth control signal is smaller than the effective pulse width of the second control signal.

22. The display panel according to claim 1, wherein Control terminals of the first light emitting control module and the second light emitting control module in the second pixel circuit both receive the first control signal; In the first mode, the effective pulse width of the first control signal is greater than the effective pulse width of the second control signal.

23. The display panel according to claim 22, wherein: The light emitting device includes a first light emitting device and a second light emitting device, the first light emitting device is coupled to the first pixel circuit, and the second light emitting device is coupled to the second pixel circuit; The light emission wavelength of the first light emitting device is shorter than the light emission wavelength of the second light emitting device.

24. A display device, characterized in that: A display panel comprising any one of claims 1 to 23.

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