Command address signal training method and memory

Abstract

The present application relates to the field of integrated circuits, and discloses a training method for command address signals and a memory. The training method includes: a controller sends a command address signal to a storage particle; the storage particle samples the command address signal; the storage particle feeds back a multi-bit target sampling value of the command address signal to the controller; and the controller adjusts the delay of the command address signal based on the multi-bit target sampling value.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a command address signal training method and a memory. Background Art

[0002] In mainstream memory architectures, the controller is responsible for managing the read and write command operations of the storage medium, and the storage particles (storage medium) are responsible for storing data and responding to the controller's commands. The storage particles need to accurately receive the command address signals sent by the controller to ensure that the data can be read or written correctly. In order to achieve efficient data transmission, an accurate timing relationship must be established between the storage particles and the controller.

[0003] However, as the memory operating rate increases, the time window for command address signal transmission becomes shorter, and the mismatch caused by process deviation and environmental influence seriously affects the correct execution of commands by memory particles. Therefore, command address training (CA training) is required before the memory reads and writes operations to ensure that the memory particles can correctly receive the command address signal in each clock cycle, thereby improving the accuracy and reliability of data transmission. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a command address signal training method and a memory, which can improve the accuracy and reliability of data transmission and make the training process more flexible.

[0005] The technical solution of the embodiment of the present application is implemented as follows:

[0006] An embodiment of the present application provides a training method for a command address signal, the method comprising: a controller sends a command address signal to a storage particle; the storage particle samples the command address signal; the storage particle feeds back a multi-bit target sampling value of the command address signal to the controller; the controller adjusts the delay of the command address signal based on the multi-bit target sampling value.

[0007] In some embodiments of the present application, the storage particle feeds back the multiple bits of the target sampling value of the command address signal to the controller, including: the storage particle feeds back the multiple bits of the target sampling value to the controller in parallel via a data bus.

[0008] In some embodiments of the present application, before the storage particle feeds back the multiple-bit target sampling value of the command address signal to the controller, the method also includes: the controller sends multiple bit identifiers to the storage particle in parallel through the data bus; wherein the multiple bit identifiers represent the number of cycles of the multiple-bit target sampling value in the command address signal.

[0009] In some embodiments of the present application, the controller adjusts the delay of the command address signal based on the multi-bit target sampling value, including: the controller compares the multi-bit target sampling value with the corresponding multi-bit expected value; if any one of the target sampling values ​​is inconsistent with the corresponding one of the expected values, the controller adjusts the delay of the command address signal until the multi-bit target sampling value is consistent with the corresponding multi-bit expected value.

[0010] In some embodiments of the present application, the storage particle samples the command address signal, including: the controller also sends a chip select signal and a clock signal to the storage particle; the storage particle samples each cycle in the command address signal in response to the chip select signal and the clock signal.

[0011] An embodiment of the present application also provides a memory, which includes: at least one storage particle, and a controller; the controller is coupled to at least one of the storage particles and controls at least one of the storage particles; the controller is configured to send a command address signal to the storage particle; the storage particle is configured to sample the command address signal and feed back a multi-bit target sampling value of the command address signal to the controller; the controller is also configured to adjust the delay of the command address signal based on the multi-bit target sampling value.

[0012] In some embodiments of the present application, the memory also includes: a data bus; the controller and at least one of the storage particles are coupled to the data bus; the controller is also configured to send multiple bit identifiers in parallel to the storage particles through the data bus; wherein the multiple bit identifiers represent the number of cycles of the multiple-bit target sampling values ​​in the command address signal; the storage particles are also configured to feed back the multiple-bit target sampling values ​​in parallel to the controller through the data bus.

[0013] In some embodiments of the present application, the storage particle includes: an input buffer and an output buffer; the storage particle is also configured to turn on the input buffer to sample the command address signal; and, after a preset time, turn on the output buffer to feed back the multi-bit target sampling value of the command address signal to the controller.

[0014] In some embodiments of the present application, the storage particle also includes: a sampling circuit and a feedback circuit; the sampling circuit is configured to sample each cycle in the command address signal in response to a chip select signal and a clock signal; the feedback circuit is coupled to the sampling circuit and is configured to select multiple bits of the target sampling value in response to multiple bit identifiers and feed them back to the controller.

[0015] In some embodiments of the present application, the sampling circuit includes: a pass gate and a first latch unit; the pass gate is configured to receive the chip select signal and the clock signal to generate a pass clock signal; the first latch unit is coupled to the pass gate, configured to receive and respond to the pass clock signal, sample each cycle in the command address signal, and obtain a sampling value for each cycle.

[0016] In some embodiments of the present application, the feedback circuit includes: a multiplexer; the multiplexer is coupled to the first latch unit and is configured to select multiple bits of the target sampling values ​​from the sampling values ​​of each cycle in response to the multiple bit identifiers, and feed back the multiple bits of the target sampling values ​​to the controller.

[0017] In some embodiments of the present application, the feedback circuit also includes: a delay unit and a second latch unit; the delay unit is coupled to the second latch unit and is configured to transmit the chip select signal to the second latch unit after delay; the second latch unit is coupled to the multiplexer and is configured to latch and output the plurality of bit identifiers to the multiplexer in response to the chip select signal; wherein the delay unit and the select gate have equal device delays; and the second latch unit and the first latch unit have equal device delays.

[0018] It can be understood that, compared to training only a single cycle of the command address signal, the training method of the command address signal in the embodiment of the present application can train multiple cycles of the command address signal, thereby ensuring that multiple cycles or even all cycles of the command address signal can be correctly sampled, thereby improving the accuracy and reliability of data transmission. At the same time, in the embodiment of the present application, any multiple cycles of the command address signal can be selected as needed for training, so that the training process is more flexible and can adapt to various different needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The memory structure of the present invention is shown in FIG. Figure 1 ;

[0020] Figure 2 The memory structure of the present invention is shown in FIG. Figure 2 ;

[0021] Figure 3 The following is a schematic diagram of the implementation process of the training method of the command address signal in the embodiment of the present application. Figure 1 ;

[0022] Figure 4 The following is a schematic diagram of the implementation process of the training method of the command address signal in the embodiment of the present application. Figure 2 ;

[0023] Figure 5 The following is a schematic diagram of the implementation process of the training method of the command address signal in the embodiment of the present application. Figure 3 ;

[0024] Figure 6 The signal waveform of the embodiment of the present application is shown as follows: Figure 1 ;

[0025] Figure 7 The signal waveform of the embodiment of the present application is shown as follows: Figure 2 ;

[0026] Figure 8 The signal waveform of the embodiment of the present application is shown as follows: Figure 3 ;

[0027] Fig. 9 Schematic diagram of the composition structure of the storage particles in the embodiment of this application Figure 1 ;

[0028] Fig.10 Schematic diagram of the composition structure of the storage particles in the embodiment of this application Figure 2 . DETAILED DESCRIPTION

[0029] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0030] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0031] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0032] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0033] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0034] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items. The units "root", "bar" or "individual" for transmission lines all represent the same meaning.

[0035] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0036] Figure 1 and Figure 2 Schematic diagram of an exemplary composition structure of the memory in an embodiment of the present application.

[0037] like Figure 1 As shown, the memory 30 may include: a controller 10 and at least one storage particle 20, wherein the controller 10 is coupled to the storage particle 20 and the host HOST. The controller 10 may manage data stored in the storage particle 20 and communicate with the host HOST.

[0038] In the present application examples, reference Figure 1 , the controller 10 can send data to / receive data from the host HOST, and can send a command CMD and an address ADDR (i.e., a command address signal CA) to the storage particle 20. The controller 10 may include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 may receive a command CMD and an address ADDR from the host HOST, and the command generator 110 may generate an access command, a row hammer refresh command, etc. by decoding the command CMD received from the host HOST, and may provide the access command and the row hammer refresh command to the storage particle 20 through the device interface 130.

[0039] In addition, the controller 10 can control memory operations such as writing and reading by providing various signals to the storage particles 20 via the device interface 130. For example, the controller 10 can provide a write command to the storage particles 20. The write command is used to instruct the storage particles 20 to perform a write operation to store data in the storage particles 20.

[0040] In the present application examples, reference Figure 1 , the storage particle 20 includes a storage cell array 220 and a peripheral circuit 210. The peripheral circuit 210 may write data DATA to the storage cell array 220 or read data DATA from the storage cell array 220 and send the data DATA to the controller 10 based on a command CMD and an address ADDR received from the controller 10, or may provide a control signal CTRL for refreshing the memory cells included in the storage cell array 220 to the row decoding circuit and the column decoding circuit. That is, the peripheral circuit 210 may perform all operations to process the data in the storage cell array 220, and the peripheral circuit 210 may include a control circuit of the storage cell array 220.

[0041] like Figure 2As shown, the storage particles 20 are arranged at different positions in the memory, and the controller 10 can transmit the command address signal CA to each storage particle 20 through the fly-by (improved daisy chain) topology. Since different storage particles 20 are located at different positions in the topology, and the wiring lengths between different storage particles 20 and the controller 10 are also different, different storage particles 20 have different transmission delays and timing characteristics. In other words, the command address signal CA is transmitted to different storage particles 20, and there will be different delays. Therefore, command address training is required before the memory performs read and write operations to ensure that each storage particle 20 can correctly receive the command address signal CA.

[0042] Figure 3 The following is a flowchart of a method for training a command address signal provided in an embodiment of the present application. Figure 3 As shown, the command address signal training method includes steps S101 to S104, which will be described in conjunction with each step.

[0043] S101: A controller sends a command address signal to a storage particle.

[0044] S102: The storage particle samples the command address signal.

[0045] In the embodiment of the present application, after entering the command address training mode (CA training mode), the controller will send a command address signal CA, and the storage particle will sample the command address signal CA, but will not parse the sampled command address signal CA. In other words, in the command address training mode, the storage particle will not perform corresponding read / write operations based on the command address signal CA.

[0046] In some embodiments of the present application, the controller also sends a chip select signal CS_N and a clock signal CK_T to the storage particles. After entering the command address training mode, the controller can send the clock signal CK_T, the command address signal CA and the chip select signal CS_N according to the timing relationship during normal operation; wherein the clock signal CK_T, the command address signal CA and the chip select signal CS_N constitute a training command (training CMD). Here, normal operation refers to the read / write operation performed by the memory without entering the command address training mode.

[0047] Accordingly, the storage particles can also sample the command address signal CA in the same manner as in normal operation, that is, the storage particles can sample each cycle of the command address signal CA in response to the chip selection signal CS_N and the clock signal CK_T.

[0048] In the present application examples, reference Figure 6 , the storage particles will use the rising edge of the clock signal CK_T to sample each cycle of the command address signal CA when the chip select signal CS_N is pulled low; that is, the storage particles will sample the cycles C0~Cn in the command address signal CA to obtain the corresponding sampling values ​​0~sampling values ​​n.

[0049] It should be noted that in Figure 6 In the example, the frequency of the clock signal CK_T is twice the frequency of the command address signal CA. The rising edge of the clock signal CK_T is used inside the storage particle to sample the command address signal CA. Therefore, when the rising edge of the clock signal CK_T is in the middle of the data to be sampled, the sampling accuracy is the highest. In addition, the width of the chip select signal CS_N is the same as the number of cycles of the command address signal CA. If the command address signal CA has N cycles, the low level of the chip select signal CS_N also has N cycles. The changing edge of the chip select signal CS_N is aligned with the falling edge of the clock signal CK_T. The changing edge of the command address signal CA has no clear timing relationship with the clock signal CK_T before CA training is completed. After CA training is completed, the changing edge of the command address signal CA should be aligned with the falling edge of the clock signal CK_T.

[0050] S103 , the storage particle feeds back the multi-bit target sampling value of the command address signal to the controller.

[0051] S104: The controller adjusts the delay of the command address signal based on the multi-bit target sampling value.

[0052] In an embodiment of the present application, after completing the sampling of the command address signal CA, the storage particle will feed back the sampled multi-bit target sampling value to the controller. For example, the storage particle can feed back the 4-bit target sampling value (sampling value 0~sampling value 3) sampled in the cycle C0~C3 of the command address signal CA to the controller. For another example, the storage particle can feed back the n-1-bit target sampling value (sampling value 1~sampling value n-1) sampled in the cycle C1~Cn-1 of the command address signal CA to the controller. For another example, the storage particle can feed back the n+1-bit target sampling value (sampling value 0~sampling value n) sampled in the cycle C0~Cn of the command address signal CA (that is, all cycles of the command address signal CA) to the controller.

[0053] Furthermore, the controller may adjust the delay of the command address signal CA based on the multi-bit target sample value fed back by the storage particle.

[0054] It can be understood that, compared with training only a single cycle of the command address signal CA, the training method of the command address signal in the embodiment of the present application can train multiple cycles of the command address signal CA, thereby ensuring that multiple cycles or even all cycles of the command address signal CA can be correctly sampled, thereby improving the accuracy and reliability of data transmission.

[0055] At the same time, in the embodiment of the present application, any multiple cycles of the command address signal CA can be selected as needed to perform training. In this way, the training process is more flexible and can adapt to various different needs.

[0056] In some embodiments of the present application, Figure 4 Steps S201 to S202 are shown to achieve Figure 3 The step S103 shown will be described in combination with each step.

[0057] S201. The controller sends multiple bit identifiers to storage particles in parallel through a data bus; the multiple bit identifiers represent the number of cycles of a multi-bit target sampling value in a command address signal.

[0058] S202: The storage particles feed back multiple target sampling values ​​in parallel to the controller via the data bus.

[0059] In the embodiment of the present application, the bit identifier represents the number of cycles that need to be trained in the command address signal CA. For example, if the cycles C0 to C3 in the command address signal CA need to be trained, the bit identifier sent by the controller to the storage particle is 0 to 3. Accordingly, the storage particle can respond to multiple bit identifiers and feedback the corresponding multi-bit target sampling value to the controller. For example, if the bit identifier received by the storage particle is 0 to 3, the storage particle can feedback the sampling value 0 to the sampling value 3 obtained by sampling the cycles C0 to C3 in the command address signal CA to the controller.

[0060] In the embodiment of the present application, the data bus (DQ bus) is used to transmit the data signal DQ and the bidirectional selection signal DQS during normal operation (i.e., when the command address training mode is not entered). The DQ bus has a bidirectional transmission characteristic, that is, the controller can transmit data to the storage particles through the DQ bus, and the storage particles can also transmit data to the controller through the DQ bus. At the same time, the DQ bus has multiple bit widths (bits), so the DQ bus can transmit multiple bits of data in parallel, that is, the DQ bus can transmit multiple bits of data at the same time.

[0061] It can be understood that data is transmitted in parallel between the controller and the storage particles via the data bus, so that multiple target sampling values ​​can be fed back to the controller at the same time, thereby improving efficiency.

[0062] In the present application examples, reference Figure 6 The DQ bus can be driven by the controller or by the storage particles. Within a period of time after the chip select CS_N is pulled high, the controller drives the DQ bus input bit identifier n to select the number of cycles that need to be trained in the command address signal CA, that is, the cycle Cn in the command address signal CA needs to be trained. After a period of time, the storage particle will output the target sampling value corresponding to the cycle Cn to the controller through the DQ bus, and the target sampling value will be maintained until the next CS_N is pulled low.

[0063] In the present application, continue to refer to Figure 6 When the DQ bus is driven by the controller, the storage particle needs to receive the signal on the DQ bus (bit identifier n), so the input buffer (INBUF) inside the storage particle needs to be opened; when the DQ bus is driven by the storage particle, the storage particle needs to output the target sampling value corresponding to the cycle Cn to the DQ bus, so the output buffer (OUTBUF) inside the storage particle needs to be opened.

[0064] In some embodiments of the present application, Figure 5 Steps S301 to S302 are shown to achieve Figure 3 The step S104 shown will be described in combination with each step.

[0065] S301. The controller compares a multi-bit target sample value with a corresponding multi-bit expected value.

[0066] S302: If any one-bit target sample value is inconsistent with the corresponding one-bit expected value, the controller adjusts the delay of the command address signal until the multi-bit target sample values ​​are consistent with the corresponding multi-bit expected values.

[0067] It should be noted that Figure 7 The example shows the process of training the cycle C0 in the command address signal CA. Figure 7 For example, the controller fixes the phase and delay of the clock signal CK_T and the chip select signal CS_N, and continuously adjusts the delay of the command address signal CA, that is, continuously adjusts the delay of the CA bus. Then, the controller can find the left and right boundaries of the correct sampling of the particle according to whether the target sampling value corresponding to the cycle Cn of the particle feedback is the same as the expectation, that is, compare whether the target sampling value is consistent with the corresponding expected value, so as to determine the passing window.

[0068] refer to Figure 7, the controller adjusted the CA delay for the first to sixth times by increasing the delay of the command address signal CA step by step. Among them, only the third to fifth CA delay adjustments, the feedback obtained the same target sampling value as expected, that is, the particle-driven C0 matched the controller-driven 0; therefore, the third to fifth CA delay adjustments passed the training, while the first, second and sixth CA delay adjustments did not pass the training. Therefore, it can be determined that the CA delay adjustment amount from the third to the fifth time passes the window. For example, if the third CA delay adjustment amount is 3, and the fifth CA delay adjustment amount is 5, then the passing window is [3, 5].

[0069] In the embodiment of the present application, the controller can perform the same operation for multiple cycles of the command address signal CA. Figure 7 Similar training, that is, the controller can compare whether the multi-bit target sampling value is consistent with the corresponding multi-bit expected value, and adjust the delay of the command address signal CA until the multi-bit target sampling value is consistent with the corresponding multi-bit expected value; in this way, the common interval in which the storage particle can correctly sample multiple cycles in the command address signal CA can be found, thereby calculating the most appropriate CA delay.

[0070] It can be understood that multiple cycles of the command address signal CA are trained, so that multiple cycles or even all cycles of the command address signal CA can be correctly sampled, thereby improving the accuracy and reliability of data transmission. At the same time, in the embodiment of the present application, any multiple cycles of the command address signal CA can be selected as needed for training, so that the training process is more flexible and can adapt to various different needs.

[0071] In the present application examples, reference Figure 1 or Figure 2 The controller 10 is configured to send a command address signal to the storage particle. The storage particle 20 is configured to sample the command address signal and feed back a multi-bit target sampling value of the command address signal to the controller. The controller 10 is also configured to adjust the delay of the command address signal based on the multi-bit target sampling value.

[0072] In the present application examples, reference Figure 1 or Figure 2 The memory 30 further includes: a data bus. The controller 10 and at least one storage particle 20 are both coupled to the data bus.

[0073] In some embodiments of the present application, the controller 10 is further configured to send multiple bit identifiers to the storage particles in parallel through the data bus; wherein the multiple bit identifiers represent the number of cycles of the multi-bit target sampled value in the command address signal. The storage particles 20 are further configured to feed back the multi-bit target sampled value to the controller in parallel through the data bus.

[0074] In some embodiments of the present application, the controller 10 is also configured to compare the multi-bit target sampling value with the corresponding multi-bit expected value; if any target sampling value is inconsistent with the corresponding multi-bit expected value, the delay of the command address signal is adjusted until the multi-bit target sampling value is consistent with the corresponding multi-bit expected value.

[0075] In the present application examples, reference Figure 1 or Figure 2 The storage particle 20 includes: an input buffer and an output buffer.

[0076] In some embodiments of the present application, the storage particle 20 is further configured to enable an input buffer to sample a command address signal; and, after a preset time, enable an output buffer to feed back a multi-bit target sampling value of the command address signal to the controller.

[0077] In the present application examples, reference Figure 8 After the chip select signal CS_N is pulled low, the storage particle will use the falling edge of the chip select signal CS_N to pull up the input buffer enable signal IBEN to turn on the input buffer, so that the storage particle can receive the data of the DQ bus driven by the controller (that is, the bit mark sent by the controller). Among them, the bit mark is used to select the number of cycles required to be trained in the command address signal CA.

[0078] Continue to refer Figure 8 , the storage particle delays the chip select signal CS_N by A cycles (i.e., Atck), and uses the rising edge of the delayed signal Sample to sample the data on the DQ bus at this time. At this time, the driver on the controller side needs to remain stable. Among them, A cycles are determined by the storage particle. Then, after completing the sampling, the storage particle will turn off the input buffer (i.e., pull the enable signal IBEN low), so that the storage particle will no longer receive data on the DQ bus driven by the controller.

[0079] Continue to refer Figure 8 After the enable signal IBEN is pulled low for B cycles (i.e., B tck), the storage particle will pull up the enable signal OBEN of the output buffer to turn on the output buffer, so that the storage particle can drive the DQ bus and output the target sample value corresponding to the bit mark from the DQ bus. Among them, the controller drive needs to be canceled before the storage particle drive.

[0080] Continue to refer Figure 8 After receiving the target sampling value fed back by the storage particle, the controller will compare the target sampling value with the expected value to determine whether the storage particle has correctly sampled the training cycle of the command address signal CA.

[0081] Continue to refer Figure 8 If training is still needed, the controller sends a low-level chip select signal CS_N again. After the chip select signal CS_N is pulled low again, the storage particles will turn off the output buffer (i.e., pull the enable signal OBEN low) while turning on the input buffer (i.e., pull up the enable signal IBEN) and stop driving the DQ bus. In this way, the command address signal CA is trained iteratively to determine the most appropriate delay of the command address signal CA.

[0082] It can be understood that since the controller sends the bit mark to the storage particle, and the storage particle feeds back the target sampling value to the controller, both are transmitted through the DQ bus. Therefore, after the storage particle completes sampling and closes the input buffer, it turns on the output buffer after a preset time (B cycles). In this way, it can be ensured that the DQ bus only transmits unidirectional data at the same time, avoiding conflicts in data transmitted on the DQ bus and avoiding transmission errors.

[0083] In some embodiments of the present application, Fig. 9 As shown, the storage particle 20 further includes: a sampling circuit 211 and a feedback circuit 212. The sampling circuit 211 is configured to sample each cycle of the command address signal in response to the chip selection signal and the clock signal. The feedback circuit 212, coupled to the sampling circuit 211, is configured to select a multi-bit target sampling value in response to a plurality of bit identifiers and feed it back to the controller.

[0084] In some embodiments of the present application, Fig.10 As shown, the sampling circuit 211 includes: a gate Gt and a first latch unit DFF1. The gate Gt is configured to receive a chip select signal CS_N and a clock signal CK_T to generate a gate clock signal ck1. The first latch unit DFF1 is coupled to the gate Gt and configured to receive and respond to the gate clock signal ck1 to sample each cycle of the command address signal CA to obtain a sampled value of each cycle.

[0085] In the present application examples, reference Fig.10 In the process of training the command address signal, the controller 10 first outputs the clock signal CK_T, the chip select signal CS_N and the command address signal CA <n:0>After receiving these signals, the storage particles 20 will pass through the input buffer IB and transmit these signals to the circuit inside the storage particles 20 in a matching manner.

[0086] The clock signal CK_T and the chip select signal CS_N are transmitted to the gate Gt. The gate Gt selects n cycles in the clock signal CK_T based on the low level of the chip select signal CS_N, that is, outputs the gate clock signal ck1 to the first latch unit DFF1. Since the chip select signal CS_N is low level effective, the gate Gt can be an OR gate.

[0087] Command address signal CA <n:0>The first latch unit DFF1 will respond to the changing edge of the clock signal ck1 to the command address signal CA <n:0>Sampling is performed in each cycle to obtain the sampling value of each cycle, that is, the sampling values ​​CA_cycle_0 / CA_cycle_1 / … / CA_cycle_n are obtained.

[0088] In some embodiments of the present application, reference Fig.10 The feedback circuit 212 includes: a multiplexer MUX. The multiplexer MUX is coupled to the first latch unit DFF1 and is configured to select a multi-bit target sampling value CA_cycle_i / CA_cycle_j from the sampling values ​​CA_cycle_0 / CA_cycle_1 / … / CA_cycle_n of each cycle in response to a plurality of bit identifiers i / j, and feed the multi-bit target sampling value CA_cycle_i / CA_cycle_j back to the controller 10. Wherein, i and j are any values ​​from 0 to n.

[0089] In the present application examples, reference Fig.10 , the controller 10 drives the data bus (DQ bus) to input the bit mark i / j, which is transmitted to the circuit in the storage particle 20 through the input buffer IB. The multiplexer MUX selects the target sampling value CA_cycle_i / CA_cycle_j of the corresponding cycle number according to the bit mark i / j. The target sampling value CA_cycle_i / CA_cycle_j is fed back to the controller 10 through the output buffer OB.

[0090] Combination Figure 8 and Fig.10 The storage particle 20 receives the bit mark i / j sent by the controller 10 through the DQ bus, and needs to jump the enable signal IBEN of the input buffer IB to a high level to turn on the input buffer IB, so that the bit mark i / j can be transmitted to the inside of the storage particle 20. Correspondingly, the storage particle 20 feeds back the target sampling value CA_cycle_i / CA_cycle_j to the controller 10 through the DQ bus, and needs to jump the enable signal OBEN of the output buffer OB to a high level to turn on the output buffer OB, so that the target sampling value CA_cycle_i / CA_cycle_j can be transmitted to the outside of the storage particle 20.

[0091] In some embodiments of the present application, reference Fig.10 The feedback circuit 212 further includes: a delay unit Del and a second latch unit DFF2. The delay unit Del is coupled to the second latch unit DFF2 and is configured to transmit the chip select signal CS_N to the second latch unit DFF2 after delay. The second latch unit DFF2 is coupled to the multiplexer MUX and is configured to latch and output a plurality of bit identifiers i / j to the multiplexer MUX in response to the chip select signal CS_N.

[0092] In the present application examples, reference Fig.10 , the controller 10 sends out a plurality of bit identifiers i / j, which are transmitted to the second latch unit DFF2 via the DQ bus and the input buffer IB. The second latch unit DFF2 latches and outputs the plurality of bit identifiers i / j in response to the changing edge of the chip select signal CS_N. In other words, the second latch unit DFF2 samples the data of the DQ bus in response to the changing edge of the chip select signal CS_N.

[0093] In the present application, continue to refer to Fig.10 The delay unit Del and the gate Gt have equal device delays, and the second latch unit DFF2 and the first latch unit DFF1 have equal device delays. In this way, the signal output by the first latch unit DFF1 (the sampling value of each cycle CA_cycle_0 / CA_cycle_1 / … / CA_cycle_n), and the signal output by the second latch unit DFF2 (multiple bit identifiers i / j), can be transmitted to the multiplexer MUX at a matching time, thereby ensuring the correct operation of the multiplexer MUX.

[0094] It should be noted that Fig.10 The input buffer IB, output buffer OB, sampling circuit 211 and feedback circuit 212 shown in FIG. 2 may all belong to Figure 1 Peripheral circuitry 210 is shown.

[0095] It should be noted that, in this article, the term "includes", "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0096] The serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0097] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A command address signal training method, characterized in that: The method comprises: The controller sends a command address signal to the storage particle, and sends a plurality of bit identifiers to the storage particle in parallel through a data bus; The storage particle samples each cycle of the command address signal to obtain a corresponding multi-bit target sampling value, and in response to the multiple bit identifiers, feeds back the multiple bits of continuous target sampling values ​​to the controller in parallel through the data bus; The controller adjusts the delay of the command address signal based on the multiple consecutive target sampling values; The plurality of bit identifiers represent the number of cycles of the plurality of consecutive target sampling values ​​in the command address signal.

2. The command address signal training method according to claim 1, characterized in that: The controller adjusts the delay of the command address signal based on the multiple target sampling values, including: The controller compares the target sampled values ​​of multiple bits with corresponding expected values ​​of multiple bits; If any of the target sampled values ​​is inconsistent with the corresponding expected value, the controller adjusts the delay of the command address signal until the multiple target sampled values ​​are consistent with the corresponding expected values.

3. The command address signal training method according to claim 1, characterized in that: The storage particle samples the command address signal, including: The controller also sends a chip selection signal and a clock signal to the storage particle; The storage particle samples each cycle of the command address signal in response to the chip selection signal and the clock signal.

4. A memory, characterized in that: The memory includes: at least one storage particle, and a controller; the controller is coupled to the at least one storage particle and controls the at least one storage particle; the memory also includes: a data bus; the controller and the at least one storage particle are both coupled to the data bus; The controller is configured to send a command address signal to the storage particle, and send a plurality of bit flags to the storage particle in parallel through a data bus; The storage particle is configured to sample each cycle of the command address signal to obtain a corresponding multi-bit target sampling value, and in response to the multiple bit identifiers, to feed back multiple bits of continuous target sampling values ​​to the controller in parallel through the data bus; The controller is further configured to adjust the delay of the command address signal based on the multiple bits of the continuous target sample values; The plurality of bit identifiers represent the number of cycles of the plurality of consecutive target sampling values ​​in the command address signal.

5. The memory according to claim 4, characterized in that: The storage particle includes: an input buffer and an output buffer; The storage particle is further configured to enable the input buffer to sample the command address signal; and, after a preset time, enable the output buffer to feed back the multi-bit target sampling value of the command address signal to the controller.

6. The memory according to claim 4, characterized in that: The storage particle further includes: a sampling circuit and a feedback circuit; The sampling circuit is configured to sample each cycle of the command address signal in response to a chip selection signal and a clock signal; The feedback circuit is coupled to the sampling circuit and is configured to select a plurality of target sampling values ​​in response to the plurality of bit flags and feed them back to the controller.

7. The memory according to claim 6, characterized in that: The sampling circuit comprises: a gate and a first latch unit; The gate is configured to receive the chip select signal and the clock signal and generate a gate clock signal; The first latch unit is coupled to the gate, and is configured to receive and respond to the gate clock signal to sample each cycle of the command address signal to obtain a sampled value of each cycle.

8. The memory according to claim 7, characterized in that: The feedback circuit includes: a multiplexer; The multiplexer is coupled to the first latch unit and is configured to select a plurality of target sampling values ​​from the sampling values ​​of each cycle in response to the plurality of bit identifiers, and feed back the plurality of target sampling values ​​to the controller.

9. The memory according to claim 8, characterized in that: The feedback circuit further includes: a delay unit and a second latch unit; The delay unit is coupled to the second latch unit and is configured to delay the chip selection signal and transmit it to the second latch unit; The second latch unit is coupled to the multiplexer and is configured to latch and output the plurality of bit flags to the multiplexer in response to the chip selection signal; Wherein, the delay unit and the gate have equal device delay; the second latch unit and the first latch unit have equal device delay.

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