A clock jitter calculation and analysis method for a frequency-division clock path

Abstract

A clock jitter calculation and analysis method of a frequency division clock path comprises: performing jitter simulation on the frequency division clock path to obtain simulation signal waveform data; traversing all circuit units on the clock path to organize circuit unit related basic data, the related basic data including: clock period or clock frequency, reference voltage of input and output pins, and clock division multiple and division position; sampling the simulation signal waveform data to extract original edge sampling data; obtaining edge sampling data on adjacent pins in a "from back to front" order on the clock path to obtain time sampling sub-sequence data after edge alignment; calculating clock period samples and clock jitter amount according to the time sampling sub-sequence data to analyze dynamic propagation characteristics of the clock jitter amount. The present application calculates the clock jitter amount on the pins on the clock path step by step based on the sampling data after edge alignment, eliminating the influence of the clock period change caused by clock division.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, and in particular to a clock jitter calculation and analysis method for a frequency division clock path. BACKGROUND

[0002] In the field of chip design and manufacture, with the progress of technology and the increase of clock frequency, the possibility of manufacturing defects, clock jitter, duty cycle distortion, process parameter variation and power supply noise increases, and it becomes more and more difficult to ensure the correctness of the clock signal. Comparing the actual clock signal with the ideal clock signal cycle by cycle, there are two kinds of errors, one is long-term clock wander, and the other is short-term clock jitter between cycles. Clock wander generally refers to the phenomenon that the jitter frequency is less than 10Hz, which is caused by the incomplete matching of the load on the clock tree or physical design, etc., and it will cause the time inconsistency of the clock reaching each flip-flop; while clock jitter is the offset relative to the ideal clock edge that does not accumulate with time, sometimes leading and sometimes lagging, which can be quantitatively described by jitter frequency and jitter amplitude. Clock jitter will produce uncertainty on the period and rising and falling edges of the clock signal, thereby forcing the designer to either increase the time margin or face the possibility of operation failure. In addition, with the continuous expansion of chip size, power supply noise (PSN) becomes more and more important in timing uncertainty, and power supply noise will lead to complex interaction between clock path and logic path, at this time it is more meaningful to measure the total combined effect than to measure the delay variation in the clock path and data path alone. Clock jitter is an important indicator for evaluating the quality of the clock signal, and it is crucial in the timing uncertainty analysis of the clock signal, which can be used as an effective data reference for engineers to set timing margin in the timing analysis stage.

[0003] A jitter simulation analysis method containing dynamic power supply noise is proposed in Chinese Patent No. CN111079293B. By connecting a voltage source containing dynamic power supply noise to the power supply pin (such as VDD) and the ground pin (such as VSS) of the circuit unit, the signal waveform on the pin of each circuit unit in the clock path is obtained through SPICE simulation, and then the overall jitter amount is calculated by sampling the signal period, including period jitter, adjacent period jitter, time interval error, and phase noise. The jitter amount at the end of the clock path is usually taken as the jitter reference value of the clock path. Due to the influence of power supply noise on each stage of circuit unit, the jitter amount of the clock signal generally increases gradually along the clock path. When the clock path contains a frequency divider (Frequency Divider) unit, the jitter amount at the end of the clock path can be taken as the jitter reference value of the generated clock signal after frequency division. However, when checking the jitter amount change on the entire clock path, it can be observed that the jitter amount on the input and output pins before and after the frequency divider unit is significantly different. This is because the period of the original clock signal increases and the frequency decreases after frequency division, and the number of sampled signal flip-flops also decreases accordingly, resulting in a significant difference in jitter amount calculated by period sampling before and after frequency division. SUMMARY

[0004] To solve the defects of the prior art, the purpose of the present application is to provide a clock jitter calculation and analysis method for frequency division clock path, which obtains edge sampling data by sampling the simulation signal waveform in the "edge alignment" scheme from "back to front" on the clock path, and calculates the jitter amount on the pins of each stage of the clock path based on the edge sampling data after edge alignment. And in order to better analyze the process of the jitter amount of the clock signal changing along the clock path, the edge jitter amount on the pins of each stage of the clock path is dynamically linked by considering the edge trigger relationship between adjacent pins on the clock path, and then compared and analyzed in turn.

[0005] To achieve the above-mentioned purpose, the clock jitter calculation and analysis method for frequency division clock path provided by the present application comprises the following steps:

[0006] Perform jitter simulation on the frequency division clock path to obtain simulation signal waveform data;

[0007] Traverse all circuit units on the clock path to organize circuit unit related basic data, including: clock period or clock frequency, reference voltage of input and output pins, and clock division multiple and frequency division position;

[0008] Sample the simulation signal waveform data to extract the original edge sampling data;

[0009] Obtaining edge sampling data on adjacent pins in a "back-to-front" order on the clock path to obtain time sampling sub-sequence data after edge alignment;

[0010] Calculating clock period samples and clock jitter amount according to the time sampling sub-sequence data, and analyzing dynamic propagation characteristics of the clock jitter amount.

[0011] Further, the step of simulating jitter on the frequency division clock path to obtain simulation signal waveform data further comprises: building a jitter simulation netlist of the frequency division clock path, and connecting a voltage source containing dynamic variation power supply noise to the power supply and ground pins of the circuit unit; and performing SPICE simulation to obtain simulation signal waveform data.

[0012] Further, the step of traversing all circuit units on the clock path and organizing circuit unit related basic data further comprises:

[0013] Traversing all circuit units on the clock path, and associating related basic data from the unit timing library, timing constraint file, and jitter simulation task with the circuit units.

[0014] Further, the step of sampling the simulation signal waveform data and extracting original edge sampling data further comprises:

[0015] Sampling the simulation signal waveform data, and extracting original edge sampling data after removing redundant data sampling points on the same edge through a data checking and cleaning mechanism;

[0016] According to the different edge flip directions, the edge sampling data is divided into rising edge and falling edge sampling data, which is recorded as time sampling sub-sequence data of the rising edge and falling edge of each stage on the clock path.

[0017] Further, the step of removing redundant data sampling points on the same edge through a data checking and cleaning mechanism further comprises:

[0018] Traversing all waveform data in time sequence, and locating the time when all edges cross the preset edge detection threshold according to the preset edge detection threshold;

[0019] Confirming the monotonicity of voltage value change near the edge sampling point, comparing the interval value between adjacent edge sampling points and the reference clock period, and analyzing the data fluctuation between adjacent edge sampling points to dynamically remove redundant data sampling points on the same edge and ensure that only one edge time data point is collected on a clock signal flip edge.

[0020] Further, the method further comprises: calculating clock characteristic data of the sampling data according to the sampling edge time sequence, quickly locating the problematic sample and sampling time by counting the maximum value and the minimum value, determining the cause of the error sample collection, and iteratively optimizing the sampling, checking and cleaning of the edge data to improve the accuracy and stability of the sample data.

[0021] Further, the step of obtaining the edge sampling data of the adjacent pins in the "back-to-front" order along the clock path and aligning the edge sampling data of the waveforms before and after frequency division further comprises:

[0022] finding the output pin position of the last frequency divider unit along the clock path;

[0023] for the waveform edge sampling data located at the position before the output pin, obtaining the edge sampling data of the adjacent pins in the "back-to-front" order, aligning the position index of the first trigger edge of the next stage pin in the edge time sampling sequence of the previous stage pin according to the trigger relationship of the edges of the pins at the front and back stages, and directly calculating the position index sequence of the remaining aligned trigger edges according to the integer ratio of the frequencies before and after the frequency division;

[0024] extracting the corresponding time samples according to the position index sequence to form the time sampling sub-sequence data after the edge alignment.

[0025] Further, the step of calculating the clock period sample and the clock jitter amount according to the time sampling sub-sequence data further comprises:

[0026] taking the time difference between the adjacent positions in the time sampling sub-sequence as a clock period sample;

[0027] obtaining the corresponding clock jitter amount based on the clock period sample using the jitter amount calculation formula.

[0028] Further, the step of analyzing the dynamic propagation characteristics of the clock jitter amount further comprises:

[0029] according to whether there is an anti-correlation between the clock signal transmission between the pins of the adjacent circuit units, relating the clock jitter amounts of the corresponding edge types of the front and back stages: if there is an anti-correlation, the clock jitter amounts of the front and back stages are transmitted from the rising edge of the front stage to the falling edge of the back stage, and from the falling edge of the front stage to the rising edge of the back stage; if there is no anti-correlation, the clock jitter amounts of the front and back stages are transmitted from the rising edge of the front stage to the rising edge of the back stage, and from the falling edge of the front stage to the falling edge of the back stage;

[0030] The clock jitter amount calculated after the edge alignment is arranged according to the front-back relationship of the clock path, and the change process of the clock jitter amount of the aligned clock signal edge with the dynamic propagation of the clock path is directly expressed by means of a table or a broken line graph.

[0031] To achieve the above object, the application further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is used to execute the computer program stored in the memory to realize the clock jitter calculation and analysis method of the frequency division clock path.

[0032] To achieve the above object, the application further provides a computer readable storage medium, wherein the storage medium stores a computer program, and the computer program is loaded and executed by a processor to realize the clock jitter calculation and analysis method of the frequency division clock path.

[0033] Compared with the prior art, the clock jitter calculation and analysis method of the frequency division clock path has the following beneficial effects:

[0034] The data resampling is completed based on the edge alignment of the clock signal edge, and the edge resampling data can be aligned in quantity and time by the edge alignment process, and the front-back alignment edges have stable edge trigger relationships.

[0035] The clock jitter amount on the pins of the clock path is calculated based on the edge sampling data after the edge alignment, the influence of the clock period change caused by the clock frequency division is eliminated, and the calculated clock jitter amount can truly reflect the offset degree of the aligned signal edges.

[0036] Other features and advantages of the application will be described in the following description, and some will become apparent from the description, or will be understood by those skilled in the art through implementation of the application. BRIEF DESCRIPTION OF DRAWINGS

[0037] The accompanying drawings are used to provide a further understanding of the application, and constitute a part of the specification, and together with the embodiments of the application, are used to explain the application, and do not constitute a limitation of the application. In the drawings:

[0038] Figure 1 The clock jitter calculation and analysis method flow chart of the frequency division clock path according to the embodiment of the application;

[0039] Figure 2 The clock signal flip edge error sampling data schematic diagram according to the embodiment of the application;

[0040] Figure 3 The electronic device structure schematic diagram according to the embodiment of the application. DETAILED DESCRIPTION

[0041] The preferred embodiments of the present application will be described herein below with reference to the accompanying drawings; it should be understood that the preferred embodiments described herein are intended to be illustrative only and the present application is not intended to be limited thereto.

[0042] Embodiments of the present application will be described below in greater detail with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it is understood that the present application can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein, but rather, the embodiments are provided so that the present application can be more thoroughly and completely understood. It should be understood that the drawings and embodiments of the present application are for illustrative purposes only and are not intended to limit the scope of the present application.

[0043] The term "comprising" and variations thereof as used herein are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment." The term "another embodiment" means "at least one additional embodiment." The term "some embodiments" means "at least some embodiments." Related terms shall be construed accordingly.

[0044] It should be noted that the terms "first", "second", and the like, as used herein, can refer to different entities or components, and do not necessarily indicate the order or sequence of performing the functions of the entities or components.

[0045] It should be noted that the terms "one", "multiple", and the like, as used herein, are illustrative and not limiting, and those skilled in the art will understand that, unless otherwise explicitly stated in the context, "one" should be understood as "one or more" and "multiple" should be understood as two or more.

[0046] In the embodiment of the present application, a clock jitter calculation and analysis method of a frequency division clock path is provided, comprising: performing frequency division clock path Jitter simulation to obtain simulation signal waveform data; traversing all circuit units on the clock path to organize circuit unit related basic data; sampling signal waveform flip edge time sequence; aligning pre- and post-frequency waveform edge sampling data; calculating clock jitter amount; and analyzing dynamic propagation characteristics of the clock jitter amount. The method provides a simulation signal waveform periodic sampling scheme of "edge alignment from back to front" on the clock path, and calculates the jitter amount on the pins of each stage on the clock path based on the periodic sampling data after edge alignment. In the analysis stage, the signal edge trigger relationship of adjacent stages is also considered, and the signal edge jitter amount on the pins of each stage is compared in sequence according to the order of the clock path, so as to study the propagation change process of the clock jitter on a specific edge on the clock path. The "edge alignment from back to front" simulation signal waveform periodic resampling scheme refers to the clock signal after frequency division, and locates the corresponding signal waveform flip edge before frequency division, so that the signal waveform edges before and after frequency division can be aligned in time sequence and quantity, thereby eliminating the influence of clock period change caused by clock frequency division, and the calculated clock jitter amount can truly reflect the offset degree of the aligned signal edges.

[0047] Figure 1 The clock jitter calculation and analysis method of the frequency division clock path according to the embodiment of the present application is shown in the flowchart, Figure 1 The flow steps with asterisks are the key technical solutions of the present application, wherein the data checking and cleaning mechanism ensures the accuracy and effectiveness of the edge sampling data; the alignment of adjacent stage flip edges and the resampling scheme solve the problem of too large difference between the clock jitter amounts before and after clock frequency division; and the edge trigger relationship is followed in the clock jitter data organization and analysis, and the propagation process of the clock jitter is fully expressed. The following will be described with reference to Figure 1 The clock jitter calculation and analysis method of the frequency division clock path of the present application will be described in detail.

[0048] In step 101, a Jitter simulation netlist is built based on the frequency division clock path. The Jitter simulation netlist of the frequency division clock path is built, and a voltage source containing dynamic change power noise is connected to the power supply and ground pins of the circuit unit.

[0049] In the embodiment of the present application, the power supply noise signal can be fitted by a sine or cosine function, or directly connected to an external configuration or a PWL (Piece-wise Linear) noise waveform file produced by a third-party tool. The power supply noise causes complex interaction between the clock path and the logic path, causing the shift of the uncertainty of the clock signal. By obtaining the accurate waveform file of the clock signal through SPICE simulation, the calculation and analysis of the clock signal jitter amount can be completed. The frequency divider unit is included in the frequency division clock path. After the clock signal passes through the frequency divider unit, the period becomes larger, the frequency decreases, and the number of flip edges decreases. By analyzing the clock division information in the simulation netlist, a Verilog-A module is constructed to realize the edge trigger transmission between the input and output pins of the clock signal in the frequency divider unit, and the clock signal division is realized. As shown in Figure 1 As shown in the simulation netlist, the SPICE simulator can record and output the waveform data of all circuit unit pin nodes in the frequency division clock path, which is the original data basis for completing the calculation and analysis of the clock jitter amount of the clock path.

[0050] In step 102, SPICE simulation is performed. By performing SPICE simulation, the simulation signal waveform data on the pins of each circuit unit is obtained.

[0051] In the embodiment of the present application, during the construction of the Jitter simulation netlist and the execution of the SPICE simulation process, the circuit design file and the simulation configuration data will be fully utilized. The power supply noise waveform on the circuit unit can be fitted by a sine or cosine function, or a more realistic PWL signal can be provided externally to complete the SPICE simulation and obtain high-precision simulation signal waveform data.

[0052] In the embodiment of the present application, a simulation data analysis module is also constructed to read the waveform data in the simulation signal waveform data file. The waveform data is generally a sequence of discrete data pairs composed of time values and voltage values, arranged in chronological order. The waveform data records the accurate clock edge trigger information of the clock signal.

[0053] In step 103, the flip edge time sequence is sampled.

[0054] In the edge time sequence sampling process of the clock signal waveform data, the existing clock reference information is fully utilized, the edge sampling data is strictly checked according to the data checking and cleaning mechanism, the error sampled data is removed, and the accuracy of subsequent edge alignment and jitter calculation is ensured. In addition, the clock characteristic data of the sampling data, such as period, pulse width, duty cycle, etc., can be calculated according to the time sequence of the edge sampling. By calculating the maximum value and the minimum value (or adding the sorting function), the problem sample and the sampling time can be quickly located, the reason for the error sample collection can be found out, the method process of the edge data sampling, checking and cleaning is iteratively optimized, and the accuracy and stability of the sample data are improved. The added sampling data checking and cleaning mechanism ensures that the original edge sampling data truly reflects the time and quantity of the flip edge that meets the actual situation.

[0055] In the embodiment, all waveform data is traversed in chronological order, and the 50% simulation voltage value of each circuit unit is taken as the edge detection threshold value. The time when all edges cross the threshold value can be located and detected, and strict edge sampling data checking rules can be formulated, such as confirming the monotonicity of the voltage value change near the edge sampling point, comparing the adjacent edge sampling point interval value and the reference clock period, analyzing the data fluctuation between adjacent edge sampling points, etc. Redundant data sampling points on the same edge are dynamically excluded to ensure that only unique edge time data points are collected on a clock signal flip edge. The original edge sampling data is extracted in this way, and then the rising edge and falling edge sampling data are divided according to the different directions of the edge flip. The time sampling sub-sequences of the rising edge and the falling edge of the i(i≥0) level on the clock path are respectively and

[0056] For example Figure 2As shown, several cases encountered in actual cases are listed, which may cause abnormal flip edge data sampling process without increasing edge data checking and cleaning mechanism. The flip edge is amplified at the edge detection threshold (i.e. 50% VDD), and the hollow point represents the real effective waveform data sequence point position generated by SPICE simulation, in which R1-R5 represent examples of rising edges, and F1-F5 represent examples of falling edges. The examples of R1-R3 and F1-F3 show that when the edge transition time is large, the waveform data points are densely distributed at the edge detection threshold, and there is a small range of voltage fluctuation, or the voltage of adjacent points is equal to the edge detection threshold. These phenomena occur in a very small time range (within 1 ps), which cannot be found by visual inspection of the waveform, but will cause edge data error sampling. The examples of R4-R5 and F4-F5 show that when the edge transition time is very small, the waveform data points are sparsely distributed at the edge detection threshold, and there is a point whose voltage is equal to the edge detection threshold. This phenomenon will also cause edge data error sampling. Figure 2 In similar examples, time samples are generally collected by data interpolation, which will cause two or more time sample data to be collected on a flip edge, while only one is actually needed. The period sample value calculated by these error time samples is very small (within 1 ps), which is greatly deviated from the reference ideal period value, and will cause the clock jitter to be abnormally large. Therefore, edge data checking and screening mechanism is added to strictly check the data monotonicity, time interval length, data fluctuation range, etc. When encountering the above similar cases, redundant time sampling points on the same flip edge are removed, so that only one valid time sampling point is collected on a flip edge, ensuring the accuracy of subsequent flip edge alignment and clock jitter calculation process.

[0057] In this embodiment, before waveform data sampling, the step of organizing circuit unit related basic data is also included. First, all circuit units on the clock path are traversed, and useful data from information sources such as unit timing library, timing constraint file, jitter simulation task, etc. are associated with the circuit units, for example, clock period (or clock frequency), actual simulation voltage value (reference voltage of input and output pins), clock division information (such as division multiple, division position, etc.), which have important role in edge sampling and edge alignment stage of signal waveform.

[0058] In step 104, the waveform edge sampling data before and after alignment is divided.

[0059] In the embodiment of the present application, the clock signal at the end of the frequency division clock path has the characteristics of minimum frequency and maximum period during the clock frequency division process, so the edge sampling data after frequency division is used to align the edge sampling data before frequency division. The last frequency divider unit output pin position K (K>0) on the clock path is found, and the waveform edge sampling data located on the previous positions {0, 1, …, K-1} need to complete the data resampling after the adjacent stage flip edge alignment. The present application takes the edge sampling data on the adjacent pins in the order of “from back to front” to perform edge alignment work, and the specific method is as follows: according to the edge trigger relationship of the pins in the front and rear stages, the position index of the first trigger edge of the pin in the rear stage in the time sampling sequence of the pin in the front stage is aligned, and then the position indexes of the remaining alignment trigger edges are directly calculated according to the frequency integer ratio (or period integer ratio) before and after frequency division, and the corresponding time samples are extracted according to the position index sequence to form the time sampling sub-sequence data after edge alignment, denoted as and According to the edge alignment scheme, the aligned and The pins after position K are equivalent to the original data and But the pins before position K are the original data and Resampling generates a time sampling sub-sequence. In addition, even if there are multiple frequency divisions in the frequency division clock path, the clock period and the number of edges of the clock signal edge sampling data on all pins can be aligned through the above edge alignment scheme.

[0060] The clock signal is transmitted on the clock path through edge triggering, and in the edge trigger relationship between the front and rear stages of the clock frequency divider unit, it can be observed that only part of the edges trigger transmission forms the clock edge after frequency division before frequency division. The edge alignment process can align the number and time of the resampled data, and the aligned edge samples of the front and rear stages have stable edge trigger relationship.

[0061] The frequency division in the present application refers to the integer frequency division in synchronous design, and the position of the remaining edges can be calculated through the clock period integer ratio before and after frequency division by aligning the first edge, but in fact, more complex frequency division cases can also refer to the “edge alignment” scheme. By comparing all time sequence data before and after frequency division, the corresponding time samples of all edge times after frequency division in the edge data before frequency division are found, that is, more complex edge alignment work needs to be completed. For the clock path with multiple frequency divisions, the final frequency division clock edge is used as a reference in the order of “from back to front” to perform the edge alignment task in turn, so that the final clock jitter data can accurately reflect the offset degree of the clock edges with edge trigger relationship before and after.

[0062] In the embodiment of the present application, the edge trigger relationship of the front and rear stages of the clock path is accurately recorded and applied in the organization and analysis of the clock jitter data to effectively organize and express the propagation of the clock jitter. The clock jitter reflects the offset degree of a certain number of signal flip-flop edges. Since the edge trigger relationship of the signals on the clock path has the in-phase or anti-phase condition, the edge trigger relationship of the front and rear stages of the clock path should be accurately recorded and applied in the organization and analysis of the clock jitter data. When there is a frequency divider unit in the clock path, the clock signal after frequency division is only formed by part of the edge trigger of the clock signal before frequency division. At this time, it is more necessary to accurately record the front and rear edge trigger relationship and the corresponding edge trigger position index. After the edge alignment is completed, the propagation process of the clock jitter can be accurately expressed, and it is explained that these jitter data reflect the offset condition of which edges before frequency division. Even if there is no frequency divider unit in the clock path, the edge trigger condition of the front and rear stages of the clock path should be analyzed to more accurately express the propagation change of the clock jitter by connecting the jitter data of the front and rear stages. In the jitter data expression, the edge flip-flop direction identifier (i.e., Rise or Fall) is added to the jitter data of each stage of the clock path. When the jitter data of the front and rear stages is compared, the edge trigger relationship between the front and rear stages can be clearly understood, and it can be verified by viewing the SPICE simulation waveform. The edge trigger relationship efficiently increases the accurate expression of the clock jitter data propagation.

[0063] In step 105, the edge clock jitter is calculated.

[0064] In the embodiment, the time sampling sub-sequence data after the edge alignment and are the effective time sequences after the trigger edge alignment. The time difference between the adjacent positions of the time sequence can be used as a clock period sample. N time data can calculate N-1 period samples. The period sample data calculated by the rising edge and the falling edge sample data of the i(th) stage (i≥0) on the clock path are respectively and Based on the period sample, the corresponding clock jitter can be obtained by referring to the mature jitter calculation formula, such as the period jitter, the adjacent period jitter, the time interval error, etc. The root mean square (RMS) and the peak-to-peak value are used to represent the period jitter. The period jitter reflects the time error between the period sample and the ideal period. The adjacent period jitter reflects the time error between the adjacent period samples, and the time interval error reflects the time error of the signal edge relative to the ideal position of the clock. Ignoring the specific type of the clock jitter, the clock jitter of the rising edge and the falling edge of the i(th) stage (i≥0) on the clock path is uniformly represented by and respectively.

[0065] Some mature jitter calculation formulas used in the present application include the following, without distinguishing rising edges and falling edges, both rising edges and falling edges can be calculated by the following formulas respectively to obtain corresponding clock jitter.

[0066] Period Jitter calculation formula of the i(i≥0) stage on the clock path:

[0067] Δp ij = p ij - p ideal (Formula 1)

[0068]

[0069]

[0070] Period Jitter i | Pk-Pk = Δp ij | max - Δp ij | min (Formula 4)

[0071] As the above formula group, formula 1 calculates the deviation Δp ij of the j(j≥1) period sample p ideal of the i(i≥0) stage and the ideal period p ij ; formula 2 calculates the mean value of the period deviation sequence m is the total number of period samples; formula 3 obtains the root mean square value (RMS) of the period jitter according to the classical standard deviation calculation formula; formula 4 takes the difference between the maximum value and the minimum value of the period deviation as the peak-to-peak value (Pk-Pk) of the period jitter.

[0072] Cycle-to-Cycle Jitter calculation formula of the i(i≥0) stage on the clock path:

[0073] Δp′ ij = p ij - p i(j-1) (Formula 5)

[0074]

[0075]

[0076]

[0077]

[0078] As shown in the above set of equations, Equation 5 calculates the jth (j≥2) period sample p ij of the ith (i≥0) stage, and the deviation Δp' between the adjacent previous period sample p i(j-1) . ij Equation 6 calculates the mean of the adjacent period deviation sequence, where m is the total number of period samples, and the total number of adjacent period deviations is one less than m; similarly, Equation 7 calculates the root mean square (RMS) of the adjacent period jitter according to the classical standard deviation calculation formula; and Equations 8 and 9 calculate the peak-to-peak (Pk-Pk) values of the positive and negative adjacent period jitter, respectively, based on all of the adjacent period deviations.

[0079] The Time Interval Error (TIE) calculation formula of the ith (i≥0) stage on the clock path is:

[0080]

[0081]

[0082]

[0083] TIEJitter i | Pk-Pk = TIE ik | max - TIE ik | min (Equation 13)

[0084] As shown in the above set of equations, Equation 10 calculates the cumulative effect TIE ik of the period deviation Δp ij , which is the result of Equation 1, i.e., TIE ik represents the time interval error of the ith (i≥0) stage accumulated to the kth (k≥1) period sample, where the period sample deviation Δp ij encoded as j (k≥j≥1) is accumulated together; Equation 11 calculates the mean of the cumulative effect of the period deviation where m is the total number of period samples, and k (m≥k≥1) represents the cumulative period number when calculating the TIE ik ; similarly, Equation 12 calculates the root mean square (RMS) of the time interval error according to the classical standard deviation calculation formula; and Equation 13 takes the difference between the maximum and minimum values of the cumulative effect of the period deviation as the peak-to-peak (Pk-Pk) value of the time interval error.

[0085] In step 106, the clock jitter data is organized and analyzed. The clock jitter amount on the input and output pins of each circuit unit is organized according to the position sequence on the clock path, and the data on the adjacent pins needs to refer to the edge trigger relationship of the clock signal propagation to link the clock jitter amount of the corresponding edges of the front and rear stages.

[0086] In the embodiment of the present application, the process is organized according to whether there is an anti-correlation between the clock signal transmission of the adjacent circuit unit pins. If there is an anti-correlation, such as the input and output terminals of the inverter, the clock jitter amount of the front and rear stages is transmitted according to and If there is no anti-correlation, such as the input and output terminals of the buffer, the two ends of the interconnection line, the clock jitter amount of the front and rear stages is transmitted according to and Based on the above transmission rules, the clock jitter amount calculated from the sampling data of the aligned edges can be organized and arranged along the front and rear stage relationship of the clock path, and the change process of the clock jitter amount of the aligned clock signal edges can be directly expressed by means of tables or line graphs.

[0087] In the embodiment of the present application, in the process of organizing and analyzing the jitter data, the edge trigger relationship and other information recorded in the edge alignment process are used to link the clock jitter amount of the clock path stage by stage, form a data table or a graph, and present the propagation characteristics of the clock jitter. The clock jitter reflects the offset size of the clock edge, which dynamically changes with the transmission of the clock signal on the clock path. In the frequency division clock path, in order to accurately express the process of the clock jitter amount along the clock path, the edge alignment work needs to be done, so that the edge samples of the front and rear stages are aligned in quantity and time, and there is a stable edge trigger relationship between the front and rear stages. When organizing the clock jitter amount of the front and rear stages, the edge trigger relationship (in phase or inverse) of the front and rear stages needs to be referred to, so that the clock jitter amount of the aligned edges can be correctly linked in front and rear, forming a correct edge trigger propagation link. The dynamic change process of the clock jitter can be more directly expressed by means of data tables or line graphs. In addition, the resampled data of the aligned edges can also be analyzed based on this edge propagation link, that is, the resampled data of the aligned edges should have consistency in quantity and time in the front and rear stages of the propagation link, and the clock jitter size can be explained by means of the statistical characteristic data or distribution histogram of the edge data samples.

[0088] Referring to Table 1, a clock path with a frequency division circuit unit is listed, and a comparison example of period jitter data before and after frequency division is given. The clock waveform before frequency division is {0 0.5}, and the clock period is 1.0 ns. The clock waveform after frequency division is {01.0}, and the clock period is 2.0 ns. The jitter simulation process introduces 5% dynamic fluctuation range of power supply noise on the voltage source (VDD) of the circuit unit. In Table 1, before the edge alignment is implemented, the number of edge samples at the input end of the frequency divider unit is twice that at the output end, and the RMS and peak-to-peak value of the period jitter data at the input end are much larger than those at the output end. After the edge alignment is implemented, the number of edge samples at the input end of the frequency divider is the same as that at the output end, the edge trigger relationship is accurate and stable (the frequency division unit has R2R and R2F edge trigger relationships), and the RMS and peak-to-peak value of the period jitter data at the input end are significantly reduced and slightly smaller than those at the output end. It can be seen that the edge alignment scheme completes resampling of the edge sample data, so that the edge samples are aligned in number and time, and the calculated clock jitter more accurately reflects the offset degree of the clock edges with edge trigger relationship between the front and rear stages.

[0089] Table 1 Comparison example of clock jitter data before and after clock frequency division

[0090]

[0091] The clock jitter calculation and analysis method of the frequency division clock path of the present application has the following advantages compared with the prior art:

[0092] (1) Explains the problem of large difference in clock jitter before and after clock division. In actual application cases of Jitter simulation, when a divider unit is included in the clock path, an abnormal phenomenon of large difference in clock jitter on the input and output pins of the divider unit can be observed, which will cause confusion among data users. By comparing the waveform data of the Jitter simulation signal, the present invention can observe that the period of the original clock signal increases, the frequency decreases, and the number of flip edges decreases after passing through the divider unit. The technical solution of edge alignment was experimented. The flip edges with a small number but a large period span after division were used as a reference, and the edge alignment of the waveform edge data before division was performed. After resampling, the clock jitter was calculated, so that the difference in the jitter amount of the original clock before and after division was significantly reduced, and a reasonable change trend was presented. According to experimental data, the number of signal edges before clock division is significantly greater than after division. The original clock jitter reflects the degree of offset of these edges. However, when passing through the divider unit, a large portion of the signal edges do not flip. In other words, the time offset on these signal edges cannot pass through the divider unit. This is the fundamental reason for the large difference in clock jitter before and after clock division. The edge sample data obtained by resampling after edge alignment effectively eliminates all signal edges that cannot pass through the divider, retaining an equal number of sample data with consistent edge triggering relationships. The calculated clock jitter also normally reflects the offset of the aligned edges, which is more consistent with actual conditions when comparing and serializing the clock jitter before and after division.

[0093] (2) Pay attention to the inspection and cleaning of clock signal edge sampling data, which is the condition for the signal edge to be fully aligned. Ensuring the quantity and quality of the signal flip edge time sampling data is the key to correctly analyzing clock jitter. The clock jitter amount of each level on the timing path is calculated based on a limited number of edge sampling data. To ensure the correctness of the data sample, when encountering abnormal sampling data, it is necessary to continuously strengthen the accuracy of the data sampling module. Figure 2In several special cases, over-sampling at the same edge may result in very small period sample data, affecting the final clock jitter result, so the sampling data needs to be strengthened and cleaned up to exclude redundant error sampling data. In addition, the alignment of the trigger edges before and after the clock signal division is based on aligning the first trigger edge samples before and after, and then calculating the remaining sample position index according to the integer ratio of the division period, so the quality of the sample data also affects the correctness of the edge alignment. Accurate sampling of the edge time ensures that the edge trigger relationship before and after the division is unique, and the edge alignment result is also unique. Whether it is the influence of setting the edge sampling voltage threshold or the deficiency of the waveform data generated by the SPICE simulator, the edge data sampling method and the checking mechanism should be optimized to ensure that only unique time sample data is collected at each signal flip edge, so as to ensure the accuracy and stability of the subsequent process steps.

[0094] (3) The expression of the clock jitter changing with the clock path propagation is improved. In the actual application case of Jitter simulation, it can be observed that the clock jitter on the rising edge and the falling edge will increase gradually with the clock path propagation. In order to better express this dynamic change trend, the clock jitter contained in the clock path needs to be arranged in sequence. Since the trigger states of the adjacent two levels of clock edges can be divided into two categories of same phase and opposite phase, in the same phase clock edge trigger, the edge jitter of the previous stage is transmitted to the same category edge of the next stage; and in the opposite phase clock edge trigger, the edge jitter of the previous stage is transmitted to the different category edge of the next stage. Generally, the clock jitter at the end of the clock path is taken as the key jitter reference value of the whole clock path. According to the accurate and stable edge trigger relationship on the clock path, the source of the clock jitter of the next stage can be traced from back to front, and vice versa, that is, the clock jitter on the aligned edge propagates along the clock path in turn. However, it should be noted that in the synchronous circuit, the trigger types of the edges before and after the frequency divider may not be single, such as a clock signal with a period of 1.0 and a waveform of (0, 0.5) before frequency division, which generates a clock signal with a period of 2.0 and a waveform of (0, 1.0) after frequency division. In this case, only the rising edge of the clock signal before frequency division completes the trigger action, that is, part of the rising edge is transmitted in the same phase to the rising edge after frequency division, and the other part of the rising edge is inverted to the falling edge after frequency division, while the trigger relationship of the remaining adjacent two levels of edges is generally a single edge trigger relationship. In the actual processing process, the source of the clock jitter on the rising edge and the falling edge needs to be traced back in turn from back to front, that is, the edge trigger relationship of the previous and next stages can be determined in the edge alignment work, and the edge time sample and the signal waveform diagram can be used to verify and explain the propagation process of the clock jitter.

[0095] In the embodiment of the application, an electronic device is also provided,Figure 3 A schematic diagram of an electronic device structure according to an embodiment of the present application is shown in FIG. 3, which shows an electronic device of the present application, including a processor 301 and a memory 302, wherein, Figure 3

[0096] The memory 302 stores a computer program, which, when read and executed by the processor 301, performs the steps in the clock jitter calculation and analysis method embodiment of the frequency-divided clock path as described above.

[0097] In an embodiment of the present application, a computer readable storage medium is also provided, which stores a computer program, wherein the computer program is configured to perform the steps in the clock jitter calculation and analysis method embodiment of the frequency-divided clock path as described above when executed.

[0098] In the present embodiment, the computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic or optical disk, and other various media that can store computer programs.

[0099] Those skilled in the art can understand that the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can modify the technical solutions described in the foregoing embodiments or make equivalent replacements to some technical features. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.​

Claims

1. A method for calculating and analyzing clock jitter of a divided-frequency clock path, characterized in that: The following steps are involved: Perform jitter simulation on the divided clock path to obtain simulation signal waveform data; Traversing all circuit units on the clock path and organizing basic data related to the circuit units, the basic data including: clock period or clock frequency, reference voltages of input and output pins, and clock frequency division multiples and division positions; Sampling the simulation signal waveform data to extract original edge sampling data; Acquire edge sampling data on adjacent pins in a "back-to-front" order on the clock path to obtain edge-aligned time sampling subsequence data; Calculating clock cycle samples and clock jitter according to the time sampling subsequence data, and analyzing dynamic propagation characteristics of the clock jitter; The step of acquiring edge sampling data on adjacent pins in a "from back to front" order on the clock path and aligning edge sampling data of waveforms before and after frequency division further includes: Find the output pin location of the last divider unit on the clock path; For the waveform edge sampling data located before the output pin, obtain the edge sampling data on adjacent pins in a "back-to-front" order. Based on the edge trigger relationship between the previous and next pins, align the position index of the first trigger edge of the next pin with the edge time sampling sequence of the previous pin. Then, directly calculate the position index sequence of the remaining aligned trigger edges based on the frequency integer ratio before and after the frequency division. Corresponding time samples are extracted according to the position index sequence to form edge-aligned time sampling subsequence data.

2. The method for calculating and analyzing clock jitter of a frequency-divided clock path according to claim 1, wherein: The step of performing jitter simulation on the divided-frequency clock path to obtain simulation signal waveform data further includes: building a jitter simulation netlist for the divided-frequency clock path, connecting a voltage source containing dynamically changing power supply noise to the power and ground pins of the circuit unit; and performing SPICE simulation to obtain simulation signal waveform data.

3. The clock jitter calculation and analysis method of the frequency-divided clock path according to claim 1, characterized in that: The step of traversing all circuit units on the clock path and organizing basic data related to the circuit units further includes: Traverse all circuit units on the clock path and associate relevant basic data from the unit timing library, timing constraint files, and jitter simulation tasks with the circuit units.

4. The method for calculating and analyzing clock jitter of a frequency-divided clock path according to claim 1, wherein: The step of sampling the simulation signal waveform data and extracting the original edge sampling data further includes: Sampling the flip edge time series of the simulation signal waveform data, removing redundant data sampling points on the same edge through a data inspection and cleaning mechanism, and extracting original edge sampling data; According to the edge flip direction, the data is divided into rising edge sampling data and falling edge sampling data, which are recorded as the time sampling subsequence data of the rising edge and falling edge of each level on the clock path.

5. The method for calculating and analyzing clock jitter of a frequency-divided clock path according to claim 4, wherein: The step of removing redundant data sampling points on the same edge through the data inspection and cleaning mechanism further includes: Traversing all waveform data in chronological order, and locating the time when all edges cross the edge detection threshold according to a preset edge detection threshold; Confirm the monotonicity of the voltage value change near the edge sampling point, compare the interval value of adjacent edge sampling points with the reference clock period, analyze the data fluctuation between adjacent edge sampling points, and dynamically remove redundant data sampling points on the same edge to ensure that a unique edge time data point is collected on a clock signal flip edge.

6. The method for calculating and analyzing clock jitter of a frequency-divided clock path according to claim 1, wherein: Also includes: Calculate the clock feature data of the sampled data according to the sampled edge time series. By counting the maximum and minimum values, quickly locate the problematic samples and sampling times, determine the cause of the erroneous sample collection, and iteratively optimize the edge data sampling, inspection, and cleaning methods and processes to improve the accuracy and stability of the sample data.

7. The method for calculating and analyzing clock jitter of a frequency-divided clock path according to claim 1, wherein: The step of calculating clock cycle samples and clock jitter according to the time sampling subsequence data further includes: Taking the time difference between adjacent positions in the time sampling subsequence as a clock cycle sample; The corresponding clock jitter is obtained by using a jitter calculation formula based on the clock cycle samples.

8. The method for calculating and analyzing clock jitter of a frequency-divided clock path according to claim 1, wherein: The step of analyzing the dynamic propagation characteristics of the clock jitter further includes: Based on whether there is an anti-phase relationship in the clock signal transmission between the pins of adjacent circuit units, the clock jitter amounts of the corresponding edge types of the previous and next stages are linked: if there is an anti-phase relationship, the clock jitter amounts of the previous and next stages are transmitted in the order of the rising edge of the previous stage to the falling edge of the next stage, and vice versa. If there is no anti-phase relationship, the clock jitter amounts of the previous and next stages are transmitted in the order of the rising edge of the previous stage to the rising edge of the next stage, and vice versa. The clock jitter calculated after edge alignment is organized and arranged along the relationship between the previous and next stages of the clock path. A table or line graph is used to intuitively express the changing process of the clock jitter of the aligned clock signal edges as it dynamically propagates along the clock path.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: The processor is configured to execute the computer program stored in the memory to implement the clock jitter calculation and analysis method for the frequency-divided clock path according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The storage medium stores a computer program, which is loaded and executed by a processor to implement the clock jitter calculation and analysis method of a frequency-divided clock path according to any one of claims 1 to 8.

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