A laser-induced bifacial localized tunneling oxidation passivation cell and its fabrication method

Abstract

This invention provides a laser-induced bifacial localized tunneling oxide passivation solar cell and its fabrication method, comprising a silicon wafer substrate, front / back silicon nitride layers, and front / back metal electrodes. On the front side of the silicon wafer substrate, a front tunneling oxide layer and a p+poly layer are sequentially disposed from the inside out, with a front LIO etched groove array formed on the surface of the p+poly layer. On the back side, a back tunneling oxide layer and an n+poly layer are sequentially disposed from the inside out, with a back LIO etched groove array formed on the surface of the n+poly layer. This invention utilizes LIO technology to remove poly in the non-gateway p+poly region on the front side of the cell. A TOPCon passivation structure can also be used on the front side with a simple process, significantly improving the open-circuit voltage Voc. Furthermore, LIO technology is used again to thin the poly in the non-gateway n+poly region on the back side of the cell, reducing parasitic light absorption, increasing the short-circuit current Isc, and improving cell efficiency.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and in particular to a laser-induced bifacial localized tunneling oxidation passivation cell and its preparation method. Background Technology

[0002] Solar cells are microelectronic devices that directly convert light energy into electrical energy. After years of development, they have various structures, including PERC (Passivated Emitter and Rear Cell), TOPCon (Tunnel Oxide Passivated Contact Solar Cell), and HJT (Heterojunction with Intrinsic Thin Layer). Currently, considering both cell efficiency and manufacturing cost, TOPCon cells are undoubtedly the mainstream. TOPCon technology involves fabricating an ultrathin tunneling oxide layer (SiOx) on the back of the cell and growing a heavily doped polycrystalline silicon layer (Poly-Si) on its surface. Together, these form a passivated contact structure. The non-conductive but extremely thin tunneling oxide layer allows high concentrations of majority carriers to pass through via quantum tunneling, but blocks minority carriers. The heavily doped polysilicon alters the band structure of silicon, making it a P-type / N-type semiconductor, thus preventing electrons / holes from approaching. Therefore, TOPCon batteries have high passivation capability and conversion efficiency, which makes them the first choice for mass production.

[0003] However, since the absorption of light by the poly layer is parasitic and does not contribute to the photocurrent (Isc), and the TOPCon structure is only fabricated on the back surface, the excellent passivation structure cannot be used on the front surface. If it is necessary to use it on the front surface, a localized structure is required, but localized structures require multiple masking and delamination processes, which are cumbersome and costly, and cannot meet market demands.

[0004] Furthermore, downstream applications in the solar cell industry chain, such as modules and power plants, are increasingly demanding bifacial cells and modules. For the back-side efficiency of cells, the bifaciality ratio (η = back-side efficiency / front-side efficiency × 100%) is gradually increasing. However, TOPCon cells currently require an n+poly layer for back-side passivation, and the parasitic light absorption of poly reduces the back-side efficiency. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a laser-induced bifacial localized tunneling oxidation passivation battery and its preparation method. Based on LIO technology, poly removal is performed in the p+poly non-gateline region on the front side of the battery. The TOPCon passivation structure can also be used on the front side through a simple process to significantly improve the open circuit voltage Voc. The LIO technology is then used to perform poly thinning in the n+poly non-gateline region on the back side of the battery to reduce parasitic light absorption, increase the short circuit current Isc, and improve the battery efficiency.

[0006] The natural oxide layer of silicon is an ultrathin oxide layer of about 1 nm. Further oxide growth requires both oxygen diffusion into the oxide layer and the ejection of "hot electrons" from the silicon. O2 diffusion is blocked 1-2 nm from the Si / SiO interface due to the lattice mismatch between Si and SiO. Under laser irradiation, hot electrons are generated in the silicon. These hot electrons can penetrate the barrier layer and atomize oxygen molecules. Therefore, some O2 molecules are dissociated into O atoms. Atomic oxygen atoms are much smaller and can easily diffuse through the barrier layer until they reach the Si / SiO interface, thus allowing for further oxide layer growth (laser-induced oxidation of silicon, LIO).

[0007] To achieve the above objectives, the present invention employs the following: a laser-induced bifacial localized tunneling oxide passivation cell, comprising a silicon wafer substrate and front / back metal electrodes, wherein a front tunneling oxide layer and a p+poly layer are sequentially disposed from the inside to the outside on the front side of the silicon wafer substrate, and an array of front LIO etching grooves are formed on the surface of the p+poly layer; a back tunneling oxide layer and an n+poly layer are sequentially disposed from the inside to the outside on the back side of the silicon wafer substrate, and an array of back LIO etching grooves are formed on the surface of the n+poly layer; the outermost layer of the front and back sides of the silicon wafer substrate is a silicon nitride layer.

[0008] The silicon substrate has a thickness of 130 μm, the front tunneling oxide layer has a thickness of 1 nm, the p+poly layer has a thickness of 100 nm, the front LIO etch groove has a depth of 100–110 nm, the back tunneling oxide layer has a thickness of 1 nm, the n+poly layer has a thickness of 100 nm, and the back LIO etch groove has a depth of 40–50 nm.

[0009] To achieve the above objectives, another aspect of the present invention employs the following: a method for preparing a laser-induced bifacial localized tunneling oxidation passivation cell, comprising the following steps performed sequentially:

[0010] (1) Select silicon wafers and texturing process;

[0011] (2) TOPCon structure is prepared on the front side of silicon wafer using PVD technology, that is, a tunneling oxide layer is prepared in the PO cavity, and then the silicon target is bombarded with Ar+ in the Paid cavity to prepare intrinsic amorphous silicon ia-Si. Borane gas is introduced to dope boron to prepare p-type doped amorphous silicon pa-Si.

[0012] (3) Use an ultraviolet picosecond laser to perform laser-induced oxidation on the gate area on the front side of the silicon wafer, so that the pa-Si of the preset gate area becomes SiO / SiO2, which is used as a subsequent mask.

[0013] (4) Alkaline etching is performed on the front side of the silicon wafer to etch the amorphous silicon layer in the non-laser oxidation area on the front side of the silicon wafer. After alkaline etching, hydrogen peroxide and weak alkaline solution are used to clean the silicon wafer to remove the influence of organic additives.

[0014] (5) The silicon wafer is annealed at high temperature in an annealing furnace to transform p-type doped amorphous silicon pa-Si into p-type doped polycrystalline silicon p+poly. After annealing, oxygen is introduced to oxidize the surface of the silicon wafer.

[0015] (6) Perform single-sided acid pickling on the silicon wafer to remove the silicon oxide layer on its back and sides;

[0016] (7) Perform alkaline polishing on the back side of the silicon wafer;

[0017] (8) TOPCon structure is prepared on the back side of silicon wafer using PVD technology, that is, a tunneling oxide layer is prepared in the PO cavity, and then the silicon target is bombarded with Ar+ in the Paid cavity to prepare intrinsic amorphous silicon ia-Si. PH3 gas is introduced to dope phosphorus element to prepare n-type doped amorphous silicon na-Si.

[0018] (9) The silicon wafer is annealed at high temperature in an annealing furnace to transform n-type doped amorphous silicon na-Si into n-type doped polycrystalline silicon n+poly.

[0019] (10) Use an ultraviolet picosecond laser to perform laser-induced oxidation on the gate line area on the back of the silicon wafer, so that the n+poly of the preset gate line area becomes SiO / SiO2, which serves as a subsequent mask.

[0020] (11) BOE cleaning: The silicon wafer is cleaned in a tank cleaning equipment. First, hydrogen peroxide and a weak alkaline solution are used to clean the organic impurities on the surface. Then, a low-temperature alkaline solution is used to etch the back of the silicon wafer. Finally, the silicon wafer is cleaned with HF / HCl solution to remove the oxides on the front and back sides.

[0021] (12) Silicon nitride antireflection films were prepared on both the front and back sides of a silicon wafer using PECVD technology;

[0022] (13) Metal paste is applied to both the front and back sides of the silicon wafer using screen printing, and then metal electrodes are prepared after sintering.

[0023] In step (1), the silicon wafer is texturized to remove the surface cutting damage layer and form a textured textured surface structure on its surface to reduce light loss; the silicon wafer is an n-type silicon wafer with a thickness of 130um and a sheet resistance of 1Ω / □.

[0024] In step (4), the silicon wafer is cleaned in a tank cleaning device. First, hydrogen peroxide and a weak alkaline solution are used to clean the organic impurities on the surface of the silicon wafer. Then, a low-temperature alkaline solution is used for alkaline etching to etch the pa-Si area of ​​the non-laser region on the front side of the silicon wafer. The etching temperature is 30-40°C and the etching solution ratio is deionized water:NaOH:ADD = 120:1:1.

[0025] In step (5), the annealing temperature is 950°C and the temperature is held for 1800 seconds to activate the doped atoms on the front side of the silicon wafer.

[0026] In step (6), silicon oxide on the back and sides of the silicon wafer is removed using a chain-type single-sided HF device, wherein the volume ratio of HF to deionized water is 1:10.

[0027] In step (7), after the silicon wafer is alkaline polished, the original solution ratio in the subsequent cleaning is deionized water:NaOH = 90:1, and finally the silicon wafer surface is cleaned with HCl+HF solution.

[0028] In step (9), the annealing temperature is 850°C and the temperature is held for 2000 seconds to activate the doped atoms on the back side of the silicon wafer.

[0029] In step (11), the silicon wafer is cleaned in a tank cleaning device. First, hydrogen peroxide and a weak alkaline solution are used to clean the organic impurities on the surface of the silicon wafer. Then, a low-temperature alkaline solution is used for alkaline etching to etch the n+poly area of ​​the non-laser region on the back of the silicon wafer. The etching temperature is 30-40°C. After alkaline etching, hydrogen peroxide and a weak alkaline solution are used again to remove the influence of organic additives.

[0030] Compared with the prior art, the technical effects of the present invention are as follows: Compared with the traditional TOPCon battery, the present invention is based on PVD technology that does not produce plating. In the present invention, poly removal is performed on the p+poly non-grid area on the front side of the battery using LIO technology. The TOPCon passivation structure can also be used on the front side through a simple process, which significantly improves the open circuit voltage Voc. The LIO technology is used again to perform poly thinning on the n+poly non-grid area on the back side of the battery, which reduces parasitic light absorption, increases the short circuit current Isc, and improves the battery efficiency. Attached Figure Description

[0031] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0032] Figure 1 This is a schematic diagram of the structure of a laser-induced bifacial localized tunneling oxidation passivation cell according to an embodiment of the present invention;

[0033] Figure 2 This is a comparison chart of the battery efficiency of the laser-induced bifacial localized tunneling oxidation passivation battery of Embodiment 1 of the present invention and several conventional batteries.

[0034] 10-Silicon substrate, 11-Front-side tunneling oxide layer, 12-p+poly layer, 21-Back-side tunneling oxide layer, 22-n+poly layer, 13(23)-Silicon nitride layer, 14(24)-Metal electrode. Detailed Implementation

[0035] To more clearly illustrate the present invention, the following description, in conjunction with preferred embodiments, further clarifies the invention. Those skilled in the art should understand that the specific descriptions below are illustrative rather than restrictive, and should not be construed as limiting the scope of protection of the present invention.

[0036] The laser-induced bifacial localized tunneling oxidation passivation cell of the present invention has the following structure: Figure 1 As shown, the silicon substrate 10 includes a silicon wafer substrate 10 and metal electrodes 14 (24) on the front and back sides. The front side of the silicon wafer substrate 10 is provided with a front tunneling oxide layer 11 and a p+poly layer 12 from the inside to the outside. The surface of the p+poly layer 12 is formed with a front LIO etching groove array. The back side of the silicon wafer substrate 10 is provided with a back tunneling oxide layer 21 and an n+poly layer 22 from the inside to the outside. The surface of the n+poly layer 22 is formed with a back LIO etching groove array. The outermost layer of the front and back sides of the silicon wafer substrate 10 is a silicon nitride layer 13 (23).

[0037] The silicon substrate has a thickness of 130 μm, the front tunneling oxide layer has a thickness of 1 nm, the p+poly layer has a thickness of 100 nm, the front LIO etching groove has a depth of 100–110 nm, the back tunneling oxide layer has a thickness of 1 nm, the n+poly layer has a thickness of 100 nm, and the back LIO etching groove has a depth of 40–50 nm.

[0038] The above-mentioned method for preparing a laser-induced bifacial localized tunneling oxidation passivation cell is implemented according to the following steps:

[0039] (1) Select silicon wafers and texturing process;

[0040] (2) TOPCon structure is prepared on the front side of silicon wafer using PVD technology, that is, a tunneling oxide layer is prepared in the PO cavity, and then the silicon target is bombarded with Ar+ in the Paid cavity to prepare intrinsic amorphous silicon ia-Si. Borane gas is introduced to dope boron to prepare p-type doped amorphous silicon pa-Si.

[0041] (3) Use an ultraviolet picosecond laser to perform laser-induced oxidation on the gate area on the front side of the silicon wafer, so that the pa-Si of the preset gate area becomes SiO / SiO2, which is used as a subsequent mask.

[0042] (4) Alkaline etching is performed on the front side of the silicon wafer to etch the amorphous silicon layer in the non-laser oxidation area on the front side of the silicon wafer. After alkaline etching, hydrogen peroxide and weak alkaline solution are used to clean the silicon wafer to remove the influence of organic additives.

[0043] (5) The silicon wafer is annealed at high temperature in an annealing furnace to transform p-type doped amorphous silicon pa-Si into p-type doped polycrystalline silicon p+poly. After annealing, oxygen is introduced to oxidize the surface of the silicon wafer.

[0044] (6) Perform single-sided acid pickling on the silicon wafer to remove the silicon oxide layer on its back and sides;

[0045] (7) Perform alkaline polishing on the back side of the silicon wafer;

[0046] (8) TOPCon structure is prepared on the back side of silicon wafer using PVD technology, that is, a tunneling oxide layer is prepared in the PO cavity, and then the silicon target is bombarded with Ar+ in the Paid cavity to prepare intrinsic amorphous silicon ia-Si. PH3 gas is introduced to dope phosphorus element to prepare n-type doped amorphous silicon na-Si.

[0047] (9) The silicon wafer is annealed at high temperature in an annealing furnace to transform n-type doped amorphous silicon na-Si into n-type doped polycrystalline silicon n+poly.

[0048] (10) Use an ultraviolet picosecond laser to perform laser-induced oxidation on the gate line area on the back of the silicon wafer, so that the n+poly of the preset gate line area becomes SiO / SiO2, which serves as a subsequent mask.

[0049] (11) BOE cleaning: The silicon wafer is cleaned in a tank cleaning equipment. First, hydrogen peroxide and a weak alkaline solution are used to clean the organic impurities on the surface. Then, a low-temperature alkaline solution is used to etch the back of the silicon wafer. Finally, the silicon wafer is cleaned with HF / HCl solution to remove the oxides on the front and back sides.

[0050] (12) Silicon nitride antireflection films were prepared on both the front and back sides of a silicon wafer using PECVD technology;

[0051] (13) Metal paste is applied to both the front and back sides of the silicon wafer using screen printing, and then metal electrodes are prepared after sintering.

[0052] Example 1:

[0053] Step (1): Select an n-type silicon wafer with a thickness of 130μm and a sheet resistance of 1Ω / □ as the silicon wafer substrate, and perform texturing treatment on it to remove the surface cutting damage layer and form a textured textured surface structure on the surface.

[0054] Step (2): TOPCon structure is prepared on the front side of silicon wafer using PVD technology, that is, a tunneling oxide layer is prepared in the PO cavity, and then the silicon target is bombarded with Ar+ in the Paid cavity to prepare intrinsic amorphous silicon ia-Si. Then, diborane gas is introduced to dope boron to prepare p-type doped amorphous silicon pa-Si.

[0055] Step (3): Use an ultraviolet picosecond laser to perform laser-induced oxidation on the gate area on the front side of the silicon wafer, so that the pa-Si of the preset gate area on the front side of the silicon wafer becomes SiO / SiO2, which serves as a subsequent mask.

[0056] Step (4) Wet cleaning: Cleaning is carried out in a tank cleaning equipment. First, hydrogen peroxide and a weak alkaline solution are used to clean the organic impurities on the surface. Then, a low-temperature alkaline solution is used to etch the non-laser area Pa-Si on the front side. Since the LIO in the laser area has become silicon oxide, it cannot be completely etched by the alkaline solution, and the Pa-Si underneath is protected. The etching solution ratio is the same as that of the texturing solution. Since the alkaline solution will still corrode SiO in hot water, the etching is carried out at a low temperature to reduce the impact on the LIO area. The etching temperature is about 30-40℃, and the etching solution ratio is deionized water:NaOH:ADD = 120:1:1. After alkaline etching, hydrogen peroxide and a weak alkaline solution are used to clean the silicon wafer to remove the influence of organic additives.

[0057] Step (5): During high-temperature annealing, the annealing temperature is 950℃ and the temperature is kept constant for 1800s to transform p-type doped amorphous silicon pa-Si into p-type doped polycrystalline silicon p+poly. After annealing, oxygen is introduced into the furnace tube to oxidize the surface of the cell.

[0058] Step (6): Use a chain-type single-sided HF equipment to perform single-sided acid washing on the silicon wafer to remove silicon oxide on the back and sides of the silicon wafer. The volume ratio of HF to deionized water in the machine is 1:10.

[0059] Step (7): After removing the silicon oxide on the back and sides of the silicon wafer, place the silicon wafer in an alkaline polishing tank. After alkaline polishing, in the subsequent cleaning, the original solution ratio is approximately deionized water: NaOH = 90:1. Finally, use HCl + HF solution to clean the surface of the silicon wafer.

[0060] Step (8): Use PVD technology to prepare TOPCon structure on the back surface, prepare front tunneling oxide layer in PO cavity, then use Ar+ to bombard silicon target in Paid cavity to prepare intrinsic amorphous silicon ia-Si of a certain thickness on the back of silicon wafer, introduce PH3 gas, dope phosphorus element, and prepare doped amorphous silicon.

[0061] Step (9): The silicon wafer is annealed at high temperature in an annealing furnace at 850°C for 2000s to transform n-type doped amorphous silicon na-Si into n-type doped polycrystalline silicon n+poly.

[0062] Step (10): Use an ultraviolet picosecond laser to perform laser-induced oxidation on the gate area on the back of the silicon wafer, so that the n+poly of the preset gate area on the back of the silicon wafer becomes SiO / SiO2, which serves as a subsequent mask.

[0063] Step (11) Wet cleaning: The silicon wafer is cleaned in a tank cleaning equipment. First, hydrogen peroxide and a weak alkaline solution are used to clean the organic impurities on the surface. Then, a low-temperature alkaline solution is used to etch the non-laser area n+poly on the back. Since the LIO in the laser area has become silicon oxide, it cannot be completely etched by the alkaline solution. The n+poly underneath is protected. The etching solution ratio is the same as that for polishing. Since the alkaline solution will still corrode SiO in hot water, the etching is carried out at a low temperature, about 30-40°C, in order to reduce the impact on the LIO area. After alkaline etching, hydrogen peroxide and a weak alkaline solution are used to clean the silicon wafer to remove the influence of organic additives. Finally, HF / HCl solution is used to clean the silicon wafer to remove the oxides on the front and back sides.

[0064] Step (12): Silicon nitride (SiNx) antireflection films are prepared on the front and back sides of the battery using plasma-enhanced chemical deposition (PECVD) to reduce light reflection.

[0065] Step (13): Apply metal paste to the front and back of the battery using screen printing equipment, process it at high temperature in a sintering furnace to prepare metal grid lines, so that the metal material combines with silicon to form an alloy, and export photogenerated carriers to complete the battery preparation.

[0066] like Figure 2 The figure shows a comparison of the efficiency of conventional TOPCon (Base Line, BL) batteries and the LIO-Total battery of this invention. It can be seen that compared to conventional TOPCon, and TOPCon (LIO-R with only back-side LIO) and TOPCon (LIO-F with only front-side LIO) batteries, the process of this invention can improve battery efficiency by approximately 0.40% / 0.24% / 0.07%. Clearly, the battery with LIO on both sides of this invention has superior performance.

[0067] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims

1. A laser-induced bifacial localized tunneling oxide passivation cell, comprising a silicon substrate and front / back metal electrodes, characterized in that, The front side of the silicon substrate has a front tunneling oxide layer and a p+ polysilicon layer arranged sequentially from the inside to the outside, and the surface of the p+ polysilicon layer has a front LIO etch groove array formed therein. The back side of the silicon substrate has a back tunneling oxide layer and an n+ polysilicon layer arranged sequentially from the inside to the outside, and the surface of the n+ polysilicon layer has a back LIO etch groove array formed therein. The outermost layer of the front and back sides of the silicon substrate is a silicon nitride layer. The depth of the LIO etching groove on the front side is 100-110 nm, and the depth of the LIO etching groove on the back side is 40-50 nm. The method for fabricating the laser-induced bifacial localized tunneling oxidation passivation cell includes the following steps performed sequentially: (1) Selection of silicon wafers and texturing process; (2) TOPCon structure is prepared on the front side of silicon wafer using PVD technology, that is, a tunneling oxide layer is prepared in the PO cavity, and then the silicon target is bombarded with Ar+ in the Paid cavity to prepare intrinsic amorphous silicon ia-Si. Borane gas is introduced to dope boron to prepare p-type doped amorphous silicon pa-Si. (3) Use an ultraviolet picosecond laser to perform laser-induced oxidation on the gate area on the front side of the silicon wafer, so that the pa-Si of the preset gate area becomes SiO / SiO2, which is used as a subsequent mask; (4) Alkaline etching is performed on the front side of the silicon wafer to etch the amorphous silicon layer in the non-laser oxidation area on the front side of the silicon wafer. After alkaline etching, hydrogen peroxide and weak alkaline solution are used to clean the silicon wafer to remove the influence of organic additives. (5) The silicon wafer is annealed at high temperature in an annealing furnace to transform p-type doped amorphous silicon pa-Si into p-type doped polycrystalline silicon p+ polycrystalline silicon layer. After annealing, oxygen is introduced to oxidize the surface of the silicon wafer. (6) Perform single-sided acid pickling on the silicon wafer to remove the silicon oxide layer on its back and sides; (7) Perform alkaline polishing on the back side of the silicon wafer; (8) TOPCon structure is prepared on the back side of silicon wafer using PVD technology, that is, a tunneling oxide layer is prepared in the PO cavity, and then the silicon target is bombarded with Ar+ in the Paid cavity to prepare intrinsic amorphous silicon ia-Si. PH3 gas is introduced to dope phosphorus element to prepare n-type doped amorphous silicon na-Si. (9) The silicon wafer is annealed at high temperature in an annealing furnace to transform the n-type doped amorphous silicon na-Si into an n-type doped polycrystalline silicon n+ polycrystalline silicon layer. (10) Use an ultraviolet picosecond laser to perform laser-induced oxidation on the gate area on the back of the silicon wafer, so that the n+ polysilicon layer in the preset gate area becomes SiO / SiO2, which serves as a subsequent mask; (11) BOE cleaning: The silicon wafer is cleaned in a tank cleaning equipment. First, hydrogen peroxide and a weak alkaline solution are used to clean the organic impurities on the surface. Then, a low-temperature alkaline solution is used to etch the back side of the silicon wafer. Finally, the silicon wafer is cleaned with HF / HCl solution to remove the oxides on the front and back sides. (12) Silicon nitride antireflection films were prepared on both the front and back sides of a silicon wafer using PECVD technology; (13) Metal paste is applied to both the front and back sides of the silicon wafer using screen printing, and then metal electrodes are prepared after sintering.

2. The laser-induced bifacial localized tunneling oxide passivation cell according to claim 1, characterized in that, The silicon substrate has a thickness of 130 μm, the front tunneling oxide layer has a thickness of 1 nm, the p+ polysilicon layer has a thickness of 100 nm, the back tunneling oxide layer has a thickness of 1 nm, and the n+ polysilicon layer has a thickness of 100 nm.

3. The laser-induced bifacial localized tunneling oxide passivation cell according to claim 1, wherein in step (1): the silicon wafer is texturized to remove the surface cutting damage layer and form a textured textured surface structure on its surface to reduce light loss; the silicon wafer is an n-type silicon wafer with a thickness of 130um and a sheet resistance of 1Ω / □.

4. The laser-induced bifacial localized tunneling oxide passivation cell according to claim 1, in step (4): the silicon wafer is cleaned in a tank cleaning device. First, hydrogen peroxide and a weak alkaline solution are used to clean the organic impurities on the surface of the silicon wafer. Then, a low-temperature alkaline solution is used for alkaline etching to etch the pa-Si of the non-laser area on the front side of the silicon wafer. The etching temperature is 30-40°C and the etching solution ratio is deionized water:NaOH:ADD=120:1:

1.

5. The laser-induced bifacial localized tunneling oxide passivation cell according to claim 1, characterized in that, In step (5), the annealing temperature is 950℃ and the temperature is held for 1800s to activate the doped atoms on the front side of the silicon wafer.

6. The laser-induced bifacial localized tunneling oxide passivation cell according to claim 1, characterized in that, In step (6): the silicon oxide on the back and sides of the silicon wafer is removed using a chain-type single-sided HF device, wherein the volume ratio of HF to deionized water is 1:

10.

7. The laser-induced bifacial localized tunneling oxide passivation cell according to claim 1, characterized in that, In step (7): after the silicon wafer is alkaline polished, in the subsequent cleaning, the original solution ratio is deionized water:NaOH=90:1, and finally the silicon wafer surface is cleaned with HCl+HF solution.

8. The laser-induced bifacial localized tunneling oxide passivation cell according to claim 1, characterized in that, In step (9), the annealing temperature is 850°C and held for 2000 seconds to activate the doped atoms on the back side of the silicon wafer.

9. The laser-induced bifacial localized tunneling oxide passivation cell according to claim 1, characterized in that, In step (11): the silicon wafer is cleaned in a tank cleaning device. First, hydrogen peroxide and a weak alkaline solution are used to clean the organic impurities on the surface of the silicon wafer. Then, a low-temperature alkaline solution is used for alkaline etching to etch the n+ polysilicon layer in the non-laser area on the back of the silicon wafer. The etching temperature is 30-40°C. After alkaline etching, hydrogen peroxide and a weak alkaline solution are used again to remove the influence of organic additives.

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