A two-step interstage gain error calibration method and apparatus for a pipelined SAR ADC

Abstract

This application belongs to the field of digital signal processing technology and discloses a two-step interstage gain error calibration method and apparatus for a pipelined SAR ADC. The method includes: putting the first-stage ADC into a metastable state and converting the input signal of the first-stage ADC; recording and accumulating the absolute value of the first digital code output by the second-stage ADC after each conversion; determining whether the accumulated value reaches a preset upper limit value; if so, stopping the conversion, dividing the average value of the accumulated value by the absolute value of the residual voltage of the first-stage ADC to obtain the initial value for iteration; inputting a preset test waveform into the second-stage ADC to obtain the second digital code; and inputting the initial value for iteration, the preset iteration step size, the pseudo-random signal, and the second digital code into an iterative formula for iteration to obtain the gain error coefficient. This application can achieve fast and accurate calibration of gain error without consuming additional digital resources.

Description

Technical Field

[0001] This application relates to the field of digital signal processing technology, and in particular to a two-step interstage gain error calibration method and apparatus for a pipelined SAR ADC. Background Technology

[0002] With the development of information technology and the rise of autonomous and intelligent devices, communication systems have placed high demands on the speed, accuracy, and power consumption of ADCs. Designing high-speed, high-precision, and low-power analog-to-digital converters (ADCs) has been a long-standing goal and direction pursued by both academia and industry. Pipelined SAR ADCs (Pipeline Successive Approximation ADCs) segment the SAR ADC into multiple low-precision sub-ADCs using residual amplifiers and perform signal quantization in a pipelined manner. After segmentation by the residual amplifier, the accuracy requirements of the SAR ADC are reduced, thus compensating for the limitation of SAR ADCs in high-precision applications and making them a key research focus in the field of analog-to-digital converters in recent years. In actual production, Pipelined SAR ADCs are affected by non-ideal factors such as the working environment, manufacturing process, and the circuit itself, including offset, noise, capacitor mismatch, limited bandwidth of operational amplifiers, and limited gain of operational amplifiers. These factors limit the overall accuracy of the Pipelined SAR ADC. To improve ADC performance, the specific error sources of the Pipelined SAR ADC are analyzed during the circuit design process, and corresponding calibration techniques are introduced for calibration.

[0003] Existing gain error calibration employs a two-step method: front-end calibration and back-end calibration. However, both steps utilize the LMS algorithm, which suffers from a very long iteration cycle and slow convergence speed. Using the LMS algorithm for both front-end and back-end calibration significantly increases the convergence time of the entire inter-stage gain calibration algorithm, resulting in an excessively long overall gain calibration time and negating any speed advantage. Furthermore, using the LMS algorithm in the front-end calibration requires additional adjustment circuitry, increasing digital resource consumption and complicating the circuitry. Summary of the Invention

[0004] This application provides a two-step interstage gain error calibration method and apparatus for a pipelined SAR ADC, which can achieve fast and accurate gain error calibration without consuming additional digital resources.

[0005] In a first aspect, embodiments of this application provide a two-step inter-stage gain error calibration method for a Pipelined SAR ADC, applied in the digital logic circuit of the Pipelined SAR ADC; the Pipelined SAR ADC includes a digital logic circuit, a first-stage ADC, and a second-stage ADC, the digital logic circuit being connected to both the first-stage ADC and the second-stage ADC, and the output terminal of the first-stage ADC being connected to the input terminal of the second-stage ADC; the method includes:

[0006] The first-stage ADC is brought into a metastable state, and the input signal of the first-stage ADC is converted according to a preset period.

[0007] Record and accumulate the absolute value of the first digital code output by the second-stage ADC after each input signal conversion;

[0008] Determine whether the accumulated value of the first digital code has reached the preset upper limit; if so, stop converting the input signal, and divide the average value of the accumulated value by the absolute value of the residual voltage output by the first stage ADC to obtain the initial value of the iteration.

[0009] Input the preset test waveform into the second-stage ADC to obtain the second digital code;

[0010] The initial value, preset iteration step size, pseudo-random signal and second digital code are input into the iterative formula for iteration until the iterative formula meets the preset convergence condition, and the gain error coefficient is obtained.

[0011] Input the target signal into the first-stage ADC;

[0012] Obtain the first output value of the first-stage ADC and the second output value of the second-stage ADC. Divide the second output value by the gain error coefficient and add it to the first output value to obtain the target output value.

[0013] Furthermore, the method also includes:

[0014] By shorting the two input terminals of the first-stage ADC, the first-stage ADC is brought into a metastable state.

[0015] Furthermore, the preset test waveform is a sine wave.

[0016] Furthermore, the preset upper limit is 32 or 64.

[0017] Furthermore, the above-mentioned initial value, preset iteration step size, pseudo-random signal, and second digital code are input into the iterative formula for iteration until the iterative formula satisfies the preset convergence condition, thus obtaining the gain error coefficient, including:

[0018] Initial steps: Subtract the product of the pseudo-random signal and the initial iteration value from the second digital code to obtain the first value;

[0019] Multiply the first value by the preset iteration step size and the pseudo-random signal to obtain the second value;

[0020] Add the initial value and the second value to obtain the iterative output value;

[0021] Determine whether the iterative output value and the initial iterative value satisfy the preset convergence condition;

[0022] If satisfied, the iterative output value or the initial iterative value will be used as the gain error coefficient.

[0023] If the condition is not met, the iteration output value is used as the initial value for the iteration, and the process returns to the initial step.

[0024] Furthermore, the preset convergence condition is: the absolute value of the difference between the iterative output value and the initial value of the iteration is within the preset convergence range.

[0025] Furthermore, the pseudo-random signal is generated through a linear feedback shift register.

[0026] Secondly, embodiments of this application provide a two-step interstage gain error calibration device for a Pipelined SAR ADC, applied in the digital logic circuit of the Pipelined SAR ADC; the Pipelined SAR ADC includes a digital logic circuit, a first-stage ADC, and a second-stage ADC, the digital logic circuit being connected to both the first-stage ADC and the second-stage ADC, and the output terminal of the first-stage ADC being connected to the input terminal of the second-stage ADC; the device includes:

[0027] The conversion module is used to bring the first-stage ADC into a metastable state and convert the input signal of the first-stage ADC according to a preset period.

[0028] The accumulator module is used to record and accumulate the absolute value of the first digital code output by the second-stage ADC after each conversion of the input signal;

[0029] The judgment module is used to determine whether the accumulated value of the first digital code has reached the preset upper limit value; if so, the conversion of the input signal is stopped, and the average value of the accumulated value is divided by the absolute value of the residual voltage output by the first stage ADC to obtain the initial value of the iteration.

[0030] The first input module is used to input the preset test waveform into the second-stage ADC to obtain the second digital code;

[0031] The iteration module is used to input the initial value of the iteration, the preset iteration step size, the pseudo-random signal and the second digital code into the iteration formula for iteration until the iteration formula meets the preset convergence condition and the gain error coefficient is obtained.

[0032] The second input module is used to input the target signal into the first-stage ADC;

[0033] The target calculation module is used to obtain the first output value of the first-stage ADC and the second output value of the second-stage ADC, divide the second output value by the gain error coefficient, and then add it to the first output value to obtain the target output value.

[0034] Thirdly, embodiments of this application provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it performs the steps of a two-step interstage gain error calibration method for a Pipelined SAR ADC as described in any of the above embodiments.

[0035] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of a two-step interstage gain error calibration method for a Pipelined SAR ADC as described in any of the above embodiments.

[0036] In summary, compared with the prior art, the beneficial effects of the technical solution provided in this application include at least the following:

[0037] This application provides a two-step interstage gain error calibration method for a pipelined SAR ADC. The first step is a metastable-based front-end calibration instead of the LMS algorithm. Compared to the LMS algorithm, the metastable-based front-end calibration has simpler circuitry and does not require additional digital resources or adjustment circuitry. The gain obtained through metastable-based calibration serves as the initial value for the second step, the background digital calibration, enabling rapid convergence. Compared to existing technologies that use the LMS algorithm for both calibration steps, this application offers simpler circuitry and faster calibration speed. Attached Figure Description

[0038] Figure 1 A flowchart illustrating a two-step interstage gain error calibration method for a Pipelined SAR ADC, provided as an exemplary embodiment of this application.

[0039] Figure 2 An internal structural diagram of a Pipelined SAR ADC provided for an exemplary embodiment of this application.

[0040] Figure 3 This is a schematic diagram of the ADC's operating state in the front-end calibration mode, provided as an exemplary embodiment of this application.

[0041] Figure 4 This is a schematic diagram of the ADC's operating state in background calibration mode, provided as an exemplary embodiment of this application.

[0042] Figure 5This is a structural diagram of a two-step interstage gain error calibration device for a Pipelined SAR ADC, provided as an exemplary embodiment of this application. Detailed Implementation

[0043] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0044] Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] Please see Figures 1-4 This application provides a two-step interstage gain error calibration method for a Pipelined SAR ADC, applied to the digital logic circuit of the Pipelined SAR ADC. The Pipelined SAR ADC includes a digital logic circuit, a first-stage ADC, and a second-stage ADC. The digital logic circuit is connected to both the first-stage and second-stage ADCs, and the output of the first-stage ADC is connected to the input of the second-stage ADC. The method includes:

[0046] Step S1: Allow the first-stage ADC to enter a metastable state and convert the input signal of the first-stage ADC according to a preset period.

[0047] Specifically, during metastable calibration, the differential input terminal of the first-stage ADC is shorted to make its equivalent differential input signal 0. At this time, the first-stage ADC circuit will definitely enter the metastable state.

[0048] Assume the first-stage ADC has m bits and the total single-ended capacitance is C. t The capacitance at position x is C[x] (1≤x≤m). First, short-circuit the differential input of the first-stage ADC. Then, the input signal V of the comparator inside the first-stage ADC... comp [1] = 0. Assuming the initial comparison result of the comparator is 1, and the CDAC array is set for the first time according to the comparison result, the differential voltage of the capacitor top plate of the first-stage ADC after this setting is -(C[1] / C t V ref (where V) ref (The reference voltage is used), at this time the comparator's input signal V comp [2] = -(C[1] / C t V ref Because V at this time comp[2] is less than 0, so the comparator's comparison result is 0. Based on this comparison result, the CDAC array is set for the second time. After the second setting, the third input signal of the comparator generated on the top plate of the CDAC array is V. comp [3] = -(C[2] / C t V ref Because of V comp [3] is less than 0, so the comparator's comparison result is 0. Based on the above analysis, it can be deduced that after the first-stage ADC completes the m-th setting, the residual voltage on the top plate is V. res =-(C[m] / C t V ref Similarly, when the differential input signal of the first-stage ADC is short-circuited, assuming the initial comparison result of the comparator is 0, the residual voltage V output by the first-stage ADC can be derived. res =(C[m] / C t V ref Therefore, it can be deduced that when the differential input of the ADC is short-circuited, regardless of whether the result of the first comparison by the comparator is 1 or 0, the absolute value of the final residual voltage output by the first-stage ADC is a known constant: |V res |=(C[m] / C t V ref .

[0049] Step S2: Record and accumulate the absolute value of the first digital code output by the second-stage ADC after each conversion of the input signal.

[0050] Step S3: Determine whether the accumulated value of the first digital code has reached the preset upper limit value; if so, stop converting the input signal, and divide the average value of the accumulated value by the absolute value of the residual voltage output by the first-stage ADC to obtain the initial value of the iteration.

[0051] Specifically, with the differential input terminals of the first-stage ADC short-circuited, the constant input signal of the first-stage ADC is converted several times, and the first digital code of the corresponding output of the second-stage ADC is recorded. Each conversion causes the first-stage ADC to undergo the above m setting once, and the output residual voltage with a known absolute value is output. By accumulating the absolute value of the first digital code, the calibration is completed when the accumulated value reaches a preset upper limit value, where the preset upper limit value can be 32 or 64. The average value of the accumulated value of the first digital code is divided by the residual voltage to obtain the preliminary result of the front-end calibration of the inter-stage gain, that is, the initial value of the iteration.

[0052] Please see Figure 2 In practical implementation, a residual amplifier may also be included between the first-stage ADC and the second-stage ADC. The residual voltage V of the first-stage ADC... resThe voltage value amplified by the residual amplifier is the input of the second-stage ADC. However, due to noise in the circuit, the voltage value output by the residual amplifier will differ even for the same input. Therefore, the first digital code output by the amplifier after quantization by the second-stage ADC will also differ. So, it is necessary to accumulate and average them to make the obtained initial value of the iteration more accurate and the final gain error coefficient more accurate.

[0053] Step S4: Input the preset test waveform into the second-stage ADC to obtain the second digital code.

[0054] The preset test waveform can be a sine wave.

[0055] Step S5: Input the initial iteration value, preset iteration step size, pseudo-random signal and second digital code into the iteration formula and iterate until the iteration formula meets the preset convergence condition to obtain the gain error coefficient.

[0056] Step S6: Input the target signal into the first-stage ADC.

[0057] The target signal is the input signal of the Pipelined SAR ADC during formal application.

[0058] Step S7: Obtain the first output value of the first-stage ADC and the second output value of the second-stage ADC. Divide the second output value by the gain error coefficient and add it to the first output value to obtain the target output value.

[0059] Specifically, after obtaining the gain error coefficient G*, the output value of the Pipelined SAR ADC is corrected using the gain error coefficient G*. That is, after calibration, the output of the Pipelined SAR ADC is Dout = Dout1 + Dout2 / G. * .

[0060] Where Dout1 is the first output value, Dout2 is the second output value, and Dout is the target output value.

[0061] The above embodiment provides a two-step interstage gain error calibration method for a pipelined SAR ADC. The first step is a metastable-based front-end calibration instead of the LMS algorithm. Compared to the LMS algorithm, the metastable-based front-end calibration has simpler circuitry and does not require additional digital resources or adjustment circuitry. The gain obtained through metastable-based calibration serves as the initial value for the second step, the background digital calibration, enabling rapid convergence. Compared to existing technologies that use the LMS algorithm for both calibration steps, this application offers a simpler circuit, faster calibration speed, and higher calibration accuracy.

[0062] In some embodiments, the above-mentioned inputting the initial iteration value, preset iteration step size, pseudo-random signal, and second digital code into the iteration formula for iteration until the iteration formula satisfies the preset convergence condition, and obtaining the gain error coefficient, includes:

[0063] Step S51, initial step: Subtract the product of the pseudo-random signal and the initial iteration value from the second digital code to obtain the first value.

[0064] Step S52: Multiply the first value by the preset iteration step size and the pseudo-random signal to obtain the second value.

[0065] Step S53: Add the initial iteration value and the second value to obtain the iteration output value.

[0066] Step S54: Determine whether the iterative output value and the initial iterative value satisfy the preset convergence condition.

[0067] The preset convergence condition is that the absolute value of the difference between the iterative output value and the initial value of the iteration is within the preset convergence range.

[0068] The preset convergence range is 0-0.005, where 0.005 is not a fixed value and can be set according to actual needs.

[0069] Step S55: If satisfied, the iterative output value or the initial iterative value is used as the gain error coefficient.

[0070] Step S56: If the condition is not met, the iterative output value is used as the initial value for the iteration, and the process returns to the initial step.

[0071] Specifically, the iterative formula is: G[i+1]=G[i]+μ×PN[i]×(Dout2[i]-PN[i]×G[i]).

[0072] μ is the preset iteration step size, PN[i] is the pseudo-random signal, Dout2[i] is the second digital code obtained after inputting the preset test waveform into the second-stage ADC, and G[1] is the front-end calibration, i.e. the initial iteration value obtained in step S3.

[0073] In the first iteration, G[1] is a known value. G[2] is obtained based on Dout2[1] and PN[1]. G[2] is used as the input for the next iteration. Together with Dout2[2] and PN[2], G[3] is obtained. This process continues until |G[i+1]-G[i]|<0.005. At this point, the iteration process can be considered to have reached a stable state. G[i+1] or G[i] is used as the stable gain error coefficient G*.

[0074] In the above embodiments, the pseudo-random signal is also called a pseudo-random code or a pseudo-random sequence.

[0075] A pseudo-random code is a sequence that has some statistical properties of random noise, and is easy to generate and process repeatedly. Pseudo-random codes can be generated by a linear feedback shift register (LFSR). The main structure of the LFSR used in this application consists of a set of registers, with an XOR logic as the feedback to generate new data input to the leftmost end of the register chain. The generated sequence is a periodic sequence, but it can exhibit randomness in statistics, i.e., a pseudo-random sequence.

[0076] Since the pseudo-random code is uncorrelated with any other signal, the expected value of PN[i]×(Dout2[i]-PN[i]×G[i]) is 0 as calibration proceeds. When this expression approaches 0, the gain error coefficient G[i+1] approaches G[i]. Thus, a stable gain error coefficient G* can be obtained after a fairly long iteration period.

[0077] This application adopts a calibration based on metastable state detection in the first step, which can greatly accelerate the convergence speed of the background digital calibration LMS algorithm. According to the simulation results of Matlab, it can speed up the process by about 80%.

[0078] Please see Figure 5 Another embodiment of this application provides a two-step interstage gain error calibration device for a Pipelined SAR ADC, applied in the digital logic circuit of the Pipelined SAR ADC; the Pipelined SAR ADC includes a digital logic circuit, a first-stage ADC, and a second-stage ADC, the digital logic circuit being connected to both the first-stage ADC and the second-stage ADC, and the output terminal of the first-stage ADC being connected to the input terminal of the second-stage ADC; the device includes:

[0079] The conversion module 101 is used to bring the first-stage ADC into a metastable state and convert the input signal of the first-stage ADC according to a preset period.

[0080] The accumulator module 102 is used to record and accumulate the absolute value of the first digital code output by the second-stage ADC after each conversion of the input signal.

[0081] The judgment module 103 is used to determine whether the accumulated value of the first digital code has reached the preset upper limit value; if so, the conversion of the input signal is stopped, and the average value of the accumulated value is divided by the absolute value of the residual voltage output by the first stage ADC to obtain the initial value of the iteration.

[0082] The first input module 104 is used to input the preset test waveform into the second-stage ADC to obtain the second digital code.

[0083] The iteration module 105 is used to input the initial value of the iteration, the preset iteration step size, the pseudo-random signal and the second digital code into the iteration formula for iteration until the iteration formula meets the preset convergence condition and the gain error coefficient is obtained.

[0084] The second input module 106 is used to input the target signal into the first-stage ADC.

[0085] The target calculation module 107 is used to obtain the first output value of the first-stage ADC and the second output value of the second-stage ADC, divide the second output value by the gain error coefficient, and then add it to the first output value to obtain the target output value.

[0086] The specific limitations of the two-step interstage gain error calibration device for a Pipelined SAR ADC provided in this embodiment can be found in the embodiment of the two-step interstage gain error calibration method for a Pipelined SAR ADC described above, and will not be repeated here. Each module in the above-described two-step interstage gain error calibration device for a Pipelined SAR ADC can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0087] This application provides a computer device that may include a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it causes the processor to perform the steps of a two-step interstage gain error calibration method for a Pipelined SAR ADC as described in any of the above embodiments. The working process, details, and technical effects of the computer device provided in this embodiment can be found in the above embodiments regarding a two-step interstage gain error calibration method for a Pipelined SAR ADC, and will not be repeated here.

[0088] This application provides a computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements the steps of a two-step interstage gain error calibration method for a Pipelined SAR ADC as described in any of the above embodiments. The computer-readable storage medium refers to a data storage medium, which may include, but is not limited to, floppy disks, optical disks, hard disks, flash memory, USB flash drives, and / or Memory Sticks. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0089] The working process, working details, and technical effects of the computer-readable storage medium provided in this embodiment can be found in the embodiment above regarding a two-step interstage gain error calibration method for a Pipelined SAR ADC, and will not be repeated here.

[0090] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM).

[0091] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A two-step interstage gain error calibration method for a pipelined SAR ADC, characterized in that, The method is applied in a digital logic circuit of a Pipelined SAR ADC; the Pipelined SAR ADC includes a digital logic circuit, a first-stage ADC, and a second-stage ADC, the digital logic circuit being connected to both the first-stage ADC and the second-stage ADC, and the output of the first-stage ADC being connected to the input of the second-stage ADC; the method includes: The first-stage ADC is brought into a metastable state, and the input signal of the first-stage ADC is converted according to a preset period. Record and accumulate the absolute value of the first digital code output by the second-stage ADC after each conversion of the input signal; Determine whether the accumulated value of the first digital code has reached a preset upper limit value; if so, stop converting the input signal, and divide the average value of the accumulated value by the absolute value of the residual voltage output by the first stage ADC to obtain the initial value of the iteration. Input the preset test waveform into the second-stage ADC to obtain the second digital code; The initial value of the iteration, the preset iteration step size, the pseudo-random signal and the second digital code are input into the iteration formula and iterated until the iteration formula satisfies the preset convergence condition to obtain the gain error coefficient. Input the target signal into the first-stage ADC; Obtain the first output value of the first-stage ADC and the second output value of the second-stage ADC, divide the second output value by the gain error coefficient, and then add it to the first output value to obtain the target output value.

2. The two-step interstage gain error calibration method for a Pipelined SAR ADC according to claim 1, characterized in that, Also includes: By shorting the two input terminals of the first-stage ADC, the first-stage ADC is brought into a metastable state.

3. The two-step interstage gain error calibration method for a Pipelined SAR ADC according to claim 1, characterized in that, The preset test waveform is a sine wave.

4. The two-step interstage gain error calibration method for a Pipelined SAR ADC according to claim 1, characterized in that, The preset upper limit value is 32 or 64.

5. The two-step interstage gain error calibration method for a Pipelined SAR ADC according to claim 1, characterized in that, The step of iterating the initial value, the preset iteration step size, the pseudo-random signal, and the second digital code into the iterative formula until the iterative formula satisfies the preset convergence condition to obtain the gain error coefficient includes: Initial step: Subtract the product of the pseudo-random signal and the initial iteration value from the second digital code to obtain the first value; Multiply the first value by the preset iteration step size and the pseudo-random signal to obtain the second value; Add the initial iteration value and the second value to obtain the iteration output value; Determine whether the iterative output value and the initial iterative value satisfy the preset convergence condition; If satisfied, the iterative output value or the initial iterative value is used as the gain error coefficient. If the condition is not met, the iterative output value is used as the initial value for the iteration, and the process returns to the initial step.

6. The two-step interstage gain error calibration method for a Pipelined SAR ADC according to claim 5, characterized in that, The preset convergence condition is that the absolute value of the difference between the iterative output value and the initial iterative value is within the preset convergence range.

7. The two-step interstage gain error calibration method for a Pipelined SAR ADC according to claim 5, characterized in that, The pseudo-random signal is generated by a linear feedback shift register.

8. A two-step interstage gain error calibration device for a pipelined SAR ADC, characterized in that, The device is applied in a digital logic circuit of a Pipelined SAR ADC; the Pipelined SAR ADC includes a digital logic circuit, a first-stage ADC, and a second-stage ADC, the digital logic circuit being connected to both the first-stage ADC and the second-stage ADC, and the output of the first-stage ADC being connected to the input of the second-stage ADC; the device includes: The conversion module is used to bring the first-stage ADC into a metastable state and convert the input signal of the first-stage ADC according to a preset period. An accumulation module is used to record and accumulate the absolute value of the first digital code output by the second-stage ADC after each conversion of the input signal; The judgment module is used to determine whether the accumulated value of the first digital code has reached a preset upper limit value; if so, the conversion of the input signal is stopped, and the average value of the accumulated value is divided by the absolute value of the residual voltage output by the first stage ADC to obtain the initial value of the iteration. The first input module is used to input a preset test waveform into the second-stage ADC to obtain a second digital code; The iteration module is used to iterate the initial iteration value, the preset iteration step size, the pseudo-random signal and the second digital code into the iteration formula until the iteration formula meets the preset convergence condition to obtain the gain error coefficient. The second input module is used to input the target signal into the first-stage ADC; The target calculation module is used to obtain the first output value of the first-stage ADC and the second output value of the second-stage ADC, divide the second output value by the gain error coefficient, and then add it to the first output value to obtain the target output value.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the two-step interstage gain error calibration method for the Pipelined SAR ADC as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the two-step interstage gain error calibration method for the Pipelined SAR ADC as described in any one of claims 1 to 7.

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