A display panel and a manufacturing method thereof, and a display device

Abstract

The present application provides a display panel and a manufacturing method thereof and a display device, the display panel comprising: a substrate including a signal line; a plurality of sub-pixels are arranged on the substrate; a pixel defining layer is arranged on the substrate, for defining the positions of the plurality of sub-pixels; an isolation structure is arranged on a side of the pixel defining layer away from the substrate, for isolating the plurality of sub-pixels; wherein a first chamfered structure is arranged at the connection between the isolation structure along the first direction and the isolation structure along the second direction, the substrate is provided with an anode hole, the anode hole is located in a shielding area formed by the corresponding isolation structure and the first chamfered structure, and the anode of at least one sub-pixel is connected to the signal line through the anode hole. Through the above method, the isolation structure is combined with the structure and position of the anode hole to optimize the aperture ratio and the utilization rate of the display area.

Description

Technical Field

[0001] The present application mainly relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] Active-matrix organic light emitting diode (AMOLED) display panel drives OLED to emit light through thin film transistors (TFT). In existing display products, the light-emitting area is emitted by the pixel units of the array, and the sub-pixel light-emitting units of the conventional array are prepared by fine metal mask (FMM) evaporation process. At present, a conductive partition structure can be selected to replace the conventional FMM process, and a conductive partition structure is designed for the periphery of each sub-pixel for EL film layer without fine mask (FMM) evaporation, and to form a conductive network on the whole surface to provide cathode signal transmission. In the process of designing the pixel film layer structure with a conductive partition structure, the TFT device of the lower layer needs to be connected to the pixel anode of the upper layer through a hole design to form a signal transmission. Summary of the invention

[0003] The main purpose of the present application is to provide a display panel and a manufacturing method thereof and a display device to solve the problem of optimizing the position layout of anode holes.

[0004] To solve the above problems, the present application provides a display panel, which includes: a substrate, the substrate including a signal line; a plurality of sub-pixels, which are arranged on the substrate; a pixel defining layer, which is arranged on the substrate, and the pixel defining layer is used to define the positions of the plurality of sub-pixels; an isolation structure, which is arranged on a side of the pixel defining layer away from the substrate, and the isolation structure is used to isolate the plurality of sub-pixels; wherein a first chamfered structure is provided at a connection between the isolation structure along a first direction and the isolation structure along a second direction, the substrate is provided with an anode hole, the anode hole is located in a shielding area formed by the corresponding isolation structure and the first chamfered structure, and the anode of at least one sub-pixel is connected to the signal line through the anode hole.

[0005] In one embodiment, the isolation structure along the first direction and the isolation structure along the second direction are connected to isolate a plurality of sub-pixels; wherein the anode of the sub-pixel adjacent to the first chamfered structure is provided with a second chamfered structure.

[0006] In one embodiment, an isolation structure along a first direction and an isolation structure along a second direction are connected to isolate four sub-pixels; wherein a line connecting two adjacent sub-pixels among the four sub-pixels is defined as a first reference line, and a line connecting two diagonal sub-pixels among the four sub-pixels is defined as a second reference line, and a width of the isolation structure along the second reference line is greater than √2 times the width along the first reference line.

[0007] In one embodiment, the isolation structure includes a main body and a top, the top is arranged on a side of the main body away from the pixel defining layer, and the top extends from both sides of the main body to form an overhang; the width of the overhang along the first reference line is equal to the width of the overhang along the second reference line.

[0008] In one embodiment, a distance between an edge of the overhang and an edge of the pixel defining layer along a first reference line is equal to a distance between an edge of the overhang and an edge of the pixel defining layer along a second reference line.

[0009] In one embodiment, the isolation structure along the first direction and the isolation structure along the second direction are connected to isolate three sub-pixels.

[0010] In one embodiment, the first chamfer structure is a straight chamfer or an arc chamfer, and the second chamfer structure is a straight chamfer or an arc chamfer.

[0011] To solve the above problems, the present application also provides a method for manufacturing a display panel, which comprises: providing a substrate, the substrate comprising a signal line, and an anode hole being arranged on the substrate; forming anodes of sub-pixels on the substrate, and the anode of at least one sub-pixel is connected to the signal line through the anode hole; forming a pixel defining layer on the substrate, the pixel defining layer being used to define the positions of a plurality of sub-pixels, and the pixel defining layer at least covers the anode hole; forming an isolation structure on the pixel defining layer, the isolation structure being used to isolate a plurality of sub-pixels; wherein a first chamfer structure is arranged at a connection between the isolation structure along a first direction and the isolation structure along a second direction, and the anode hole is located in a shielding area formed by the corresponding isolation structure and the chamfer structure.

[0012] In one embodiment, after forming an isolation structure on the pixel defining layer, the method further includes: forming a light-emitting layer of a sub-pixel on the anode; forming a cathode of the sub-pixel on the light-emitting layer; and forming an encapsulation layer on the isolation structure and the cathode.

[0013] To solve the above problems, the present application also provides a display device, which includes a display panel and a power supply for powering the display panel, wherein the display panel is a display panel as described in any of the above embodiments, or a display panel manufactured using a manufacturing method as described in any of the above embodiments.

[0014] By the above method, the isolation structure is combined with the structure and position of the anode hole to be optimized to occupy the non-luminous area in the display panel, improve the luminous effect of the display panel, and improve the aperture ratio and the utilization rate of the display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0016] Figure 1 is a schematic diagram of a top view of a display panel according to an embodiment of the present application;

[0017] Figure 2 is a schematic diagram of a top view of the structure of a second embodiment of a display panel provided by the present application;

[0018] Figure 3 yes Figure 1 A second example structural schematic diagram of;

[0019] Figure 4 yes Figure 1 A third exemplary structural diagram of ;

[0020] Figure 5 yes Figure 4 Schematic diagram of the cross-sectional structure of the neutron pixel Ⅰ-Ⅰ region;

[0021] Figure 6 yes Figure 4 Schematic diagram of the cross-sectional structure of the neutron pixel II-II region;

[0022] Figure 7 yes Figure 1 A schematic structural diagram of a cross section of a neutron pixel III-III region in a first embodiment;

[0023] Figure 8 yes Figure 1 A schematic structural diagram of a cross section of a neutron pixel III-III region in a second embodiment;

[0024] Figure 9a to Figure 9d is a schematic diagram of the position of the anode holes A arranged in the sub-pixels in the first embodiment of the display panel provided by the present application;

[0025] Figure 10a to Figure 10c is a schematic diagram of the positions of the anode holes A arranged in the sub-pixels in the second embodiment of the display panel provided by the present application;

[0026] Fig.11It is a schematic diagram of the steps of an embodiment of a method for manufacturing a display panel provided by the present application;

[0027] Figure 12a to Figure 12c yes Fig.11 A structural diagram of the process steps;

[0028] Fig.13 yes Fig.11 Schematic diagram of the subsequent steps of step S40;

[0029] Fig.14 It is a structural schematic diagram of an embodiment of a display device provided in the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be appreciated that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the art without making creative work are within the scope of protection of the present application.

[0031] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0032] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0033] With the gradual development of display panels, in order to make the sub-pixels of each color in the display picture corresponding to the display panel sufficiently dispersed and make the display picture more delicate, the sub-pixels of each color are usually arranged in a circular manner along the first direction, and the sub-pixels of the same color between adjacent rows of sub-pixels are staggered in the second direction, ensuring that there are no overly large monochrome pixel blocks composed of at least two sub-pixels of the same color in the display panel, thereby ensuring the resolution of the display picture. The defect of the prior art is that the human eye is usually more sensitive to the light emitted by the sub-pixels of a certain color among the sub-pixels of all colors, and the same number of sub-pixels of each color in each pixel group will cause the number of sub-pixels of the color that the human eye is most sensitive to be the same as the number of sub-pixels of any other color that the human eye is less sensitive to, resulting in a poor display effect of the display panel. In addition, if the number of sub-pixels of the color that the human eye is most sensitive to is directly increased in each pixel group, although it can increase the pixel density of the sub-pixels of a specific color, it will also lead to an increase in the non-display area occupied by the anode wiring and anode holes that need to be configured in each pixel group, thereby resulting in a decrease in the aperture ratio of the display panel. It can be seen that the existing display panel cannot increase the pixel density of the sub-pixels of a specific color while ensuring a high aperture ratio, resulting in a poor display effect of the existing display panel.

[0034] Therefore, in the pixel design, the position of the anode hole needs to be fully considered to occupy the original non-luminous area as much as possible, and at the same time, the conductive partition structure is designed to improve the luminous effect of the product. Therefore, the present application provides a display panel and its manufacturing method and a display device to solve the above problems.

[0035] See also Figure 1 As shown, Figure 1 It is a schematic diagram of the top structure of an embodiment of a display panel provided by the present application; wherein, the display panel 100 includes: a substrate 10, a sub-pixel 20, a pixel defining layer 30 and an isolation structure 40; specifically, the substrate 10 includes a signal line 11; a plurality of sub-pixels 20 are arranged on the substrate 10; the pixel defining layer 30 is arranged on the substrate 10, and the pixel defining layer 30 is used to define the positions of the plurality of sub-pixels 20; the isolation structure 40 is arranged on the side of the pixel defining layer 30 away from the substrate 10, and the isolation structure 40 is used to isolate the plurality of sub-pixels 20; wherein, a first chamfered structure E1 is provided at a connection G between the isolation structure 40 along the first direction and the isolation structure 40 along the second direction, and the substrate is provided with an anode hole A, and the anode hole A is located in a shielding area formed by the corresponding isolation structure 40 and the first chamfered structure E1, and the anode 21 of at least one sub-pixel 20 is connected to the signal line 11 through the anode hole A.

[0036] Among them, Figure 1As shown, an anode hole A is provided under the isolation structure 40 at the corner of the adjacent sub-pixel 20, and the anode hole A provides a signal connection for the sub-pixel 20; the signal line 11 corresponding to the substrate 10 and the anode 21 in the sub-pixel 20 are connected through the corresponding anode hole A using the anode lead 12.

[0037] It can be understood that the substrate 10 plays a role in supporting the entire panel in the display panel 100. The substrate 10 is generally divided into two types: a hard substrate and a soft substrate. The hard substrate is usually made of rigid materials such as glass or plastic, has good stability and durability, and is suitable for large-size display screens and professional displays; while the soft substrate is usually made of soft plastic or metal foil and other materials, and is suitable for flexible displays and wearable devices. The quality and performance of the substrate 10 directly affect the display effect and service life of the display. Therefore, when manufacturing and selecting the display panel 100, the selection of the substrate 10 is particularly important. Among them, the material of the packaging substrate 10 may include a hard packaging substrate and a flexible packaging substrate, and the selection of the material includes but is not limited to BT material, ABF material, MIS material, PI (polyimide) and PE (polyester) resin and other materials or their combinations.

[0038] The sub-pixel 20 of the display panel 100 is a basic unit that constitutes a pixel in the display screen. In a liquid crystal display screen, a pixel is usually composed of three sub-pixels 20, for example, brightness adjustment units for red, green and blue. The sub-pixels 20 of these three colors can present various colors by adjusting different combinations of brightness, so that the display screen can display color images. The arrangement of the sub-pixels 20 is usually an alternating arrangement of red, green and blue, also known as an RGB arrangement. For the sub-pixels 20 in the liquid crystal display panel 100, the main materials used include transparent conductive materials, liquid crystal materials and filters. Transparent conductive materials are mainly used as electrodes to transmit signals and control current; liquid crystal materials are used to control the degree of light penetration to achieve pixel brightness adjustment; filters are used to filter light of a specific color to ensure the accuracy of displayed colors. Specifically, in one embodiment, the sub-pixels 20 include an anode 21, a light-emitting layer 22 and a cathode 23 that are stacked in sequence. Specifically, in one embodiment, the plurality of sub-pixels 20 include corresponding red, green and blue (RGB) primary colors, that is, each color in each pixel is called a sub-pixel 20, and each sub-pixel 20 emits light of different colors, for example, red light, blue light or green light, through the light-emitting layer 22 therein when powered on.

[0039] Among them, the anode material of the anode 21 is mainly used as the anode of the device, and its work function is required to be as high as possible to improve the hole injection efficiency. The selection of anode materials includes but is not limited to chromium, titanium, gold, silver, copper, aluminum, ITO, their combination or other suitable conductive materials.

[0040] The cathode material of the cathode 23 is mainly used as the cathode of the device. The lower the metal work function of the cathode material, the easier the electron injection is, the higher the luminous efficiency is, the less Joule heat is generated during operation, and the device life is greatly improved. The selection of the cathode 23 material includes but is not limited to chromium, titanium, gold, silver, copper, aluminum, ITO, a combination thereof or other suitable conductive materials; the cathode 23 material and the anode 21 material can be the same material or different materials, which are set according to actual needs.

[0041] The light-emitting layer 22 may include one or more of: HIL (Hole Injection Layer), HTL (Hole Transfer Layer), EML (Emitting Layer) and ETL (Electron Transfer Layer). Among them, the organic light-emitting materials in the light-emitting layer 22 are generally divided into two categories: high molecular polymers, small molecule organic substances and complex light-emitting materials; high molecular polymers are usually conductive conjugated polymers or semiconductor conjugated polymers, which can be formed into films by spin coating, are simple to make and low in cost, but their purity is not easy to improve, and they are inferior to small molecule organic compounds in terms of durability, brightness and color. Organic small molecule light-emitting materials are mainly organic dyes, which have the advantages of strong chemical modification, wide selection range, easy purification, high quantum efficiency, and can produce various color emission peaks such as red, green, blue, and yellow, but most of them have concentration quenching problems in the solid state. Complex light-emitting materials are between organic and inorganic substances, with both high fluorescence quantum efficiency of organic substances and high stability of inorganic substances, and are regarded as a type of light-emitting material with great application prospects.

[0042] The pixel defining layer 30 is used to define the opening of the sub-pixel 20 in the display panel 100 to avoid interference between the colors therein; the material of the pixel defining layer 30 can be an organic material, an organic material with an inorganic coating disposed thereon, or an inorganic material. The organic material of the pixel defining layer 30 includes, but is not limited to, polyimide. The inorganic material of the pixel defining layer 30 includes, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2N2O), magnesium fluoride (MgF2), or a combination thereof.

[0043] Optionally, in one embodiment, if Figure 1As shown, the isolation structure 40 along the first direction is connected to the isolation structure 40 along the second direction to isolate a plurality of sub-pixels 20; wherein the anode 21 of the sub-pixel 20 adjacent to the first chamfered structure E1 is provided with a second chamfered structure E2. In one embodiment, the chamfer sizes between the first chamfered structures E1 or between the second chamfered structures E2 may be the same or different sizes, and similarly, the chamfer sizes of the first chamfered structure E1 and the second chamfered structure E2 may be the same or different sizes, which may be set according to actual design requirements and are not specifically limited here. For example, the chamfer size of one sub-pixel 20 is 4μm, while the chamfer sizes of the other two adjacent sub-pixels 20 are 5μm.

[0044] Optionally, in one embodiment, the first chamfer structure E1 is a straight chamfer or an arc chamfer, and the second chamfer structure E2 is a straight chamfer or an arc chamfer. Figure 1 and Figure 2 As shown, Figure 2 It is a schematic diagram of the top structure of the second embodiment of the display panel 100 provided in the present application; it can be understood that for the chamfered structure, so that the size of the connecting portion is increased, the size of the corresponding anode hole A can be better designed, and the size of the anode hole A must be smaller than the size diameter of the pixel defining layer 30 and the isolation structure 40 at the connecting portion.

[0045] Optionally, in one embodiment, if Figure 1 As shown, the isolation structure 40 along the first direction and the isolation structure 40 along the second direction are connected to isolate four sub-pixels 20, a line connecting two adjacent sub-pixels 20 among the four sub-pixels 20 is defined as a first reference line, a line connecting two diagonal sub-pixels 20 among the four sub-pixels 20 is defined as a second reference line, and a width of the isolation structure 40 along the second reference line is greater than √2 times the width along the first reference line.

[0046] It can be understood that in the above structural scheme, if Figure 3 As shown, Figure 3 yes Figure 1Schematic diagram of the second example structure; when the sub-pixel 20 and the pixel definition layer are chamfered, the anode hole A is set in the shielding area formed between the first chamfer structure E1 of the diagonal sub-pixel 20 and the corresponding isolation structure 40; it can be understood that when the chamfer is not set, the coverage area of ​​the pixel definition layer 30 of the first chamfer structure E1 between adjacent sub-pixels 20 is S1, that is, the connection part described above. For example, in one embodiment, S1 is a square area with a side length of L0, wherein the coverage spacing of the pixel definition layer 30 between two sub-pixels 20 is L1. Specifically, in one embodiment, L1 is less than or equal to 15μm, and L0=L1. In other embodiments, when the chamfer sizes between adjacent sub-pixels 20 are different, the coverage area S1 is a quadrilateral. For example, when the chamfers between adjacent sub-pixels 20 are right angles and have the same chamfer sizes, the extended connecting lines of the chamfers between adjacent sub-pixels 20 form an S2 region, where S2 is a square region with a side length of L2, where L2 is greater than √2 times L0.

[0047] Optionally, in one embodiment, wherein, refer to Figure 4 , Figure 5 and Figure 6 As shown, Figure 4 yes Figure 1 A third exemplary structural diagram of ; Figure 5 yes Figure 4 Schematic diagram of the cross-sectional structure of the neutron pixel Ⅰ-Ⅰ region; Figure 6 yes Figure 4 Schematic diagram of the cross-sectional structure of the neutron pixel II-II region; wherein, the isolation structure 40 includes a main body 41 and a top 42, the top 42 is arranged on the side of the main body 41 away from the pixel defining layer 30, and the top 42 extends from both sides of the main body 41 to form an overhang; the width of the overhang along the first reference line is equal to the width of the overhang along the second reference line.

[0048] Optionally, in one embodiment, the distance between the edge of the overhang and the edge of the pixel defining layer 30 along the first reference line is equal to the distance between the edge of the overhang and the edge of the pixel defining layer 30 along the second reference line.

[0049] Understandable, such as Figure 5 As shown, the coverage distance of the pixel defining layer 30 between adjacent sub-pixels 20 is D1 and the width of the top 42 is D2, the distance between the edge end of the main body 41 contacting the top 42 and the top 42 from the side of the main body 41 away from the pixel defining layer 30 is X1, and the distance from the side of the overhanging portion from the side of the main body 41 away from the pixel defining layer 30 to the side of the covering edge of the pixel defining layer 30 on the same side is Y1; for example, in one embodiment, Y is less than or equal to 5μm. In one embodiment, as Figure 6As shown, in the II-II region, the coverage distance of the pixel defining layer 30 between adjacent sub-pixels 20 in the isolation structure 40 is D3 and the width of the top 42 is D4, the distance between the edge end of the main body 41 in contact with the top 42 and the top 42 from the side of the main body 41 away from the pixel defining layer 30 is X2, and the distance from the side of the overhanging portion from the side of the main body 41 away from the pixel defining layer 30 to the same side on the covered edge of the pixel defining layer 30 is Y2; wherein, X1=X2, Y1=Y2. In one embodiment, for the setting of the anode hole A, the diameter of the anode hole A is smaller than the width of the isolation structure 40, and when the anode lead 12 is set to cover the corresponding anode hole A, the width of the anode lead 12 cannot be short-circuited with the anode of the adjacent sub-pixel 20. Therefore, in the width setting of the anode lead 12, it is necessary to satisfy that its width is smaller than the width of the top 42 of the isolation structure 40; in other embodiments, the width of the anode lead 12 may also be larger than the width of the top 42 of the isolation structure 40, but it is necessary to satisfy that the anode lead 12 is separated from the adjacent sub-pixel 20 by an insulating pixel defining layer 30.

[0050] The isolation structure 40 separates the adjacent sub-pixels 20 to avoid the cathode conduction between the adjacent sub-pixels 20 and the color interference between them, so as to better solve the problems of low resolution and low yield of panel devices. The material of the main body 41 is a conductive metal or other metal oxide. For example, the material of the main body 41 can be, but is not limited to: aluminum (Al), magnesium (Mg), copper (Cu), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IGZO) and other conductive metals or other metal oxides or their combinations, that is, it can meet the use conditions of the implementation scheme, and no specific limitation is made here; the material of the top 42 is an insulating material, for example, it can be, but is not limited to, silicon monoxide (SiO), silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiNO) and other materials.

[0051] In the above embodiment, due to the presence of the anode hole A, Figure 7 and Figure 8 As shown, Figure 7 yes Figure 1 A schematic structural diagram of a cross section of a neutron pixel III-III region in a first embodiment; Figure 8 yes Figure 1Schematic diagram of the structure of the second embodiment of the cross-section of the III-III region of the sub-pixel; when the anode hole A is set to be relatively deep, but since the thickness of the pixel defining layer 30 is set to be relatively thin, after filling the anode hole A, deposition will occur at the position of the anode hole A, and then a relatively small pit will appear on the surface of the isolation structure 40; however, in the embodiment, the width of the upper isolation structure 40 on both sides is greater than the set diameter of the anode hole A, so the pit will only be recessed in the middle of the isolation structure 40 and will not affect the stability of the overall structure of the display panel 100 and the evaporation function.

[0052] Among them, in the above embodiments, different arrangement schemes also correspond to different arrangements of the sub-pixels 20. Specifically, for example, in one embodiment, for the arrangement of the strip-shaped sub-pixels 20, as Figure 9a to Figure 9d shown, where Figure 9a to Figure 9d is a schematic diagram of the position of the anode hole A in the sub-pixel arrangement of the first embodiment of the display panel provided by the present application; specifically, for the arrangement of such strip-shaped pixels similar to a quadrilateral, the setting of the anode hole A can be correspondingly set at different directional positions; it can be understood as Figure 9a to Figure 9d shown, the anode hole A is set at the upper left corner, or the lower left corner, or the upper right corner, or the lower right corner of a plurality of sub-pixels 20, that is, below the overhanging structure at the overlapping part of the corresponding first direction and the second direction, and the anode lead 12 is correspondingly used to connect the anode 21 and the signal line 11 through the anode hole A. In another embodiment, for a T-shaped arrangement similar to a character "pin", as Figure 10a to Figure 10c shown in Figure 10a to Figure 10c is a schematic diagram of the position of the anode hole A in the sub-pixel arrangement of the second embodiment of the display panel provided by the present application; optionally, in one embodiment, the isolation structure 40 along the first direction and the isolation structure 40 along the second direction are connected to isolate three sub-pixels 20. As Figure 10a to Figure 10c shown, among the three sub-pixels 20, the left two sub-pixels 20 are arranged vertically and then arranged side by side with the right sub-pixel 20 to form a pixel arrangement similar to a character "pin", where the isolation structure 40 along the first direction and the isolation structure 40 along the second direction are connected to form a T-shaped structure region; correspondingly, as Fig.10a shown, the upper left sub-pixel 20 is provided with an anode hole A at the lower left corner, the lower left sub-pixel 20 is provided with an anode hole A at the upper right corner, and the right sub-pixel 20 is provided with an anode hole A at the upper left corner. Each sub-pixel 20 uses the anode lead 12 to connect the anode 21 and the signal line 11 in the substrate 10 through the anode hole A. Correspondingly, as Fig.10bAs shown, the upper left sub-pixel 20 is provided with an anode hole A in the upper right corner, the lower left sub-pixel 20 is provided with an anode hole A in the upper left corner, and the right sub-pixel 20 is provided with an anode hole A in the middle T-shaped intersection area. Each sub-pixel 20 uses an anode lead 12 to connect the anode 21 and the signal line 11 in the substrate 10 through the anode hole A. Correspondingly, Fig.10c As shown, the upper left sub-pixel 20 is provided with an anode hole A in the upper left corner, the lower left sub-pixel 20 is provided with an anode hole A in the upper left corner, and the sub-pixel 20 on the right is provided with an anode hole A in the middle T-shaped intersection area. Each sub-pixel 20 uses an anode lead 12 to connect the anode 21 and the signal line 11 in the substrate 10 through the anode hole A.

[0053] It can be understood that the sub-pixel 20 in the above description is Figure 9a to Figure 9d and Figure 10a to Figure 10c In the embodiment, the sub-pixels 20 are all formed by linear chamfers. In other embodiments, the sub-pixels 20 may also be formed by arc chamfers, such as Figure 2 As shown, the corresponding arrangement mode and the setting mode of the anode hole A are the same.

[0054] To solve the above problems, the present application also provides a method for manufacturing a display panel 100, such as Fig.11 and Figure 12a to Figure 12c As shown, Fig.11 It is a schematic diagram of the steps of an embodiment of a method for manufacturing a display panel provided by the present application; Figure 12a to Figure 12c yes Fig.11 Specifically, the manufacturing method of the display panel 100 includes the following steps:

[0055] Step S10: providing a substrate, the substrate comprising a signal line, and an anode hole is arranged on the substrate.

[0056] Understandable, such as Fig.12a As shown, an anode hole A is set on the substrate 10, and the signal line 11 in the substrate 10 is connected to the anode 21 in the sub-pixel 20 through the anode hole A to achieve signal transmission and conduction, thereby achieving control of the display image, such as a TFT (Thin Film Transistor) thin film transistor substrate 10.

[0057] Step S20: forming anodes of sub-pixels on the substrate, wherein the anode of at least one sub-pixel is connected to a signal line through an anode hole.

[0058] like Figure 12b As shown, the structural material of the anode 21 is the same as that in the above embodiment, and no further details are given here. After the anode 21 is formed, the anode 21 is chamfered to form a second chamfered structure E2, so as to leave a position for the anode hole A.

[0059] Step S30: forming a pixel defining layer on the substrate, the pixel defining layer is used to define the positions of a plurality of sub-pixels, and the pixel defining layer at least covers the anode hole.

[0060] like Fig.12c As shown, the pixel defining layer 30 is used to define the opening of the sub-pixel 20 in the display panel 100 to avoid interference between the colors therein; the material of the pixel defining layer 30 can be an organic material, an organic material with an inorganic coating disposed thereon, or one of inorganic materials. The organic material of the pixel defining layer 30 includes, but is not limited to, polyimide. The inorganic material of the pixel defining layer 30 includes, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2N2O), magnesium fluoride (MgF2), or a combination thereof. Among them, the pixel defining layer 30 can also be chamfered to leave enough space for the anode hole A to increase the opening ratio.

[0061] Step S40: forming an isolation structure on the pixel defining layer, the isolation structure being used to isolate a plurality of sub-pixels; wherein a first chamfer structure is provided at the connection between the isolation structure along the first direction and the isolation structure along the second direction, and the anode hole is located in a shielding area formed by the corresponding isolation structure and the chamfer structure.

[0062] like Figure 7 and Fig.12c As shown, the isolation structure 40 includes a main body 41 and a top 42, which are sequentially formed on the pixel defining layer 30. The material of the main body 41 is a conductive metal or other metal oxide. For example, the material of the main body 41 may include but is not limited to: aluminum (Al), magnesium (Mg), copper (Cu), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IGZO) and other conductive metals or other metal oxides or their combinations, that is, they meet the use conditions of the implementation scheme, and are not specifically limited here; the material of the top 42 is an insulating material, for example, it may include but is not limited to silicon monoxide (SiO), silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiNO) and other materials.

[0063] See also Fig.13 As shown, Fig.13 yes Fig.11 Schematic diagram of the subsequent steps of step S40; specifically, after forming the isolation structure 40 on the pixel defining layer 30, it also includes:

[0064] Step S50: forming a light-emitting layer of a sub-pixel on the anode.

[0065] The light emitting layer 22 may emit different colors, for example, three primary colors of red, green and blue (RGB), so as to emit light of different colors when power is supplied to the light emitting layer 22 .

[0066] Step S60: forming a cathode of a sub-pixel on the light-emitting layer.

[0067] like Figure 7 As shown, the material of the cathode 23 may include but is not limited to chromium, titanium, gold, silver, copper, aluminum, ITO, a combination thereof or other suitable conductive materials; wherein the cathode 23 material and the anode 21 material may be the same material or different materials, and are set according to actual needs.

[0068] Step S70: forming a packaging layer on the isolation structure and the cathode.

[0069] The encapsulation layer is mainly used to protect and isolate the sub-pixels 20, protect their structure and prevent crosstalk, and isolate them from the external environment to prevent impurities, oxygen, moisture and other substances in the air from polluting and corroding the display panel 100, and to prevent external force damage and other problems. The encapsulation methods used include but are not limited to chemical vapor deposition (CVD), atomic layer deposition technology (ALD) and mixed barrier layer methods.

[0070] Traditional packaging technology is to package electrodes and various organic functional layers on a rigid substrate. Generally, a cover plate is added to the device, and a desiccant is attached, and then the substrate and the cover plate are combined by a sealant such as epoxy resin; while thin film packaging is the mainstream packaging technology at present. Thin film packaging materials are mainly divided into inorganic packaging materials, organic packaging materials and inorganic-organic composite packaging materials. Among them, inorganic-organic composite packaging materials have the advantages of good water and oxygen barrier properties of inorganic packaging materials and good film-forming properties of organic packaging materials, and are the mainstream choice of packaging materials. The key core material of OLED devices is the ultra-thin organic electroluminescent layer 22, which is extremely sensitive to water, oxygen and heat, which is also the reason for its poor stability. Therefore, after the display panel 100 is completed, a packaging layer is usually formed on this basis to protect the display panel 100 and extend the service life of the display panel 100.

[0071] To solve the above problems, the present application also provides a display device, see Fig.14 As shown, Fig.14 1 is a schematic diagram of a structure of an embodiment of a display device provided by the present application. The display device 300 includes a display panel 100 and a power supply 200, wherein the display panel is any display panel 100 described in the above embodiments or a display panel 100 manufactured by the above manufacturing method, and the power supply 200 supplies energy to the display panel to provide a stable picture output to the display device 300 through the display panel 100.

[0072] The display panel provided in the present application includes: a substrate 10, a sub-pixel 20, a pixel defining layer 30 and an isolation structure 40; specifically, the substrate 10 includes a signal line 11; a plurality of sub-pixels 20 are arranged on the substrate 10, and the sub-pixels 20 include at least an anode 21; the pixel defining layer 30 is arranged on the substrate 10, and the pixel defining layer 30 is used to define the positions of the plurality of sub-pixels 20; the isolation structure 40 is arranged on a side of the pixel defining layer 30 away from the substrate 10, and the isolation structure 40 is used to isolate the plurality of sub-pixels 20; wherein the isolation structure 40 along the first direction and the isolation structure 40 along the second direction are connected to form a connecting portion, the connecting portion includes an overlapping portion corresponding to both the first direction and the second direction, and a chamfered portion corresponding to the angle between the first direction and the second direction, the connecting portion forms a projection area on the substrate 10, the substrate 10 is provided with an anode hole A located in the projection area, and at least one anode 21 of the plurality of anodes 21 adjacent to the connecting portion is connected to the signal line 11 through the anode hole A.

[0073] By the above method, the isolation structure is combined with the structure and position of the anode hole to be optimized to occupy the non-luminous area in the display panel, improve the luminous effect of the display panel, and improve the aperture ratio and the utilization rate of the display area.

[0074] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: The display panel comprises: a substrate, the substrate comprising a signal line; A plurality of sub-pixels are disposed on the substrate; A pixel defining layer, disposed on the substrate, and used to define positions of a plurality of sub-pixels; An isolation structure, disposed on a side of the pixel defining layer away from the substrate, the isolation structure being used to isolate a plurality of the sub-pixels; A first chamfered structure is provided at the connection between the isolation structure along the first direction and the isolation structure along the second direction, the substrate is provided with an anode hole, the anode hole is located in a shielding area formed by the isolation structure and the first chamfered structure, and the anode of at least one of the sub-pixels is connected to the signal line through the anode hole.

2. The display panel according to claim 1, characterized in that: The isolation structure along the first direction and the isolation structure along the second direction are connected to isolate the plurality of sub-pixels; Wherein, the anode of the sub-pixel adjacent to the first chamfered structure is provided with a second chamfered structure.

3. The display panel according to claim 2, characterized in that: The isolation structure along the first direction and the isolation structure along the second direction are connected to isolate four sub-pixels; Among them, a line connecting two adjacent sub-pixels among the four sub-pixels is defined as a first reference line, a line connecting two diagonal sub-pixels among the four sub-pixels is defined as a second reference line, and a width of the isolation structure along the second reference line is greater than √2 times the width along the first reference line.

4. The display panel according to claim 3, characterized in that: The isolation structure comprises a main body and a top portion, wherein the top portion is arranged on a side of the main body away from the pixel defining layer, and the top portion extends from both sides of the main body to form an overhang portion; The width of the overhang portion along the first reference line is equal to the width of the overhang portion along the second reference line.

5. The display panel according to claim 4, characterized in that: A distance between an edge of the overhang and an edge of the pixel defining layer along the first reference line is equal to a distance between an edge of the overhang and an edge of the pixel defining layer along the second reference line.

6. The display panel according to claim 2, characterized in that: The isolation structure along the first direction and the isolation structure along the second direction are connected to isolate the three sub-pixels.

7. The display panel according to claim 2, characterized in that: The first chamfer structure is a linear chamfer or an arc chamfer, and the second chamfer structure is a linear chamfer or an arc chamfer.

8. A method for manufacturing a display panel, characterized in that: The manufacturing method of the display panel includes: Providing a substrate, the substrate comprising a signal line, and an anode hole is arranged on the substrate; forming anodes of sub-pixels on the substrate, wherein the anode of at least one sub-pixel is connected to the signal line through the anode hole; forming a pixel defining layer on the substrate, wherein the pixel defining layer is used to define positions of a plurality of sub-pixels, and the pixel defining layer at least covers the anode hole; An isolation structure is formed on the pixel defining layer, and the isolation structure is used to isolate the multiple sub-pixels; wherein a first chamfer structure is provided at the connection between the isolation structure along the first direction and the isolation structure along the second direction, and the anode hole is located in a shielding area formed by the isolation structure and the chamfer structure.

9. The method for manufacturing a display panel according to claim 8, characterized in that: After forming the isolation structure on the pixel defining layer, the method further includes: forming a light-emitting layer of a sub-pixel on the anode; forming a cathode of a sub-pixel on the light-emitting layer; An encapsulation layer is formed on the isolation structure and the cathode.

10. A display device, characterized in that: The display device includes a display panel and a power supply for supplying power to the display panel, wherein the display panel is a display panel as described in any one of claims 1 to 7, or a display panel manufactured by the manufacturing method as described in claim 8 or 9.

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