Preparation method of epitaxial GaN HEMT high voltage device on SiC JFET wafer

Abstract

The present invention provides a method for preparing an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer, the method comprising: growing a buffer layer and an n-SiC epitaxial layer from bottom to top from an obliquely cut n+SiC substrate to manufacture a SiC epitaxial wafer; treating the surface of the SiC epitaxial wafer to form a P-well and n+SiC contact region to manufacture a SiC JFET structure; performing treatment to form epitaxial graphene; performing epitaxial growth on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer; and respectively taping out SiC JFET and MIS-recessed gate HEMT HyFET devices, and SiC JFET and P-GaN HEMT HyFET devices through SiC / GaN hybrid epitaxial wafers that do not contain a P-GaN cap layer and contain a P-GaN cap layer. This method avoids the surface of the GaN HEMT epitaxial layer being too rough, thereby improving the material mobility and square resistance quality.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer. Background Art

[0002] Gallium nitride (GaN) and silicon carbide (SiC) are very suitable for manufacturing high-efficiency power switching devices due to their high critical breakdown electric field and relatively large carrier mobility. SiC field effect transistors have a large channel resistance due to the low hole mobility of p-SiC, while GaN HEMT devices have the characteristics of small channel resistance. The advantages of GaN and SiC are highly complementary, and it is very attractive to build a power device that can utilize the technical advantages of GaN and SiC.

[0003] In the related art, n-SiC transition and epitaxial layers are introduced on the beveled SiC substrate. After ion implantation, direct conventional GaN HEMT heterostructure epitaxial growth will make the surface of the GaN HEMT epitaxial layer rough, thus resulting in poor material mobility and square resistance quality. Summary of the invention

[0004] In view of this, the object of the present invention is to provide a method for preparing a high-voltage device of epitaxial GaN HEMT on a SiC JFET wafer, so as to avoid the surface of the GaN HEMT epitaxial layer being too rough, thereby improving the material mobility and square resistance quality.

[0005] In a first aspect, an embodiment of the present invention provides a method for preparing an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer, comprising: growing a buffer layer and an n-SiC epitaxial layer from bottom to top on a beveled n+SiC substrate to manufacture a SiC epitaxial wafer; treating the surface of the SiC epitaxial wafer to form a P-well and an n+SiC contact region to manufacture a SiC JFET structure; treating the surface of the SiC JFET structure to form an epitaxial graphene; epitaxially growing a III-nitride heterostructure on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer; if the epitaxial growth does not include a P-GaN layer, then fabricating a SiC JFET and a MIS-recess gate HEMT HyFET device by tape-out of a SiC / GaN hybrid epitaxial wafer that does not include a P-GaN cap layer; if the epitaxial growth includes an epitaxial P-GaN layer, then fabricating a SiC JFET and a P-GaN HEMT HyFET device by tape-out of a SiC / GaN hybrid epitaxial wafer that includes a P-GaN cap layer.

[0006] In a preferred embodiment of the present invention, the above-mentioned surface treatment of the SiC epitaxial wafer to form the contact area between P-well and n+SiC includes: using a mask process, ion implantation and activation process to make the contact area between P-well and n+SiC on the surface of the SiC epitaxial wafer.

[0007] In a preferred embodiment of the present invention, the material of the mask layer used for ion implantation is one of photoresist, silicon oxide, silicon nitride and other amorphous material hard masks, and the thickness range of the mask layer material is [0.5, 5] microns; after P-type ion and N-type ion implantation in the contact area, the mask layer is etched and removed, and the etching depth range of the SiC outer layer under the mask layer is [0, 200] nanometers.

[0008] In a preferred embodiment of the present invention, the surface of the SiC JFET structure is processed to form epitaxial graphene, including: forming an epitaxial graphene single crystal film on the surface of the SiC JFET structure by a preset method; the preset method is one of high temperature heat treatment technology, molecular beam epitaxy technology and carbon source introduction chemical vapor deposition technology.

[0009] In a preferred embodiment of the present invention, the above-mentioned high-temperature heat treatment technology includes one of HTCVD, MOCVD and high-temperature heat treatment in an activated furnace tube under Ar pressure, the Ar pressure range is [1, 2000] torr, and the treatment temperature range of the high-temperature heat treatment is [900-1700] degrees Celsius; the molecular beam epitaxy technology is a heat treatment under high vacuum conditions, and the corresponding temperature range is [800, 1350] degrees Celsius.

[0010] In a preferred embodiment of the present invention, when the epitaxial growth does not include an epitaxial P-GaN layer, epitaxial growth of a III-nitride heterostructure is performed on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer, including: sequentially epitaxially growing a III-Nitride starting layer, a III-Nitrid buffer layer, a III-Nitride channel layer and a III-Nitride barrier layer on the surface of the epitaxial graphene to prepare a SiC / GaN hybrid epitaxial wafer.

[0011] In a preferred embodiment of the present invention, when the epitaxial growth includes an epitaxial P-GaN layer, epitaxial growth of a III-nitride heterostructure is performed on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer, including: sequentially epitaxially growing a III-Nitride starting layer, a III-Nitrid buffer layer, a III-Nitride channel layer, a III-Nitride barrier layer and a P-GaN layer on the surface of the epitaxial graphene to prepare a SiC / GaN hybrid epitaxial wafer.

[0012] In a preferred embodiment of the present invention, the III-Nitride starting layer is one of AlN, AlGaN and GaN, and the thickness range of the III-Nitride starting layer is [0, 500] nanometers; the III-Nitride channel layer is one of GaN, InGaN, and AlGaN with a low Al component, and the thickness range of the III-Nitride channel layer is [20, 800] nanometers; the III-Nitride barrier layer is one of GaN, AlGaN and AlN, and the thickness range of the III-Nitride barrier layer is [0, 40] nanometers; the thickness range of the P-GaN layer is [50, 150] nanometers.

[0013] In a preferred embodiment of the present invention, SiC JFET and P-GaN HEMT HyFET devices are manufactured by tape-out of a SiC / GaN hybrid epitaxial wafer including a P-GaN cap layer, including: SiC JFET and P-GaN HEMT HyFET devices are obtained by process manufacturing of a SiC / GaN hybrid epitaxial wafer including a P-GaN cap layer; the process manufacturing includes: surface passivation, photolithography, III-Nitride TSV etching, graphene insulation treatment of the bottom and side surfaces of TSV, metal deposition, alloying annealing and electrode opening interconnection.

[0014] In a preferred embodiment of the present invention, the substrate is 4H-SiC or 6H-SiC, a substrate material with a bevel angle of 4° or 8°; the n-SiC epitaxial layer includes a SiC starting buffer layer, and the thickness range of the SiC starting buffer layer is [0.2, 3] microns; the thickness range of the n-SiC epitaxial layer is [8, 40] microns.

[0015] In a second aspect, an embodiment of the present invention further provides a device for preparing an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer, the device comprising: a SiC epitaxial wafer manufacturing module, used to grow a buffer layer and an n-SiC epitaxial layer from a beveled n+SiC substrate from bottom to top to manufacture a SiC epitaxial wafer; a contact region forming module, used to form a P-well and an n+SiC contact region on the surface of the SiC epitaxial wafer to manufacture a SiC JFET structure; an epitaxial graphene forming module, used to process the surface of the SiC JFET structure to form epitaxial graphene; an epitaxial growth module, used to perform epitaxial growth of a III-nitride heterostructure on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer; a first tape-out manufacturing module, used to tape-out a SiC JFET and a MIS-recessed gate HEMT through a SiC / GaN hybrid epitaxial wafer that does not include a P-GaN cap layer if the epitaxial growth does not include a P-GaN layer HyFET device; a second tape-out manufacturing module, used for, if the epitaxial growth includes an epitaxial P-GaN layer, taping out SiC JFET and P-GaN HEMT HyFET devices by SiC / GaN hybrid epitaxial wafers including a P-GaN cap layer.

[0016] The embodiments of the present invention bring the following beneficial effects:

[0017] The embodiment of the present invention provides a method for preparing an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer, wherein a buffer layer and an n-SiC epitaxial layer are grown from a beveled n+SiC substrate from bottom to top to manufacture a SiC epitaxial wafer, a surface of the SiC epitaxial wafer is treated to form a P-well and an n+SiC contact region, a SiC JFET structure is manufactured, a surface of the SiC JFET structure is treated to form an epitaxial graphene, and an epitaxial growth of a III-nitride heterostructure is performed on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer, if the epitaxial growth does not include a P-GaN layer, a SiC JFET and a MIS-recessed gate HEMT HyFET device are manufactured by tape-out of a SiC / GaN hybrid epitaxial wafer that does not include a P-GaN cap layer, and if the epitaxial growth includes an epitaxial P-GaN layer, a SiC JFET and a P-GaN HEMT HyFET device are manufactured by tape-out of a SiC / GaN hybrid epitaxial wafer that includes a P-GaN cap layer. In this way, the surface of the GaN HEMT epitaxial layer is prevented from being too rough, thereby improving the material mobility and square resistance quality.

[0018] Other features and advantages of the present disclosure will be set forth in the following description, or some features and advantages may be inferred or unambiguously determined from the description, or may be learned by implementing the above-mentioned technology of the present disclosure.

[0019] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A flow chart of a method for preparing an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer provided in an embodiment of the present invention;

[0022] Figure 2 A demonstration diagram of a method for preparing an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer provided by an embodiment of the present invention;

[0023] Figure 3 A schematic structural diagram of a device for preparing an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] Gallium nitride (GaN) and silicon carbide (SiC) are very suitable for manufacturing high-efficiency power switching devices due to their high critical breakdown electric field and relatively large carrier mobility. SiC field effect transistors have a large channel resistance due to the low hole mobility of p-SiC, while GaN HEMT devices have the characteristics of small channel resistance. The advantages of GaN and SiC are highly complementary, and it is very attractive to build a power device that can utilize the technical advantages of GaN and SiC.

[0026] In the related art, n-SiC transition and epitaxial layers are introduced on the beveled SiC substrate. After ion implantation, direct conventional GaN HEMT heterostructure epitaxial growth will make the surface of the GaN HEMT epitaxial layer rough, thus resulting in poor material mobility and square resistance quality.

[0027] Specifically, the compatibility of GaN and SiC epitaxial technologies is poor. SiC homoepitaxial growth is usually performed on an off-axis substrate with a bevel angle of 4° or 8°. In contrast, GaN-on-SiC heteroepitaxial growth is usually performed on an on-axis SiC substrate with a bevel angle of less than 0.25°, and the quality of GaN epitaxially grown on the bevel is poor. After the P-well is activated by injection, the SiC transition layer is epitaxially grown for the second time and activated after injection of n+, resulting in a rough surface, which results in poor material mobility and square resistance quality.

[0028] In the related art, GaN is bonded to the surface of a SiC JFET wafer through a bonding process, which requires a relatively high etching and bonding process.

[0029] Specifically, the etching and bonding processes have high requirements. Since the polarity is reversed after bonding, the secondary epitaxial heterostructure is difficult to form, so etching damage is difficult to avoid, which in turn causes poor material mobility and square resistance quality.

[0030] Based on this, an embodiment of the present invention provides a method for preparing an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer, wherein a buffer layer and an n-SiC epitaxial layer are grown from a beveled n+SiC substrate from bottom to top to manufacture a SiC epitaxial wafer, a surface of the SiC epitaxial wafer is treated to form a P-well and n+SiC contact region, a SiC JFET structure is manufactured, the surface of the SiC JFET structure is treated to form an epitaxial graphene, and a III-nitride heterostructure is epitaxially grown on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer. If the epitaxial growth does not include a P-GaN layer, a SiC JFET and a MIS-recessed gate HEMT HyFET device are manufactured by tape-out of a SiC / GaN hybrid epitaxial wafer that does not include a P-GaN cap layer. If the epitaxial growth includes an epitaxial P-GaN layer, a SiC JFET and a P-GaN HEMT HyFET device are manufactured by tape-out of a SiC / GaN hybrid epitaxial wafer that includes a P-GaN cap layer. In this way, the surface of the GaN HEMT epitaxial layer is prevented from being too rough, thereby improving the material mobility and square resistance quality.

[0031] To facilitate understanding of this embodiment, a method for preparing an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer disclosed in an embodiment of the present invention is first introduced in detail.

[0032] Example 1

[0033] The embodiment of the present invention provides a method for preparing a high-voltage GaN HEMT device epitaxially on a SiC JFET wafer. Figure 1 A flow chart of a method for preparing an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer provided in an embodiment of the present invention.

[0034] And for ease of understanding, Figure 2 A demonstration diagram of a method for preparing an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer provided in an embodiment of the present invention, corresponding to the preparation method in Example 1.

[0035] like Figure 1 As shown, the method for preparing the epitaxial GaN HEMT high voltage device on the SiC JFET wafer may include the following steps:

[0036] Step S101 , growing a buffer layer and an n-SiC epitaxial layer from bottom to top on an obliquely cut n+SiC substrate to produce a SiC epitaxial wafer.

[0037] The substrate is 4H-SiC or 6H-SiC, and the substrate material is beveled at 4° or 8°; the n-SiC epitaxial layer includes a SiC starting buffer layer, and the thickness interval of the SiC starting buffer layer is [0.2, 3] microns; the thickness interval of the n-SiC epitaxial layer is [8, 40] microns, and the room temperature carrier concentration after nitrogen doping concentration is 1E15cm -3 ~2E16cm -3 .

[0038] Step S102 , forming a contact region between P-well and n+SiC by surface treatment on the SiC epitaxial wafer to manufacture a SiC JFET structure.

[0039] Specifically, making the contact area between P-well and n+SiC on the surface of the SiC epitaxial wafer may include: making the contact area between P-well and n+SiC on the surface of the SiC epitaxial wafer using a mask process, ion implantation and activation process.

[0040] Among them, the material of the mask layer used for ion implantation is one of photoresist, silicon oxide, silicon nitride and other amorphous material hard masks, and the thickness range of the mask layer material is [0.5, 5] microns; after P-type ion and N-type ion implantation in the contact area, the mask layer is etched and removed, and the etching depth range of the SiC outer layer under the mask layer is [0, 200] nanometers.

[0041] Step S103, processing the surface of the SiC JFET structure to form epitaxial graphene.

[0042] Specifically, processing the surface of the SiC JFET structure to form epitaxial graphene may include: forming an epitaxial graphene single crystal thin film on the surface of the SiC JFET structure in a preset manner.

[0043] Among them, the preset method is one of high temperature heat treatment technology, molecular beam epitaxy technology and carbon source introduction chemical vapor deposition technology.

[0044] The formed epitaxial graphene single crystal film may be a single layer or a multilayer.

[0045] Among them, high-temperature heat treatment technology includes HTCVD, MOCVD and one of the high-temperature heat treatments in an activated furnace tube in Ar gas pressure. The Ar gas pressure range is [1, 2000] Torr, and the treatment temperature range of the high-temperature heat treatment is [900-1700] degrees Celsius; molecular beam epitaxy technology is a heat treatment under high vacuum conditions, and the corresponding temperature range is [800, 1350] degrees Celsius.

[0046] As a way to achieve this, the graphene single crystal film can also be replaced with other van der Waals two-dimensional materials, such as MoS2 or WS2. By using remote epitaxy on the surface of van der Waals two-dimensional materials, the lattice mismatch between III-Nitride and the substrate can be alleviated, and a higher quality III-Nitride heterostructure can be epitaxially grown to effectively improve device performance.

[0047] Furthermore, after the epitaxial graphene single crystal film is formed, the surface of the graphene single crystal film may be processed to form graphene oxide.

[0048] Among them, the treatment includes surface treatment process and plasma treatment.

[0049] Step S104, epitaxial growth of a III-nitride heterostructure is performed on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer.

[0050] Specifically, when the epitaxial growth does not include an epitaxial P-GaN layer, epitaxial growth of a III-nitride heterostructure is performed on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer, which may include: sequentially epitaxially growing a III-Nitride starting layer, a III-Nitrid buffer layer, a III-Nitride channel layer and a III-Nitride barrier layer on the surface of the epitaxial graphene to prepare a hybrid epitaxial wafer.

[0051] Specifically, when the epitaxial growth includes an epitaxial P-GaN layer, epitaxial growth of a III-nitride heterostructure is performed on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer, which may include: sequentially epitaxially growing a III-Nitride starting layer, a III-Nitrid buffer layer, a III-Nitride channel layer, a III-Nitride barrier layer and a P-GaN layer on the surface of the epitaxial graphene to prepare a hybrid epitaxial wafer.

[0052] Among them, the III-Nitride starting layer is one of AlN, AlGaN and GaN, and the thickness range of the III-Nitride starting layer is [0, 500] nanometers; the III-Nitride channel layer is one of GaN, InGaN, and AlGaN with a low Al component, and the thickness range of the III-Nitride channel layer is [20, 800] nanometers; the III-Nitride barrier layer is one of GaN, AlGaN and AlN, and the thickness range of the III-Nitride barrier layer is [0, 40] nanometers; the thickness range of the P-GaN layer is [50, 150] nanometers.

[0053] It should be noted that, if after forming an epitaxial graphene single crystal film, the surface of the graphene single crystal film is treated to form graphene oxide, epitaxial growth of a III-nitride heterostructure is performed on the surface of the graphene oxide to obtain a SiC / GaN hybrid epitaxial wafer.

[0054] Step S105 , if the epitaxial growth does not include a P-GaN layer, SiC JFET and MIS-recessed gate HEMT HyFET devices are fabricated by tape-out of a SiC / GaN hybrid epitaxial wafer that does not include a P-GaN cap layer.

[0055] Specifically, if the epitaxial growth does not include a P-GaN layer, the SiC JFET and MIS-recessed gate HEMT HyFET devices are manufactured by tape-out of a SiC / GaN hybrid epitaxial wafer that does not include a P-GaN cap layer, which may include: SiC JFET and MIS-recessed gate HEMT HyFET devices are manufactured by surface passivation, photolithography, dry etching and other recessed gate processes through a SiC / GaN hybrid epitaxial wafer that does not include a P-GaN cap layer.

[0056] Step S106 , if the epitaxial growth includes an epitaxial P-GaN layer, SiC JFET and P-GaN HEMT HyFET devices are fabricated by tape-out of a SiC / GaN hybrid epitaxial wafer including a P-GaN cap layer.

[0057] Specifically, the SiC JFET and P-GaN HEMT HyFET devices are manufactured by tape-out of a SiC / GaN hybrid epitaxial wafer including a P-GaN cap layer, which may include: obtaining SiC JFET and P-GaN HEMT HyFET devices through process manufacturing of a SiC / GaN hybrid epitaxial wafer including a P-GaN cap layer; the process manufacturing includes: surface passivation, photolithography, III-Nitride TSV etching, graphene insulation treatment of the bottom and side surfaces of TSV, metal deposition, alloying annealing and electrode opening interconnection.

[0058] In the embodiment of the present application, by covering with two-dimensional materials, such as graphene, directly remote epitaxy of GaN HEMT heterostructures is achieved to realize the integration of beveled 4H-SiC JFET and GaN HEMT on the same wafer, which can avoid the damage of GaN materials and interface states caused by etching of the bonding scheme, thereby obtaining high-voltage and high-reliability SiC / GaN high-power hybrid transistor devices. Covering with two-dimensional materials, such as graphene or graphene oxide, reduces the surface roughness of 4H-SiC after ion implantation activation, and can alleviate the vertical stacking mismatch effect of conventional epitaxial 2H III-Nitride of beveled 4H SiC, thereby realizing direct epitaxy of higher-quality GaN HEMT heterostructures. The graphitization process of SiC wafer surface is simple, which can be realized by various machines in compound semiconductor Fab, has good processing compatibility, low difficulty, and has the advantages of stable structure and high reliability, meets mass production requirements, and has good market application prospects.

[0059] The method for preparing an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer provided by an embodiment of the present invention can be performed by growing a buffer layer and an n-SiC epitaxial layer from bottom to top on an obliquely cut n+SiC substrate to manufacture a SiC epitaxial wafer, treating the surface of the SiC epitaxial wafer to form a P-well and n+SiC contact region, manufacturing a SiC JFET structure, treating the surface of the SiC JFET structure to form epitaxial graphene, epitaxially growing a III-nitride heterostructure on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer, if the epitaxial growth does not include a P-GaN layer, then the SiC JFET and MIS-recessed gate HEMT HyFET devices are manufactured by taping out a SiC / GaN hybrid epitaxial wafer that does not include a P-GaN cap layer, and if the epitaxial growth includes an epitaxial P-GaN layer, then the SiC JFET and P-GaN HEMT HyFET devices are manufactured by taping out a SiC / GaN hybrid epitaxial wafer that includes a P-GaN cap layer. In this way, the surface of the GaN HEMT epitaxial layer is prevented from being too rough, thereby improving the material mobility and square resistance quality.

[0060] Example 2

[0061] Corresponding to the above method embodiment, the embodiment of the present invention provides a device for preparing a high-voltage device of epitaxial GaN HEMT on a SiC JFET wafer, Figure 3 A schematic diagram of a structure of a device for preparing an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the preparation device of the epitaxial GaN HEMT high voltage device on the SiC JFET wafer may include:

[0062] The SiC epitaxial wafer manufacturing module 301 is used to grow a buffer layer and an n-SiC epitaxial layer from bottom to top on an obliquely cut n+SiC substrate to manufacture a SiC epitaxial wafer.

[0063] The contact region forming module 302 is used to form a contact region between P-well and n+SiC on the surface of the SiC epitaxial wafer to manufacture a SiC JFET structure.

[0064] The epitaxial graphene forming module 303 is used to process the surface of the SiC JFET structure to form epitaxial graphene.

[0065] The epitaxial growth module 304 is used to perform epitaxial growth of a III-nitride heterostructure on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer.

[0066] The first tape-out module 305 is used to tape-out SiC JFET and MIS-recess gate HEMT HyFET devices by using a SiC / GaN hybrid epitaxial wafer that does not include a P-GaN cap layer if the epitaxial growth does not include a P-GaN layer.

[0067] The second wafer production module 306 is used to produce SiC JFET and P-GaN HEMT HyFET devices by using a SiC / GaN hybrid epitaxial wafer including a P-GaN cap layer if the epitaxial growth includes an epitaxial P-GaN layer.

[0068] The device for preparing an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer provided in an embodiment of the present invention can grow a buffer layer and an n-SiC epitaxial layer from bottom to top on an obliquely cut n+SiC substrate to manufacture a SiC epitaxial wafer, perform surface treatment on the SiC epitaxial wafer to form a P-well and n+SiC contact region, manufacture a SiC JFET structure, treat the surface of the SiC JFET structure to form epitaxial graphene, perform epitaxial growth of a III-nitride heterostructure on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer, if the epitaxial growth does not include a P-GaN layer, SiC JFET and MIS-recess gate HEMT HyFET devices are manufactured by tape-out of a SiC / GaN hybrid epitaxial wafer that does not include a P-GaN cap layer, and if the epitaxial growth includes an epitaxial P-GaN layer, SiC JFET and P-GaN HEMT HyFET devices are manufactured by tape-out of a SiC / GaN hybrid epitaxial wafer that includes a P-GaN cap layer. In this way, the surface of the GaN HEMT epitaxial layer is prevented from being too rough, thereby improving the material mobility and square resistance quality.

[0069] In some embodiments, the contact region forming module is also used to form the contact regions of P-well and n+SiC on the surface of the SiC epitaxial wafer by using masking process, ion implantation and activation process.

[0070] In some embodiments, the material of the mask layer used for ion implantation is one of photoresist, silicon oxide, silicon nitride and other amorphous material hard masks, and the thickness range of the mask layer material is [0.5, 5] microns; after P-type ion and N-type ion implantation in the contact area, the mask layer is etched and removed, and the etching depth range of the SiC outer layer under the mask layer is [0, 200] nanometers.

[0071] In some embodiments, the epitaxial graphene formation module is also used to form an epitaxial graphene single crystal film on the surface of the SiC JFET structure in a preset manner; the preset manner is one of high temperature heat treatment technology, molecular beam epitaxy technology and carbon source introduction chemical vapor deposition technology.

[0072] In some embodiments, the high temperature heat treatment technology includes one of HTCVD, MOCVD and high temperature heat treatment in an activated furnace tube in Ar gas pressure, the Ar gas pressure range is [1, 2000] torr, and the treatment temperature range of the high temperature heat treatment is [900-1700] degrees Celsius; molecular beam epitaxy technology is a heat treatment under high vacuum conditions, and the corresponding temperature range is [800, 1350] degrees Celsius.

[0073] In some embodiments, the epitaxial growth module is also used to sequentially epitaxially grow a III-Nitride starting layer, a III-Nitrid buffer layer, a III-Nitride channel layer and a III-Nitride barrier layer on the surface of the epitaxial graphene to prepare a SiC / GaN hybrid epitaxial wafer.

[0074] In some embodiments, the epitaxial growth module is also used to sequentially epitaxially grow a III-Nitride starting layer, a III-Nitrid buffer layer, a III-Nitride channel layer, a III-Nitride barrier layer and a P-GaN layer on the surface of the epitaxial graphene to prepare a SiC / GaN hybrid epitaxial wafer.

[0075] In some embodiments, the III-Nitride starting layer is one of AlN, AlGaN and GaN, and the thickness range of the III-Nitride starting layer is [0, 500] nanometers; the III-Nitride channel layer is one of GaN, InGaN, and AlGaN with a low Al component, and the thickness range of the III-Nitride channel layer is [20, 800] nanometers; the III-Nitride barrier layer is one of GaN, AlGaN and AlN, and the thickness range of the III-Nitride barrier layer is [0, 40] nanometers; the thickness range of the P-GaN layer is [50, 150] nanometers.

[0076] In some embodiments, the second wafer production module obtains SiC JFET and P-GaN HEMT HyFET devices through a SiC / GaN hybrid epitaxial wafer including a P-GaN cap layer through process production; the process production includes: surface passivation, photolithography, III-Nitride TSV etching, TSV bottom side graphene insulation treatment, metal deposition, alloying annealing and electrode opening interconnection.

[0077] In some embodiments, the substrate is 4H-SiC or 6H-SiC, a substrate material with a bevel of 4° or 8°; the n-SiC epitaxial layer includes a SiC starting buffer layer, and the thickness range of the SiC starting buffer layer is [0.2, 3] microns; the thickness range of the n-SiC epitaxial layer is [8, 40] microns.

[0078] The device provided in the embodiment of the present invention has the same implementation principle and technical effects as those of the aforementioned method embodiment. For the sake of brief description, for matters not mentioned in the device embodiment, reference may be made to the corresponding contents in the aforementioned method embodiment.

[0079] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A method for preparing a high-voltage GaN HEMT device epitaxially on a SiC JFET wafer, characterized in that: The method comprises: Growing a buffer layer and an n-SiC epitaxial layer from bottom to top on an obliquely cut n+SiC substrate to produce a SiC epitaxial wafer; the substrate is 4H-SiC or 6H-SiC; Treating the surface of the SiC epitaxial wafer to form a contact region between P-well and n+SiC, and fabricating a SiC JFET structure; Treating the surface of the SiC JFET structure to form epitaxial graphene; Epitaxially growing a III-nitride heterostructure on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer; If the epitaxial growth does not include a P-GaN layer, then SiC JFET and MIS-recessed gate HEMT HyFET devices are fabricated by tape-out of the SiC / GaN hybrid epitaxial wafer that does not include a P-GaN cap layer; If the epitaxial growth includes an epitaxial P-GaN layer, SiC JFET and P-GaN HEMT HyFET devices are fabricated by tape-out of the SiC / GaN hybrid epitaxial wafer including the P-GaN cap layer; The surface of the SiC JFET structure is processed to form epitaxial graphene, comprising: Forming an epitaxial graphene single crystal thin film on the surface of the SiC JFET structure by a preset method; the preset method is one of a high temperature heat treatment technology, a molecular beam epitaxy technology and a carbon source introduction chemical vapor deposition technology; After the epitaxial graphene single crystal film is formed, the surface of the epitaxial graphene single crystal film is treated to form graphene oxide; wherein the treatment includes a surface treatment process and a plasma treatment.

2. The method according to claim 1, characterized in that The step of forming a contact area between P-well and n+SiC by surface treatment on the SiC epitaxial wafer comprises: The contact area between P-well and n+SiC is manufactured on the surface of the SiC epitaxial wafer by using mask process, ion implantation and activation process.

3. The method according to claim 2, characterized in that The material of the mask layer used for ion implantation is one of photoresist, silicon oxide, silicon nitride and other amorphous material hard masks, and the thickness range of the material of the mask layer is [0.5, 5] microns; after P-type ion and N-type ion implantation in the contact area, the mask layer is etched and removed, and the etching depth range of the SiC outer layer under the mask layer is [0, 200] nanometers.

4. The method according to claim 1, characterized in that: The high-temperature heat treatment technology includes one of HTCVD, MOCVD and high-temperature heat treatment in an activated furnace tube in Ar gas pressure, the Ar gas pressure range is [1, 2000] torr, and the treatment temperature range of the high-temperature heat treatment is [900, 1700] degrees Celsius; the molecular beam epitaxy technology is a heat treatment under high vacuum conditions, and the corresponding temperature range is [800, 1350] degrees Celsius.

5. The method according to claim 1, characterized in that When the epitaxial growth does not include an epitaxial P-GaN layer, epitaxial growth of a III-nitride heterostructure is performed on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer, comprising: Sequentially epitaxially growing a III-Nitride starting layer, a III-Nitrid buffer layer, a III-Nitride channel layer and a III-Nitride barrier layer on the surface of the epitaxial graphene to prepare the SiC / GaN hybrid epitaxial wafer; When the epitaxial growth includes an epitaxial P-GaN layer, epitaxial growth of a III-nitride heterostructure is performed on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer, comprising: A III-Nitride starting layer, a III-Nitrid buffer layer, a III-Nitride channel layer, a III-Nitride barrier layer and a P-GaN layer are sequentially epitaxially grown on the surface of the epitaxial graphene to prepare the SiC / GaN hybrid epitaxial wafer.

6. The method according to claim 5, characterized in that The III-Nitride starting layer is one of AlN, AlGaN and GaN, and the thickness range of the III-Nitride starting layer is [0, 500] nanometers; the III-Nitride channel layer is one of GaN, InGaN, and AlGaN with a low Al component, and the thickness range of the III-Nitride channel layer is [20, 800] nanometers; the III-Nitride barrier layer is one of GaN, AlGaN and AlN, and the thickness range of the III-Nitride barrier layer is [0, 40] nanometers; the thickness range of the P-GaN layer is [50, 150] nanometers.

7. The method according to claim 1, characterized in that The method of manufacturing SiC JFET and P-GaN HEMT HyFET devices by tape-out of the SiC / GaN hybrid epitaxial wafer including the P-GaN cap layer comprises: The SiC / GaN hybrid epitaxial wafer including the P-GaN cap layer is processed to obtain SiC JFET and P-GaN HEMT HyFET devices; The process includes: surface passivation, photolithography, III-Nitride TSV etching, TSV bottom side graphene insulation treatment, metal deposition, alloying annealing and electrode opening interconnection.

8. The method according to any one of claims 1 to 7, characterized in that: The substrate is 4H-SiC or 6H-SiC, a substrate material with a bevel of 4° or 8°; the n-SiC epitaxial layer includes a SiC starting buffer layer, and the thickness range of the SiC starting buffer layer is [0.2, 3] microns; the thickness range of the n-SiC epitaxial layer is [8, 40] microns.

9. A device for preparing a high-voltage GaN HEMT device epitaxially on a SiC JFET wafer, characterized in that: A method for fabricating an epitaxial GaN HEMT high-voltage device on a SiC JFET wafer according to any one of claims 1 to 8, the device comprising: SiC epitaxial wafer production module, used to grow buffer layers and n-SiC epitaxial layers from the oblique n+SiC substrate from bottom to top to produce SiC epitaxial wafers; A contact region forming module, used for forming a contact region between P-well and n+SiC on the surface of the SiC epitaxial wafer to manufacture a SiC JFET structure; An epitaxial graphene forming module, used for processing the surface of the SiC JFET structure to form epitaxial graphene; An epitaxial growth module, used for performing epitaxial growth of a III-nitride heterostructure on the surface of the epitaxial graphene to obtain a SiC / GaN hybrid epitaxial wafer; A first tape-out manufacturing module, for, if the epitaxial growth does not include a P-GaN layer, tape-out the SiC / GaN hybrid epitaxial wafer without a P-GaN cap layer to manufacture SiC JFET and MIS-recessed gate HEMT HyFET devices; The second wafer production module is used for producing SiC JFET and P-GaN HEMT HyFET devices by taping out the SiC / GaN hybrid epitaxial wafer including a P-GaN cap layer if the epitaxial growth includes an epitaxial P-GaN layer.

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