Semiconductor device

Abstract

The semiconductor device includes a vertical field-effect transistor having a low-concentration impurity layer (33), a body region (18), a gate trench (17) extending in a first direction parallel to the upper surface of the low-concentration impurity layer (33), a gate insulating film (16) formed inside the gate trench (17), and a gate conductor (15) formed on the gate insulating film (16). The body region (18) includes a first body portion (181) that includes an active region and has a certain depth, and a second body portion (182) that is adjacent to the first body portion (181) and has a certain length in a second direction orthogonal to the first direction in the upper surface of the low-concentration impurity layer (33) and has a certain interval at a position shallower than the depth of the first body portion (181). The second body portion (182) has a portion where regions with relatively high impurity concentration and relatively low impurity concentration appear alternately and periodically along the first direction in a cross-section of a plane perpendicular to the second direction.

Description

[0001] This application is a divisional application of the Chinese patent application with an application date of 2023 / 01 / 18, application number 202380011171.1, and invention name “Semiconductor Device”. Technical Field

[0002] The present disclosure relates to a semiconductor device, and more particularly to a chip size package type semiconductor device. Background Art

[0003] It is required that the breakdown voltage of a vertical field effect transistor be stabilized.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2008-10723 Summary of the invention

[0007] Problems to be solved by the invention

[0008] The maximum voltage that can be applied between the drain and the source to ensure safe driving of the vertical field effect transistor is described in the product specification sheet and is referred to as the specification maximum voltage (rated voltage).

[0009] If a voltage higher than the maximum voltage of the specification is applied, impact ionization occurs somewhere in the structure of the vertical field effect transistor. The applied voltage at this time is the withstand voltage of the vertical field effect transistor. The vertical field effect transistor must be designed so that the withstand voltage is higher than the maximum voltage of the specification.

[0010] In the case of a vertical field effect transistor having a gate trench, the top of the gate trench is a portion that is susceptible to impact ionization in response to voltage application, and the breakdown voltage of the vertical field effect transistor may vary due to the manufacturing finish of the gate trench.

[0011] Patent Document 1 discloses the structure of a vertical field effect transistor and shows an example of the structure of an end portion of a body region.

[0012] Means used to solve problems

[0013] In order to solve the above-mentioned problems, the semiconductor device disclosed in the present invention is a semiconductor device of chip size package type that can be mounted face-down, characterized in that it has a vertical field effect transistor, the vertical field effect transistor comprising: a semiconductor substrate of the first conductivity type, containing impurities of the first conductivity type; a low-concentration impurity layer of the first conductivity type, formed on the semiconductor substrate in contact therewith, containing impurities of the first conductivity type at a concentration lower than the concentration of impurities of the first conductivity type of the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type, formed in the low-concentration impurity layer; a source region of the first conductivity type, formed in the body region; a gate trench, formed from the upper surface of the low-concentration impurity layer to a depth that penetrates the body region and reaches a part of the low-concentration impurity layer, and extending in a first direction parallel to the upper surface of the low-concentration impurity layer; a gate insulating film, formed inside the gate trench; and a gate conductor, formed on the upper surface of the gate trench on the gate insulating film; assuming that the direction of the upper surface of the low-concentration impurity layer that is orthogonal to the first direction is a second direction, and assuming that the direction that is orthogonal to both the first direction and the second direction is a third direction, the body region includes: a first body portion, which includes an active region forming a conduction channel in a plan view of the low-concentration impurity layer, and has a constant depth from the upper surface of the low-concentration impurity layer; and a second body portion, which, in the plan view, is adjacent to the first body portion on the side of a peripheral region surrounding the active region, and has a limited length in the second direction and has a certain depth from the upper surface of the low-concentration impurity layer at a position shallower than the depth of the first body portion, and the second body portion, in a cross-sectional view of a plane including the first direction and the third direction, has a portion in which regions with a relatively high concentration of the second conductive type impurities and regions with a relatively low concentration of the second conductive type impurities appear alternately and periodically along the first direction.

[0014] The semiconductor device disclosed herein may be configured such that, in a cross-sectional view taken along a plane including the first direction and the third direction, the second body portion has shallow and deep portions that appear alternately and periodically along the first direction.

[0015] The semiconductor device disclosed in the present invention may also be such that, in a cross-sectional view taken along a plane including the second direction and the third direction, the depth of the first body portion is denoted as D1 in μm, the depth of the second body portion in an interval in which the depth of the second body portion is constant and which is closest to the first body portion is denoted as D2 in μm, a point on the lower surface of the body region where the depth D1 of the first body portion reaches an end and is connected to the lower surface of the second body portion is denoted as a first connection point, and a point on the lower surface of the second body portion which is farthest from the first body portion and where the depth D2 reaches an end is denoted as a second connection point, then, in a cross-sectional view taken along a plane including the second direction and the third direction, the depth of the second body portion in the second direction is denoted as D2. The second body portion decreases monotonically, and the second body portion has: a first interval, which is an interval in which the lower surface of the second body portion changes from the first connection point to the depth of the second body portion to D2; and a second interval, which is an interval in which the lower surface of the second body portion changes from the second connection point to the body region to a point where the end is reached on the upper surface of the low-concentration impurity layer. When the length from the first connection point to the point where the body region ends on the upper surface of the low-concentration impurity layer in the second direction is L1 in μm, and when the length from the second connection point to the point where the body region ends on the upper surface of the low-concentration impurity layer in the second direction is L2 in μm, the relationship D2>D1×L2 / L1 exists.

[0016] The semiconductor device disclosed in the present invention may also be that, in a cross-section of a plane including the first direction and the third direction, the depth of the shallow part of the second body portion appearing alternately and periodically in the first direction is d21 in μm, the depth of the deep part is d22 in μm, and the period is a in μm, then in the first direction, the closest interval of the depth of the second body portion being d22-(d22-d21) / 4 is approximately equal to a×D2 / D1.

[0017] According to the above structure, when a voltage higher than the maximum voltage of the specification is applied between the drain and source of the vertical field effect transistor, the deviation of the withstand voltage caused by the completion state of the gate trench can be avoided, and a sufficient margin can be ensured for the maximum voltage of the specification. In addition, the terminal structure of the body region can be controlled relatively easily and freely by a single impurity injection, so the manufacturing cost of the semiconductor device can be reduced.

[0018] The semiconductor device of the present disclosure may also be a chip - scale package - type semiconductor device capable of being mounted face - down, and includes a vertical field - effect transistor. The vertical field - effect transistor has: a semiconductor substrate of a first conductivity type, containing impurities of the first conductivity type; a low - concentration impurity layer of the first conductivity type, formed in contact therewith on the semiconductor substrate, containing impurities of the first conductivity type with a lower concentration than the impurity concentration of the first conductivity type in the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type, formed in the low - concentration impurity layer; a source region of the first conductivity type, formed in the body region; a source electrode, electrically connected to the body region and the source region; a gate trench, formed from the upper surface of the low - concentration impurity layer to a depth that penetrates the body region and reaches a part of the low - concentration impurity layer, extending in a first direction parallel to the upper surface of the low - concentration impurity layer; a gate insulating film, formed inside the gate trench; and a gate conductor, formed on the gate insulating film inside the gate trench. When the direction orthogonal to the first direction in the upper surface of the low - concentration impurity layer is defined as the second direction, and the direction orthogonal to both the first direction and the second direction is defined as the third direction, the body region includes: a first body part, in a plan view of the low - concentration impurity layer, including an active region where a conduction channel is formed, and the depth from the upper surface of the low - concentration impurity layer is fixed at D1 in μm; and a second body part, in the plan view, adjacent to the first body part on the outer - peripheral - region side surrounding the active region, having an interval with a depth from the upper surface of the low - concentration impurity layer fixed at D2 in μm, which is shallower than the depth of the first body part and has a finite length in the second direction. When the depth from the upper surface of the low - concentration impurity layer to the lower surface of the source region is Ds in μm, D2 < Ds < D1. In the interval from the upper surface of the low - concentration impurity layer to the depth D2, the impurity concentration distribution of the second conductivity type in the third direction of the first body part and the impurity concentration distribution of the second conductivity type in the third direction of the second body part are consistent in the range where the impurity concentration of the second conductivity type is 1E19 cm －3 or more.

[0019] The semiconductor device of the present disclosure may also be such that, in a cross - section of the plane including the second direction and the third direction, the oxide film in direct contact with the low - concentration impurity layer is disposed on the outer - peripheral - region side of the semiconductor device with respect to the boundary between the first body part and the second body part in the second direction.

[0020] The semiconductor device disclosed in the present invention may also be such that, in a cross-sectional view of a plane including the second direction and the third direction, an interval in which the depth of the second body portion is fixed at D2 is an interval closest to the first body portion among the intervals in which the depth of the second body portion is fixed, a point in the lower surface of the body region where the depth D1 of the first body portion reaches an end and is connected to the lower surface of the second body portion is set as a first connection point, and a point in the lower surface of the second body portion where the depth D2 reaches an end and is farthest from the first body portion is set as a second connection point, in a cross-sectional view of a plane including the second direction and the third direction In a cross-sectional view of a plane along the third direction, the depth of the second body portion decreases monotonically in the second direction; the second body portion comprises: a first interval, which is an interval in which the depth of the lower surface of the second body portion changes from the first connection point to the second body portion toward D2; and a second interval, which is an interval in which the lower surface of the second body portion changes from the second connection point to the body region toward a point where the end is reached at the upper surface of the low-concentration impurity layer, and in a cross-sectional view of a plane including the second direction and the third direction, the second interval of the second body portion is located directly below the oxide film.

[0021] The semiconductor device disclosed in the present invention may also be such that, when the length from the first connection point in the second direction to the point where the body region reaches the end at the upper surface of the low-concentration impurity layer is L1 in μm, the maximum voltage BVDSS between the drain and the source of the semiconductor device in V is BVDSS ≤ 26.4 × (L1) 2 -36.4×L1+31.5.

[0022] According to the above-mentioned structure, the contact resistance between the body region and the source electrode can be reduced, and when a voltage higher than the maximum voltage of the specification is applied between the drain and the source of the vertical field effect transistor, the deviation in the withstand voltage caused by the completion condition of the gate trench can be avoided, and sufficient margin can be ensured for the maximum voltage of the specification.

[0023] The semiconductor device disclosed herein may also be such that, in a cross-sectional view of a plane including the second direction and the third direction, a gate wiring structure having the same potential as the gate conductor in the second direction is provided only on the peripheral region side of the semiconductor device that is closer to the second body portion.

[0024] According to the above-described structure, the end portion of the body region is less susceptible to the influence of the electric field from the gate wiring, so that the breakdown voltage of the vertical field effect transistor can be stabilized within a target range.

[0025] The semiconductor device disclosed in the present invention may also be that, in the third direction, the upper surface of the gate conductor inside the gate trench is higher than the interface between the source region and the body region, and the sum of the length from the upper surface of the gate conductor to the interface between the source region and the body region and the length from the interface between the body region and the low-concentration impurity layer to the top of the gate trench is constant within the surface of the semiconductor device.

[0026] According to the above-described structure, it is possible to suppress manufacturing variations in the threshold voltage Vth [V] of the vertical field effect transistor, and thus it is possible to improve the manufacturing yield caused by the Vth variations.

[0027] Effects of the Invention

[0028] An object of the present disclosure is to provide a semiconductor device capable of stabilizing the breakdown voltage of a vertical field effect transistor and exhibiting a breakdown voltage having a sufficient margin with respect to a specified maximum voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment.

[0030] Figure 2A It is a schematic plan view showing an example of the structure of the semiconductor device according to the first embodiment.

[0031] Figure 2B This is a schematic cross-sectional view showing a main current flowing in the semiconductor device according to the first embodiment.

[0032] Figure 3A It is a plan view schematically showing a rough unit structure of the first transistor according to the first embodiment.

[0033] Figure 3B This is a schematic three-dimensional diagram of a rough unit structure of the first transistor in the first embodiment.

[0034] Figure 4 It is a schematic plan view showing an example of the structure of the semiconductor device according to the first embodiment.

[0035] Figure 5A This is a schematic cross-sectional view showing an example of the structure of the periphery of the semiconductor device in the semiconductor device of the first embodiment.

[0036] Figure 5B Yes Figure 5A A schematic cross-sectional view of a portion of the enlarged portion.

[0037] Figure 5C is for Figure 5A The structure of the periphery of the semiconductor device shown is a schematic cross-sectional view with the result of simulation of impact ionization image superimposed thereon.

[0038] Figure 6 This is a graph showing the relationship between the breakdown voltage of each structure and the difference in depth between the first body portion and the second body portion when the difference in depth between the first body portion and the second body portion of the semiconductor device according to the first embodiment is changed.

[0039] Figure 7 It is a schematic cross-sectional view showing a state of one step in the manufacturing process of the semiconductor device according to the first embodiment.

[0040] Figure 8 It is a schematic cross-sectional view showing a state of one step in the manufacturing process of the semiconductor device according to the first embodiment.

[0041] Fig. 9 It is a schematic cross-sectional view showing a state of one step in the manufacturing process of the semiconductor device according to the first embodiment.

[0042] Fig. 10A It is a schematic cross-sectional view showing the result of simulation of the structure of the semiconductor device according to the first embodiment.

[0043] Fig. 10B This is a graph showing the results of a simulation of the doping concentration of the semiconductor device according to the first embodiment.

[0044] Fig. 10C is a graph showing the results of simulating the doping concentration of the semiconductor device of the first embodiment. Fig. 10B A diagram showing an enlarged portion of a portion.

[0045] Fig. 10D Yes Fig. 10A A schematic cross-sectional view showing a portion of the device with emphasis.

[0046] Fig.11A This is a schematic cross-sectional view showing an example of the structure of the periphery of the semiconductor device in the semiconductor device of the second embodiment.

[0047] Fig. 11B Yes Fig.11A A schematic cross-sectional view of a portion of the enlarged portion.

[0048] Fig. 11C Yes Fig.11A The structure of the periphery of the semiconductor device shown is a schematic cross-sectional view with the result of simulation of impact ionization image superimposed thereon.

[0049] Fig.11D This is a schematic cross-sectional view showing an example of the peripheral structure of the semiconductor device of the semiconductor device according to the second embodiment.

[0050] Fig.12These are the results of simulations of the second conductivity type impurity distribution in the first body portion and the second body portion of the semiconductor device according to the second embodiment.

[0051] Fig.13A It is the simulation result of the impact ionization image of each structure when the length of the second body part of the semiconductor device of Embodiment 2 is changed.

[0052] Fig. 13B This is a graph showing the relationship between VDS and IDS of each structure when the length of the second body portion of the semiconductor device according to the second embodiment is changed.

[0053] Fig. 13C This is a graph showing the relationship between the breakdown voltage of each structure and the length of the second body portion when the length of the second body portion of the semiconductor device according to the second embodiment is changed.

[0054] Fig.14 It is a schematic cross-sectional view showing an example of the structure of the periphery of a semiconductor device in a semiconductor device of a comparative example.

[0055] Fig.15A1 It is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a comparative example.

[0056] Fig.15A2 It is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a comparative example.

[0057] Fig.15A3 It is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a comparative example.

[0058] Fig.15A4 It is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a comparative example.

[0059] Figure 15A5 It is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a comparative example.

[0060] Fig.15A6 It is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a comparative example.

[0061] Fig.15B1 It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment.

[0062] Fig.15B2 It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment.

[0063] Figure 15B3 It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment.

[0064] Figure 15B4It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment.

[0065] Figure 15B5 It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment.

[0066] Fig.16A It is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to a comparative example.

[0067] Fig. 16B It is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment. DETAILED DESCRIPTION

[0068] [1. Structure of semiconductor device]

[0069] Hereinafter, before the embodiments of the present disclosure described later, matters common to each embodiment will be described.

[0070] The vertical field effect transistor disclosed in the present invention is described by taking a dual structure as an example, but the dual structure is not necessarily required, and may be a vertical field effect transistor with a single structure or a vertical field effect transistor with a triple structure or more.

[0071] Figure 1 It is a cross-sectional view showing an example of the structure of a semiconductor device. Figure 2A This is a plan view, and the size, shape, and arrangement of electrode pads of the semiconductor device are only examples. Figure 2B This is a cross-sectional view schematically showing a main current flowing in a semiconductor device. Figure 1 and Figure 2B yes Figure 2A I-I section.

[0072] like Figure 1 and Figure 2A As shown, the semiconductor device 1 includes a semiconductor layer 40, a metal layer 30, a first vertical field effect transistor 10 (hereinafter also referred to as "transistor 10") formed in a first region A1 in the semiconductor layer 40, and a second vertical field effect transistor 20 (hereinafter also referred to as "transistor 20") formed in a second region A2 in the semiconductor layer 40. Figure 2A As shown in FIG. 1 , the first region A1 and the second region A2 are adjacent to each other in a plan view of the semiconductor layer 40 , dividing the semiconductor device 1 into two equal parts in terms of area. Figure 2A In FIG. 1 , a virtual boundary line 90 between the first area A1 and the second area A2 is indicated by a dotted line.

[0073] The semiconductor layer 40 is formed by stacking a semiconductor substrate 32 and a low-concentration impurity layer 33. The semiconductor substrate 32 is arranged on the back side of the semiconductor layer 40, and is composed of silicon of the first conductivity type containing impurities of the first conductivity type. The low-concentration impurity layer 33 is arranged on the surface side of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, contains impurities of the first conductivity type at a concentration lower than the concentration of the impurities of the first conductivity type of the semiconductor substrate 32, and is of the first conductivity type. The low-concentration impurity layer 33 can be formed on the semiconductor substrate 32 by epitaxial growth, for example. In addition, the low-concentration impurity layer 33 is also a drift layer of the transistor 10 and the transistor 20, and is sometimes referred to as a drift layer in this specification.

[0074] The metal layer 30 is formed in contact with the back side of the semiconductor layer 40 and is composed of silver (Ag) or copper (Cu). In addition, the metal layer 30 may contain a trace amount of elements other than metals mixed as impurities in the manufacturing process of the metal material. In addition, the metal layer 30 may be formed on the entire surface of the back side of the semiconductor layer 40, or may not be formed on the entire surface.

[0075] like Figure 1 and Figure 2A As shown, a first body region 18 including impurities of a second conductivity type different from the first conductivity type is formed in the first region A1 of the low concentration impurity layer 33. In the first body region 18, a first source region 14 including impurities of the first conductivity type, a first gate conductor 15, and a first gate insulating film 16 are formed.

[0076] The first gate insulating film 16 is formed inside a plurality of first gate trenches 17 formed to a depth penetrating the first body region 18 from the upper surface of the semiconductor layer 40 to a portion of the low-concentration impurity layer 33 , and the first gate conductor 15 is formed on the first gate insulating film 16 .

[0077] The first source electrode 11 includes a portion 12 and a portion 13 , and the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13 . The first gate conductor 15 is an embedded gate electrode embedded in the semiconductor layer 40 , and is electrically connected to the first gate electrode pad 119 .

[0078] The portion 12 of the first source electrode 11 is a layer to be joined to the solder during reflow in face-down mounting, and can be made of a metal material including one or more of nickel, titanium, tungsten, and palladium as a non-limiting example. The surface of the portion 12 can be plated with gold or the like.

[0079] The portion 13 of the first source electrode 11 is a layer connecting the portion 12 and the semiconductor layer 40 , and may be made of a metal material including one or more of aluminum, copper, gold, and silver as a non-limiting example.

[0080] A second body region 28 containing second conductivity type impurities is formed in the second region A2 of the low concentration impurity layer 33. In the second body region 28, a second source region 24 containing first conductivity type impurities, a second gate conductor 25, and a second gate insulating film 26 are formed.

[0081] The second gate insulating film 26 is formed inside a plurality of second gate trenches 27 formed to a depth penetrating the second body region 28 from the upper surface of the semiconductor layer 40 to reach a portion of the low-concentration impurity layer 33 , and the second gate conductor 25 is formed on the second gate insulating film 26 .

[0082] The second source electrode 21 includes a portion 22 and a portion 23 , and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23 . The second gate conductor 25 is an embedded gate electrode embedded in the semiconductor layer 40 , and is electrically connected to the second gate electrode pad 129 .

[0083] The portion 22 of the second source electrode 21 is a layer to be joined to the solder during reflow in face-down mounting, and can be made of a metal material including one or more of nickel, titanium, tungsten, and palladium as a non-limiting example. The surface of the portion 22 can be plated with gold or the like.

[0084] The portion 23 of the second source electrode 21 is a layer connecting the portion 22 and the semiconductor layer 40 , and may be made of a metal material including one or more of aluminum, copper, gold, and silver as a non-limiting example.

[0085] With the above-described structures of the transistors 10 and 20, the semiconductor substrate 32 functions as a common drain region shared by the first drain region of the transistor 10 and the second drain region of the transistor 20. A portion of the low-concentration impurity layer 33 on the side in contact with the semiconductor substrate 32 may also function as a common drain region. In addition, the metal layer 30 functions as a common drain electrode shared by the drain electrode of the transistor 10 and the drain electrode of the transistor 20.

[0086] like Figure 1As shown, the first body region 18 is covered by an interlayer insulating layer 34 having an opening, and a portion 13 of the first source electrode 11 connected to the first source region 14 via the opening of the interlayer insulating layer 34 is provided. The interlayer insulating layer 34 and the portion 13 of the first source electrode 11 are covered by a passivation layer 35 having an opening, and a portion 12 connected to the portion 13 of the first source electrode 11 via the opening of the passivation layer 35 is provided.

[0087] The second body region 28 is covered by an interlayer insulating layer 34 having an opening, and a portion 23 of the second source electrode 21 connected to the second source region 24 via the opening of the interlayer insulating layer 34 is provided. The interlayer insulating layer 34 and the portion 23 of the second source electrode 21 are covered by a passivation layer 35 having an opening, and a portion 22 connected to the portion 23 of the second source electrode 21 via the opening of the passivation layer 35 is provided.

[0088] Therefore, the plurality of first source electrode pads 116 and the plurality of second source electrode pads 126 refer to regions where the first source electrode 11 and the second source electrode 21 are partially exposed on the surface of the semiconductor device 1, so-called terminal portions. Similarly, the one or more first gate electrode pads 119 and the one or more second gate electrode pads 129 refer to the first gate electrode 19 (at Figure 1 , Figure 2A , Figure 2B ) and the second gate electrode 29 (not shown in the figure) Figure 1 , Figure 2A , Figure 2B An area partially exposed on the surface of the semiconductor device 1 (not shown), a so-called terminal portion.

[0089] In the semiconductor device 1, for example, the first conductivity type may be set to N type, the second conductivity type may be set to P type, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low-concentration impurity layer 33 may be N type semiconductors, and the first body region 18 and the second body region 28 may be P type semiconductors.

[0090] In addition, in the semiconductor device 1, for example, the first conductivity type may be set to P type, the second conductivity type may be set to N type, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low-concentration impurity layer 33 may be P type semiconductors, and the first body region 18 and the second body region 28 may be N type semiconductors.

[0091] In the following description, the on-operation of the semiconductor device 1 is described assuming that the transistor 10 and the transistor 20 are so-called N-channel transistors in which the first conductivity type is N-type and the second conductivity type is P-type.

[0092] Note that the transistor 10 and the transistor 20 are described here on the premise that they have symmetry and have no difference in function, characteristics, structure, etc. Figure 1 , Figure 2A , Figure 2B Although the description has been made based on the premise of symmetry, symmetry is not necessarily a necessary condition for the dual-structure vertical field effect transistor of the chip size package type of the present invention.

[0093] The single-structure vertical field effect transistor can be roughly considered to be a structure formed by only one side (transistor 10) of the double-structure vertical field effect transistor. However, in the chip-scale package type, a drain electrode pad needs to be provided on the surface side of the semiconductor layer 40 having the source electrode pad 116 and the gate electrode pad 119. In this case, a drain lead structure electrically connected to the drain layer provided on the back side of the semiconductor layer 40 needs to be formed in advance from the surface side of the semiconductor layer 40.

[0094] [2. Operation of vertical field effect transistor]

[0095] Figure 3A and Figure 3B The plan view and the perspective view are respectively a rough unit structure of the transistor 10 (or the transistor 20) repeatedly formed in the X direction and the Y direction of the semiconductor device 1. Figure 3A and Figure 3B In the figure, the semiconductor substrate 32, the first source electrode 11 (or the second source electrode 21), the passivation layer 35, and the interlayer insulating layer 34 are not shown for easy understanding.

[0096] The Y direction is parallel to the upper surface of the semiconductor layer 40 (low-concentration impurity layer 33) and is a direction in which the first gate trench 17 and the second gate trench 27 extend. In addition, the X direction is a direction parallel to the upper surface of the semiconductor layer 40 (low-concentration impurity layer 33) and orthogonal to the Y direction, and the Z direction is a direction orthogonal to both the X direction and the Y direction and indicates the height direction of the semiconductor device 1. In the present disclosure, the Y direction is sometimes expressed as the first direction, the X direction is expressed as the second direction, and the Z direction is expressed as the third direction.

[0097] like Figure 3A and Figure 3B As shown, in the transistor 10, a first connection portion 18A electrically connecting the first body region 18 and the first source electrode 11 is provided. The first connection portion 18A is a region of the first body region 18 where the first source region 14 is not formed, and contains the same second conductivity type impurities as the first body region 18. The first source region 14 and the first connection portion 18A are repeatedly arranged alternately and periodically along the Y direction. The same is true for the transistor 20.

[0098] In the semiconductor device 1, when a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21, and a voltage higher than a threshold value is applied to the second gate electrode 29 (second gate conductor 25) with reference to the second source electrode 21, a conduction channel is formed near the second gate insulating film 26 in the second body region 28. As a result, a main current flows through the path of the first source electrode 11-first connecting portion 18A-first body region 18-low-concentration impurity layer 33-semiconductor substrate 32-metal layer 30-semiconductor substrate 32-low-concentration impurity layer 33-conduction channel formed in the second body region 28-second source region 24-second source electrode 21, and the semiconductor device 1 is turned on. In addition, a PN junction (also called a main junction) is formed at the interface between the second body region 28 and the low-concentration impurity layer 33 in this conduction path, and functions as a body diode. Furthermore, since the main current flows through the metal layer 30 , by making the metal layer 30 thicker, the cross-sectional area of ​​the main current path is increased, and the on-resistance of the semiconductor device 1 can be reduced.

[0099] Similarly, in the semiconductor device 1, when a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first source electrode 11, and a voltage higher than a threshold value is applied to the first gate electrode 19 (first gate conductor 15) with reference to the first source electrode 11, a conduction channel is formed near the first gate insulating film 16 in the first body region 18. As a result, a main current flows through the path of the second source electrode 21-second connecting portion 28A-second body region 28-low-concentration impurity layer 33-semiconductor substrate 32-metal layer 30-semiconductor substrate 32-low-concentration impurity layer 33-conductivity channel formed in the first body region 18-first source region 14-first source electrode 11, and the semiconductor device 1 is turned on. In addition, a PN junction (also called a main junction) is formed at the interface between the first body region 18 and the low-concentration impurity layer 33 in this conduction path, and functions as a body diode.

[0100] [3. Active area and peripheral area (end)]

[0101] Figure 4 FIG. 1 is a plan view showing an example of the shapes of the first body region 18 and the second body region 28 and the first active region 112 and the second active region 122 in the plan view of the semiconductor layer 40 (low-concentration impurity layer 33) among the components of the semiconductor device 1. Figure 4 Although not shown in the figure, both the first gate trench 17 and the second gate trench 27 extend in the Y direction.

[0102] The first active region 112 is a minimum range that includes all of the portions where a conduction channel is formed when a voltage above a threshold value is applied to the first gate electrode 19 (first gate conductor 15) of the transistor 10. The portion where the conduction channel is formed is a portion where each of the plurality of first gate trenches 17 is adjacent to the first source region 14. In a plan view of the semiconductor layer 40, the first active region 112 is included in the first body region 18.

[0103] The second active region 122 is a minimum range that includes all of the portions where a conduction channel is formed when a voltage above a threshold value is applied to the second gate electrode 29 (second gate conductor 25) of the transistor 20. The portion where the conduction channel is formed is a portion where each of the plurality of second gate trenches 27 is adjacent to the second source region 24. In a plan view of the semiconductor layer 40, the second active region 122 is included in the second body region 28.

[0104] A region surrounding the first active region 112 in the first region A1 is referred to as a first outer peripheral region, and a region surrounding the second active region 122 in the second region A2 is referred to as a second outer peripheral region.

[0105] In the present disclosure, in the first peripheral region of the semiconductor device 1, the first body region 18 gradually becomes shallower in both the X and Y directions and reaches the end. In addition, in the second peripheral region of the semiconductor device 1, the second body region 28 gradually becomes shallower in both the X and Y directions and reaches the end.

[0106] The following describes the characteristics and effects of the shape of the body region end in each embodiment, and first describes how to identify the lower surface of the first body region 18 or the second body region 28, that is, the main junction 18b. In the present disclosure, the lower surface of the body region and the main junction have the same meaning.

[0107] As an example of a method for identifying the main junction 18b, there is a method in which the semiconductor device 1 is cut to expose the XZ plane or the YZ plane, a certain range in the cross section including the first peripheral region or the second peripheral region is subjected to a staining process and then observed by SEM (Scanning Electron Microscope). The staining process is a method of etching with a chemical solution in which nitric acid, hydrofluoric acid, and acetic acid are mixed in a certain proportion, thereby making the color tone of the semiconductor region containing P-type impurities black and making the interface between the body region and the drift layer clear.

[0108] As another example of a method for identifying the main junction 18b, there is a method in which the semiconductor device 1 is cut to expose the XZ plane or the YZ plane, and a certain range in the cross section including the first peripheral region or the second peripheral region is measured using a scanning capacitance microscopy method (SCM).

[0109] Although it is difficult to measure the impurity concentration of a semiconductor on the observed surface, SCM can measure the conductivity type with high accuracy, so it can measure the conductivity type of a semiconductor in a cross section. In SCM, the difference between N-type and P-type is usually expressed by the capacitance change that depends on the carrier concentration, and numerical data of the signal intensity whose absolute value represents its polarity is obtained for each unit part measured.

[0110] The position of the main junction 18b is neither N-type nor P-type in principle, so it is sufficient to track the position where the numerical data is 0 or near 0. Therefore, if the position in the X direction is plotted on the horizontal axis and the signal strength of the polarity is plotted on the vertical axis, the position where the vertical axis is 0 can be considered to be the position of the main junction 18b.

[0111] In the present disclosure, the main node 18b is sometimes described as being flat, but this does not necessarily mean that a strict flatness is specified, but includes a case where it is considered to be generally flat in average position based on a distribution obtained by SCM or an image obtained by SEM.

[0112] In the following description of each embodiment, emphasis is not placed on the dual structure of the semiconductor device 1, and each component is described without distinction between the first and second components unless otherwise stated. The reference numerals used for the first components are representative.

[0113] (Implementation Method 1)

[0114] [1-1. Shape of the end structure of the body region]

[0115] Figure 5A Schematically shows a portion of the structure of the outer peripheral region in the X direction of the semiconductor device 1 according to the first embodiment (hereinafter sometimes referred to as the end structure or terminal structure). Figure 5B yes Figure 5A , which is a part of an enlarged view of a part of the end structure of the body region 18.

[0116] In addition, Figure 5A and Figure 5B and the following Figure 5C In the figure, the passivation layer 35 and the metal layer 30 are omitted.

[0117] In the case of the dual-type semiconductor device 1, in a plan view, since the first peripheral region surrounds the first active region 112 and the second peripheral region surrounds the second active region 122, a similar structure is also provided on the central side of the semiconductor device 1 (near the boundary line 90 between the transistor 10 and the transistor 20). It can also be understood that, Figure 5A The cross-sectional view shown is Figure 4 The dashed-line frames shown are common views of cross sections viewed from the arrow side.

[0118] like Figure 5A As shown, the body region 18 includes a first body portion 181 and a second body portion 182. The first body portion 181 includes the active region 112 forming the conductive channel, and has a certain depth from the upper surface of the low-concentration impurity layer 33. The second body portion 182 does not include the active region 112, and in the plan view of the low-concentration impurity layer 33, is adjacent to the first body portion 181 on the side of the peripheral region surrounding the active region 112, has a limited length in the X direction, and has a certain depth from the upper surface of the low-concentration impurity layer 33 at a position shallower than the depth of the first body portion 181.

[0119] In the cross-section view of the plane (XZ plane) including the X direction and the Z direction, let the depth of the first body portion 181 (the length from the upper surface to the lower surface of the first body portion 181, i.e., the length in the Z direction to the main junction 18b) be D1 [μm], let the depth of the interval closest to the first body portion 181 in the interval of the depth of the second body portion 182 (the length from the upper surface to the lower surface of the second body portion 182, i.e., the length in the Z direction to the main junction 18b) be D2 [μm], then D1>D2. Figure 5A or Figure 5B In the figure, since there is only one section with a constant depth in the second body portion 182, the depth of the section is D2.

[0120] In the same cross-sectional view, the first body portion 181 is a portion of the body region 18 where the lower surface 18b of the body region 18 is flat at a depth D1 in a range including the active region 112. The second body portion 182 is a portion from a point where the lower surface 18b of the body region 18 starts to rise in the +Z direction on the peripheral region side to a point where the lower surface 18b of the body region 18 ends on the upper surface of the low-concentration impurity layer 33 on the peripheral region side.

[0121] Under the same cross-sectional view, in the lower surface 18b of the body region 18, when the point where the depth D1 of the first body portion 181 reaches the end and connects with the lower surface of the second body portion 182 is set as the first connection point 18a1, the boundary 18a between the first body portion 181 and the second body portion 182 becomes a straight line in the Z direction passing through the first connection point 18a1.

[0122] Furthermore, in the same cross-sectional view, the second body portion 182 includes a first section of a finite length in the X direction from the first connection point 18a1 to the lower surface 18b of the body region 18, which changes to a depth D2. The first connection point 18a1 can be understood to be included in the first body portion 181, and can also be understood to be included in the first section of the second body portion 182. In addition, in the second body portion 182, it can be understood that the first section includes a section having a depth of D2 and maintained flat.

[0123] In the same cross-sectional view, when the position farthest from the first body portion 181 in the X direction and where the depth D2 reaches the end is defined as the second connection point 18a2, the second body portion 182 includes a second section of a finite length in the X direction from the second connection point 18a2 to the point where the body region 18 reaches the end on the upper surface of the low-concentration impurity layer 33. The second section includes the second connection point 18a2.

[0124] In the same cross-sectional view, when the first section includes a section of the second body portion 182 having a depth of D2 and maintained flat, the second connection point 18a2 is a point on the lower surface 18b of the body region 18 that connects the first section and the second section of the second body portion 182 .

[0125] When the lower surface of the second body portion 182 is geometrically understood in the same cross-sectional view, the second connection point 18a2 can be said to be an inflection point closest to the first connection point 18a1 and having the same folding direction as the first connection point 18a1.

[0126] In the same cross-sectional view, the lower surface 18b of the body region 18 in the first interval does not have a portion deeper than D1 within the range where the depth changes from D1 to D2. In addition, in the same cross-sectional view, the lower surface 18b of the body region 18 in the second interval does not have a portion deeper than D2 within the range where the depth changes from D2 to zero (the upper surface of the low-concentration impurity layer 33). That is, in the same cross-sectional view, the depth of the second body portion 182 decreases monotonically in the X direction.

[0127] In the same cross-sectional view, the length of the second body portion 182 along the X direction is L1 [μm]. L1 is the length in the X direction from the first connection point 18 a 1 to the point where the second body portion 182 ends on the upper surface of the low-concentration impurity layer 33 .

[0128] In the same cross-sectional view, the length of the second section along the X direction in the second body portion 182 is L2 [μm]. L2 is the length in the X direction from the second connection point 18 a 2 to the point where the second body portion 182 ends on the upper surface of the low-concentration impurity layer 33 .

[0129] Furthermore, in the same cross-sectional view, no semiconductor region exhibiting the second conductivity type exists on the outer peripheral region side of the semiconductor device 1 relative to the second body portion 182 .

[0130] The magnitude relationship between D1 and D2 and the magnitudes of L1 and L2 are factors that determine the curvature of the main junction (also referred to as the main junction end) in the peripheral region of the semiconductor device 1, which will be described later. The extension of the depletion layer is affected by the curvature of the main junction end, and the ease of occurrence of impact ionization is determined.

[0131] [1-2. Effect of providing end structure in body region]

[0132] exist Figure 5C Indicates the use of Figure 5A The structure shown in the figure shows the impact ionization image in the simulation when the rated voltage (here 22V) of the product specifications is applied between the drain and source. Figure 5C In the example, the difference in collision ionization rate is represented by the intensity of the color and is locally superimposed on Figure 5A As can be seen from this, along the main junction 18b (the lower surface 18b of the body region 18), the location where the electric field intensity becomes the strongest and impact ionization is likely to occur is in the second section of the second body portion 182.

[0133] In the second body portion 182, there is a shallower portion (D1>D2), so that Figure 5C As shown by the white line in FIG. 1 , the extension of the depletion layer sandwiching the main junction 18 b is restricted.

[0134] Furthermore, the second connection point 18a2 and the second region on the peripheral side thereof are affected by the shape of the main junction 18b, and the density of equipotential lines increases, the electric field strength increases, and impact ionization is easily generated. Therefore, the second region of the second body portion 182 becomes the structure with the lowest withstand voltage for the voltage applied between the drain and the source.

[0135] use Figure 5B Conditions that are favorable for lowering the withstand voltage in the second range will be described.

[0136] like Figure 5B As shown, in the cross-section view of the XZ plane, a straight line connecting the first connection point 18a1 and a point on the upper surface of the low-concentration impurity layer 33 where the body region 18 reaches its end (for convenience, it is referred to as the upper surface end point) is defined as straight line 1. When the angle formed by straight line 1 and the upper surface of the low-concentration impurity layer 33 is defined as θ1, tanθ1=D1 / L1.

[0137] When a voltage is applied between the drain and the source, the depletion layer expands upward and downward sandwiching the main junction 18b. Focusing on the lower end of the depletion layer, the lower end of the depletion layer at the first connection point 18a1 exists at a certain distance from the main junction 18b in the -Z direction. Let the straight line passing through this point and parallel to the straight line 1 be the straight line 3.

[0138] In addition, the above-mentioned certain distance is determined by the impurity concentration of the second conductivity type near the main junction 18b of the first body portion 181, the impurity concentration of the first conductivity type of the low-concentration impurity layer 33, and the like.

[0139] If it is assumed that the main junction 18b of the second body portion 182 has the same shape as the straight line 1, the lower end of the depletion layer can be approximated by the straight line 3. In this case, the lower end of the depletion layer in the second body portion 182 is uniform, and there is no portion where the electric field strength increases particularly significantly.

[0140] However, if the main junction 18b of the second body portion 182 is Figure 5B of the shape shown, then especially since the second connection point 18a2 protrudes downward (in the -Z direction) from the straight line 1, the expansion of the depletion layer in the second region including the second connection point 18a2 is suppressed. As a result, the electric field strength increases, so a portion with a low breakdown voltage can be provided in the second region.

[0141] When the angle θ2 (tanθ2 = D2 / L2) formed by the straight line 2 connecting the second connection point 18a2 and the upper surface end point and the upper surface of the low-concentration impurity layer 33 is set, in order for the second connection point 18a2 to protrude downward from the straight line 1, it is preferable that θ2 > θ1 holds. In other words, regarding the depth D2 in the second body portion 182, it is preferable that the relationship D1×L2 / L1 < D2 < D1 holds.

[0142] In the first body portion 181 including the active region 112, the portion where the breakdown voltage becomes low is, from a structural point of view, near the top of the gate trench 17. When impact ionization occurs near the top of the gate trench 17, a deviation in the breakdown voltage occurs due to the manufacturing completion state of the gate trench 17. Therefore, by deliberately providing a structure that is more likely to cause impact ionization than the top of the gate trench 17 in the outer peripheral region of the semiconductor device 1, the deviation in the breakdown voltage can be suppressed.

[0143] Therefore, as the transistor 10, it is preferable from the aspect of stabilizing the breakdown voltage of the transistor 10 to deliberately design so that the breakdown voltage in the second body portion 182 is lower than the breakdown voltage in the first body portion 181.

[0144] That is, it is preferable that the following relationship holds: the maximum voltage (rated voltage) between the drain and the source indicated by the product specifications of the transistor 10 < the breakdown voltage of the second body portion 182 < the breakdown voltage of the first body portion 181.

[0145] In Figure 6 An example of the relationship between the difference (D1 - D2 [μm]) in the depth D1 of the first body portion 181 and the depth D2 of the second body portion 182 and the breakdown voltage BVDSS [V] is plotted. When the drain-source current is IDS [A] and the drain-source voltage is VDS [V], BVDSS [V] is the VDS when IDS = 1.0 μA, and this is defined as the breakdown voltage in this structure (BVDSS = VDS @ IDS = 1.0 μA). In Figure 6 , while fixing the value of D1 together with other parameters represented by L1 and L2, only the value of D2 is changed.

[0146] According to Figure 6 , the larger D1 - D2 is, that is, the shallower the second connection point 18a2 is, the lower the breakdown voltage is, and it finally converges. From the viewpoint of stabilizing the breakdown voltage of the transistor 10, it is preferable that the breakdown voltage in the second region is low. That is, the following relationship holds: the maximum rated voltage between the drain and source represented by the product specifications of the transistor 10 < the breakdown voltage in the second body portion 182 < the breakdown voltage in the first body portion 181.

[0147] According to Figure 6 's results, if d = D1 - D2 [μm], then the maximum rated voltage BVDSS between the drain and source is preferably in the relationship of BVDSS ≤ 9534×d 4 +7087×d 3 +1970×d 2 +249×d + 31.

[0148] However, when D2 is too shallow, the breakdown voltage in the second region becomes too low, so it may be difficult to ensure a sufficient margin for the maximum rated voltage of the transistor 10. If d = D1 - D2 is adjusted on the basis of making the relationship D1×L2 / L1 < D2 hold as described above, the breakdown voltage in the second region can be made low, and a sufficient margin for the breakdown voltage for the desired maximum rated voltage can be ensured.

[0149] In addition, in the present disclosure, it is preferable that in the plan view of the semiconductor device 1, there is no semiconductor region showing the second conductivity type on the outer peripheral region side of the semiconductor device 1 compared to the second body portion 182. If there is a semiconductor region showing the second conductivity type on the outer peripheral region side of the semiconductor device 1 compared to the second body portion 182, due to its influence, the main junction 18b further extends toward the outer peripheral region side of the semiconductor device 1. As a result, the breakdown voltage in the second body portion 182 increases, and there may be a case where the desired effect of the present disclosure is offset.

[0150] [1 - 3. Method for forming the end structure of the body region]

[0151] Hereinafter, a method for manufacturing the transistor 10 according to the first embodiment, particularly a method for forming the end structure of the body region 18 will be described.

[0152] Figure 7 This is a schematic diagram showing a state immediately before second conductivity type impurities are implanted to form the body region 18 in the process of manufacturing the structure of the first embodiment.

[0153] Figure 7 (A) is a schematic diagram of the semiconductor device 1 when viewed in a plane (XY plane), and the lower side shows the Figure 7 Schematic diagram of the XZ plane when the XZ plane is observed along the lines I-I and II-II shown in (A). Figure 7 (B) and Figure 7 The (C) are respectively along Figure 7 Schematic diagram of (A) when observing the YZ plane through the III-III line and the IV-IV line.

[0154] exist Figure 7 In (A), (B), and (C), in the region forming the end structure of the body region 18, the resist is patterned so that openings are alternately and periodically provided in the Y direction. Along the Y direction, the period is a1 [μm], and the width of the resist opening is a2 [μm]. The schematic representation of the state immediately after the second conductivity type impurity is injected in this state is Figure 8 (A), (B), (C).

[0155] In principle, the second conductivity type impurities are injected only into the resist openings. However, if the injection is performed at a limited angle, some degree of injection may also be performed into the region of the semiconductor layer 40 covered by the resist. Figure 8 The XZ cross-sectional view of the lower section in (A) and Figure 8 This situation is also taken into consideration in (C).

[0156] Schematically indicates that Figure 8 The states of (A), (B), and (C) are as follows: the state after the resist is removed and heat treated is Fig. 9 The implanted second conductivity type impurities diffuse due to heat and reach a position deeper than that immediately after the implantation.

[0157] exist Figure 7 In (A), there is no significant difference in the depth of the impurity just after the injection between the region that is not covered by the resist over the entire length in the Y direction (line III-III) and the region where the resist periodically opens in the Y direction (line IV-IV) ( Figure 8 (B) and (C)).

[0158] However, if heat treatment is performed, the impurities reach a deeper position in the region (III-III line) that is not covered by the resist over the entire length in the Y direction, whereas in the region (IV-IV line) where the resist periodically opens in the Y direction, the impurities diffuse not only in the Z direction but also in the Y direction from the implanted region to the non-implanted region. As a result, at the IV-IV line, the diffusion of the second conductivity type impurities converges at a relatively shallow position compared to the III-III line.

[0159] Thus, at the end of the body region 18, as Fig. 9 As shown in the lower side of (A), a portion corresponding to the second body portion 182 and having a shallow depth of the second conductive type impurity is formed. By controlling the dimensions of the width a2 and the period a1 of the opening of the resist, as well as the implantation conditions and the heat treatment conditions, the shape of the second body portion 182, in particular the shape of the main junction 18b, can be controlled.

[0160] As described above, in the manufacturing method of the first embodiment, by patterning the resist and implanting the second conductivity type impurity only once, the first body portion 181 and the second body portion 182 can be formed simultaneously, so that the manufacturing cost can be reduced.

[0161] According to the manufacturing method of the present embodiment 1, although there are differences depending on the injection conditions and the heat treatment conditions, in the planar view (XY plane) of the semiconductor device 1, the second body portion 182 includes regions where the impurity concentration of the second conductive type is relatively high and regions where the impurity concentration is relatively low, which appear alternately and periodically.

[0162] In addition, in the cross-section viewed along the YZ plane, the second body portion 182 includes a portion where a region with a relatively high concentration and a region with a relatively low concentration of the second conductivity type impurity appear alternately and periodically.

[0163] In the cross-sectional view of the YZ plane, the second body portion 182 includes shallow and deep portions that appear alternately and periodically along the Y direction. In this case, the lower surface of the second body portion 182 has a concavoconvex shape along the Y direction in the same cross-sectional view.

[0164] In the plan view of the semiconductor device 1, the second conductivity type impurity is a relatively high concentration region. Figure 8 The area corresponding to the resist opening in (A), (B), and (C) corresponds to an area where the concentration of impurities of the second conductive type is relatively high in the cross-section viewed in the YZ plane, and further corresponds to the depth where the second body portion 182 is periodically generated along the Y direction in the cross-section viewed in the YZ plane.

[0165] Similarly, in the plan view of the semiconductor device 1, the second conductivity type impurity is a relatively low concentration region. Figure 8 (A), (B), and (C) correspond to the area covered by the resist, which corresponds to the area where the impurities of the second conductive type are at a relatively low concentration in the cross-section viewed in the YZ plane, and further corresponds to the shallow area where the second body portion 182 is periodically generated along the Y direction in the cross-section viewed in the YZ plane.

[0166] exist Fig. 10A 2 shows, as an example, the result of a simulation of a cross section of the transistor 10 manufactured by the present manufacturing method along the YZ plane. Fig. 10A In the simulation shown, the period of the resist pattern is set to 0.8 μm, and the width of the resist opening is set to 0.2 μm. It can be seen that, although it also depends on the manufacturing conditions, the main junction 18b has a periodic concave-convex shape along the Y direction, and the second body portion 182 includes shallow and deep portions that are alternately and periodically present along the Y direction.

[0167] Fig. 10B is a graph showing the results of a simulation of the doping concentration of the transistor 10 manufactured by the same manufacturing method. Fig. 10C It will be Fig. 10B The figure is an enlarged view of the range partially surrounded by the middle. The horizontal axis is the depth from the upper surface of the semiconductor layer 40 (low-concentration impurity layer 33), and the vertical axis is the doping concentration. The so-called doping concentration is the concentration that also takes into account the conductivity type of the impurity. The impurity concentration of the first conductivity type and the impurity concentration of the second conductivity type are equal, and the value is offset and becomes zero. That is, the place where the value is zero is the main junction 18b.

[0168] exist Fig. 10B , Fig. 10C In the Fig. 10A The doping concentrations in the Z direction at the shallow part (Pos1) of the second body portion 182 and at the deep part (Pos2) of the second body portion 182 are shown. It can be seen that under the manufacturing conditions exemplified here, the difference in depth in the Z direction is present with a width of about 0.04 to 0.05 μm.

[0169] use Fig. 10D , the relationship between the opening size related to impurity injection during the manufacture of the second body portion 182 and the final shape of the main junction 18b is explained.

[0170] Fig. 10D To promote understanding Fig. 10A The range indicated by the white box is highlighted in the schematic diagram. Fig. 10D In the example, the shape of the main node 18b is changed to a shape similar to a sine function. Fig. 10D The dimensions within are also shown in a different relationship to the actual dimensions.

[0171] As Figure 8 shown in (A) and (C) of, in the region of the end structure of the formation region 18, the resist is laid out, and openings are provided alternately and periodically in the Y direction. When the period in the Y direction is a1 [μm] and the width of the opening of the resist is a2 [μm], in Fig. 10D , the distance connecting adjacent maximum points of the main junction 18b corresponds to the period a1.

[0172] Since impurity implantation is performed in the openings of the resist in (A) and (C) of Figure 8 , in Fig. 10D , each minimum point of the main junction 18b corresponds to the central position of the opening of the resist in the Y direction. Similarly, in Fig. 10D , each maximum point of the main junction 18b corresponds to the central position of the non-opening portion of the resist in the Y direction.

[0173] In a cross-section in the YZ plane, since the impurities implanted into the openings of the resist diffuse to the non-implantation regions on both sides in the Y direction through heat treatment, the second body portion 182 becomes shallower from the center of the opening of the resist toward both sides in the Y direction as the impurity concentration decreases. Due to the diffusion of impurities, the main junction 18b can be understood as having a width that changes from each minimum point to half of the amplitude toward both sides in the Y direction, which is approximately equal to the width where impurities are actually implanted, that is, the width of the opening of the resist.

[0174] Therefore, if corresponding to Fig. 10D , when the depth at which the second body portion 182 becomes shallower is d21 [μm] and the depth at which it becomes deeper is d22 [μm] (it can be considered that there is a relationship of d21 < D2 < d22), the depth of the second body portion 182 in the Y direction becomes the closest interval of d22 - (d22 - d21) / 4, which is approximately the same as the width a2 of the opening of the resist.

[0175] Here, when n is the number of repetitions of setting openings in the resist, in order for the second body portion 182 to be shallower, the volume of impurities that cannot be implanted, L1×(a1×n)×(D1 - D2), and the volume of the region in the second body portion 182 that is not implanted with impurities because it is covered by the resist, L1×((a1 - a2)×n)×D1, must be of the same order. Therefore, the relationship a2 = a1×D2 / D1 holds.

[0176] Regarding Fig. 10DIn terms of the corresponding relationship, in the Y direction, the closest interval of the depth of the second body portion 182 to d22-(d22-d21) / 4 is approximately equal to a1×D2 / D1. Here, approximately equal refers to the range of 1 / 2 to 2 times the value of a1×D2 / D1. This takes into account the fluctuation caused by the injection angle or heat treatment conditions during impurity injection.

[0177] Furthermore, the second conductivity type impurity concentration in the body region 18 of the transistor 10 manufactured by the manufacturing method of the first embodiment typically increases from 1.0E18 cm-1 to 1.0E18 cm-1 from the upper surface of the low-concentration impurity layer 33 toward the main junction 18 b. －3 Level to 1.0E16cm －3 The concentration of the second conductivity type impurity in the first body portion 181 is gradually reduced by at least one digit. The concentration distribution of the second conductivity type impurity falls within the range of D1 in the Z direction in the first body portion 181, whereas it is compressed within the range of D2 in the Z direction in the second body portion 182. Therefore, the concentration gradient of the second conductivity type impurity in the second body portion 182 in the Z direction is greater than the concentration gradient of the second conductivity type impurity in the first body portion 181 in the Z direction.

[0178] (Implementation Method 2)

[0179] [2-1. Shape of the end structure of the body region]

[0180] Fig.11A Schematically shows a part of the structure of the outer peripheral region in the X direction of the semiconductor device 1 in the second embodiment (hereinafter sometimes referred to as the end structure or terminal structure). Fig. 11B Yes Fig.11A A portion of , that is, an enlarged view of a portion of the end structure of the body region 18.

[0181] In addition, Fig.11A and Fig. 11B and the following Fig. 11C In the figure, the passivation layer 35 and the metal layer 30 are omitted.

[0182] In the drawings, the same reference numerals are given to portions corresponding to the structures described in Embodiment 1, and description of the same contents as in Embodiment 1 is omitted.

[0183] The difference between the second embodiment and the first embodiment is that the depth D2 of the second body portion 182 is significantly smaller than the depth D1 of the first body portion 181. Fig.11A In the example of FIG. 1 , assuming that the depth from the upper surface of the low-concentration impurity layer 33 to the lower surface of the first source region 14 is Ds [μm], D2 <Ds<D1。

[0184] In addition, in the first body portion 181 and the second body portion 182, the second conductivity type impurity concentration p2 [cm －3 ] and the second conductivity type impurity concentration p1 [cm －3 ] is quite different, which is also a feature of the second embodiment.

[0185] exist Fig.12 (A) shows the second conductivity type impurity concentration distribution in the depth direction of the first body portion 181 (solid line) and the second body portion 182 (dashed line) of the second embodiment. Fig.12 (B) shows the first conductivity type impurity concentration distribution in the depth direction of the first body portion 181 (solid line) and the second body portion 182 (dashed line). Fig.12 (A) and (B) are data obtained using process simulation.

[0186] according to Fig.12 (A) shows the second conductivity type impurity concentration distribution in the first body portion 181 (solid line) and the second conductivity type impurity concentration distribution in the second body portion 182 (dashed line). In the interval from the upper surface of the low-concentration impurity layer 33 to the depth D2, the second conductivity type impurity concentration is 1E19 cm －3 The above range is consistent.

[0187] Furthermore, according to Fig.12 In (B), the first conductivity type impurity concentration distribution at a position deeper than D2 is the same in the first body portion 181 (solid line) and in the drift layer 33 directly below the second body portion 182 (dashed line).

[0188] Even if the first conductive type impurity exists, the second conductive type impurity exists in a higher concentration than the first conductive type impurity, which functions as the body region 18. Therefore, the main junction 18b in the first body portion 181 is located at a depth of D1 below D2. On the other hand, the second body portion 182 reaches the main junction 18b at a depth of D2.

[0189] In the second embodiment, no semiconductor region exhibiting the second conductivity type exists on the outer peripheral region side of the semiconductor device 1 relative to the second body portion 182 .

[0190] also, Fig.12In (A), z1 and z2 are the points where the impurity concentrations of the second conductivity type in the first body part 181 and the second body part 182 are the same as the impurity concentration of the first conductivity type in the low-concentration impurity layer 33. That is, they represent the positions of the main junctions 18b of the respective parts. By obtaining the impurity concentration distributions of the first conductivity type and the second conductivity type respectively, it is possible to identify the depth D1 of the first body part 181 and the depth D2 of the second body part 182 according to z1 and z2 respectively as shown in (A) of Fig.12 As shown in (A) of

[0191] [2-2. Effect of setting the end structure in the body region]

[0192] In Fig. 11C shows the impact ionization image in the simulation when the rated voltage of the product specification (here 22V) is applied between the drain and the source using the structure shown in Fig.11A . In Fig. 11C , the difference in the impact ionization rate is represented by the shade of color, and it is partially superimposed on Fig.11A to represent. From this, it can be seen that in the main junction 18b, the part where the electric field strength becomes the strongest and impact ionization is likely to occur is in the second interval of the second body part 182.

[0193] In the second body part 182, the part shallower than the depth D1 of the first body part 181 has a certain length (L1>0, D2<Ds), so that as shown by the white line in Fig. 11C , the diffusion of the depletion layer sandwiching the main junction 18b is restricted. In particular, since the second body part 182 has a high impurity concentration of 1E19 cm －3 or more, the upper end of the depletion layer is particularly likely to be restricted by diffusion.

[0194] In addition, the second connection point 18a2 and the second interval on the outer peripheral region side thereof are affected by the shape of the main junction 18b, so that the density of the equipotential lines becomes high, the electric field strength increases, and impact ionization is likely to occur. Therefore, the second interval of the second body part 182 becomes the structure with the lowest breakdown voltage for the voltage application between the drain and the source.

[0195] In Fig.13A shows the result of simulating the ease of occurrence of impact ionization when the length L1 of the second body part 182 is changed in six levels based on the structure shown in Fig.11A (D2<Ds) and the structure with the impurity concentration distributions shown in (A) and (B) of Fig.12 .

[0196] In Fig.13A , compared with Fig. 11CSimilarly, the impact ionization image in the simulation when the rated voltage of the product specification (here 22V) is applied between the drain and source is shown. Fig. 13B This is the result of simulating the relationship between VDS and IDS at each level. VDS [V] is the drain-source voltage, and IDS [A] is the drain-source current.

[0197] Fig.13A In the figure, the lengths of the second body portion 182 are 0.7 μm, 0.6 μm, 0.5 μm, 0.4 μm, 0.3 μm, and 0.2 μm, respectively, from the left, and they are all common in that impact ionization is most likely to occur in the second section of the second body portion 182. However, the withstand voltage increases in the above order.

[0198] Fig. 13B In the plot of VDS-IDS shown, the above order is corresponded from the left. If the VDS when IDS=1.0μA is set as the withstand voltage under this structure (here set as BVDSS[V]), the withstand voltage is BVDSS=18.9V, 19.3V, 19.9V, 21.1V, 22.9V, and 25.3V in 6 levels from the left. It can be considered that if a voltage higher than it is applied as VDS, collision ionization occurs and the body diode avalanche breakdown occurs. That is, even if the impurity concentration distribution, D1, and D2 at the main junction end are the same, the withstand voltage of the second body portion 182 can be controlled to be lower by making the length L1 of the second body portion 182 longer.

[0199] The level of L1 = 0.2 μm is substantially equivalent to the case where there is no portion fixed to the depth D2 in the second body portion 182. Although the main junction end rises in a nearly vertical shape, so that impact ionization is easily generated at the end position, the withstand voltage of 25.3 V at this time is not much different from the withstand voltage of the first body portion 181.

[0200] Therefore, the withstand voltage when the second body portion 182 cannot effectively perform the desired function of the present disclosure is 25.3 V. The transistor 10 functions without problems until a voltage lower than 25.3 V is applied, but avalanche breakdown occurs when a voltage higher than 25.3 V is applied. The product specification maximum voltage of the transistor 10 must be lower than 25.3 V.

[0201] However, if Fig.13A As shown, if L1>0.2μm is set and the second body portion 182 is provided, the withstand voltage of this portion is reduced, so the withstand voltage of the second body portion 182 can be controlled to be lower than the withstand voltage of the first body portion 181. As a result, avalanche breakdown occurs in the second body portion 182 before the first body portion 181, so the withstand voltage of the transistor 10 can be stabilized.

[0202] When the horizontal axis is set to L1 and the vertical axis is set to BVDSS, the Fig. 13B result is plotted as Fig. 13C . If the result is expressed by an approximate formula, it can be seen that BVDSS = 26.4×(L1) 2 - 36.4×L1 + 31.5 (L1 > 0.2). Therefore, when the depth of the first body portion 181 and the second body portion 182 is D2 < Ds, and the length of the second body portion 182 is higher than 0.2 μm, by setting the breakdown voltage of the transistor 10 to be lower than 26.4×(L1) 2 - 36.4×L1 + 31.5, the following desired relationship can be established: the maximum rated voltage between the drain and source of the transistor 10 < the breakdown voltage of the second body portion 182 < the breakdown voltage of the first body portion 181.

[0203] In addition, the above relational expression is the result in the case where D2 < Ds < D1, and the impurity concentration distribution of the second conductivity type in the range from the upper surface of the low-concentration impurity layer 33 to the depth D2 is Fig.12 as shown in (A) of Fig. 11C , but if it is adjusted in the direction of further promoting the impact ionization of the second body portion 182 as Fig.12 shown, it also holds. Therefore, it is preferable that D2 < Ds, and the impurity concentration of the second conductivity type in the range up to the depth D2 preferably includes a portion higher than

[0204] the case shown in (A) of －3 . As described above, in the second embodiment, in the body region 18, in the region from the upper surface of the low-concentration impurity layer 33 to the depth D2, there is a high-concentration range where the impurity concentration of the second conductivity type is 1E19 cm

[0205] or more. Since this high-concentration layer occupies the position where the body region 18 contacts the source electrode 11, it also serves to reduce the contact resistance between the source electrode 11 and the body region 18.

[0206] The condition of D2 < Ds unified in the second embodiment is a necessary condition to obtain the effect of reducing the contact resistance between the source electrode 11 and the body region 18, which will be described in the manufacturing method of the second embodiment. Fig.11D The second embodiment can also be said to be a form in which a high-concentration second-conductivity-type impurity layer having the function of reducing the contact resistance between the source electrode 11 and the body region 18 protrudes at the end portion of the body region 18. Regarding the protrusion of the high-concentration second-conductivity-type impurity layer at the end portion of the body region 18, for example, it can also be as

[0207] As described above, the second body portion 182 having a changed length, depth, and concentration is provided at the end portion of the body region 18, and the restriction of the diffusion of the depletion layer is controlled, thereby preparing a portion where the withstand voltage of the transistor 10 is lowest. The second body portion 182 may be provided so as to surround the outer circumference of the first body portion 181 in a plan view, or may be provided only at any side of the outer circumference of the substantially rectangular shape of the first body portion 181, or may be provided only at a local portion.

[0208] exist Fig.14 Schematic diagram of a comparative example in which the end structure of the body region is formed with a structure similar to that of the present embodiment 2. In the comparative example shown here, the same reference numerals are used for components corresponding to the components of the present disclosure.

[0209] In the comparative example, the body region 18 is gradually shallower at the end of the body region 18. The shallower portion is a structure corresponding to the second body portion 182 of the second embodiment. The structure corresponding to the second body portion 182 in the comparative example has a portion containing the first conductive type impurity with a higher concentration than that of the low-concentration impurity layer 33 only directly below it, thereby controlling the main junction 18b to be set at a shallower position.

[0210] In the structure of the comparative example, high concentration impurities are distributed in the upper body region 18 and the lower drift layer 33 with the main junction 18b sandwiched between the portion corresponding to the second body portion 182. Therefore, compared with the structure of the second embodiment, the depletion layer is difficult to expand not only at the upper end but also at the lower end, and impact ionization is more likely to occur. Since the withstand voltage of the portion corresponding to the second body portion 182 is significantly lowered, it is difficult to ensure a margin compared to the maximum voltage of the semiconductor device 1.

[0211] On the other hand, in the structure of the second embodiment, since the withstand voltage of the second body portion 182 does not become extremely low, there is an advantage that a sufficient margin can be easily secured for the maximum voltage of the specification of the semiconductor device 1 .

[0212] [2-3. Method for forming the end structure of the body region]

[0213] Hereinafter, a method of manufacturing the transistor 10 according to the second embodiment will be described with particular emphasis on the formation of the end structure of the body region 18 .

[0214] FIG. 15A1 to FIG. 15A6 It means manufacturing Fig.14 A schematic diagram of the construction process of the comparative example shown, Figures 15B1 to 15B5 It is a schematic diagram showing the process of manufacturing the structure of the second embodiment.

[0215] like Fig.15A1 and Fig.15B1 As shown, the point that the low-concentration impurity layer 33 is processed is common in the comparative example and the second embodiment.

[0216] First, a method for manufacturing a structure of a comparative example is described. First, in order to provide an end structure corresponding to the second body portion 182, a step of injecting first conductive type impurities at a concentration higher than that of the low-concentration impurity layer 33 is performed in advance as the location for providing the end structure ( Fig.15A2 In order to carry out this process, a resist is applied on a semiconductor wafer, and an exposure process is carried out using a reticle to open only the location to be set. The first conductivity type impurity is implanted only in the opening portion.

[0217] exist Fig.15A2 After the process shown in FIG. 1 , in the low concentration impurity layer 33, only Fig.15A2 The portion into which the first conductivity type impurity is implanted in the process shown exists as a portion having a different first conductivity type impurity concentration.

[0218] Then, if Fig.15A3 As shown, in order to form the body region 18 (corresponding to the first body portion 181 and the second body portion 182), a resist is applied on the semiconductor wafer, and an exposure process is performed using an intermediate mask that opens the location where the body region 18 is to be set, and impurities of the second conductive type are injected into the opening portion.

[0219] At this time, in the range of forming the body region 18, the second conductivity type impurities are uniformly implanted under the same conditions in parallel. In order to distinguish from the conditions of the second conductivity type impurity implantation performed in other steps later, it is conveniently referred to as the second condition. Under the second condition, adjustment is made so that the concentration of the second conductivity type impurities is less than 1E19cm －3 part.

[0220] exist Fig.15A3 In the process shown in FIG. 1 , since the low-concentration impurity layer 33 is already Fig.15A2 In the process shown, the first conductivity type impurity is locally implanted at a high concentration, so only in this portion, the second conductivity type impurity concentration and the first conductivity type impurity concentration are equal at a relatively shallow position. Therefore, the main junction 18b can be set shallowly only in this portion. This becomes a portion equivalent to the second body portion 182 described in the second embodiment.

[0221] In the manufacturing method shown in the comparative example, the gate trench 17, the gate insulating film 16, the gate conductor 15, the gate conductor wiring 15a connecting the gate conductor 15 to the gate electrode 19 formed in the subsequent process, and the interlayer insulating layer are formed. Fig.15A4As shown, the first source region 14 is formed by selectively implanting impurities of the first conductivity type from the upper surface of the body region 18. Figure 3A , Figure 3B The configuration of the first source region 14 is shown.

[0222] Next, on the upper surface of the semiconductor layer 40, Fig.15A3 The second conductivity type impurity concentration in the body region 18 formed in the step shown is high, and 1E19 cm ―3 The above second conductivity type impurities form a body contact layer ( Figure 15A5 ). The injection conditions at this time are to match those in Fig.15A3 The conditions for implantation performed in the process shown in FIG. 1 (the second condition) are distinguished from the conditions for implantation performed in the process shown in FIG. 1 and are referred to as the first condition. Figure 15A5 In the illustrated process, resist coating is not performed, and implantation is performed using the oxide film 36 provided on the upper surface of the semiconductor layer 40 as a mask. Therefore, it is preferable to adjust the first condition so that the oxide film 36 is not penetrated.

[0223] In the manufacturing method of the comparative example, Figure 15A5 After the steps shown in FIG. 1 , the source electrode 11 and the gate electrode 19 are formed through various steps. Fig.15A6 ), and then forming a passivation layer (not shown) and the like, and finally completing the transistor 10.

[0224] On the other hand, in the manufacturing method of the second embodiment, Figures 15B1 to 15B5 As shown in FIG. 1 , the presence or absence of steps and the order of steps are partially different from those in the manufacturing method of the comparative example. First, in the manufacturing method of the present embodiment 2, there is no Fig.15A2 In addition, in the manufacturing method of the present embodiment 2, the manufacturing method of the comparative example is Fig.15A3 The process shown corresponds to the process Figure 15B4 Postpone.

[0225] In the manufacturing method of the second embodiment, Fig.15B1 From the state shown, first, the gate trench 17, the gate insulating film 16, the gate conductor 15, the gate conductor wiring 15a connecting the gate conductor 15 to the gate electrode 19 formed in a subsequent step, and the interlayer insulating layer are formed.

[0226] Next, the first conductivity type impurities are selectively implanted from the upper surface of the low concentration impurity layer 33 to form the source region 14 ( Fig.15B2 ). If only this step is extracted, the Fig.15A4 There are no changes to the process shown.

[0227] Next, in the manufacturing method of the second embodiment, the formation of the body contact layer corresponding to the manufacturing method of the comparative example is performed. Figure 15A5 ( Figure 15B3 ) The body contact layer is formed on the upper part of the body region 18. Since the body region 18 is constituted in two stages together with the next process described later, Figure 15B3 The process shown is the so-called first body region formation process.

[0228] In the first body region formation process ( Figure 15B3 ), the condition of implanting impurities of the second conductivity type at a high concentration of 1E19 cm ―3 or more is defined as the first condition. The first condition can also be understood as equivalent to the implantation condition of the process represented by Figure 15A5 in the manufacturing method of the comparative example. In the first body region formation process ( Figure 15B3 ), the oxide film 36 already formed on the semiconductor layer 40 is used as the mask for implantation. Therefore, resist coating and exposure processing using an intermediate mask are not required. The first body region formation process ( Figure 15B3 ) has no change compared with the process represented by Figure 15A5 in the manufacturing method of the comparative example, except that the impurity implantation region is different in the plan view.

[0229] In addition, in the first body region formation process ( Figure 15B3 ), the conditions must be selected in consideration of the diffusion during the heat treatment to be performed later, so that the depth at which the impurities are implanted is D2. It is important that D2 < Ds. This is because, at this stage, since the source region 14 has already been formed, if D2 > Ds, it may damage the formation of the conduction channel, which is the main function of the transistor 10.

[0230] Next, in the second embodiment, as Figure 15B4 shown, the formation of the first body portion 181 is performed in the body region 18. This is the second body region formation process. At this time, a resist is coated on the semiconductor wafer, and an exposure process is performed to open only the region where the first body portion 181 is to be formed. For the opened portion of the resist, impurities of the second conductivity type are implanted under the second condition so that the concentration becomes lower than 1E19 cm －3 . It can be understood that the second condition is equivalent to the implantation condition of the process represented by Fig.15A3 in the manufacturing method of the comparative example.

[0231] The intermediate mask used in the second body region formation process ( Figure 15B4 ) is equivalent to the intermediate mask used in the process represented by Fig.15A3 in the manufacturing method of the comparative example.

[0232] In the second body region formation process ( Figure 15B4) in the first step ( Figure 15B3 ) is formed by injecting the second conductive type impurity into a region narrower than the region in the plan view to form the first body portion 181. The second step ( Figure 15B4 )The body contact layer in the end portion into which the second conductive type impurities are implanted becomes the second body portion 182.

[0233] In addition, here, the body contact layer and the high-concentration second conductivity type impurity layer have the same meaning.

[0234] The length L1 of the second body portion 182 is obtained by forming the second step ( Figure 15B4 ) is controlled by designing the intermediate mask used in the body region. Figure 15B3 ) is used to adjust the depth D2 of the second body portion 182.

[0235] In the manufacturing method of the second embodiment, Figure 15B4 After the steps shown in FIG. 1 , the source electrode 11 and the gate electrode 19 are formed through various steps. Figure 15B5 ), and then forming a passivation layer (not shown) and the like, and finally completing the transistor 10.

[0236] In other words, the manufacturing method of the second embodiment is a manufacturing method of a semiconductor device as follows: a first step of forming a body region is performed, followed by a second step of forming a body region, in which the second conductivity type impurities are implanted from the upper surface of the low concentration impurity layer 33 under the first condition into the region where the body region 18 is formed in a plan view, so that a second conductivity type impurity concentration of 1E19 cm is formed in the region from the upper surface of the low concentration impurity layer 33 to the depth D2. －3 In the above-mentioned body region forming second step, the region which becomes the first body portion 181 in the plan view is selected, and the second conductivity type impurity is implanted from the upper surface of the low concentration impurity layer 33 under the second condition, so that the second conductivity type impurity concentration is less than 1E19cm in the interval from the depth D2 to D1. －3 part.

[0237] In addition, the manufacturing method is a method in which the first conductivity type impurity and the second conductivity type impurity are not implanted into the portion where the second body portion 182 is formed after the low concentration impurity layer 33 is formed and before the first step of forming the body region. As described above, a semiconductor device 1 can be obtained that has a larger margin for the maximum rated voltage than the conventional comparative example.

[0238] The manufacturing method of the second embodiment has three main advantages.

[0239] The first point is that one process can be omitted, namely Fig.15A2 The process shown is necessary in the comparative example to form the second body portion 182. Since the number of intermediate masks used can be reduced by one, the manufacturing method is easy and the manufacturing cost can be reduced.

[0240] The second point is that Figure 15B5 As shown, the second body portion 182 is not arranged directly below the gate conductor wiring 15a.

[0241] When the transistor 10 is driven, a voltage equal to or higher than the threshold value Vth [V] is applied to the gate conductor wiring 15a. Therefore, an electric field is generated from the gate conductor wiring 15a, and there is a possibility that the withstand voltage of the second body portion 182 changes from the target design value.

[0242] However, in the structure of the second embodiment, the oxide film 36 directly in contact with the low-concentration impurity layer 33 is limitedly arranged only in the outer peripheral region of the semiconductor device 1 relative to the boundary 18 a between the first body portion 181 and the second body portion 182 in the second direction.

[0243] Alternatively, the gate conductor wiring 15 a having the same potential as the gate conductor 15 is arranged only on the outer peripheral region side of the semiconductor device 1 with respect to the second body portion 182 in the second direction.

[0244] Strictly speaking, if Fig. 11B As shown, the second section of the second body portion 182 may be directly below the oxide film 36 in direct contact with the low-concentration impurity layer 33, but is preferably not directly below the gate conductor wiring 15a. In addition, the first body portion 181 is preferably in contact with the source electrode 11, but may be a structure in which the first section of the second body portion 182 is not in contact with the source electrode 11.

[0245] With the above-described structure, the second body portion 182 is less likely to be affected by the electric field generated from the gate conductor wiring 15 a , and the effect of stabilizing the breakdown voltage can be obtained.

[0246] The third point is that the variation in the threshold value Vth for driving the transistor 10 caused by the structural finish during manufacturing can be reduced.

[0247] In the manufacturing method of this embodiment 2, Fig.15B2 , Figure 15B3 , Figure 15B4As shown, since the formation of the source region 14 and the formation of the body region 18 in the transistor 10 are performed continuously (the first step of forming the body region and the second step of forming the body region), the state of the upper surface of the low-concentration impurity layer 33 is unified between these steps. Therefore, the impurity implantation performed in each step is not affected by the state of the upper surface of the low-concentration impurity layer 33 and does not cause deviations separately.

[0248] This is expressed in Fig. 16B According to the state of the upper surface of the low-concentration impurity layer 33, the source region 14 is formed ( Fig.15B2 ) performs the first conductivity type impurity implantation, and even under the same implantation conditions, the depth of the source region 14 after the implantation varies. Fig. 16B (1) is an example of a case where the source region 14 is formed relatively shallowly in a certain upper surface state. Fig. 16B (2) is an example of a case where the source region 14 is formed relatively deeply in other upper surface states.

[0249] In the manufacturing method of the second embodiment, the first step of forming the body region ( Figure 15B3 ) and the second step of forming the body region ( Figure 15B4 ), since the upper surface state of the low concentration impurity layer 33 remains unchanged, Fig. 16B In the upper surface state (1), the body region 18 is also formed relatively shallowly like the source region 14. Fig. 16B In the upper surface state (2), the body region 18 is also formed relatively deep like the source region 14 .

[0250] In either upper surface state, the source region 14 and the body region 18 are formed similarly shallow or deep, so the channel length corresponding to the difference does not change. Therefore, it is possible to suppress the occurrence of variations in the threshold Vth for the drive transistor 10 due to the channel length.

[0251] The state of the upper surface of the low-concentration impurity layer 33 also includes the in-plane variation of the semiconductor device 1 , but in the manufacturing method of the second embodiment, since it corresponds to the state of the upper surface of this part, it has the effect of suppressing the in-plane variation of the conductive channel length.

[0252] In contrast, in the manufacturing method of the comparative example, in the formation of the body region 18 ( Fig.15A3 ) and the formation of the source region 14 ( Fig.15A4), a process of forming the gate trench 17, the gate insulating film 16, the gate conductor 15, the gate conductor wiring 15a and the interlayer insulating layer is inserted. Therefore, at the time of injecting the second conductivity type impurities for forming the body region 18 and the time of injecting the first conductivity type impurities for forming the source region 14, the state of the upper surface of the low concentration impurity layer 33 changes.

[0253] This is expressed in Fig.16A According to the state of the upper surface of the low-concentration impurity layer 33, the formation of the body region 18 ( Fig.15A3 ) performs the second conductivity type impurity implantation, and even under the same implantation conditions, the depth of the body region 18 after the implantation varies. Fig.16A (1) is an example of a case where the body region 18 is formed relatively shallowly in a certain upper surface state. Fig.16A (2) is an example in which the body region 18 is formed relatively deeply in other upper surface states.

[0254] In the manufacturing method of the comparative example, since the source region 14 is formed later ( Fig.15A4 ) the upper surface state of the low concentration impurity layer 33 changes surely, so Fig.16A As shown in (1) and (2) of FIG. 1 , the depth of the source region 14 is determined independently of the depth of the body region 18. Therefore, the conduction channel length corresponding to the difference is not uniform. Due to the influence of the variation in the structural completion state and the in-plane variation, the threshold Vth for driving the transistor 10 has a large variation caused by the conduction channel length.

[0255] That is, in the manufacturing method of the second embodiment, it is preferable that the step of forming the source region 14 , the first step of forming the body region, and the second step of forming the body region are continuous in this order. As a result, the on-channel length of the formed transistor 10 is constant within the plane of the semiconductor device 1 .

[0256] In other words, the above-mentioned feature is as follows. That is, in the semiconductor device 1 of the second embodiment, in the third direction (Z direction) orthogonal to both the first direction (Y direction) and the second direction (X direction), the upper surface of the gate conductor 15 inside the gate trench 17 is above the interface between the source region 14 and the body region 18, and the length from the upper surface of the gate conductor 15 to the interface (main junction) between the source region 14 and the drift layer 33 is constant within the surface of the semiconductor device 1.

[0257] Alternatively, in the third direction (Z direction) orthogonal to both the first direction (Y direction) and the second direction (X direction), the upper surface of the gate conductor 15 inside the gate trench 17 is above the interface between the source region 14 and the body region 18, and the sum of the length from the upper surface of the gate conductor 15 to the interface between the source region 14 and the body region 18 and the length from the interface (main junction) 18b between the body region 18 and the drift layer 33 to the top of the gate trench 17 is constant within the surface of the semiconductor device 1.

[0258] The term "consistent" here does not strictly mean constant size, but means that the conduction channel length is within a range of ±10% at a plurality of randomly selected measurement locations. Within the range of ±10%, there is no obstacle to obtaining the effects of the second embodiment.

[0259] As described above, the manufacturing method of the second embodiment is superior to the manufacturing method of the conventional comparative example due to the three advantages.

[0260] Industrial Applicability

[0261] The semiconductor device including the vertical field effect transistor of the present invention can be widely used as a device for controlling the conduction state of a current path.

[0262] Description of symbols

[0263] 10 transistor (first vertical field effect transistor)

[0264] 11 1st source electrode

[0265] Part 12 and 13

[0266] 141st source region

[0267] 15 1st gate conductor

[0268] 15a Gate conductor wiring

[0269] 16 1st gate insulating film

[0270] 171st gate trench

[0271] 181st body area

[0272] 18A 1st connection area

[0273] 18aBoundary between the first and second body parts

[0274] 18a1 1st connection point

[0275] 18a2 Second connection point

[0276] 18b Main junction (PN junction, lower surface of body region)

[0277] 19 1st gate electrode

[0278] 20 transistors (second vertical field effect transistors)

[0279] 21 second source electrode

[0280] Part 22 and 23

[0281] 24 Second source region

[0282] 25 2nd gate conductor

[0283] 26 second gate insulating film

[0284] 27 2nd gate trench

[0285] 28 Second body area

[0286] 28A Second connection area

[0287] 29 second gate electrode

[0288] 30 Metal Layer

[0289] 32 Semiconductor substrate

[0290] 33 Low concentration impurity layer or drift layer

[0291] 34 Interlayer insulation layer

[0292] 35 Passivation layer

[0293] 36 Oxide film

[0294] 40 Semiconductor layer

[0295] 90Boundary line between transistors

[0296] 112 1st active area

[0297] 116 1st source pad

[0298] 119 1st gate pad

[0299] 122 Second active area

[0300] 126 2nd source pad

[0301] 129 2nd gate pad

[0302] 181 Part 1

[0303] 182 Part 2

Claims

1. A semiconductor device, which is a chip size package type semiconductor device capable of face-down mounting, It is characterized in that A vertical field effect transistor is provided, wherein the vertical field effect transistor has: A semiconductor substrate of the first conductivity type, comprising impurities of the first conductivity type; a first conductivity type low concentration impurity layer formed on and in contact with the semiconductor substrate, containing the first conductivity type impurities at a concentration lower than the first conductivity type impurity concentration of the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type, formed in the low-concentration impurity layer; The source region of the first conductivity type is formed in the body region; a gate trench formed from the upper surface of the low-concentration impurity layer to a depth penetrating the body region and reaching a portion of the low-concentration impurity layer, and extending in a first direction parallel to the upper surface of the low-concentration impurity layer; A gate insulating film formed inside the gate trench; as well as a gate conductor formed on the gate insulating film inside the gate trench; When a direction perpendicular to the first direction on the upper surface of the low-concentration impurity layer is defined as a second direction, and a direction perpendicular to both the first direction and the second direction is defined as a third direction, The above body area include: a first body portion, which includes an active region forming a conductive channel in a plan view of the low-concentration impurity layer and has a constant depth from an upper surface of the low-concentration impurity layer; and a second body portion, which is adjacent to the first body portion on the peripheral region side surrounding the active region in the plan view, has a finite length in the second direction and has a certain depth from the upper surface of the low-concentration impurity layer at a position shallower than the depth of the first body portion, The second body portion has, in a cross-section along a plane including the first direction and the third direction, a portion where regions with a relatively high concentration of the second conductivity type impurities and regions with a relatively low concentration of the second conductivity type impurities appear alternately and periodically along the first direction.

2. The semiconductor device according to claim 1, It is characterized in that In a cross-sectional view along a plane including the first direction and the third direction, the second body portion has shallow and deep portions that appear alternately and periodically along the first direction.

3. The semiconductor device according to claim 1, It is characterized in that In a cross-sectional view of a plane including the second direction and the third direction, let the depth of the first body portion be D1 in μm, let the depth of the second body portion in an interval closest to the first body portion in an interval in which the depth of the second body portion is constant be D2 in μm, let the point on the lower surface of the body region where the depth D1 of the first body portion reaches an end and connects to the lower surface of the second body portion be a first connection point, let the point on the lower surface of the second body portion farthest from the first body portion and where the depth D2 reaches an end be a second connection point, In a cross-sectional view taken along a plane including the second direction and the third direction, the depth of the second body portion decreases monotonically in the second direction; The second body portion has: The first section is a section where the depth of the lower surface of the second body portion from the first connection point to the second body portion changes to D2; and a second section where the lower surface of the second body portion changes from the second connection point to the body region to a point where the lower surface ends at the upper surface of the low-concentration impurity layer; When the length from the first connection point in the second direction to the point where the body region reaches the end on the upper surface of the low-concentration impurity layer is L1 in μm, and the length from the second connection point in the second direction to the point where the body region reaches the end on the upper surface of the low-concentration impurity layer is L2 in μm, It is in the relationship of D2>D1×L2 / L1.

4. The semiconductor device according to claim 3, It is characterized in that In a cross-sectional view taken along a plane including the first direction and the third direction, the depth of the shallow portion of the second body portion appearing alternately and periodically in the first direction is d21 in μm, the depth of the deep portion is d22 in μm, and the period is a in μm. In the first direction, a closest section of the second body portion having a depth of d22-(d22-d21) / 4 is substantially equal to a×D2 / D1.

Images