Tracking circuits, analog-to-digital converters and analog-to-digital conversion methods, chips and electronic devices

Abstract

The present disclosure relates to a tracking circuit, an analog-to-digital converter, an analog-to-digital conversion method, a chip, and an electronic device. The tracking circuit is connected to a successive approximation analog-to-digital converter, and is used to track the input signal M times after the successive approximation analog-to-digital converter converts the input signal N times to obtain a conversion result, so as to obtain a tracking result for calibrating the conversion result; wherein the tracking circuit includes a plurality of first branch circuits, each of which includes a first capacitor and a first conversion switch, and each of which includes a control terminal, a first connection terminal, and a plurality of second connection terminals. The tracking circuit of the embodiment of the present disclosure can effectively reduce the quantization error and comparator noise of the successive approximation analog-to-digital converter, thereby improving the accuracy of the successive approximation analog-to-digital converter at a relatively low cost.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a tracking circuit, an analog-to-digital converter, an analog-to-digital conversion method, a chip, and an electronic device. Background Art

[0002] Analog-to-Digital Converter (ADC) realizes the conversion of analog signals to digital signals. It is a key component of the interface between analog systems and digital systems and plays an important role in applications such as consumer electronics and industrial electronics. Successive approximation register analog-to-digital converter (SAR ADC) is an important and widely used analog-to-digital converter architecture. With its advantages such as simple circuit structure and low power consumption, it has been widely used in various systems, such as portable medical devices, artificial intelligence, and autonomous driving. With the continuous development of these application fields, the accuracy requirements for successive approximation register analog-to-digital converters are also getting higher and higher. Summary of the invention

[0003] The present disclosure provides a tracking circuit, an analog-to-digital converter, an analog-to-digital conversion method, a chip, and an electronic device.

[0004] According to one aspect of the present disclosure, a tracking circuit is provided, the tracking circuit being connected to a successive approximation analog-to-digital converter, and being used for tracking an input signal M times after the successive approximation analog-to-digital converter converts an input signal N times to obtain a conversion result, so as to obtain a tracking result for calibrating the conversion result; the tracking circuit comprises a plurality of first branch circuits, each of which comprises a first capacitor and a first conversion switch, and each of which comprises a control terminal, a first connection terminal and a plurality of second connection terminals; wherein the top plate of each first capacitor is connected to the same point, the bottom plate of each first capacitor is connected to the first connection terminal of the first conversion switch in the same first branch circuit, the control terminal of the first conversion switch is connected to a digital logic module of the successive approximation analog-to-digital converter, the first conversion switch is used for selecting a target connection terminal from a plurality of second connection terminals to be connected to the first connection terminal according to a tracking control signal from the digital logic module, and the second connection terminals at the same position in each first conversion switch are connected to the same point.

[0005] In one possible implementation, when the digital-to-analog converter of the successive approximation analog-to-digital converter is top plate sampling, the top plate of each first capacitor is connected to the input signal, the second connection end at the first position in each first conversion switch is connected to a first reference voltage, and the second connection end at the second position in each first conversion switch is connected to a second reference voltage, and the first reference voltage is higher than the second reference voltage.

[0006] In one possible implementation, when the digital-to-analog converter of the successive approximation analog-to-digital converter is bottom plate sampling, the top plate of each first capacitor is connected to a reference voltage, the second connection end at the first position in each first conversion switch is connected to a first reference voltage, the second connection end at the second position in each first conversion switch is connected to a second reference voltage, and the second connection end at the third position in each first conversion switch is connected to the input signal, and the first reference voltage is higher than the second reference voltage.

[0007] In a possible implementation, the digital-to-analog converter includes N or N-1 second branch circuits, each second branch circuit includes a second capacitor and a second conversion switch, each second conversion switch includes a control end, a first connection end and multiple second connection ends, the bottom plate of each second capacitor is connected to the first connection end of the second conversion switch in the same second branch circuit, the top plate of each first capacitor and the top plate of each second capacitor are connected to the same point, the control end of each first conversion switch and the control end of each second conversion switch are connected to the digital logic module of the successive approximation analog-to-digital converter, and the second connection end at the same position in each first conversion switch and the second connection end at the same position in each second conversion switch are connected to the same point.

[0008] In a possible implementation, the tracking circuit includes M first branch circuits, and the capacitance of the first capacitor in each first branch circuit is equal and is determined according to the minimum capacitance of the second capacitor in the digital-to-analog converter of the successive approximation analog-to-digital converter.

[0009] In a possible implementation, the tracking circuit further includes a decoding circuit, the input end of the decoding circuit is connected to the digital logic module of the successive approximation analog-to-digital converter, the output end of the decoding circuit is connected to the control end of each first conversion switch, and the decoding circuit is used to convert the tracking control signal from the digital logic module into a binary digital code, so that each first conversion switch selects a target connection end from a plurality of second connection ends to connect to the first connection end according to the binary digital code; when the decoding circuit exists in the tracking circuit, the tracking circuit includes K first branch circuits, and the capacitance of the first capacitor in any i-th first branch circuit is 2 i-1The product of the value of the second capacitor and the preset value is determined according to the minimum capacitance value of the second capacitor in the digital-to-analog converter of the successive approximation analog-to-digital converter, i is any integer from 1 to K, 2 K-1 Greater than or equal to M.

[0010] According to one aspect of the present disclosure, there is provided an analog-to-digital converter, comprising: a successive approximation analog-to-digital converter, and a tracking circuit as described above, wherein the tracking circuit is connected to the successive approximation analog-to-digital converter, and the analog-to-digital converter is used to: convert an input signal N times by the successive approximation analog-to-digital converter to obtain a conversion result; track the input signal M times by the tracking circuit to obtain a tracking result for calibrating the conversion result; and determine an output result of the analog-to-digital converter based on the conversion result and the tracking result.

[0011] According to one aspect of the present disclosure, there is provided an analog-to-digital conversion method, which is applied to an analog-to-digital converter, the analog-to-digital converter comprising: a successive approximation analog-to-digital converter, and a tracking circuit as described above, the tracking circuit being connected to the successive approximation analog-to-digital converter, the analog-to-digital conversion method comprising: converting an input signal N times by the successive approximation analog-to-digital converter to obtain a conversion result; tracking the input signal M times by the tracking circuit to obtain a tracking result for calibrating the conversion result; and determining an output result of the analog-to-digital converter based on the conversion result and the tracking result.

[0012] According to another aspect of the present disclosure, a chip is provided, wherein the chip includes the tracking circuit as described above.

[0013] According to another aspect of the present disclosure, an electronic device is provided, comprising the tracking circuit as described above.

[0014] In an embodiment of the present disclosure, a tracking circuit is connected to a successive approximation analog-to-digital converter, and is used to track the input signal M times after the successive approximation analog-to-digital converter converts the input signal N times to obtain a conversion result, so as to obtain a tracking result for calibrating the conversion result; the tracking circuit includes a plurality of first branch circuits, each of which includes a first capacitor and a first conversion switch, and each of which includes a control end, a first connection end, and a plurality of second connection ends; wherein the top plate of each first capacitor is connected to the same point, the bottom plate of each first capacitor is connected to the first connection end of the first conversion switch in the same first branch circuit, the control end of the first conversion switch is connected to the digital logic module of the successive approximation analog-to-digital converter, the first conversion switch is used to select a target connection end from the plurality of second connection ends to be connected to the first connection end according to a tracking control signal from the digital logic module, and the second connection end at the same position in each first conversion switch is connected to the same point. The tracking circuit of the embodiment of the present disclosure can effectively reduce the quantization error and comparator noise of the successive approximation analog-to-digital converter, thereby improving the accuracy of the successive approximation analog-to-digital converter at a lower cost.

[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0017] Figure 1 A schematic diagram of the circuit structure of a successive approximation analog-to-digital converter in the related art is shown.

[0018] Figure 2 A schematic diagram of the circuit structure of a digital-to-analog converter in the related art is shown.

[0019] Figure 3 A schematic diagram showing the working process and waveform of a successive approximation analog-to-digital converter in the related art without comparator noise is shown.

[0020] Figure 4 A schematic diagram showing the working process and waveform of a successive approximation analog-to-digital converter in the related art with comparator noise is shown.

[0021] Figure 5 A schematic diagram of a tracking circuit according to an embodiment of the present disclosure is shown.

[0022] Figure 6 A schematic diagram showing another tracking circuit according to an embodiment of the present disclosure is shown.

[0023] Figure 7 A schematic diagram showing another tracking circuit according to an embodiment of the present disclosure is shown.

[0024] Figure 8 A schematic diagram of a digital-to-analog converter and a tracking circuit having N second branch circuits according to an embodiment of the present disclosure is shown.

[0025] Fig. 9 A schematic diagram showing the working process of a tracking circuit according to an embodiment of the present disclosure.

[0026] Fig.10 A schematic diagram of a digital-to-analog converter and a tracking circuit having N-1 second branch circuits according to an embodiment of the present disclosure is shown.

[0027] Fig.11 A schematic diagram showing another tracking circuit with a decoding circuit according to an embodiment of the present disclosure is shown.

[0028] Fig.12 A flow chart of an analog-to-digital conversion method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0029] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0030] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0031] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0032] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0033] Figure 1 A schematic diagram of the circuit structure of a successive approximation analog-to-digital converter in the related art is shown in FIG. Figure 1 As shown, the successive approximation analog-to-digital converter can be composed of a digital-to-analog converter 1 (Digital-to-Analog Converter, DAC), a comparator 2 and a digital logic module 3. The digital-to-analog converter 1 can convert the input signal (for example Figure 1 The differential signal V ip and V in ) for sampling, and receives the conversion control signal of the digital logic module 3; the comparator 2 compares the output voltages of the two digital-to-analog converters 1, and outputs the binary digital codes "0" and "1" to represent the comparison result; the digital logic module 3 processes the output result of the comparator 2, and outputs the conversion result D of the successive approximation analog-to-digital converter. sar , and outputs a conversion control signal for the digital-to-analog converter 1.

[0034] The operations of one comparison by the comparator 2, one data transmission by the digital logic module 3, one difference by the digital-to-analog converter 1 and one reset by the comparator 2 can be called one conversion. Each conversion will output a 1-bit digital code, such as the digital code "0" and "1". The successive approximation analog-to-digital converter converts the data one by one, so that the conversion result D output by the successive approximation analog-to-digital converter is represented by a multi-bit binary digital code. sar , which can approximate the simulated input signal.

[0035] In a successive approximation analog-to-digital converter, the digital-to-analog converter 1 may be composed of a sampling switch and a capacitor array. Figure 2 A schematic diagram of the circuit structure of a digital-to-analog converter 1 in the related art is shown. Figure 2 As shown, two circuit structures of digital-to-analog converters 1 are given. The left part is a digital-to-analog converter 1 for top plate sampling, which may include a sampling switch S and a capacitor array 11_A; the right part is a digital-to-analog converter 1 for bottom plate sampling, which may include a sampling switch S and a capacitor array 11_B. The capacitance values ​​in the capacitor array may be designed in the form of binary weights. For example, for an N-bit successive approximation analog-to-digital converter, the weights of the capacitance values ​​in the digital-to-analog converter 1 are 1, 2, 4, ... 2 respectively. N-1 , wherein the capacitor with the lowest weight is the least significant bit (LSB) capacitor, and the capacitor with the highest weight is the most significant bit (MSB) capacitor. The top plates of all capacitors can be connected together, and the bottom plates of each capacitor can receive the control of the digital logic module 3 and be connected to the corresponding potential.

[0036] like Figure 2As shown in the left part, for the top plate sampling digital-to-analog converter 1, the sampling switch S can be used to collect the input signal V in To the top plate of the capacitor of the capacitor array 11_A, the bottom plate of each capacitor in the capacitor array 11_A can be selectively connected to the first reference voltage V according to the instruction of the digital logic module 3. refp Or the second reference voltage V refn .

[0037] Similar, such as Figure 2 As shown in the right part, for the digital-to-analog converter 1 with bottom-plane sampling, the sampling switch S can be used to collect the reference voltage V cm To the top plate of the capacitor of the capacitor array 11_B, the bottom plate of each capacitor in the capacitor array 11_B can be selectively connected to the first reference voltage V according to the instruction of the digital logic module 3. refp , the second reference voltage V refn 、Input signal V in one of the.

[0038] Among them, the first reference voltage V refp Greater than the second reference voltage V refn , for example, the first reference voltage V refp is the positive reference voltage, the second reference voltage V refn is the negative reference voltage.

[0039] Figure 3 A schematic diagram showing the working process and waveform of a successive approximation analog-to-digital converter in the related art without comparator noise is shown as follows: Figure 3 As shown, the workflow of the successive approximation analog-to-digital converter can be divided into two stages: sampling and conversion. Taking the top plate sampling digital-to-analog converter 1 as an example, in the sampling stage, the input signal (for example Figure 1 The differential signal V ip and V in ) is collected on the top plate of each capacitor in the digital-to-analog converter 1; after the sampling is completed, the comparator 2 compares the voltages on the top plates of the capacitors of the two digital-to-analog converters 1, and the comparison results are processed by the digital logic module 3, and the conversion control signals D are output in sequence. N-1 , D N-2 ...D2, D1, D0 are used to adjust the connection potential of each capacitor bottom plate conversion switch in the digital-to-analog converter 1.

[0040] For example, if the conversion control signal is 1, the capacitor bottom plate can be connected to the first reference voltage V refp If the conversion control signal is -1, the capacitor bottom plate can be connected to the second reference voltage V refnBy controlling the connection potential of the bottom plate of the capacitor in the digital-to-analog converter 1, the voltage of the top plate of each capacitor in the digital-to-analog converter 1 can be adjusted until the differential voltage of the top plates of the capacitors in the two digital-to-analog converters 1 is approached to zero.

[0041] Among them, in the capacitor array of the digital-to-analog converter 1, the adjustment range of each capacitor to the top plate voltage is proportional to the weight of the capacitor. The adjustment range of the most significant bit capacitor is the largest, which can reach the maximum value V ref =V refp -V refn ; After that, the capacitance goes from high to low, and the voltage adjustment range of the top plate of the digital-to-analog converter 1 decreases proportionally.

[0042] The output conversion control signal D N-1 , D N-2 ...D2, D1, and D0 are combined to obtain the digital output signal of the successive approximation analog-to-digital converter, that is, the conversion result D sar , which can be expressed as

[0043] Without considering errors such as comparator noise, after N conversions, the absolute value of the differential voltage on the top plate of the capacitor in the DAC 1 will be less than the error value V ref / 2 N , where V ref is the first reference voltage V refp and the second reference voltage V refn The error value also represents the quantization error of the successive approximation analog-to-digital converter, such as Figure 3 As shown, the quantization error indicates the highest accuracy that the successive approximation analog-to-digital converter can achieve, that is, the quantization accuracy. For an N-bit successive approximation analog-to-digital converter, its quantization accuracy SQNR = 6.02×N+1.76 dB. To improve the quantization accuracy, it is necessary to increase the number of bits of the capacitor array in the digital-to-analog converter 1. However, the area and complexity of the capacitor array are exponentially related to the number of bits N. To increase the quantization accuracy by 6 dB, it is necessary to add a highest-bit capacitor to the digital-to-analog converter 1, for example, the weights of the capacitor values ​​are 1, 2, 4...2 respectively. N-1 In the case of N The area and complexity of the DAC 1 will increase by two times if the capacitors are added, which limits the number of bits of the successive approximation DAC. Considering the hardware cost, the capacitor array of the DAC 1 is mostly below 12 bits.

[0044] In addition, even without considering the area and complexity of the DAC 1, the accuracy of the SAR ADC cannot be increased indefinitely. When the number of bits of the SAR ADC increases to a certain extent, the comparator noise will become an important factor limiting the accuracy of the SAR ADC.

[0045] Figure 4 A schematic diagram showing the working process and waveform of a successive approximation analog-to-digital converter in the related art with comparator noise is shown. Figure 4 As shown in the figure, the gray area represents the noise of the comparator. When the differential voltage of the capacitor top plate in the digital-to-analog converter 1 enters the range of the comparator noise, the comparison result will be wrong with a certain probability. Figure 4 As shown, when the D0 bit is converted, due to the existence of comparator noise, the comparison is wrong, which will lead to a large error. In this case, the accuracy of the successive approximation analog-to-digital converter will be limited by the noise of the comparator. Continuing to increase the number of bits of the capacitor array in the digital-to-analog converter 1 will not improve the accuracy of the successive approximation analog-to-digital converter. If the noise of the comparator is to be reduced, the power consumption of the comparator 2 needs to be greatly increased. For example, to reduce the comparator noise by 6 decibels, the power consumption of the comparator 2 needs to be increased by 4 times.

[0046] It can be seen that, limited by the problems of quantization error and comparator noise, the accuracy that can be achieved by the successive approximation analog-to-digital converter has a large room for improvement. To reduce the quantization error of the successive approximation analog-to-digital converter, it is necessary to increase the number of bits of the capacitor array in the digital-to-analog converter 1. However, the area and complexity of the capacitor array are exponentially related to the number of bits. For example, to reduce the quantization error by 6 decibels, the most significant bit capacitor will be added to the capacitor array of the digital-to-analog converter 1, and the area and complexity of the digital-to-analog converter 1 will increase by two times. Correspondingly, to reduce the comparator noise, it is necessary to greatly increase the power consumption of the comparator 2. For example, to reduce the comparator noise by 6 decibels, the power consumption of the comparator 2 will increase by 4 times. These two solutions to improve the accuracy of the successive approximation analog-to-digital converter are both relatively expensive and inefficient.

[0047] In view of this, an embodiment of the present disclosure provides a tracking circuit. Figure 1 The successive approximation analog-to-digital converter shown is added with a tracking circuit. After the successive approximation analog-to-digital converter converts the input signal N times to obtain a conversion result, the tracking circuit can be used to track the input signal M times to obtain a tracking result. The tracking result can be used to calibrate the conversion result, thereby more efficiently improving the accuracy of the successive approximation analog-to-digital converter. Adding a tracking circuit to the successive approximation analog-to-digital converter can reduce comparator noise and quantization error at the same time. Compared with the solution of increasing the number of bits of the capacitor array in the digital-to-analog converter 1 and increasing the power consumption of the comparator in the related art, the area, complexity and power consumption costs brought by the tracking circuit are very low.

[0048] Figure 5 A schematic diagram of a tracking circuit according to an embodiment of the present disclosure is shown. Figure 5As shown, the tracking circuit 4 is connected to a successive approximation analog-to-digital converter, which may include a digital-to-analog converter 1, a comparator 2 and a digital logic module 3. The successive approximation analog-to-digital converter is used to convert an input signal (e.g. Figure 5 The differential signal V ip and V in ) Perform N conversions to obtain the conversion result D sar , the conversion result D sar A multi-bit digital code.

[0049] In the example, the input signal can be any analog voltage to be converted into a multi-bit digital code, such as temperature, light, humidity, pressure, speed, position, distance, quantity, electrocardiogram, radio frequency, audio, radio and other signals collected by an analog circuit system or sensor. The embodiments of the present disclosure do not limit the source and category of the input signal.

[0050] In the example, the operations of one comparison by the comparator 2, one data transfer by the digital logic module 3, one difference by the digital-to-analog converter 1 and one reset of the comparator 2 can be referred to as one conversion, and each conversion will output a 1-bit digital code.

[0051] like Figure 5 As shown, the tracking circuit 4 is used to convert the input signal N times in the successive approximation analog-to-digital converter to obtain a conversion result D sar Afterwards, the input signal is tracked M times to obtain the conversion result D for calibration. sar The tracking results of D track For example, the digital logic module 3 of the successive approximation analog-to-digital converter can be based on the conversion result D sar and tracking results D track , determine the output result D after calibration out =D sar +D track , where the calibrated output result D out The accuracy is higher than the conversion result D sar .

[0052] like Figure 5 As shown, the tracking circuit 4 includes a plurality of first branch circuits, each of which includes a first capacitor and a first conversion switch, and each of which includes a control terminal, a first connection terminal, and a plurality of second connection terminals. For example, the first conversion switch may be a single-pole multi-throw switch, and the number of multi-throws is the same as the number of second connection terminals. If the first conversion switch includes two second connection terminals, the first conversion switch may be a single-pole double-throw switch; if the first conversion switch includes three second connection terminals, the first conversion switch may be a single-pole three-throw switch. The embodiments of the present disclosure do not specifically limit the specific form of the first conversion switch.

[0053] Among them, the top plate of each first capacitor is connected to the same point, the bottom plate of each first capacitor is connected to the first connection end of the first conversion switch in the same first branch circuit, the control end of the first conversion switch is connected to the digital logic module 3 of the successive approximation analog-to-digital converter, and the first conversion switch is used to select a target connection end from multiple second connection ends to connect to the first connection end according to a tracking control signal from the digital logic module 3, and the second connection ends at the same position in each first conversion switch are connected to the same point.

[0054] The number of first branch circuits included in the tracking circuit 4 is proportional to the number of tracking times M performed on the input signal. The more the number of first branch circuits is, the more the number of tracking times M performed on the input signal is.

[0055] Optionally, the digital-to-analog converter 1 of the successive approximation analog-to-digital converter may be a top plate sampling or a bottom plate sampling. In the case where the digital-to-analog converter 1 of the successive approximation analog-to-digital converter is a top plate sampling, the first conversion switch of the tracking circuit 4 may include two second connection terminals, and in the case where the digital-to-analog converter 1 of the successive approximation analog-to-digital converter is a bottom plate sampling, the first conversion switch of the tracking circuit 4 may include three second connection terminals.

[0056] In the example, Figure 6 A schematic diagram showing another tracking circuit according to an embodiment of the present disclosure is shown. Figure 6 As shown, in the case where the DAC 1 of the successive approximation ADC is top plate sampling, the top plate of each first capacitor is connected to the input signal V in The second connection terminal at the first position of each first conversion switch is connected to the first reference voltage V refp The second connection terminal at the second position of each first conversion switch is connected to the second reference voltage V refn , the first reference voltage V refp Greater than the second reference voltage V refn .

[0057] In this way, the sampling switch S can be used to collect the input signal V in To the top plate of each first capacitor, the bottom plate of each first capacitor can be selectively connected to the first reference voltage V according to the instruction of the tracking control signal output by the digital logic module 3. refp Or the second reference voltage V refn , in order to achieve the input signal V in Multiple tracking.

[0058] In the example, Figure 7 A schematic diagram showing another tracking circuit according to an embodiment of the present disclosure is shown. Figure 7As shown, in the case where the DAC 1 of the successive approximation ADC is bottom plate sampling, the top plate of each first capacitor is connected to a reference voltage V cm The second connection terminal at the first position of each first conversion switch is connected to the first reference voltage V refp The second connection terminal at the second position of each first conversion switch is connected to the second reference voltage V refn The second connection end at the third position of each first conversion switch is connected to the input signal V in , the first reference voltage V refp Greater than the second reference voltage V refn .

[0059] In this way, the sampling switch S can be used to collect the reference voltage V cm To the top plate of each first capacitor, the bottom plate of each first capacitor can be selectively connected to the first reference voltage V according to the instruction of the tracking control signal output by the digital logic module 3. refp , the second reference voltage V refn 、Input signal V in One of the input signals V in Multiple tracking.

[0060] Among them, the first reference voltage V refp Greater than the second reference voltage V refn , for example, the first reference voltage V refp is the positive reference voltage, the second reference voltage V refn is a negative reference voltage. In the embodiment of the present disclosure, the first reference voltage V refp and the second reference voltage V refn There is no restriction on the specific value of .

[0061] In a possible implementation, the digital-to-analog converter 1 includes N or N-1 second branch circuits, each second branch circuit includes a second capacitor and a second conversion switch, each second conversion switch includes a control end, a first connection end and multiple second connection ends, the bottom plate of each second capacitor is connected to the first connection end of the second conversion switch in the same second branch circuit, the top plate of each first capacitor and the top plate of each second capacitor are connected to the same point, the control end of each first conversion switch and the control end of each second conversion switch are connected to the digital logic module 3 of the successive approximation analog-to-digital converter, and the second connection end at the same position in each first conversion switch and the second connection end at the same position in each second conversion switch are connected to the same point.

[0062] Taking the DAC 1 of the successive approximation ADC as an example for top plate sampling, Figure 8 FIG. 1 is a schematic diagram showing a digital-to-analog converter 1 having N second branch circuits and a tracking circuit 4 according to an embodiment of the present disclosure. It should be understood that Figure 8 This is an example of top plate sampling. The principle of bottom plate sampling is similar to that of top plate sampling. Please refer to the relevant introduction of top plate sampling, which will not be repeated here.

[0063] like Figure 8 As shown, the digital-to-analog converter 1 may include a sampling switch S and a capacitor array 11_A, the capacitor array 11_A may include N second branch circuits, each second branch circuit includes a second capacitor and a second conversion switch, each second conversion switch includes a control end, a first connection end and two second connection ends, and the bottom plate of each second capacitor is connected to the first connection end of the second conversion switch in the same second branch circuit.

[0064] The sampling switch S may be one or more of various types of switch devices such as a relay, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a silicon carbide (SiC) power tube, etc., which are not listed one by one in the embodiments of the present disclosure. The sampling switch S may include a first electrode, a second electrode and a control electrode, wherein the control electrode is used to control the closing or opening of the sampling switch.

[0065] The tracking circuit 4 includes M first branch circuits, each of which includes a first capacitor and a first conversion switch, each of which includes a control terminal, a first connection terminal and two second connection terminals, and the bottom plate of each first capacitor is connected to the first connection terminal of the first conversion switch in the same first branch circuit. The capacitance of the first capacitor in each first branch circuit is equal, which is determined according to the minimum capacitance value of the second capacitor in the digital-to-analog converter 1 of the successive approximation analog-to-digital converter. For example, the capacitance values ​​of the N second capacitors in the digital-to-analog converter 1 are 1, 2, 4...2 respectively. N-1 , the minimum capacitance value of the second capacitor in the digital-to-analog converter 1 is 1, and the capacitance value of the first capacitor in each first branch circuit can be set to 1.

[0066] The top plate of each first capacitor and the top plate of each second capacitor are connected to the same point, which is also connected to a sampling switch S, and the sampling switch S can be used to collect the input signal V in To the capacitor top plate of each first capacitor and each second capacitor.

[0067] The control end of each first conversion switch and the control end of each second conversion switch are connected to the digital logic module 3 of the successive approximation analog-to-digital converter, and the second connection end at the first position of each first conversion switch and the second connection end at the first position of each second conversion switch are connected to the same point for connecting the first reference voltage V refp The second connection end at the second position of each first conversion switch and the second connection end at the second position of each second conversion switch are connected to the same point for connecting the second reference voltage V refn .

[0068] In this way, the control terminals of the N second conversion switches can receive the conversion control signals D0 to D1 from the digital logic module 3. N-1 , and according to the conversion control signal D0~D N-1 The first connection terminal of each second conversion switch is selected by the indication of whether to connect the second connection terminal at the first position of the second conversion switch or the second connection terminal at the second position, so as to realize that the bottom plates of the N second capacitors are selected to connect the first reference voltage V refp Or the second reference voltage V refn , complete the input signal V in N conversions.

[0069] For example, for the first conversion, if the conversion control signal D0 is 1, the bottom plate of the second capacitor with a capacitance value of 1 is selected to connect to the first reference voltage V refp If the conversion control signal D0 is 0, the bottom plate of the second capacitor with a capacitance value of 1 is selected to connect to the second reference voltage V refn ;

[0070] Similarly, for the second conversion, if the conversion control signal D1 is 1, the bottom plate of the second capacitor with a capacitance value of 2 is selected to connect to the first reference voltage V refp If the conversion control signal D1 is 0, the bottom plate of the second capacitor with a capacitance value of 2 is selected to connect to the second reference voltage V refn ;

[0071] Similarly, for the Nth conversion, if the conversion control signal D N-1 is 1, the capacitance value is 2 N-1 The bottom plate of the second capacitor is selected to connect the first reference voltage V refp , if the conversion control signal D N-1 is 0, the capacitance value is 2 N-1 The bottom plate of the second capacitor is selected to connect the second reference voltage V refn .

[0072] Then, the control terminals of the M first conversion switches can receive the tracking control signals T1 to T2 from the digital logic module 3. M, and according to the tracking control signal T1~T M The indication of the first connection terminal of each first conversion switch is selected to connect the second connection terminal at the first position of the first conversion switch or the second connection terminal at the second position, so as to realize that the bottom plates of the M first capacitors are selected to connect the first reference voltage V refp Or the second reference voltage V refn , complete the input signal V in M tracking times.

[0073] For example, for the first tracking, if the tracking control signal T1 is 1, Figure 8 The bottom plate of the first capacitor on the left side is connected to the first reference voltage V refp , if the tracking control signal T1 is 0, Figure 8 The bottom plate of the first capacitor on the left side is connected to the second reference voltage V refn ;

[0074] Similarly, for the second tracking, if the tracking control signal T2 is 1, Figure 8 The bottom plate of the second first capacitor on the left side is connected to the first reference voltage V refp , if the tracking control signal T2 is 0, Figure 8 The bottom plate of the second first capacitor on the left side is connected to the second reference voltage V refn ;

[0075] Similarly, for the Mth tracking, if the tracking control signal T M is 1, Figure 8 The bottom plate of the first capacitor on the right side is connected to the first reference voltage V refp , if the tracking control signal T M is 0, Figure 8 The bottom plate of the first capacitor on the right side is connected to the second reference voltage V refn .

[0076] Fig. 9 A schematic diagram showing the working process of the tracking circuit according to an embodiment of the present disclosure is shown as follows: Fig. 9 As shown, after N conversions are completed, M tracking will continue. During the conversion phase, due to the existence of comparator noise, some bits may have comparison errors, such as Fig. 9 A comparison error occurs at the D0 bit in the DAC, resulting in a large conversion error. In the following tracking phase, N trackings can still maintain the differential voltage of the capacitor top plate in the DAC 1 near 0. Due to the existence of comparator noise, comparison errors may also occur in the tracking phase, but the comprehensive results generated by multiple trackings can greatly reduce the impact of comparator noise.

[0077] like Figure 5As shown, the successive approximation analog-to-digital converter of the tracking circuit 4 is added, and its output result D out =D sar +D track ,in, is the conversion result generated by N conversions, D track is the tracking result generated by M tracking times, and the tracking result D track It is composed of tracking control signals T1, T2, T3...T M-1 , T M The combined results produced.

[0078] The following is the tracking result D track The derivation method can be used to res To represent the top plate differential voltage of the second capacitor in the digital-to-analog converter 1 after N conversions are completed, the top plate differential voltage V res =V ip -V in -1 / W·D sar Among them, the differential signal V ip and V in is the input signal of the successive approximation analog-to-digital converter, W is the gain factor of the digital-to-analog converter 1, for example, W = 2 N , D track It is the tracking result generated by M tracking times.

[0079] The purpose of M tracking is to calculate the top plate differential voltage V res Further fine conversion is performed. The comparator noise at each comparison during tracking can be represented by n(1), n(2), ..., n(M), and the quantization error at each comparison during tracking can be represented by q(1), q(2), ..., q(M). The power of the comparator noise and the quantization error are n respectively. 2 and q 2 .

[0080] Before the first tracking comparison, the input voltage of the comparator is the top plate differential voltage V res , is the residual voltage after N conversions, which can be expressed as:

[0081]

[0082] In formula (1), V ip and V in The input signal of the successive approximation analog-to-digital converter is in the form of a differential signal, D sar is the conversion result generated by N conversions, D i In the conversion phase, the successive approximation analog-to-digital converter converts the 1-bit conversion control signal output by the digital logic module 3 for the i-th time, and W is the gain coefficient of the digital-to-analog converter 1, for example, W=2 N, which represents the proportional coefficient when the digital output is converted to the analog input.

[0083] During the first tracking comparison, under the influence of comparator noise, the output digital result is T1, and the signal equation can be established, namely:

[0084] V res +n(1)+q(1)=1 / W·T1 (2)

[0085] In formula (2), n(1) represents the comparator noise during the first tracking, q(1) represents the quantization error of comparator 2 during the first tracking, and V res represents the top plate differential voltage during the first tracking, T1 represents the 1-bit tracking control signal output by the digital-to-analog converter 1 during the first tracking, and W is the gain coefficient of the digital-to-analog converter 1.

[0086] Before the second tracking comparison, since the result of the first tracking is fed back to the DAC 1, the input voltage of the comparator 2 becomes V res -T1 / W. During the second tracking comparison, under the influence of comparator noise, the output digital result is T2, and the signal equation can be established, namely:

[0087] V res -T1 / W +n(2)+q(2)=1 / W·T2 (3)

[0088] In formula (3), n(2) represents the comparator noise during the second tracking, q(2) represents the quantization error of comparator 2 during the second tracking, and V res represents the top plate differential voltage during the second tracking, T1 represents the 1-bit tracking control signal output by the digital-to-analog converter 1 during the first tracking, T2 represents the 1-bit tracking control signal output by the digital-to-analog converter 1 during the second tracking, and W is the gain coefficient of the digital-to-analog converter 1.

[0089] Similarly, the signal equation that can be established by the third tracking comparison is:

[0090] V res -(T1+T2) / W+n(3)+q(3)=1 / W·T3 (4)

[0091] In formula (4), n(3) represents the comparator noise during the third tracking, q(3) represents the quantization error of comparator 2 during the third tracking, and V res It represents the top plate differential voltage during the third tracking, T1 represents the 1-bit tracking control signal output by the digital-to-analog converter 1 during the first tracking, T2 represents the 1-bit tracking control signal output by the digital-to-analog converter 1 during the second tracking, T3 represents the 1-bit tracking control signal output by the digital-to-analog converter 1 during the third tracking, and W is the gain coefficient of the digital-to-analog converter 1.

[0092] And so on, until the Mth tracking comparison, the signal equation that can be established is:

[0093]

[0094] In formula (5), n(M) represents the comparator noise during the Mth tracking, q(M) represents the quantization error of comparator 2 during the Mth tracking, and V res represents the top plate differential voltage at the Mth tracking, T i represents the 1-bit tracking control signal output by the digital-to-analog converter 1 for the i-th tracking, and W is the gain coefficient of the digital-to-analog converter 1.

[0095] By summing up the above signal equations, we can get the expression:

[0096]

[0097] In formula (6), M represents the number of tracking times, n(i) represents the comparator noise during the i-th tracking, q(i) represents the quantization error of comparator 2 during the i-th tracking, and V res represents the top plate differential voltage at the Mth tracking, T k represents the 1-bit tracking control signal output by the digital-to-analog converter 1 for the kth tracking, and W is the gain coefficient of the digital-to-analog converter 1.

[0098] Then we can get:

[0099]

[0100] In formula (7), W is the gain factor of the digital-to-analog converter 1, V ip and V in is the differential input signal of the successive approximation analog-to-digital converter, M represents the number of tracking times, n(i) represents the comparator noise during the i-th tracking, represents the comparator noise after M tracking comparisons, q(i) represents the quantization error of comparator 2 comparison during the i-th tracking, represents the quantization error after M tracking comparisons, T k represents the 1-bit tracking control signal output by the digital-to-analog converter 1 for the k-th tracking, The tracking result D generated by M tracking track , The output result D of the successive approximation analog-to-digital converter with tracking circuit 4 added out .

[0101] According to formula (7), after M tracking comparisons, the power of the comparator noise is reduced by M times, that is:

[0102]

[0103] In formula (8), M represents the number of tracking times, n(i) represents the noise of the comparator during the i-th tracking, represents the power of the comparator noise after M tracking times, n 2 represents the power of the comparator noise when M tracking is not performed.

[0104] Similarly, after M tracking comparisons, the power of the quantization error of the successive approximation analog-to-digital converter is also reduced by M times, that is:

[0105]

[0106] In formula (9), M represents the number of tracking times, q(i) represents the quantization error of the successive approximation analog-to-digital converter during the i-th tracking, = represents the power of the quantization error of the successive approximation analog-to-digital converter after M tracking times, q 2 Represents the power of the successive approximation ADC quantization error without performing M trackings.

[0107] According to formula (8) and formula (9), if the tracking comparison is performed four times, the comparator noise and quantization error can be reduced by 6 dB (4 times), at the cost of only adding four least significant bit capacitors and slightly increasing the working time of the successive approximation analog-to-digital converter. The cost of power consumption, area and circuit complexity is very low.

[0108] Fig.10 FIG. 1 is a schematic diagram of a digital-to-analog converter and a tracking circuit having N-1 second branch circuits according to an embodiment of the present disclosure. It should be understood that Fig.10 This is an example of top plate sampling. The principle of bottom plate sampling is similar to that of top plate sampling. Please refer to the relevant introduction of top plate sampling, which will not be repeated here.

[0109] like Fig.10 As shown, the digital-to-analog converter 1 may include a sampling switch S and a capacitor array 11_A, the capacitor array 11_A may include N-1 second branch circuits, each second branch circuit includes a second capacitor and a second conversion switch, each second conversion switch includes a control end, a first connection end and two second connection ends, and the bottom plate of each second capacitor is connected to the first connection end of the second conversion switch in the same second branch circuit.

[0110] The tracking circuit 4 includes M first branch circuits, each of which includes a first capacitor and a first conversion switch, each of which includes a control terminal, a first connection terminal and two second connection terminals, and the bottom plate of each first capacitor is connected to the first connection terminal of the first conversion switch in the same first branch circuit. The capacitance of the first capacitor in each first branch circuit is equal, which is determined according to the minimum capacitance of the second capacitor in the digital-to-analog converter 1 of the successive approximation analog-to-digital converter. For example, the capacitance values ​​of the N-1 second capacitors in the digital-to-analog converter 1 are 2, 4, ..., 2 respectively. N-1 The minimum capacitance value of the second capacitor in the digital-to-analog converter 1 is 2, and the capacitance value of the first capacitor in each first branch circuit can be set to half of the minimum capacitance value 2, that is, the capacitance value of the first capacitor in each first branch circuit is set to 1.

[0111] The top plate of each first capacitor and the top plate of each second capacitor are connected to the same point, which is also connected to a sampling switch S, and the sampling switch S can be used to collect the input signal V in To the capacitor top plate of each first capacitor and each second capacitor.

[0112] The control end of each first conversion switch and the control end of each second conversion switch are connected to the digital logic module 3 of the successive approximation analog-to-digital converter, and the second connection end at the first position of each first conversion switch and the second connection end at the first position of each second conversion switch are connected to the same point for connecting the first reference voltage V refp The second connection end at the second position of each first conversion switch and the second connection end at the second position of each second conversion switch are connected to the same point for connecting the second reference voltage V refn .

[0113] In this way, the control terminals of the N-1 second conversion switches can receive the conversion control signals D1 to D2 from the digital logic module 3. N-1 , and according to the conversion control signal D1~D N-1 The indication of the first connection terminal of each second conversion switch is selected to connect the second connection terminal at the first position of the second conversion switch or the second connection terminal at the second position, so as to realize that the bottom plates of N-1 second capacitors are selected to connect the first reference voltage V refp Or the second reference voltage V refn , complete the input signal V in N-1 conversions. Among them, when the input signal V in After N-1 real conversions are performed, the last Nth conversion may be a preset default value. In fact, the Nth conversion is not really performed, but D0 is defaulted to 0, or D0 is 1, so that the last least significant bit capacitor in the capacitor array 11_A can be omitted, which has almost no effect on the result.

[0114] Then, the control terminals of the M first conversion switches can receive the tracking control signals T1 to T2 from the digital logic module 3. M , and according to the tracking control signal T1~T M The indication of the first connection terminal of each first conversion switch is selected to connect the second connection terminal at the first position of the first conversion switch or the second connection terminal at the second position, so as to realize that the bottom plates of the M first capacitors are selected to connect the first reference voltage V refp Or the second reference voltage V refn , complete the input signal V in M tracking times.

[0115] It can be seen that the comparison Figure 8 , omitting the least significant bit capacitor of the last bit in the capacitor array 11_A has almost no effect on the result. The rest of the operation process and results are consistent with the above scheme and will not be repeated here.

[0116] Fig.11 FIG. 2 is a schematic diagram showing another tracking circuit with a decoding circuit according to an embodiment of the present disclosure. It should be understood that Fig.11 This is an example of top plate sampling. The principle of bottom plate sampling is similar to that of top plate sampling. Please refer to the relevant introduction of top plate sampling, which will not be repeated here.

[0117] like Fig.11 As shown, the digital-to-analog converter 1 may include a sampling switch S and a capacitor array 11_A, the capacitor array 11_A may include N-1 second branch circuits, each second branch circuit includes a second capacitor and a second conversion switch, each second conversion switch includes a control terminal, a first connection terminal and two second connection terminals, and the bottom plate of each second capacitor is connected to the first connection terminal of the second conversion switch in the same second branch circuit. It should be understood that Fig.11 Taking the capacitor array 11_A including N-1 second branch circuits as an example, the capacitor array 11_A may also include N second branch circuits, that is, except for the weights of the capacitance values ​​being 2, 4, ..., 2 respectively. N-1 , a second branch circuit with a capacitance value having a weight of 1 may also be added, and the present disclosure does not impose any specific limitation on this.

[0118] The tracking circuit 4 includes K first branch circuits, each of which includes a first capacitor and a first conversion switch, each of which includes a control end, a first connection end and two second connection ends, and the bottom plate of each first capacitor is connected to the first connection end of the first conversion switch in the same first branch circuit.

[0119] The top plate of each first capacitor and the top plate of each second capacitor are connected to the same point, which is also connected to a sampling switch S, and the sampling switch S can be used to collect the input signal Vin To the capacitor top plate of each first capacitor and each second capacitor.

[0120] The control end of each first conversion switch and the control end of each second conversion switch are connected to the digital logic module 3 of the successive approximation analog-to-digital converter, and the second connection end at the first position of each first conversion switch and the second connection end at the first position of each second conversion switch are connected to the same point for connecting the first reference voltage V refp The second connection end at the second position of each first conversion switch and the second connection end at the second position of each second conversion switch are connected to the same point for connecting the second reference voltage V refn .

[0121] In this way, the control terminals of the N-1 second conversion switches can receive the conversion control signals D1 to D2 from the digital logic module 3. N-1 , and according to the conversion control signal D1~D N-1 The indication of the first connection terminal of each second conversion switch is selected to connect the second connection terminal at the first position of the second conversion switch or the second connection terminal at the second position, so as to realize that the bottom plates of N-1 second capacitors are selected to connect the first reference voltage V refp Or the second reference voltage V refn , complete the input signal V in N-1 conversions. Among them, when the input signal V in After N-1 real conversions are performed, the last Nth conversion may be a preset default value. In fact, the Nth conversion is not really performed, but D0 is defaulted to 0, or D0 is 1, so that the last least significant bit capacitor in the capacitor array 11_A can be omitted, which has almost no effect on the result.

[0122] The tracking circuit 4 also includes a decoding circuit, the input end of the decoding circuit is connected to the digital logic module 3 of the successive approximation analog-to-digital converter, the output end of the decoding circuit is connected to the control end of each first conversion switch, and the decoding circuit is used to convert the tracking control signals T1 to T2 from the digital logic module 3 M Convert to binary code B k- 1B k ...B2B1B0, so that each first conversion switch is configured according to the binary digital code B k-1 B k ...B2B1B0, selecting a target connection end from a plurality of second connection ends to connect to the first connection end;

[0123] When the decoding circuit exists in the tracking circuit 4, the tracking circuit 4 includes K first branch circuits, and the capacitance of the first capacitor in any i-th first branch circuit is 2 i-1The product of the value of the second capacitor and the preset value is determined according to the minimum capacitance value of the second capacitor in the digital-to-analog converter 1 of the successive approximation analog-to-digital converter, i is any integer from 1 to K, 2 K-1 Greater than or equal to M.

[0124] For example, the capacitance values ​​of the N-1 second capacitors in the digital-to-analog converter 1 are 2, 4, ..., 2 respectively. N-1 , the minimum capacitance value of the second capacitor in the digital-to-analog converter 1 is 2, and the preset value can be half of the minimum capacitance value 2, that is, the preset value is 1. The capacitance value of the first capacitor in the first branch circuit of the first (i=1) is 2 1-1 The product of the preset value 1 is 1, and the capacitance of the first capacitor in the second (i=2) first branch circuit is 2 2-1 The product of the preset value 1 is 2, and so on, the capacitance of the first capacitor in the Kth (i=K) first branch circuit is 2 K-1 The product of the preset value 1 and 2 K-1 Thus, the capacitance values ​​of the N first capacitors in the tracking circuit 4 are 1, 2, 4, ..., 2 respectively. K-1 .

[0125] In this way, the control terminals of the K first conversion switches can be controlled according to the tracking control signals T1 to T M Converted binary code B k-1 B k ...B2B1B0 indicates that the first connection terminals of the K first conversion switches are selected to be connected to the second connection terminals at the first position of the first conversion switches or to the second connection terminals at the second position, thereby realizing that the bottom plates of the K first capacitors are selectively connected to the first reference voltage V refp Or the second reference voltage V refn , complete the input signal V in M tracking times.

[0126] For example, assuming that M is 16 and K is 4, if the first tracking control signal T1 is 1 and B3B2B1B0 is 0001, that is, the first capacitor with a capacitance of 1 is connected to the first reference voltage V refp , the other three first capacitors are connected to the second reference voltage V refn ; If the 16th tracking control signal T 16 is 1, B3B2B1B0 is 1111, that is, each first capacitor is connected to the first reference voltage V refp .

[0127] In this way, a smaller number of first capacitors can be used to implement the tracking circuit 4, effectively reducing the quantization error and comparator noise of the analog-to-digital converter, thereby improving the accuracy, with very low costs in terms of area, complexity and power consumption.

[0128] In one possible implementation, Figure 5 As shown, the analog-to-digital converter includes a successive approximation analog-to-digital converter and a tracking circuit 4, wherein the tracking circuit 4 is connected to the successive approximation analog-to-digital converter, and the analog-to-digital converter is used to: Figure 5 The differential signal V ip and V in ) performs N conversions to obtain a conversion result; tracks the input signal M times through the tracking circuit 4 to obtain a tracking result for calibrating the conversion result; determines the output result D of the analog-to-digital converter according to the conversion result and the tracking result out .

[0129] By using an analog-to-digital converter with a tracking circuit 4, after multiple conversions of a successive approximation analog-to-digital converter are completed, the quantization error and comparator noise of the analog-to-digital converter can be effectively reduced by continuing to perform several bit tracking conversions, thereby improving the accuracy, and the costs of area, complexity and power consumption are very low.

[0130] The output of the analog-to-digital converter is D out It can be expressed as:

[0131]

[0132] In formula (10), D out represents the output of the digital converter, Indicates the conversion result of the successive approximation analog-to-digital converter, N indicates the number of conversions, D i Indicates that in the conversion phase, the successive approximation analog-to-digital converter converts the 1-bit conversion control signal output by the digital logic module 3 for the i-th time; Indicates the tracking result, T k Represents the result of each tracking comparison, and M is the number of tracking comparisons.

[0133] It can be understood that the above-mentioned various embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not go into details.

[0134] Fig.12 A flowchart of an analog-to-digital conversion method according to an embodiment of the present disclosure is shown. The analog-to-digital conversion method is applied to Figure 5 The analog-to-digital converter shown in the figure comprises: a successive approximation analog-to-digital converter and a tracking circuit 4, wherein the tracking circuit 4 is connected to the successive approximation analog-to-digital converter. Fig.12 As shown, the analog-to-digital conversion method includes:

[0135] In step S11, the successive approximation analog-to-digital converter performs N conversions on the input signal to obtain a conversion result;

[0136] In step S12, the input signal is tracked M times by the tracking circuit 4 to obtain a tracking result for calibrating the conversion result;

[0137] In step S13, the output result of the analog-to-digital converter is determined according to the conversion result and the tracking result.

[0138] According to another aspect of the present disclosure, a chip is provided, the chip comprising the tracking circuit 4 as described above.

[0139] According to another aspect of the present disclosure, an electronic device is provided, the electronic device comprising the tracking circuit 4 as described above. The electronic device may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc., and the present disclosure does not limit this.

[0140] Based on the same concept, the present application also provides a terminal device, including a shell, a processor, a memory and the analog-to-digital converter with a tracking circuit 4 described in the above embodiment, the processor and the memory are arranged in the shell, the memory is coupled to the processor, the analog-to-digital converter with a tracking circuit 4 is used to convert an analog signal into a digital signal, and input the digital signal to the processor; the processor is used to process the digital signal.

[0141] The terminal device may be a mobile phone, tablet computer, television, display, laptop, user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, vehicle-mounted device, wearable device, or any other product or component with data processing function. Other essential components of the terminal device should be understood by ordinary technicians in the field, and will not be elaborated here, nor should they be used as limitations to this application.

[0142] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0143] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0144] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0145] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0146] It can be understood that the above-mentioned embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned scheme of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0147] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0148] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0149] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A tracking circuit, characterized in that: The tracking circuit is connected to a successive approximation analog-to-digital converter, and is used to track the input signal M times after the successive approximation analog-to-digital converter converts the input signal N times to obtain a conversion result, so as to obtain a tracking result for calibrating the conversion result; The tracking circuit includes a plurality of first branch circuits, each of which includes a first capacitor and a first conversion switch, and each of which includes a control terminal, a first connection terminal, and a plurality of second connection terminals; Wherein, the top plate of each first capacitor is connected to the same point, the bottom plate of each first capacitor is connected to the first connection end of the first conversion switch in the same first branch circuit, the control end of the first conversion switch is connected to the digital logic module of the successive approximation analog-to-digital converter, the first conversion switch is used to select a target connection end from a plurality of second connection ends to connect to the first connection end according to a tracking control signal from the digital logic module, and the second connection ends at the same position in each first conversion switch are connected to the same point; Wherein, the digital-to-analog converter of the successive approximation analog-to-digital converter comprises N or N-1 second branch circuits, each second branch circuit comprises a second capacitor and a second conversion switch, each second conversion switch comprises a control end, a first connection end and a plurality of second connection ends, the bottom plate of each second capacitor is connected to the first connection end of the second conversion switch in the same second branch circuit, the top plate of each first capacitor and the top plate of each second capacitor are connected to the same point, the control end of each first conversion switch and the control end of each second conversion switch are connected to the digital logic module of the successive approximation analog-to-digital converter, and the second connection end at the same position in each first conversion switch and the second connection end at the same position in each second conversion switch are connected to the same point; The tracking circuit includes M first branch circuits, and the capacitance of the first capacitor in each first branch circuit is equal and is determined according to the minimum capacitance of the second capacitor in the digital-to-analog converter of the successive approximation analog-to-digital converter.

2. The tracking circuit according to claim 1, characterized in that: When the digital-to-analog converter of the successive approximation analog-to-digital converter is top plate sampling, the top plate of each first capacitor is connected to the input signal, the second connection end at the first position in each first conversion switch is connected to a first reference voltage, and the second connection end at the second position in each first conversion switch is connected to a second reference voltage, and the first reference voltage is higher than the second reference voltage.

3. The tracking circuit according to claim 1, characterized in that: When the digital-to-analog converter of the successive approximation analog-to-digital converter is bottom plate sampling, the top plate of each first capacitor is connected to a reference voltage, the second connection end at the first position in each first conversion switch is connected to a first reference voltage, the second connection end at the second position in each first conversion switch is connected to a second reference voltage, the second connection end at the third position in each first conversion switch is connected to the input signal, and the first reference voltage is higher than the second reference voltage.

4. The tracking circuit according to any one of claims 1 to 3, characterized in that: The tracking circuit further comprises a decoding circuit, wherein an input end of the decoding circuit is connected to a digital logic module of the successive approximation analog-to-digital converter, and an output end of the decoding circuit is connected to a control end of each first conversion switch. The decoding circuit is used to convert the tracking control signal from the digital logic module into a binary digital code, so that each first conversion switch selects a target connection terminal from a plurality of second connection terminals to connect to the first connection terminal according to the binary digital code; When the decoding circuit exists in the tracking circuit, the tracking circuit includes K first branch circuits, and the capacitance of the first capacitor in any i-th first branch circuit is 2 i-1 The product of the value of the second capacitor and the preset value is determined according to the minimum capacitance value of the second capacitor in the digital-to-analog converter of the successive approximation analog-to-digital converter, i is any integer from 1 to K, 2 K-1 Greater than or equal to M.

5. An analog-to-digital converter, characterized in that: The analog-to-digital converter comprises: a successive approximation analog-to-digital converter, and a tracking circuit according to any one of claims 1 to 4, wherein the tracking circuit is connected to the successive approximation analog-to-digital converter, and the analog-to-digital converter is used to: The successive approximation analog-to-digital converter converts the input signal N times to obtain a conversion result; Tracking the input signal M times by the tracking circuit to obtain a tracking result for calibrating the conversion result; An output result of the analog-to-digital converter is determined according to the conversion result and the tracking result.

6. An analog-to-digital conversion method, characterized in that: The analog-to-digital conversion method is applied to an analog-to-digital converter, the analog-to-digital converter comprising: a successive approximation analog-to-digital converter, and a tracking circuit according to any one of claims 1 to 4, the tracking circuit being connected to the successive approximation analog-to-digital converter, the analog-to-digital conversion method comprising: The successive approximation analog-to-digital converter converts the input signal N times to obtain a conversion result; Tracking the input signal M times by the tracking circuit to obtain a tracking result for calibrating the conversion result; An output result of the analog-to-digital converter is determined according to the conversion result and the tracking result.

7. A chip, characterized in that: The chip comprises the tracking circuit as claimed in any one of claims 1 to 4.

8. An electronic device, characterized in that: The electronic device comprises a tracking circuit as claimed in any one of claims 1 to 4.

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