Array substrate, display panel and display device

Abstract

The application provides an array substrate, a display panel and a display device. The array substrate comprises: a substrate; a plurality of sub-pixels; a plurality of gate lines and a plurality of data lines, the gate lines and the data lines intersect, and the sub-pixels are located at positions defined by adjacent two gate lines and adjacent two data lines; the sub-pixel comprises a pixel driving circuit and a light emitting device connected to each other; the pixel driving circuit comprises a driving module and a first control module; wherein the pixel driving circuit further comprises an auxiliary anode, the auxiliary anode is located between the anode and the substrate, and the auxiliary anode is electrically connected to the anode; the first power supply signal line comprises a first part and a second part electrically connected to each other, the first part of the first power supply signal line is arranged in the same layer as the first control signal line, and the second part of the first power supply signal line is arranged in the same layer as the auxiliary anode. The array substrate can improve the problem of high voltage drop of the first power supply signal line and the problem of signal crosstalk between adjacent two sub-pixels.

Claims

1. An array substrate, wherein, include: Substrate; Multiple sub-pixels arranged in an array on the substrate; The system comprises multiple gate lines and multiple data lines, wherein the gate lines and data lines intersect, and the sub-pixel is located at a position defined by two adjacent gate lines and two adjacent data lines; the sub-pixel includes an electrically connected pixel driving circuit and a light-emitting device; wherein the pixel driving circuit includes: The driving module is electrically connected to the first node, the second node, and the anode of the light-emitting device, respectively. It is configured to conduct the path between the second node and the anode under the control of the voltage of the first node, and to generate a current in the path for emitting light from the light-emitting device; the second node is coupled to the first power signal line. A first control module is electrically connected to a first control signal line, a second power signal line, and the anode of the light-emitting device, and is configured to transmit a second power signal transmitted by the second power signal line to the anode under the control of a first control signal transmitted by the first control signal line. The first control module includes a third transistor. The pixel driving circuit further includes an auxiliary anode, which is located between the anode and the substrate and is electrically connected to the anode. The first power signal line includes a first part and a second part that are electrically connected. The first part of the first power signal line is disposed on the same layer as the first control signal line, and the second part of the first power signal line is disposed on the same layer as the auxiliary anode. The first part and the second part of the first power signal line are located on different layers.

2. The array substrate according to claim 1, wherein, The pixel driving circuit also includes a second control module; The second control module is electrically connected to the first power signal line, the second control signal line and the driving module respectively, and is configured to transmit the first power signal transmitted in the first power signal line to the driving module under the control of the second control signal transmitted in the second control signal line, thereby assisting in generating a current in the path to make the light-emitting device emit light. The second control module includes a second transistor. Wherein, the orthographic projection of the second control module on the substrate overlaps with the orthographic projection of the second part of the first power signal line on the substrate.

3. The array substrate according to claim 2, wherein, The pixel driving circuit also includes an input module; The input module is electrically connected to the gate line, the data line and the first node respectively, and is configured to write the data signal transmitted by the data line into the first node under the control of the scan signal transmitted by the gate line. The orthographic projection of the input module on the substrate overlaps with the orthographic projection of the gate line on the substrate, and the orthographic projection of the input module on the substrate overlaps with the orthographic projection of the second control signal line on the substrate.

4. The array substrate according to claim 3, wherein, The input module and the second control module are located on the same side of the drive module, and the first control module is located on the side of the drive module away from the second control module.

5. The array substrate according to claim 4, wherein, The input module includes a first transistor, and the driving module includes a driving transistor; The gate of the first transistor is electrically connected to the gate line, the source of the first transistor is electrically connected to the data line, and the drain of the first transistor is electrically connected to the gate of the driving transistor. The gate of the second transistor is electrically connected to the second control signal line, the source of the second transistor is electrically connected to the first power signal line, and the drain of the second transistor is electrically connected to the source of the driving transistor. The gate of the third transistor is electrically connected to the first control signal line, the source of the third transistor is electrically connected to the drain of the driving transistor, and the drain of the third transistor is electrically connected to the second power supply signal line.

6. The array substrate according to claim 5, wherein, The pixel driving circuit further includes a first trace, the extension direction of the first trace intersects the extension direction of the first control signal line, the first trace is electrically connected to the gate of the third transistor and the first control signal line respectively, and the first trace and the data line are arranged on the same layer.

7. The array substrate according to claim 6, wherein, The orthographic projection of the gate of the third transistor on the substrate overlaps with the orthographic projection of the first control signal line on the substrate. The orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the gate of the third transistor on the substrate. The orthographic projection of the first trace on the substrate extends from the side of the gate of the third transistor near the first control signal line to the side of the gate of the third transistor away from the first control signal line. The orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the active region of the third transistor on the substrate.

8. The array substrate according to claim 6, wherein, The pixel driving circuit further includes a second trace, the extension direction of which is consistent with the extension direction of the data line. The second trace is electrically connected to the source of the second transistor and the first power signal line, respectively. The second trace and the data line are arranged on the same layer.

9. The array substrate according to claim 8, wherein, The extension direction of the second trace intersects the extension direction of the gate line, and the orthographic projection of the second trace on the substrate overlaps with the orthographic projection of the gate line on the substrate. The orthographic projection of the second trace on the substrate extends from the location of the orthographic projection of the source of the second transistor on the substrate to the location of the orthographic projection of the first portion of the first power signal line on the substrate.

10. The array substrate according to claim 8, wherein, The orthographic projection of the second control signal line on the substrate overlaps with the orthographic projections of the gate of the first transistor and the gate of the second transistor on the substrate, respectively. The orthographic projection of the gate line on the substrate overlaps with the orthographic projection of the gate of the first transistor on the substrate, and the orthographic projection of the gate line on the substrate overlaps with the orthographic projection of the active region of the first transistor on the substrate.

11. The array substrate according to claim 10, wherein, Within the same region of the second control signal line, the distance between the gate of the first transistor and the gate of the driving transistor in a direction parallel to the data line is greater than the distance between the gate of the second transistor and the gate of the driving transistor in a direction parallel to the data line.

12. The array substrate according to claim 10, wherein, Within the region where the sub-pixels are located in the same row, along the direction parallel to the data line, the minimum distance between the overlapping segment of the second control signal line and the gate of the first transistor and the gate line is less than the minimum distance between the overlapping segment of the second control signal line and the gate of the second transistor and the gate line.

13. The array substrate according to claim 10, wherein, The orthographic projection of the data line on the substrate overlaps with the orthographic projection of the first portion of the first power signal line on the substrate. The orthographic projections of the first transistor, the second transistor, the second control signal line, and the gate line on the substrate are respectively located within the orthographic projection of the second portion of the first power signal line on the substrate.

14. The array substrate according to claim 13, wherein, The first power signal line further includes a third part, the extension direction of which intersects the extension direction of the first control signal line. The third portion of the first power signal line connects the first portions of the first power signal line in two adjacent rows of the sub-pixels together. The orthographic projection of the third portion of the first power signal line on the substrate overlaps with the orthographic projection of the data line on the substrate and the orthographic projection of the first control signal line on the substrate.

15. The array substrate according to claim 14, wherein, The first portion and the third portion of the first power signal line, when projected onto the substrate, together form a grid, and the sub-pixel is located in the closed area defined by the grid.

16. The array substrate according to any one of claims 6-15, wherein, The array substrate includes a semiconductor layer located on the substrate, the semiconductor layer including a first portion, a second portion, a third portion, a fourth portion, a fifth portion and a sixth portion; The area of ​​the fourth portion of the semiconductor layer projected onto the substrate is larger than the area of ​​the other portions projected onto the substrate. The first part of the semiconductor layer includes the source, drain, and active region of the first transistor; the second part of the semiconductor layer includes the source, drain, and active region of the second transistor; the third part of the semiconductor layer includes the source, drain, and active region of the third transistor; the fourth part of the semiconductor layer includes the source, drain, and active region of the driving transistor; the fifth and sixth parts are both electrically connected to the substrate. In one of the sub-pixel regions, the second part and the fourth part of the semiconductor layer are integrated; in the same row of sub-pixels perpendicular to the extension direction of the data line, two sub-pixels are grouped together, and in the same group of sub-pixels regions, the two third parts of the semiconductor layer are integrated.

17. The array substrate according to claim 16, wherein, In the same group of sub-pixels, the two third transistors are symmetrically arranged, and the two sixth portions of the semiconductor layer are symmetrically arranged.

18. The array substrate according to claim 16, wherein, The array substrate further includes a gate layer located on the side of the semiconductor layer away from the substrate. The gate layer includes the gate of each transistor. The orthographic projection of the gate layer on the substrate overlaps with the orthographic projection of the semiconductor layer on the substrate. The region in the semiconductor layer that overlaps with the orthographic projection of the gate layer on the substrate is the active region of each transistor. The region in the semiconductor layer that does not overlap with the orthographic projection of the gate layer on the substrate is the source or drain of each transistor. The area of ​​the orthographic projection of the gate of the driving transistor on the substrate is larger than the area of ​​the orthographic projection of the gates of the other transistors on the substrate.

19. The array substrate according to claim 18, wherein, The array substrate further includes a first conductive layer located on the side of the gate layer away from the substrate. The first conductive layer includes a third power signal line, the gate line, the second control signal line, and the second power signal line; The third power signal line is electrically connected to the fifth part of the semiconductor layer, and the second power signal line is electrically connected to the sixth part of the semiconductor layer.

20. The array substrate according to claim 19, wherein, In the region where the sub-pixels are located in the same row perpendicular to the extension direction of the data line, the third power signal line includes a first line segment and a plurality of second line segments. The first line segment is connected to each of the second line segments respectively. The second line segments are electrically connected to the fifth part of the semiconductor layer. The extension direction of the first line segment intersects with the extension direction of the data line. The extension direction of each of the second line segments is consistent with the extension direction of the data line. The orthographic projection of the first line segment on the substrate overlaps with the orthographic projection of the driving transistor on the substrate. The orthographic projection of the second line segment on the substrate overlaps with the orthographic projection of the fifth part of the semiconductor layer on the substrate. In the region where the sub-pixels are located in the same row perpendicular to the extension direction of the data line, the second power signal line includes a third segment, a plurality of fourth segments, and a plurality of fifth segments. The third segment is connected to each of the fourth segments and each of the fifth segments respectively. The fourth segments are electrically connected to the drain of the third transistor. The fifth segments are electrically connected to the sixth part of the semiconductor layer. The extension direction of each of the fourth segments and each of the fifth segments is consistent with the extension direction of the data line. The extension direction of the third segment intersects with the extension direction of the data line. The orthographic projection of the fifth segment on the substrate overlaps with the orthographic projection of the sixth part of the semiconductor layer on the substrate.

21. The array substrate according to claim 20, wherein, The first conductive layer further includes a first connection portion, a second connection portion, and a third connection portion. The first connection portion is electrically connected to the source of the third transistor and the drain of the driving transistor, respectively. The second connection portion is electrically connected to the gate of the driving transistor and the drain of the first transistor, respectively. The third connection portion is electrically connected to the source of the first transistor and the data line, respectively. The orthographic projection of the third connection portion on the substrate overlaps with the orthographic projection of the first portion of the first power signal line on the substrate.

22. The array substrate according to claim 21, wherein, The pixel driving circuit further includes a compensation module, which is electrically connected to the first node, the second node and the first power signal line respectively, and is configured to compensate the threshold voltage of the driving module. The compensation module includes a first capacitor and a second capacitor. The first plate of the first capacitor is electrically connected to the source of the driving transistor, and the second plate of the first capacitor is electrically connected to the gate of the driving transistor. The first plate of the second capacitor is electrically connected to the source of the driving transistor, and the second plate of the second capacitor is electrically connected to the first power signal line.

23. The array substrate according to claim 22, wherein, The array substrate further includes a second conductive layer located on the side of the first conductive layer away from the substrate, the second conductive layer including the data line and the first conductive pattern, the first conductive pattern being electrically connected to the source of the driving transistor; The second conductive layer also includes the first trace and the second trace.

24. The array substrate according to claim 23, wherein, The array substrate further includes a third conductive layer located on the side of the second conductive layer away from the substrate, the third conductive layer including the first control signal line, the second electrode of the first capacitor, and a first portion of the first power signal line; In the region where the sub-pixels are located in the same row perpendicular to the extension direction of the data line, the first part of the first power signal line includes a sixth segment and a plurality of seventh segments, each of the seventh segments being connected to the sixth segment. The seventh segment is located between the second plates of two adjacent first capacitors, and the sixth segment is located on the side of the second plate of each first capacitor away from the first control signal line. The sixth segment is in the same extension direction as the first control signal line. The orthographic projection of the sixth line segment on the substrate overlaps with the orthographic projection of the first transistor on the substrate, and the orthographic projection of the seventh line segment on the substrate overlaps with the orthographic projection of the data line on the substrate.

25. The array substrate according to claim 24, wherein, The array substrate further includes a capacitive conductive layer located on the side of the third conductive layer away from the substrate. The capacitive conductive layer includes a second conductive pattern. The orthographic projection of the second conductive pattern on the substrate overlaps with the orthographic projection of the first conductive pattern on the substrate, and the second conductive pattern is indirectly electrically connected to the first conductive pattern.

26. The array substrate according to claim 25, wherein, The array substrate further includes a fourth conductive layer located on the side of the capacitor conductive layer away from the substrate. The fourth conductive layer includes a third conductive pattern, which is electrically connected to the first conductive pattern and to the second conductive pattern. The first conductive pattern, the second conductive pattern, and the third conductive pattern together serve as the first electrode of the first capacitor and the first electrode of the second capacitor.

27. The array substrate according to claim 26, wherein, The fourth conductive layer also includes a third portion of the first power signal line and an adapter cable; The third part of the first power signal line electrically connects the seventh line segment in two adjacent rows of the sub-pixels together. The adapter line is electrically connected to the sixth line segment and the second part of the first power signal line respectively. The orthographic projection of the adapter line on the substrate overlaps with the orthographic projection of the sixth line segment on the substrate.

28. The array substrate according to claim 27, wherein, The array substrate further includes a fifth conductive layer located on the side of the fourth conductive layer away from the substrate, and a sixth conductive layer located on the side of the fifth conductive layer away from the substrate. The fifth conductive layer includes the second electrode of the second capacitor, and the sixth conductive layer includes the second part of the first power signal line and the auxiliary anode. The second electrode of the second capacitor is electrically connected to the second part of the first power signal line. The orthographic projection of the auxiliary anode on the substrate overlaps with the orthographic projections of the third transistor and the driving transistor on the substrate.

29. The array substrate according to claim 28, wherein, In the region where the sub-pixels are located in the same row perpendicular to the extension direction of the data line, the shape of the orthographic projection of the second part of the first power signal line on the substrate is comb-shaped, and the area of ​​the orthographic projection of the second part of the first power signal line on the substrate is larger than the area of ​​the orthographic projection of the first part of the first power signal line on the substrate.

30. The array substrate according to claim 29, wherein, In the region where the sub-pixels are located in the same row perpendicular to the extension direction of the data line, the second part of the first power signal line includes a main extension and a plurality of branch extensions. The orthographic projection of the main extension on the substrate covers the orthographic projections of the first transistor, the second transistor, the gate line, the second control signal line, and the sixth line segment on the substrate. The branch extension is located in the region between two adjacent auxiliary anodes, and the branch extension overlaps with the orthographic projections of the seventh line segment and the data line on the substrate.

31. A display panel, wherein, Includes the array substrate as described in any one of claims 1-30.

32. A display device, wherein, Includes the display panel as described in claim 31.

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