Fixed-point non-integer multiple decimation method and apparatus for high-precision harmonic analysis

Abstract

The application discloses a non-integer times decimation method and device for high-precision harmonic analysis, two counters are arranged and used for saving time ordinal count value CNT1 and decimation coefficient count value CNT2 respectively, when detecting that data valid signal valid of input data x[n] is valid, time ordinal count value CNT1 is set as CNT1+1, when CNT1 is greater than or equal to CNT2, decimation point value is calculated through linear interpolation according to previous sampling point value and current sampling point value, then decimation coefficient count value is accumulated non-integer times decimation coefficient M, namely CNT2=CNT2+M, thereby non-integer times decimation is realized. The application realizes non-integer times decimation based on linear interpolation, thereby reducing harmonic error, and thereby being more suitable for high-precision harmonic analysis.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing technology, and more specifically, relates to a fixed-point non-integer downsampling method and apparatus for high-precision harmonic analysis. Background Technology

[0002] Reducing harmonic interference is a crucial issue in industrial production, and harmonic analysis plays a vital role in power quality analysis. Achieving accurate harmonic analysis and preventing spectral leakage in Fast Fourier Transform (FFT) largely depends on the application of synchronous sampling.

[0003] In engineering, ADCs typically use fixed-frequency sampling, but the frequency of the external input waveform is unknown. To prevent spectral leakage, it's necessary to extract the entire cycle of the input waveform for FFT. For design convenience, the number of FFT points is usually fixed. Therefore, after extracting the entire cycle of the waveform, a sampling operation is needed to downsample this data to the number of points required for the FFT in the device. Since the frequency of the external input waveform is unknown, the number of points per cycle of this waveform is also unknown before sampling, and may not be an integer multiple of the number of points per cycle required for FFT. Therefore, after frequency measurement, a sampling coefficient needs to be calculated based on the frequency, and then the extracted entire cycle waveform data is downsampled by a non-integer multiple.

[0004] Currently, data sampling mainly includes integer multiple sampling and decimal multiple sampling.

[0005] Integer multiple sampling is the most common sampling method when sampling data. For example, 2x sampling means sampling one point every two sampling points (sampling coefficient of 2), 3x sampling means sampling one point every three sampling points (sampling coefficient of 3), and Nx sampling means sampling one point every N sampling points (sampling coefficient of N). For a sine wave, if one period of the signal obtained after synchronous sampling originally has 4096 points, and now it is to be sampled into one period of 512 points before performing FFT transformation, then the sampling coefficient is 4096 / 512 = 8, which means sampling one point every 8 points.

[0006] Fractional sampling is more complex than integer sampling. For example, in synchronous sampling in a power analyzer, if the ADC always operates at a fixed frequency and the input signal frequency is unknown, the number of sampling points per cycle of the waveform needs to be determined by frequency measurement. For sine waves of different frequencies, the number of sampling points per cycle could be random numbers such as 5634, 7813, or 6838. If these points need to be sampled into 512 points per cycle before performing an FFT, the sampling coefficient becomes (taking 5634 as an example): 5634 / 512 = 11.00390625. This increases the difficulty of data sampling for FPGAs.

[0007] Researchers (Yang Yunpeng, Mao Weicong, etc.) have used the method of "non-equal interval sampling" to approximate the decimal sampling. However, research has shown that this method may introduce unacceptable harmonic errors and is not suitable for situations where high accuracy of harmonic analysis is required. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a non-integer downsampling method and apparatus for high-precision harmonic analysis. The non-integer downsampling is achieved based on linear interpolation, thereby reducing harmonic errors and making it more suitable for high-precision harmonic analysis.

[0009] To achieve the above-mentioned objective, the fixed-point non-integer downsampling method for high-precision harmonic analysis of the present invention includes the following steps:

[0010] S1: Determine the non-integer multiple sampling coefficient M according to actual needs;

[0011] S2: Initialize two counters, storing the time sequence count value CNT1 and the sampling coefficient count value CNT2 respectively, where:

[0012] The time sequence counter value CNT1 is used to count the valid signals of the input data x[n], and its initial value is -1;

[0013] The sampling coefficient count value CNT2 is used to record the sampling accumulation coefficient, and its initial value is 0.

[0014] S3: When the valid signal of input data x[n] is detected, set the time sequence count value CNT1 = CNT1 + 1;

[0015] S4: Determine whether CNT1≥CNT2. If yes, proceed to step S5; otherwise, return to step S3.

[0016] S5: The sampling value [CNT2] is calculated using the following formula:

[0017] [CNT2]=(1-frac(CNT2))×[CNT1-1]+frac(CNT2)×[CNT1]

[0018] Where [z] represents the value of the sampled data at time number z, and frac(CNT2) represents the decimal of the sampling coefficient CNT2;

[0019] S6: Determine whether the sampling end condition has been met. If yes, end the sampling; otherwise, proceed to step S7.

[0020] S7: Set the sampling coefficient count value CNT2 = CNT2 + M, and return to step S3.

[0021] Furthermore, the present invention also provides a fixed-point non-integer downsampling device for high-precision harmonic analysis, characterized in that it includes a first data register, a second data register, a time sequence counter, a sampling coefficient counter, a comparator, a pre-sampling point register, a post-sampling point register, a sampling coefficient decimal register, a sampling coefficient decimal complement calculator, a sampling coefficient decimal complement register, and a sampling value calculator, wherein:

[0022] The first data register is used to receive input data x[n] and the corresponding valid data signal. When the valid data signal is pulled high, the current data x[n] is stored and the existing data x[n-1] is loaded into the second data register.

[0023] The second data register is used to store the data x[n-1] sent from the first data register;

[0024] The time sequence counter is used to count the valid signal of the input data x[n]. Its initial value, CNT1, is -1, and the bit width of CNT1 is W. H The time-series counter simultaneously monitors the valid signal (valid) and the draw-valid signal (draw_valid) of the input data x[n]. The counting rules for its count value CNT1 are as follows:

[0025] When both the sampling valid signal draw_valid and the data valid signal valid are valid, the time sequence counter loads the integer value CNT2[W] of the sampling coefficient count value CNT2 from the sampling coefficient counter. H -1:W L Let the time sequence count value CNT1 = CNT1 + 1 – CNT2[W] H -1:W L ];

[0026] When the sampling valid signal draw_valid is valid, but the data valid signal valid is invalid, the time sequence counter loads the integer value CNT2[W] of the sampling coefficient count value CNT2 from the sampling coefficient counter. H -1:W L Let the time sequence count value CNT1 = CNT1 – CNT2[W] H -1:W L ];

[0027] When the sampling valid signal draw_valid is invalid, but the data valid signal valid is valid, then set the time sequence count value CNT1 = CNT1 + 1;

[0028] When both the sampling valid signal draw_valid and the data valid signal valid are invalid, the time sequence count value CNT1 remains unchanged;

[0029] The sampling coefficient counter is used to accumulate the sampling accumulation coefficient based on the sampling valid signal draw_valid received from the comparator. The initial value of its sampling coefficient count value CNT2 is 0, and the bit width of count value CNT2 is W. H +W L W H W is an integer bit width. L The decimal width is specified; whenever the valid draw_valid signal is valid, the ordinal count value CNT2 = CNT2[W L -1:0]+M, where CNT2[W L -1:0] represents the decimal value of the count value CNT2, and M represents the preset non-integer multiple sampling coefficient;

[0030] The comparator is used to load the count value CNT1 of the time sequence counter and the count value CNT2 of the sampling coefficient counter, and to perform a bit-width W operation on the lower bits of the count value CNT1. L After padding with zeros, compare the results. If CNT1 ≥ CNT2, then make the valid point signal draw_valid valid for one clock cycle; otherwise, keep the valid point signal draw_valid invalid.

[0031] The previous sampling point register is used to load the previous sampling point data [CNT1-1] from the second data register and store it when the valid sampling point signal draw_valid is detected.

[0032] The post-sample point register is used to load the current sample point data [CNT1] from the first data register and store it when the valid sampling point signal draw_valid is detected.

[0033] The fractional register of the sampling coefficient is used to load the fractional value CNT2[W] of the sampling coefficient from the sampling coefficient counter when the sampling valid signal draw_valid is detected. L -1:0];

[0034] The decimal complement calculator for sampling coefficients is used to load the decimal value CNT2[W] of the sampling coefficient from the sampling coefficient counter when the valid sampling signal draw_valid is detected. L -1:0] and calculate its complement 1-CNT2[W L -1:0] and output to the fractional complement register of the sampling coefficient;

[0035] The fractional complement register for the sampling coefficient is used to receive the complement 1-CNT2[W] when the sampling validity signal draw_valid is valid. L -1:0] and register it;

[0036] The sampling point calculator is used to load the previous sampling point data [CNT1-1], the current sampling point data [CNT1], and the decimal value of the sampling point coefficient CNT2 [W] from the previous sampling point register, the next sampling point register, the sampling point coefficient decimal register, and the sampling point coefficient decimal complement calculator. L -1:0] and its complement 1-CNT2[W L [-1:0], calculate and output the sampled value DATA:

[0037] DATA = (1-CNT2[W L -1:0])×[CNT1-1]+CNT2[W L -1:0]×[CNT1].

[0038] This invention relates to a non-integer downsampling method and apparatus for high-precision harmonic analysis. Two counters are set up to store the time sequence count value CNT1 and the sampling coefficient count value CNT2, respectively. When a valid signal (valid) is detected for the input data x[n], the time sequence count value CNT1 = CNT1 + 1 is set. When CNT1 ≥ CNT2, the sampling value is calculated by linear interpolation based on the previous sampling point value and the current sampling point value. Then, the non-integer multiple sampling coefficient M is added to the sampling coefficient count value, i.e., CNT2 = CNT2 + M, thereby achieving non-integer downsampling.

[0039] This invention proposes a non-integer downsampling method based on linear interpolation and implements it on FPGA based on fixed-point numbers to meet the requirements of low resource consumption, low hardware cost, high accuracy and small frequency offset when implementing it on FPGA. It also greatly reduces the harmonic error caused by the "nearest neighbor fractional sampling method (non-uniform fractional sampling)" used in previous synchronous sampling. Attached Figure Description

[0040] Figure 1 Example diagram of sampling points for non-integer multiples of data;

[0041] Figure 2 This is a flowchart illustrating a specific implementation of the fixed-point non-integer downsampling method for high-precision harmonic analysis in this invention.

[0042] Figure 3 This is a structural diagram of a specific implementation of the fixed-point non-integer multiple downsampling device for high-precision harmonic analysis in this embodiment;

[0043] Figure 4 This is a structural diagram of the time sequence counter in this embodiment;

[0044] Figure 5 This is a structural diagram of the sampling coefficient counter in this embodiment;

[0045] Figure 6 This is a table showing the changes in count values ​​when the sampling coefficient is 3.3 in this embodiment;

[0046] Figure 7 This is a graph showing the mean square error of the waveform after sampling in this embodiment of the present invention and the comparison method as a function of the input frequency. Detailed Implementation

[0047] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.

[0048] To better illustrate the technical solution of the present invention, a brief explanation of the principle derivation of the present invention will be given first.

[0049] Assume the sampling rate of fixed-frequency sampling is f s The frequency of the signal under test is f. x In this fixed-frequency mode, the number of periods N1 of the signal to be synchronized is:

[0050] N1=f s / f x

[0051] Now, for the frequency of the signal being measured, the signal needs to be synchronized to have N2 points per cycle (N1≥N2), and J consecutive cycles are sent to the FFT module for calculation. Therefore, the original sampled signal needs to be downsampled, reducing the number of sampling points per cycle from N1 to N2. In this case, the downsampling coefficient M = N1 / N2.

[0052] For ease of description, “[z]” is used to represent the numerical value of the sampled data at time number z. Figure 1 This is an example diagram of sampling points for non-integer multiples of data. Assuming that after frequency measurement, the sampling coefficient for a certain frame of data is calculated to be 3.3, meaning that for a sampled frame of data, starting from position 0, one point is sampled every 3.3 units. The sampling positions are 0, 3.3, 6.6, 9.9, 13.2, 16.5…, resulting in the following sampling values: [0], [3.3], [6.6], [9.9], [13.2], [16.5]… It can be seen that the sampling positions of the above data are obtained by accumulating the sampling coefficients; therefore, this invention refers to it as the sampling accumulation coefficient.

[0053] In the traditional decimal sampling method (non-equal interval sampling), the actual points extracted are: [0], [3], [7],

[10] ,

[13] ,

[17] , etc. This invention proposes an interpolation-based extraction method to perform more accurate decimal sampling of the sampled data. That is, this invention will use the data from points [3] and [4] to calculate [3.3], use the data from points [6] and [7] to calculate [6.6], use the data from points [9] and

[10] to calculate [9.9], etc. (the point at [0] can be the first data in the original frame of data to be extracted).

[0054] The following example uses the numerical value [6.6] to illustrate how to calculate the numerical value [6.6] using the numerical values ​​[6] and [7]. Assuming linear interpolation is used, the calculation method for the numerical value [6.6] is easily obtained as follows:

[0055] [6.6] = [6] + ([7] - [6]) × mod (6.6, 1)

[0056] Here, mod(6.6,1) means taking 6.6 modulo 1, which is the decimal part of 6.6, i.e., 0.6. Therefore:

[0057] [6.6] = [6] + ([7] - [6]) × 0.6

[0058] More generally, suppose that for two adjacent sampling points, their position ordinal numbers in a frame of data to be sampled are A and B, and now a fractional decimation calculation needs to be performed between them. The sampling accumulation coefficient obtained by frequency measurement, calculation, and accumulation of this frame of data is C, and the fractional part of C is D. Then:

[0059] [C] = [A] + ([B] - [A]) × D

[0060] Therefore, the formula for calculating the sampling value can be obtained:

[0061] [C] = (1-D)×[A] + D×[B]

[0062] Based on the above principles, this invention proposes a fixed-point non-integer downsampling method for high-precision harmonic analysis. Figure 2 This is a flowchart illustrating a specific implementation of the fixed-point non-integer downsampling method for high-precision harmonic analysis in this invention. Figure 2 As shown, the specific steps of the fixed-point non-integer multiple downsampling method for high-precision harmonic analysis in this invention include:

[0063] S201: Determine the sampling coefficient:

[0064] The sampling coefficient M, which is a non-integer multiple, is determined according to actual needs.

[0065] S202: Initialize the counter:

[0066] In order to record the position ordinal number of each data in a set of data frames to be processed, and to record the cumulative value of the sampling coefficient, i.e. the sampling cumulative coefficient, the present invention sets up two counters to store the time ordinal count value CNT1 and the sampling coefficient count value CNT2 respectively.

[0067] The time sequence count value CNT1 is used to count the valid data signals of the input data x[n] (each valid data signal corresponds to one valid data point). Since the first data in the input data x[n] is directly output and its sampling position is 0, the initial value of the count value CNT1 is set to -1, so that the count value of the first data is 0, realizing the output of the first data. It can be seen that the count value CNT1 is used to record the position sequence number of each data in the input data frame to be processed, that is, 0, 1, 2, 3, 4, 5, 6... etc. mentioned earlier.

[0068] The sampling coefficient counter value CNT2 is used to record the sampling accumulation coefficient. That is, after each data sampling, the counter value CNT2 is incremented by the sampling coefficient M, i.e., CNT2 = CNT2 + M. The initial value of the counter value CNT2 is 0. In other words, before the start of sampling for each frame, the counter value CNT2 is loaded with the sampling coefficient calculated for the current data frame, such as 3.3 in the previous example. Subsequently, during decimal sampling, CNT2 is incremented by the sampling coefficient for each data point extracted, resulting in the current sampling accumulation coefficient, which is 0, 3.3, 6.6, 9.9, 13.2, etc., as mentioned above.

[0069] S203: Accumulate the counter value CNT1:

[0070] When a valid signal is detected in the input data frame, the time sequence count value CNT1 is set to CNT1+1.

[0071] S204: Determine whether CNT1≥CNT2. If yes, proceed to step S205; otherwise, return to step S203.

[0072] S205: Calculate the sampled values:

[0073] Let the previous sampling point number A = CNT1-1, the next sampling point number B = CNT1, and the accumulated sampling coefficient C = CNT2, D = frac(CNT2), where frac(CNT2) represents the decimal of the sampling coefficient CNT2. For fixed-point numbers, the modulo operation of powers of 2 is essentially truncating the lower bits of the fixed-point number, since 1 = 2^2. 0 Therefore, mod(CNT2,1) actually takes the lower fractional part of CNT2.

[0074] After substituting into the sampling value calculation formula, the formula for calculating the sampling value [CNT2] is as follows:

[0075] [CNT2]=(1-frac(CNT2))×[CNT1-1]+frac(CNT2)×[CNT1]

[0076] According to the previous definition, [z] represents the value of the sampling point data at time number z. Then [CNT1-1] and [CNT1] represent the values ​​of the sampling point data at time numbers CNT1-1 and CNT1, respectively. [CNT2] is the value of the sampling point data at time number CNT2, which is the required sampling point value.

[0077] S206: Determine whether the sampling termination condition has been met. If so, end the sampling process; otherwise, proceed to step S207. The sampling termination condition can be determined according to actual needs.

[0078] S207: Accumulate counter CNT2:

[0079] Set the sampling coefficient counter CNT2 = CNT2 + M, and return to step S203.

[0080] Based on the above fixed-point non-integer downsampling method, this invention designs a fixed-point non-integer downsampling device for high-precision harmonic analysis using an FPGA. In the FPGA, if counters CNT1 and CNT2 count according to the method set in the fractional sampling method, then since the update time of a frame of data can be very long, continuously accumulating would inevitably require setting counters CNT1 and CNT2 with huge bit widths, which would result in a significant waste of register resources. For example, for an ADC with a sampling rate of 5MHz and an update time set to 1s, 5×10⁻⁶ data would be recorded within a certain update time. 6Each data point occupies a 23-bit binary number. This is only the bit width of the integer part. Assuming the fractional part is set to 16 bits for higher precision, the minimum bit width of CNT2 will be 23 + 16 = 39 bits. Large-bit-width counters suffer from poor timing in FPGA implementations; the larger the bit width, the worse the timing, making it impossible to operate at higher clock frequencies. Therefore, in designing the fractional sampling device, the accumulation method of the counter was modified to limit the values ​​of counters CNT1 and CNT2 to near the sampling coefficient.

[0081] Figure 3 This is a structural diagram of a specific implementation of the fixed-point non-integer multiple downsampling device for high-precision harmonic analysis in this embodiment. Figure 3 For the sake of simplicity, the clock signal and the reset signals for each register have been omitted. For example... Figure 3 As shown, the fixed-point non-integer downsampling device for high-precision harmonic analysis in this embodiment includes a first data register 1, a second data register 2, a time sequence counter 3, a sampling coefficient counter 4, a comparator 5, a pre-sampling point register 6, a post-sampling point register 7, a sampling coefficient decimal register 8, a sampling coefficient decimal complement calculator 9, a sampling coefficient decimal complement register 10, and a sampling value calculator 11. Each component will be described in detail below.

[0082] The first data register 1 is used to receive input data x[n] and the corresponding valid data signal. When the valid data signal is pulled high, the current data x[n] is stored and the existing data x[n-1] is sent to the second data register 2.

[0083] The second data register 2 is used to store the data x[n-1] sent by the first data register 1. Obviously, the first data register 1 and the second data register 2 are used to record the data values ​​of every two adjacent data in a frame of input data. Once the two points meet the sampling condition at a certain moment, the data in the first data register 1 and the second data register 2 can be used to perform linear interpolation calculation.

[0084] The time sequence counter 3 is used to count the valid signal of the input data x[n]. Its initial value of time sequence counter CNT1 is -1, and the bit width of counter CNT1 is W. HObviously, since the count value CNT1 counts the valid data signal and is always an integer, only the integer bit width needs to be set. In the subsequent comparison processing of comparator 5, the fractional part is padded with 0s. This setting is mainly to align the decimal point of the count value CNT1 with the fixed-point number in the count value CNT2. The time sequence counter 3 simultaneously monitors the valid data signal and the draw valid signal of the input data x[n]. The counting rule of its count value CNT1 is as follows:

[0085] When both the sampling valid signal draw_valid and the data valid signal are valid, meaning the sampling condition is met and the next input data is also valid, then when the next system clock is valid, the time sequence counter 3 loads the high-order part of the sampling coefficient count value CNT2 from the sampling coefficient counter 4, which is the integer value CNT2[W H -1:W L Let the time sequence count value CNT1 = CNT1 + 1 – CNT2[W] H -1:W L ].

[0086] When the sampling valid signal draw_valid is valid, but the data valid signal valid is invalid, that is, the sampling condition is met at the current time, but the data input for the next clock is invalid, then when the next system clock is valid, the time sequence counter 3 loads the integer value CNT2[W] of the sampling coefficient count value CNT2 from the sampling coefficient counter 4. H -1:W L Let the time sequence count value CNT1 = CNT1 – CNT2[W] H -1:W L ].

[0087] When the sampling valid signal draw_valid is invalid, but the data valid signal valid is valid, then set the time sequence count value CNT1 = CNT1 + 1.

[0088] When both the sampling valid signal draw_valid and the data valid signal valid are invalid, the time sequence count value CNT1 remains unchanged.

[0089] Figure 4 This is a structural diagram of the time sequence counter in this embodiment. For example... Figure 4 As shown, in this embodiment, the time sequence counter 3 includes a time sequence count value calculator 31, a multiplexer 32, and a time sequence count value register 33, wherein:

[0090] The Time Ordinal Count Calculator 31 calculates three possible values ​​for time ordinal counts:

[0091] CNT1 = CNT1 + 1 – CNT2[W] H -1:W L ]

[0092] CNT1 = CNT1 – CNT2[W H -1:W L ]

[0093] CNT1 = CNT1 + 1

[0094] Multiplexer 32 is used to output the possible result values ​​of the strobe time sequence count values ​​based on the valid point sampling signal draw_valid and the valid data signal, as follows:

[0095] When both the sampling valid signal draw_valid and the data valid signal valid are valid, CNT1 = CNT1 + 1 – CNT2[W H -1:W L The time sequence count value is output to the time sequence count value register 33;

[0096] When the sampling valid signal draw_valid is valid, but the data valid signal valid is invalid, then CNT1 = CNT1 – CNT2[W H -1:W L The time sequence count value is output to the time sequence count value register 33;

[0097] When the sampling valid signal draw_valid is invalid, but the data valid signal valid is valid, CNT1 = CNT1 + 1 is output as the time sequence count value to the time sequence count value register 33;

[0098] When both the sampling valid signal draw_valid and the data valid signal valid are invalid, the existing time sequence count value is output to the time sequence count value register 33.

[0099] The time sequence count register 33 is used to store the received time sequence count value.

[0100] The sampling coefficient counter 4 is used to accumulate the sampling accumulation coefficient according to the sampling valid signal draw_valid received from the comparator 5. The initial value of its sampling coefficient count value CNT2 is 0. Similarly, the bit width of the count value CNT2 is W. H +W L W H W is an integer bit width. L The decimal place width is specified. Each time a valid sampling signal goes high, the sampling ordinal count value CNT2 = CNT2[W].L -1:0]+M, where, CNT2[0:W L -1] represents the decimal value of the count value CNT2, that is, the low-order part, and M represents the preset non-integer multiple sampling coefficient.

[0101] Figure 5 This is a structural diagram of the sampling coefficient counter in this embodiment. For example... Figure 5 As shown, in this embodiment, the sampling coefficient counter 4 includes a sampling coefficient accumulation value calculation module 41, a multiplexer 42, and a sampling coefficient count value register 43, wherein:

[0102] The sampling coefficient cumulative value calculation module 41 is used to calculate the possible result value of the sampling coefficient count value: CNT2 = CNT2[W L -1:0]+M.

[0103] Multiplexer 32 is used to output the possible result values ​​of the sampling coefficient count value selected by the sampling valid signal draw_valid, according to the following rules:

[0104] When the valid sampling signal draw_valid is valid, CNT2 = CNT2[W L -1:0]+M is output as the sampling coefficient count value to the sampling coefficient count value register 43;

[0105] When the sampling valid signal draw_valid is invalid, the existing sampling coefficient count value is output to the sampling coefficient count value register 43.

[0106] The sampling coefficient count register 43 is used to store the received time sequence count values.

[0107] Table 1 shows the variation pattern of the count values ​​in this embodiment.

[0108]

[0109] Table 1

[0110] As shown in Table 1, the values ​​of the valid data signal and the draw_valid sampling signal represent the level of the current clock cycle, while the values ​​of CNT1 and CNT2 represent the values ​​of CNT1 and CNT2 when the next rising edge of the clock arrives under the current valid and draw_valid conditions. It can be seen that in this invention, the sampling coefficient counter 4 only accumulates the fractional part of the count value CNT2 when accumulating it, while the time sequence counter 3 subtracts the integer part of the count value CNT2 when counting the valid data signal. Therefore, after each sampling condition is met, CNT1 and CNT2 do not grow indefinitely, but rather "shift towards 0," keeping their relative sizes constant. Only the values ​​recorded by CNT1 and CNT2 are reduced by the shift operation, and the integer part of CNT2 is subtracted from both CNT1 and CNT2. This keeps the values ​​of CNT1 and CNT2 at a low level (near the sampling coefficient) and prevents them from accumulating to overflow. In this way, for the fractional sampling processing of ultra-long data frames, the counter can also be set to a smaller bit width, resulting in better timing when implementing it on an FPGA.

[0111] Comparator 5 is used to load the count value CNT1 of the time sequence counter 3 and the count value CNT2 of the sampling coefficient counter 4, and performs a bit-width operation on the lower bit of the count value CNT1. L The comparison is performed after padding with zeros. If CNT1 ≥ CNT2, the valid point signal draw_valid is enabled for one clock cycle; otherwise, draw_valid remains disabled. It's important to note that this comparator is combinational logic, not sequential logic.

[0112] The previous sampling point register 6 is used to load the previous sampling point data [CNT1-1] from the second data register 2 and store it when the valid sampling point signal draw_valid is detected.

[0113] The post-sampling point register 7 is used to load the current sampling point data [CNT1] from the first data register 1 and store it when the valid sampling point signal draw_valid is detected.

[0114] The fractional register 8 is used to load the fractional value CNT2[W] of the sampling coefficient from the sampling coefficient counter when the sampling valid signal draw_valid is detected. L -1:0] and register it.

[0115] The decimal complement calculator 9 for sampling coefficients is used to load the decimal value CNT2[W] of the sampling coefficient from the sampling coefficient counter when the valid sampling signal draw_valid is detected. L-1:0] and calculate its complement 1-CNT2[W L -1:0] and output to the decimal complement register 10. It should be noted that the decimal complement calculator here is a combinational logic, not a sequential logic.

[0116] The fractional complement register 10 is used to receive the complement 1-CNT2[W] when the valid signal draw_valid is detected. L -1:0] and register it.

[0117] The sampling point calculator 11 is used to load the previous sampling point data [CNT1-1], the current sampling point data [CNT1], and the decimal value of the sampling point coefficient CNT2 [W] from the previous sampling point register 6, the next sampling point register 7, the sampling point coefficient decimal register 8, and the sampling point coefficient decimal complement register 10. L -1:0] and its complement 1-CNT2[W L [-1:0], calculate and output the sampled value DATA:

[0118] DATA = (1-CNT2[W L -1:0])×[CNT1-1]+CNT2[W L -1:0]×[CNT1]

[0119] like Figure 3 As shown, in this embodiment, the sampling numerical calculator 11 includes a first multiplier 111, a second multiplier 112, and an adder 113, wherein:

[0120] The first multiplier 111 is used to calculate the current sampling point data [CNT1] and the decimal value of the sampling coefficient CNT2[W]. L The product of -1:0] is P1 = CNT2[W L -1:0]×[CNT1] and output to adder 113.

[0121] The second multiplier 112 is used to calculate the fractional complement of the previous sampling point data [CNT1-1] and the sampling coefficient, 1-CNT2[W]. L The product of -1:0] is P2 = (1-CNT2[W L -1:0])×[CNT1-1] and output to adder 113.

[0122] Adder 113 is used to calculate the sum of product P1 and product P2, thereby obtaining the sampled value DATA = P1 + P2.

[0123] As can be seen, in this embodiment, the first multiplier 111 and the second multiplier 112 first calculate the corresponding product in parallel, and then add them together to obtain the sampling value output. While the calculation is being performed, the front-end data continues to be input, and the time sequence counter CNT1 and the sampling coefficient counter CNT2 continue to count and compare. The entire system is in a pipelined parallel state, thereby improving the sampling efficiency.

[0124] To better illustrate the technical effects of the present invention, specific examples are used to explain the timing of the present invention.

[0125] Example 1

[0126] In this embodiment, taking a sampling coefficient of 3.3 as an example, the timing variation of the fixed-point non-integer multiple downsampling device of the present invention is explained. Figure 6 This is a table showing the changes in count values ​​for a sampling coefficient of 3.3 in this embodiment. For example... Figure 6 As shown, each cell represents one clock cycle. The initial value of the time sequence count CNT1 is -1, and the initial value of the sampling coefficient count CNT2 is 0. When the first valid data signal arrives, the time sequence count CNT1 becomes 0, CNT1 = CNT2, and the data in the first data register becomes d0. The values ​​(0 and d0) in the first and second data registers are then entered into the pre-sampling point register and the post-sampling point register on the next rising edge of the clock. Then, interpolation operations are performed (i.e., multiplication over one clock cycle and addition over one clock cycle), and the result is output after two clock cycles, thus outputting d0 (green part). At the same time, valid data d1 is input, and the sampling coefficient count CNT2 = 0 + 3.3 = 3.3.

[0127] On the next rising clock edge after inputting data d1, CNT1+1 becomes 1, and the data in the first and second data registers are recursively converted to d1 and d0. Data continues to be input until CNT1 ≥ CNT2, which is 4 ≥ 3.3 in the table. At the next rising clock edge, the current values ​​(d3 and d4) in the first and second data registers are entered into the previous and next sampling point registers, respectively. Then, interpolation is performed (i.e., multiplication over one clock cycle and addition over one clock cycle), and d3.3 (green part) is output two clock cycles later. At the same time, on the next rising clock edge that satisfies the sampling condition, CNT2 = the fractional part of CNT2 + the sampling coefficient, which is 0.3 + 3.3 = 3.6 in the table. If the input data is still valid, then CNT1 = CNT1+1 - (the integer part of CNT2), which is 4 + 1 - 3 = 2, and then the statistics continue to be calculated, repeating this process.

[0128] If the external input data is invalid (i.e., the next data has not yet arrived) when the sampling condition is met, then on the next rising clock edge, CNT1 = CNT1 - (the integer part of CNT2), as shown in the red "Invalid Input" section of the table above. This continues until the last required sampling output is reached.

[0129] Example 2

[0130] Next, using the 5MHz / 8192-point synchronous sampling standard of the Yokogawa WT5000 power analyzer, we simulated and compared the error between the previously used method based on "non-equal interval sampling" and the non-integer multiple downsampling method of this invention in MATLAB using double-type floating-point numbers, and the magnitude of the error between the sampling method and the standard sine signal.

[0131] Table 2 is the input data parameter table when the number of FFT points is 8192 (5MHz fixed frequency sampling) in this embodiment.

[0132]

[0133] Table 2

[0134] As shown in Table 2, "fundamental frequency" is the frequency of the lowest frequency component of the input sine wave data, "sampling rate" is the equivalent sampling rate after synchronous sampling, the number after f indicates the number of sampling points required in one cycle, and the window width indicates the number of cycles to be sampled. In this embodiment, Table 2 is used as the standard for synchronous sampling to compare the two sampling methods.

[0135] Figure 7 This is a graph showing the mean square error of the waveform after sampling in this embodiment of the present invention and the comparison method, as a function of the input frequency. Figure 7 As shown, compared with non-equal interval decimal sampling, the decimal sampling algorithm based on linear interpolation has an order-of-magnitude improvement in accuracy. The higher the frequency, the more obvious the absolute value of the improvement, while at lower frequencies, the order-of-magnitude improvement is even greater.

[0136] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.

Claims

1. A fixed-point non-integer downsampling method for high-precision harmonic analysis, characterized in that, Includes the following steps: S1: Determine the non-integer multiple sampling coefficient M according to actual needs; S2: Initialize two counters, storing the time sequence count value CNT1 and the sampling coefficient count value CNT2 respectively, where: The time sequence counter value CNT1 is used to count the valid signals of the input data x[n], and its initial value is -1; The sampling coefficient count value CNT2 is used to record the sampling accumulation coefficient, and its initial value is 0. S3: When the valid signal of input data x[n] is detected, set the time sequence count value CNT1 = CNT1 + 1; S4: Determine whether CNT1≥CNT2. If yes, proceed to step S5; otherwise, return to step S3. S5: The sampling value [CNT2] is calculated using the following formula: [CNT2]=(1-frac(CNT2))×[CNT1-1]+frac(CNT2)×[CNT1] Where [z] represents the value of the sampled data at time number z, and frac(CNT2) represents the decimal of the sampling coefficient CNT2; S6: Determine whether the sampling end condition has been met. If yes, end the sampling; otherwise, proceed to step S7. S7: Set the sampling coefficient count value CNT2 = CNT2 + M, and return to step S3.

2. A fixed-point non-integer downsampling device for high-precision harmonic analysis, characterized in that, It includes a first data register, a second data register, a time sequence counter, a sampling coefficient counter, a comparator, a pre-sampling point register, a post-sampling point register, a sampling coefficient decimal register, a sampling coefficient decimal complement calculator, a sampling coefficient decimal complement register, and a sampling value calculator, wherein: The first data register is used to receive input data x[n] and the corresponding valid data signal. When the valid data signal is pulled high, the current data x[n] is stored and the existing data x[n-1] is loaded into the second data register. The second data register is used to store the data x[n-1] sent from the first data register; The time sequence counter is used to count the valid signal of the input data x[n]. Its initial value, CNT1, is -1. Bit width is W H The time-series counter simultaneously monitors the valid signal (valid) and the draw-valid signal (draw_valid) of the input data x[n]. The counting rules for its count value CNT1 are as follows: When both the sampling valid signal draw_valid and the data valid signal valid are valid, the time sequence counter loads the integer value CNT2[W] of the sampling coefficient count value CNT2 from the sampling coefficient counter. H -1:W L Let the time sequence count value CNT1 = CNT1 + 1 – CNT2[W] H -1:W L ]; When the sampling valid signal draw_valid is valid, but the data valid signal valid is invalid, the time sequence counter loads the integer value CNT2[W] of the sampling coefficient count value CNT2 from the sampling coefficient counter. H -1:W L Let the time sequence count value CNT1 = CNT1 – CNT2[W] H -1:W L ]; When the sampling valid signal draw_valid is invalid, but the data valid signal valid is valid, then set the time sequence count value CNT1 = CNT1 + 1; When both the sampling valid signal draw_valid and the data valid signal valid are invalid, the time sequence count value CNT1 remains unchanged; The sampling coefficient counter is used to accumulate the sampling accumulation coefficient based on the sampling valid signal draw_valid received from the comparator. The initial value of its sampling coefficient count value CNT2 is 0, and the bit width of count value CNT2 is W. H +W L W H W is an integer bit width. L The decimal width is specified; whenever the valid draw_valid signal is valid, the ordinal count value CNT2 = CNT2[W L -1:0]+M, where CNT2[W L -1:0] represents the decimal value of the count value CNT2, and M represents the preset non-integer multiple sampling coefficient; The comparator is used to load the count value CNT1 of the time sequence counter and the count value CNT2 of the sampling coefficient counter, and to perform a bit-width W operation on the lower bits of the count value CNT1. L After padding with zeros, compare the results. If CNT1 ≥ CNT2, then make the valid point signal draw_valid valid for one clock cycle; otherwise, keep the valid point signal draw_valid invalid. The previous sampling point register is used to load the previous sampling point data [CNT1-1] from the second data register and store it when the valid sampling point signal draw_valid is detected. The post-sample point register is used to load the current sample point data [CNT1] from the first data register and store it when the valid sampling point signal draw_valid is detected. The fractional register of the sampling coefficient is used to load the fractional value CNT2[W] of the sampling coefficient from the sampling coefficient counter when the sampling valid signal draw_valid is detected. L -1:0]; The decimal complement calculator for sampling coefficients is used to load the decimal value CNT2[W] of the sampling coefficient from the sampling coefficient counter when the valid sampling signal draw_valid is detected. L -1:0] and calculate its complement 1-CNT2[W L -1:0] and output to the fractional complement register of the sampling coefficient; The fractional complement register for the sampling coefficient is used to receive the complement 1-CNT2[W] when the sampling validity signal draw_valid is valid. L -1:0] and register it; The sampling point calculator is used to load the previous sampling point data [CNT1-1], the current sampling point data [CNT1], and the decimal value of the sampling point coefficient CNT2 [W] from the previous sampling point register, the next sampling point register, the sampling point coefficient decimal register, and the sampling point coefficient decimal complement calculator. L -1:0] and its complement 1-CNT2[W L [-1:0], calculate and output the sampled value DATA: DATA=(1-CNT2[W L -1:0])×[CNT1-1]+CNT2[W L -1:0]×[CNT1]。 3. The fixed-point non-integer multiple downsampling device according to claim 2, characterized in that, The time sequence counter includes a time sequence count value calculator, a multiplexer, and a time sequence count value register, wherein: The time sequence number calculator calculates three possible values ​​for a time sequence number: CNT1=CNT1+1–CNT2[W H -1:W L ] CNT1=CNT1–CNT2[W H -1:W L ] CNT1 = CNT1 + 1 The multiplexer is used to output the possible results of the strobe time sequence count values ​​based on the valid point signal draw_valid and the valid data signal, as follows: When both the sampling valid signal draw_valid and the data valid signal valid are valid, CNT1 = CNT1 + 1 – CNT2[W H -1:W L The time sequence count value is output to the time sequence count value register. When the sampling valid signal draw_valid is valid, but the data valid signal valid is invalid, then CNT1 = CNT1 – CNT2[W H -1:W L The time sequence count value is output to the time sequence count value register. When the sampling valid signal draw_valid is invalid, but the data valid signal valid is valid, CNT1 = CNT1 + 1 is output as the time sequence count value to the time sequence count value register; When both the sampling valid signal draw_valid and the data valid signal valid are invalid, the existing time sequence count value is output to the time sequence count value register; The time sequence count register is used to store the received time sequence count values.

4. The fixed-point non-integer multiple downsampling device according to claim 2, characterized in that, The sampling coefficient counter includes a sampling coefficient accumulation value calculation module, a multiplexer, and a sampling coefficient count value register, wherein: The sampling coefficient cumulative value calculation module is used to calculate the possible result value of the sampling coefficient count value: CNT2 = CNT2[W L -1:0]+M; The multiplexer is used to output the possible results of the sampling coefficient count value based on the sampling validity signal draw_valid, and the specific rules are as follows: When the valid sampling signal draw_valid is valid, CNT2 = CNT2[W L -1:0]+M is output as the sampling coefficient count value to the sampling coefficient count value register; When the sampling valid signal draw_valid is invalid, the existing sampling coefficient count value is output to the sampling coefficient count value register; The sampling coefficient count register is used to store the received time sequence count values.

5. The fixed-point non-integer multiple downsampling device according to claim 2, characterized in that, The sampling numerical calculator includes a first multiplier, a second multiplier, and an adder, wherein: The first multiplier is used to calculate the current sample point data [CNT1] and the decimal value of the sampling coefficient CNT2[W]. L The product of -1:0] is P1 = CNT2[W L -1:0]×[CNT1] and output to the adder; The second multiplier is used to calculate the fractional complement of the previous sampling point data [CNT1-1] and the sampling coefficient, 1-CNT2[W]. L The product of -1:0] is P2 = (1-CNT2[W L -1:0])×[CNT1-1] and output to the adder; The adder is used to calculate the sum of the product P1 and the product P2, thus obtaining the sampled value DATA = P1 + P2.

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