Pixel driving circuit and driving method thereof, display device

Abstract

A pixel driving circuit and a driving method thereof, and a display device, the pixel driving circuit comprising: a driving sub-circuit providing a driving current to a fourth node under the control of signals of a first node and a third node; a first control sub-circuit providing a signal of a reference signal line or the fourth node to the first node and a signal of the first node to a second node under the control of signals of a reset signal line and a first scan signal line; a second control sub-circuit providing a signal of a data signal line or a first power supply line to the second node under the control of signals of a second scan signal line and at least one control signal line; a third control sub-circuit providing a signal of the reference signal line to a fifth node under the control of a signal of the reset signal line; and a light emitting control sub-circuit providing a signal of the first power supply line to the third node and a signal of the fourth node to the fifth node under the control of signals of a first light emitting signal line and a second light emitting signal line, wherein the signal of the first power supply line is a negative voltage signal.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, display technology, and particularly to a pixel driving circuit and its driving method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, embodiments of this disclosure provide a pixel driving circuit, including: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a light emission control sub-circuit;

[0005] The driving sub-circuit is electrically connected to the first node, the third node and the fourth node respectively, and is configured to provide driving current to the fourth node under the control of the signals of the first node and the third node.

[0006] The first control sub-circuit is electrically connected to the reset signal line, the reference signal line, the first scan signal line, the first node, the second node, and the fourth node, respectively, and is configured to provide the reference signal line or the fourth node to the first node and the first node with the signal of the first node under the control of the signals of the reset signal line and the first scan signal line;

[0007] The second control sub-circuit is electrically connected to the second scan signal line, the second node, at least one control signal line, a data signal line, and the first power line, respectively, and is configured to provide the data signal line or the first power line signal to the second node under the control of the signals of the second scan signal line and at least one control signal line.

[0008] The third control sub-circuit is electrically connected to the reset signal line, the reference signal line and the fifth node respectively, and is configured to provide the reference signal line signal to the fifth node under the control of the reset signal line signal;

[0009] The light-emitting control sub-circuit is electrically connected to the first power line, the first light-emitting signal line, the second light-emitting signal line, the third node, the fourth node, and the fifth node, respectively. It is configured to provide the signal of the first power line to the third node and the signal of the fourth node to the fifth node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line.

[0010] The signal of the first power line is a negative voltage signal.

[0011] In some possible implementations, the fifth node is electrically connected to the second electrode of the light-emitting device, the first electrode of the light-emitting device is electrically connected to the second power line, and the signal of the second power line is a positive voltage signal.

[0012] In some possible implementations, at least one control signal line includes: a third scan signal line;

[0013] The second control sub-circuit is electrically connected to the second scan signal line, the second node, the third scan signal line, the data signal line, and the first power line, respectively, and is configured to provide the data signal line or the first power line signal to the second node under the control of the signals of the second scan signal line and the third scan signal line.

[0014] In some possible implementations, the first scan signal line and the third scan signal line are the same signal line.

[0015] In some possible implementations, the second control sub-circuit includes: a fourth transistor, an eighth transistor, and a first capacitor;

[0016] The control electrode of the fourth transistor is electrically connected to the second scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second node.

[0017] The control electrode of the eighth transistor is electrically connected to the third scan signal line, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the first power supply line.

[0018] The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power line.

[0019] In some possible implementations, at least one control signal line includes: a first scan signal line;

[0020] The second control sub-circuit is electrically connected to the second scan signal line, the second node, the third node, the first scan signal line, the data signal line, and the first power line, respectively, and is configured to provide the data signal line or the first power line or the third node signal to the second node under the control of the signals of the second scan signal line and the first scan signal line.

[0021] In some possible implementations, the second control sub-circuit includes: a fourth transistor, an eighth transistor, and a first capacitor;

[0022] The control electrode of the fourth transistor is electrically connected to the second scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second node.

[0023] The control electrode of the eighth transistor is electrically connected to the first scan signal line, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the third node.

[0024] The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power line.

[0025] In some possible implementations, the first control sub-circuit includes: a second transistor, a third transistor, and a second capacitor;

[0026] The control electrode of the second transistor is electrically connected to the reset signal line, the first electrode of the second transistor is electrically connected to the reference signal line, and the second electrode of the second transistor is electrically connected to the first node.

[0027] The control electrode of the third transistor is electrically connected to the first scan signal line, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the fourth node.

[0028] The second capacitor includes a first plate and a second plate. The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the second node.

[0029] In some possible implementations, the third control sub-circuit includes: a seventh transistor;

[0030] The control electrode of the seventh transistor is electrically connected to the reset signal line, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the reference signal line.

[0031] In some possible implementations, the driving sub-circuit includes: a first transistor;

[0032] The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the third node.

[0033] In some possible implementations, the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor;

[0034] The control electrode of the fifth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the fourth node.

[0035] The control electrode of the sixth transistor is electrically connected to the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first power supply line.

[0036] In some possible implementations, the driving sub-circuit includes: a first transistor; the first control sub-circuit includes: a second transistor, a third transistor, and a second capacitor; the second control sub-circuit includes: a fourth transistor, an eighth transistor, and a first capacitor; the third control sub-circuit includes: a seventh transistor; and the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor.

[0037] The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the third node.

[0038] The control electrode of the second transistor is electrically connected to the reset signal line, the first electrode of the second transistor is electrically connected to the reference signal line, and the second electrode of the second transistor is electrically connected to the first node.

[0039] The control electrode of the third transistor is electrically connected to the first scan signal line, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the fourth node.

[0040] The control electrode of the fourth transistor is electrically connected to the second scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second node.

[0041] The control electrode of the fifth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the fourth node.

[0042] The control electrode of the sixth transistor is electrically connected to the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first power supply line.

[0043] The control electrode of the seventh transistor is electrically connected to the reset signal line, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the reference signal line.

[0044] The control electrode of the eighth transistor is electrically connected to the third scan signal line, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the first power supply line.

[0045] The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power line.

[0046] The second capacitor includes a first plate and a second plate. The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the second node.

[0047] In some possible implementations, the driving sub-circuit includes: a first transistor; the first control sub-circuit includes: a second transistor, a third transistor, and a second capacitor; the second control sub-circuit includes: a fourth transistor, an eighth transistor, and a first capacitor; the third control sub-circuit includes: a seventh transistor; and the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor.

[0048] The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the third node.

[0049] The control electrode of the second transistor is electrically connected to the reset signal line, and the first electrode of the second transistor is electrically connected to the reference signal line.

[0050] The second terminal of the second transistor is electrically connected to the first node;

[0051] The control electrode of the third transistor is electrically connected to the first scan signal line, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the fourth node.

[0052] The control electrode of the fourth transistor is electrically connected to the second scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second node.

[0053] The control electrode of the fifth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the fourth node.

[0054] The control electrode of the sixth transistor is electrically connected to the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first power supply line.

[0055] The control electrode of the seventh transistor is electrically connected to the reset signal line, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the reference signal line.

[0056] The control electrode of the eighth transistor is electrically connected to the first scan signal line, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the third node.

[0057] The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power line.

[0058] The second capacitor includes a first plate and a second plate. The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the second node.

[0059] In some possible implementations, at least one of the first to eighth transistors is an N-type transistor.

[0060] In some possible implementations, the difference between the voltage value of the second power line and the voltage value of the reference signal line is less than the set light-up threshold.

[0061] In some possible implementations, the range of the light emission threshold is set to [1V, 2V].

[0062] In a second aspect, embodiments of this disclosure provide a display device, including a pixel driving circuit as described in any embodiment of the first aspect.

[0063] Thirdly, embodiments of this disclosure provide a method for driving a pixel driving circuit, configured to drive a pixel driving circuit as described in any embodiment of the first aspect, the method comprising:

[0064] The driving sub-circuit, under the control of the signal from the first node, determines the driving current flowing between the third and fourth nodes;

[0065] Under the control of the reset signal line and the first scan signal line, the first control sub-circuit provides the reference signal line or the signal of the fourth node to the first node, and provides the signal of the first node to the second node;

[0066] The second control sub-circuit provides a data signal line or a first power line signal to the second node under the control of the second scan signal line and at least one control signal line.

[0067] The third control sub-circuit provides the reference signal line signal to the fifth node under the control of the reset signal line signal;

[0068] Under the control of the signals from the first and second light-emitting signal lines, the light-emitting control sub-circuit provides the signal from the first power line to the third node and the signal from the fourth node to the fifth node;

[0069] The signal of the first power line is a negative voltage signal.

[0070] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0071] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0072] Figure 1 This is a schematic diagram of the structure of a pixel driving circuit provided in an example embodiment of the present disclosure;

[0073] Figure 2 An equivalent circuit diagram of a driving sub-circuit provided for an exemplary embodiment;

[0074] Figure 3 An equivalent circuit diagram of a first control sub-circuit provided for an exemplary embodiment;

[0075] Figure 4A An equivalent circuit diagram of a second control sub-circuit provided for an exemplary embodiment;

[0076] Figure 4B An equivalent circuit diagram of a second control sub-circuit provided for an exemplary embodiment;

[0077] Figure 5 An equivalent circuit diagram of a third control sub-circuit provided for an exemplary embodiment;

[0078] Figure 6 An equivalent circuit diagram of a light-emitting control sub-circuit provided for an exemplary embodiment;

[0079] Figure 7 An equivalent circuit diagram of a pixel driving circuit provided for an exemplary embodiment;

[0080] Figure 8 for Figure 7 The provided timing diagram of the pixel driving circuit;

[0081] Figure 9A The equivalent circuit diagram for the working process of the pixel driving circuit is shown below.

[0082] Figure 9B The equivalent circuit diagram for the second working process of the pixel driving circuit;

[0083] Figure 9C The equivalent circuit diagram for the third working process of the pixel driving circuit;

[0084] Figure 9D The equivalent circuit diagram for the operation process of the pixel driving circuit is shown in section four.

[0085] Figure 10 An equivalent circuit diagram of a pixel driving circuit provided for an exemplary embodiment;

[0086] Figure 11 for Figure 10 The provided timing diagram of the pixel driving circuit;

[0087] Figure 12A The equivalent circuit diagram for the working process of the pixel driving circuit is shown below.

[0088] Figure 12B The equivalent circuit diagram for the second working process of the pixel driving circuit;

[0089] Figure 12C The equivalent circuit diagram for the third working process of the pixel driving circuit;

[0090] Figure 12D The equivalent circuit diagram for the operation process of the pixel driving circuit is shown in section four. Detailed Implementation

[0091] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0092] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0093] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0094] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0095] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0096] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0097] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0098] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0099] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0100] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0101] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0102] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0103] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0104] OLED or QLED display panels include a substrate and multiple sub-pixels disposed on the substrate. At least one sub-pixel includes a pixel driving circuit. The node potential of the driving sub-circuit in the pixel driving circuit affects the reliability and uniformity of the display.

[0105] Figure 1 This is a schematic diagram of the pixel driving circuit provided in an example embodiment of the present disclosure, as shown below. Figure 1 As shown, the pixel driving circuit may include: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and an emissive control sub-circuit.

[0106] The driving sub-circuit is electrically connected to the first node N1, the third node N3 and the fourth node N4 respectively, and is configured to provide driving current to the fourth node N4 under the control of the signals of the first node N1 and the third node N3.

[0107] The first control sub-circuit is electrically connected to the reset signal line RE, the reference signal line Ref, the first scan signal line Gate1, the first node N1, the second node N2, and the fourth node N4, respectively. It is configured to provide the reference signal line Ref or the signal of the fourth node N4 to the first node N1 and the signal of the first node N1 to the second node N2 under the control of the signals of the reset signal line RE and the first scan signal line Gate1.

[0108] The second control sub-circuit is connected to the second scan signal line Gate2, the second node N2, at least one control signal line CK, the data signal line Data, and the first power line VSS, respectively. It is configured to provide the data signal line Data or the first power line VSS signal to the second node N2 under the control of the signals of the second scan signal line Gate2 and at least one control signal line CK.

[0109] The third control sub-circuit is electrically connected to the reset signal line RE, the reference signal line Ref, and the fifth node N5, respectively, and is configured to provide the reference signal line Ref to the fifth node N5 under the control of the signal from the reset signal line RE.

[0110] The light-emitting control sub-circuit is electrically connected to the first power line VSS, the first light-emitting signal line EM1, the second light-emitting signal line EM2, the third node N3, the fourth node N4, and the fifth node N5, respectively. It is configured to provide the first power line VSS signal to the third node N3 and the fourth node N4 signal to the fifth node N5 under the control of the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2.

[0111] Among them, the signal of the first power line VSS is a negative voltage signal.

[0112] In this embodiment, the driving sub-circuit, under the control of the signals of the first node N1 and the third node N3, provides a driving current to the fourth node N4. The light-emitting control sub-circuit, under the control of the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2, provides a signal of the first power line VSS to the third node N3. The signal of the first power line VSS is a negative voltage signal. The node of the driving sub-circuit (the third node N3) is connected to the first power line VSS with a negative voltage signal through the light-emitting control sub-circuit, so that the node potential of the driving sub-circuit depends on the negative voltage signal of the first power line. This avoids the problem of inconsistent anode potentials of the light-emitting devices, which would affect the uniformity of the display, when the node potential of the driving sub-circuit depends on the anode potential of the light-emitting device due to factors such as uneven characteristics of the light-emitting device on the display panel, device aging, or temperature changes (such as temperature rise).

[0113] In one exemplary embodiment, the fifth node N5 is electrically connected to the second electrode (cathode) of the light-emitting device L, and the first electrode (anode) of the light-emitting device L is connected to the second power line VDD, wherein the signal of the second power line VDD is a positive voltage signal.

[0114] In one exemplary embodiment, the light-emitting device L can be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). The OLED may include a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0115] In this embodiment, the light-emitting control sub-circuit, under the control of the signals from the first and second light-emitting signal lines, provides the signal from the fourth node to the fifth node. The fifth node is electrically connected to the second electrode of the light-emitting device, and the first electrode of the light-emitting device is electrically connected to the second power supply line of the positive voltage signal. By reversing the connection method of the light-emitting device, the power supply voltage output from the first power supply line VSS of the negative voltage signal provides a driving voltage to the second electrode (cathode) of the light-emitting device L through the driving sub-circuit and the light-emitting control sub-circuit, driving the light-emitting device L to emit light. This avoids the node voltage of the driving transistor being affected by the potential of the first electrode (anode) of the light-emitting device L, ensuring the reliability and uniformity of the display.

[0116] Figure 2 An equivalent circuit diagram of a driver sub-circuit provided for an exemplary embodiment. (e.g.) Figure 2 As shown, in one exemplary embodiment, the driving sub-circuit may include: a first transistor T1.

[0117] In one exemplary embodiment, such as Figure 2 As shown, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth node N4, and the second electrode of the first transistor T1 is electrically connected to the third node N3.

[0118] In one exemplary embodiment, the first transistor T1 can be referred to as the driving transistor. The first transistor T1 determines the driving current flowing between the third node N3 and the fourth node N4 based on the potential difference between its control electrode (also the first node N1) and its second electrode (also the third node N3).

[0119] The second electrode (also the third node N3) of the first transistor T1 is electrically connected to the first power supply line VSS of the negative voltage signal through the light-emitting control sub-circuit. This avoids the potential difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the first transistor T1 from being affected by the potential of the first electrode (anode) of the light-emitting device L, thus ensuring the reliability and uniformity of the display.

[0120] Figure 2An exemplary structure of the driver sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the driver sub-circuit is not limited to this.

[0121] In one exemplary embodiment, the difference between the voltage value VD of the second power line VDD and the voltage value Vref of the reference signal line Ref is less than a set light-emitting threshold.

[0122] In one exemplary embodiment, the range of the set light emission threshold can be [1V, 2V]. For example, VD-Vref < 2V, or VD-Vref < 1V.

[0123] In this embodiment of the disclosure, the difference between the voltage value VD of the second power line VDD and the voltage value Vref of the reference signal line Ref is less than the set light emission threshold, which can ensure that the light-emitting device L will not emit light at an unexpected time when the pixel driving circuit is working. For example, it can ensure that the light-emitting device L does not emit light during the sampling stage or compensation stage of the threshold voltage Vth of the first transistor T1 when the pixel driving circuit is working.

[0124] Figure 3 An equivalent circuit diagram of a first control sub-circuit provided for an exemplary embodiment. (e.g.) Figure 3 As shown, in an exemplary embodiment, the first control sub-circuit includes: a second transistor T2, a third transistor T3, and a second capacitor C2.

[0125] In one exemplary embodiment, such as Figure 3 As shown, the control electrode of the second transistor T2 is electrically connected to the reset signal line RE, the first electrode of the second transistor T2 is electrically connected to the reference signal line Ref, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first scan signal line Gate1, the first electrode of the third transistor T3 is electrically connected to the first node N1, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the second node N2.

[0126] Figure 3 An exemplary structure of the first control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the first control sub-circuit is not limited to this.

[0127] In one exemplary embodiment, at least one control signal line CK may include: a third scan signal line Gate3; and a second control sub-circuit, which is electrically connected to the second scan signal line Gate2, the second node N2, the third scan signal line Gate3, the data signal line Data, and the first power line VSS, respectively, and is configured to provide the data signal line Data or the first power line VSS signal to the second node N2 under the control of the signals of the second scan signal line Gate2 and the third scan signal line Gate3.

[0128] In one exemplary embodiment, the first scan signal line Gate1 and the third scan signal line Gate3 can be the same signal line.

[0129] Figure 4A An equivalent circuit diagram of a second control sub-circuit provided for an exemplary embodiment. (e.g.) Figure 4A As shown, in one exemplary embodiment, the second control sub-circuit includes: a fourth transistor T4, an eighth transistor T8, and a first capacitor C1.

[0130] In one exemplary embodiment, such as Figure 4A As shown, the control electrode of the fourth transistor T4 is electrically connected to the second scan signal line Gate2, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the eighth transistor T8 is electrically connected to the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected to the second node N2, and the second electrode of the eighth transistor T8 is electrically connected to the first power supply line VSS; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the second node N2, and the second plate C12 of the first capacitor is electrically connected to the first power supply line VSS.

[0131] Figure 4A An exemplary structure of the second control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the second control sub-circuit is not limited to this.

[0132] In one exemplary embodiment, at least one control signal line CK may include: a first scan signal line Gate1; and a second control sub-circuit, which is electrically connected to the second scan signal line Gate2, the second node N2, the third node N3, the first scan signal line Gate1, the data signal line Data, and the first power line VSS, respectively, and is configured to provide the data signal line Data or the first power line VSS or the third node N3 signal to the second node N2 under the control of the signals of the second scan signal line Gate2 and the first scan signal line Gate1.

[0133] Figure 4BAn equivalent circuit diagram of a second control sub-circuit provided for an exemplary embodiment. (e.g.) Figure 4B As shown, in one exemplary embodiment, the second control sub-circuit includes: a fourth transistor T4, an eighth transistor T8, and a first capacitor C1.

[0134] In one exemplary embodiment, such as Figure 4B As shown, the control electrode of the fourth transistor T4 is electrically connected to the second scan signal line Gate2, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the eighth transistor T8 is electrically connected to the first scan signal line Gate1, the first electrode of the eighth transistor T8 is electrically connected to the second node N2, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the second node N2, and the second plate C12 of the first capacitor is electrically connected to the first power supply line VSS.

[0135] Figure 4B An exemplary structure of the second control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the second control sub-circuit is not limited to this.

[0136] Figure 5 An equivalent circuit diagram of a third control sub-circuit provided for an exemplary embodiment. (e.g.) Figure 5 As shown, in one exemplary embodiment, the third control sub-circuit includes a seventh transistor T7.

[0137] In one exemplary embodiment, such as Figure 5 As shown, the control electrode of the seventh transistor T7 is electrically connected to the reset signal line RE, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected to the reference signal line Ref.

[0138] Figure 5 An exemplary structure of the third control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the third control sub-circuit is not limited to this.

[0139] Figure 6 An equivalent circuit diagram of a light-emitting control sub-circuit provided for an exemplary embodiment. (e.g.) Figure 6 As shown, in one exemplary embodiment, the light-emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6.

[0140] In one exemplary embodiment, such as Figure 6As shown, the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected to the fifth node N5, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply line VSS.

[0141] In one exemplary embodiment, the fifth transistor T5 can be referred to as the first light-emitting transistor, and the sixth transistor T6 can be referred to as the second light-emitting transistor. When a valid level signal is input to the first light-emitting signal line EM1 and the second light-emitting signal line EM2, the fifth transistor T5 and the sixth transistor T6 are turned on. The power supply voltage output from the first power supply line VSS provides a driving voltage to the second terminal of the light-emitting device L through the turned-on sixth transistor T6, the turned-on first transistor T1, and the turned-on fifth transistor T5, driving the light-emitting device L to emit light.

[0142] Figure 6 An exemplary structure of the light-emitting control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the light-emitting control sub-circuit is not limited to this.

[0143] Figure 7 An equivalent circuit diagram of a pixel driving circuit provided for an exemplary embodiment. (e.g.) Figure 7 As shown, in an exemplary embodiment, the pixel driving circuit may include: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a light-emitting control sub-circuit. The driving sub-circuit includes: a first transistor T1; the first control sub-circuit includes: a second transistor T2, a third transistor T3, and a second capacitor C2; the second control sub-circuit includes: a fourth transistor T4, an eighth transistor T8, and a first capacitor C1; the third control sub-circuit includes: a seventh transistor T7; and the light-emitting control sub-circuit includes: a fifth transistor T5 and a sixth transistor T6.

[0144] In one exemplary embodiment, such as Figure 7As shown, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first terminal of the first transistor T1 is electrically connected to the fourth node N4, and the second terminal of the first transistor T1 is electrically connected to the third node N3; the control electrode of the second transistor T2 is electrically connected to the reset signal line RE, the first terminal of the second transistor T2 is electrically connected to the reference signal line Ref, and the second terminal of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first scan signal line Gate1, the first terminal of the third transistor T3 is electrically connected to the first node N1, and the second terminal of the third transistor T3 is electrically connected to the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected to the second scan signal line Gate2, the first terminal of the fourth transistor T4 is electrically connected to the data signal line Data, and the second terminal of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the first light emission signal line EM1, the first terminal of the fifth transistor T5 is electrically connected to the fifth node N5, and the second terminal of the fifth transistor T5 is electrically connected to the fourth node N4; The control electrode of transistor T6 is electrically connected to the second light-emitting signal line EM2; the first electrode of transistor T6 is electrically connected to the third node N3; and the second electrode of transistor T6 is electrically connected to the first power supply line VSS. The control electrode of transistor T7 is electrically connected to the reset signal line RE; the first electrode of transistor T7 is electrically connected to the fifth node N5; and the second electrode of transistor T7 is electrically connected to the reference signal line Ref. The control electrode of transistor T8 is electrically connected to the third scan signal line Gate3; the first electrode of transistor T8 is electrically connected to the second node N2; and the second electrode of transistor T8 is electrically connected to the first power supply line VSS. The first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor is electrically connected to the second node N2; and the second plate C12 of the first capacitor is electrically connected to the first power supply line VSS. The second capacitor C2 includes a first plate C21 and a second plate C22. The first plate C21 of the second capacitor is electrically connected to the first node N1; and the second plate C22 of the second capacitor is electrically connected to the second node N2.

[0145] In one exemplary embodiment, the first scan signal line and the third scan signal line can be the same signal line. The control electrode of the third transistor T3 and the control electrode of the eighth transistor T8 can reuse the same signal line.

[0146] In one exemplary embodiment, such as Figure 7 As shown, at least one of the transistors from the first transistor T1 to the eighth transistor T8 is an N-type transistor.

[0147] Figure 7 An exemplary structure of a pixel driving circuit is shown. It will be readily understood by those skilled in the art that the implementation of the pixel driving circuit is not limited to this.

[0148] Figure 8 for Figure 7 The provided timing diagram of the pixel driving circuit is shown. Figure 9A This is an equivalent circuit diagram illustrating the working process of a pixel driving circuit. Figure 9B The equivalent circuit diagram for the second working process of the pixel driving circuit is shown below. Figure 9C The equivalent circuit diagram for the third operation process of the pixel driving circuit is shown below. Figure 9D The equivalent circuit diagram for the fourth step of the pixel driving circuit operation process is shown below. Figure 7 The operation of the pixel driving circuit illustrated in this exemplary embodiment of the disclosure may include:

[0149] Phase 1, P1, is called the initialization phase (also known as the reset phase). The reset signal line RE is high, while the signals of the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first scan signal line Gate1, the second scan signal line Gate2, and the third scan signal line Gate3 are all low. With the reset signal line RE high, the second transistor T2 is turned on, and the reference signal line Ref is provided to the first node N1 to initialize the gate electrode of the first transistor T1 (i.e., the first node N2), for example, by clearing its internal pre-stored voltage. The seventh transistor T7 is turned on, and the reference signal line Ref is provided to the fifth node N5. Meanwhile, the third transistor T3 through the sixth transistor T6, and the eighth transistor T8 are turned off.

[0150] The fifth node N5 is electrically connected to the second electrode (cathode) of the light-emitting device L. When the seventh transistor T7 is turned on, the fifth node N5 provides the initial voltage of the reference signal line Ref to the second electrode of the light-emitting device L, initializing (resetting) the second electrode of the light-emitting device L. For example, it clears the internal pre-stored voltage, completing the initialization and ensuring that the light-emitting device L does not emit light. During this stage, the light-emitting device L does not emit light.

[0151] The second stage, P2, is called the compensation stage (also known as the sampling stage of the threshold voltage Vth of the first transistor T1). The signals of the first scan signal line Gate1, the third scan signal line Gate3, and the second light-emitting signal line EM2 are all high-level signals, while the signals of the reset signal line RE, the second scan signal line Gate2, and the first light-emitting signal line EM1 are all low-level signals. When the reset signal line RE is low, the second transistor T2 and the seventh transistor T7 are off. When the signal of the first scan signal line Gate1 is high, the third transistor T3 is on; when the signal of the second light-emitting signal line EM2 is high, the sixth transistor T6 is on. The signal at the first node N1 flows through the on-state third transistor T3, the on-state first transistor T1, and the on-state sixth transistor T6 to the first power supply line VSS. At this time, the voltage at the first node N1 is the sum of the power supply voltage Vs of the first power supply line VSS and the threshold voltage Vth of the first transistor T1, and the power supply voltage Vs of the first power supply line VSS is charged into the second capacitor C2. The signal on the third scan signal line Gate3 is high, the eighth transistor T8 is turned on, and the power supply voltage of the first power line VSS is written to the second node N2, that is, the voltage of the second node N2 is the power supply voltage Vs of the first power line VSS. Meanwhile, the fourth transistor T4 and the fifth transistor T5 are off. During this stage, the light-emitting device L does not emit light.

[0152] In the P2 stage, the difference between the voltage value VD of the second power line VDD and the voltage value Vref of the reference signal line Ref is less than the set light-emitting threshold. The set light-emitting threshold can be in the range of [1V, 2V], which can ensure that the light-emitting device L does not emit light during the sampling or compensation stage of the threshold voltage Vth of the first transistor T1 when the pixel driving circuit is working.

[0153] Phase 3 (P3): This is called the write phase. The signal on the second scan signal line Gate2 is high, while the signals on the reset signal line RE, the first scan signal line Gate1, the third scan signal line Gate3, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are all low. When the signal on the first scan signal line Gate1 is low, the third transistor T3 is off; when the signal on the third scan signal line Gate3 is low, the eighth transistor T8 is off; when the signal on the second light-emitting signal line EM2 is low, the sixth transistor T6 is off. When the signal on the second scan signal line Gate2 is high, the fourth transistor T4 is on, and the data signal line Data is written to the second node N2. At this time, the voltage value V2 of the signal at the second node N2 is the same as the voltage value Vdata of the data signal line Data. Under the action of the second capacitor C2, the voltage value of the signal at the first node N1 in this phase changes compared to the previous phase. At this time, the voltage of the first node N1 changes to Vdata + Vth. During this phase, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 are off. During this stage, the light-emitting device L does not emit light.

[0154] In the P3 phase, the voltage value V2 of the signal at the second node N2 is the voltage value Vdata of the data signal line Data. The voltage of the data signal line Data will not be divided by the first capacitor C1 and the second capacitor C2, which can reduce the voltage drop across the data signal line Data.

[0155] The fourth stage, P4, is called the light-emitting stage. The signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are both high-level signals, while the signals of the reset signal line RE and the first scan signal lines Gate1 to Gate3 are all low-level signals. The signal of the second scan signal line Gate2 is also low-level, and the fourth transistor T4 is off. With the first light-emitting signal line EM1 and the second light-emitting signal line EM2 both high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on. The power supply voltage output from the first power supply line VSS provides a driving voltage to the second terminal of the light-emitting device L through the turned-on sixth transistor T6, the turned-on first transistor T1, and the turned-on fifth transistor T5, driving the light-emitting device L to emit light.

[0156] During the pixel circuit driving process, the driving current flowing through the first transistor T1 (driving transistor) is determined by the voltage difference Vgs between the gate electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the first node N1 is Vdata + Vth, and the voltage value of the third node N3 is the power supply voltage Vs of the first power supply line VSS, the driving current of the first transistor T1 is:

[0157] I = K * (Vgs -Vth) 2 =K*(Vdata+Vth-Vs-Vth) 2＝ K*(Vdata-Vs) 2

[0158] Where I is the driving current flowing through the first transistor T1, which is also the driving current driving the light-emitting device L, K is a constant, and V gs This is the voltage difference between the gate electrode and the second electrode of the first transistor T1.

[0159] Figure 10 An equivalent circuit diagram of a pixel driving circuit provided for an exemplary embodiment. (e.g.) Figure 10 As shown, in an exemplary embodiment, the pixel driving circuit may include: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a light-emitting control sub-circuit. The driving sub-circuit includes: a first transistor T1; the first control sub-circuit includes: a second transistor T2, a third transistor T3, and a second capacitor C2; the second control sub-circuit includes: a fourth transistor T4, an eighth transistor T8, and a first capacitor C1; the third control sub-circuit includes: a seventh transistor T7; and the light-emitting control sub-circuit includes: a fifth transistor T5 and a sixth transistor T6.

[0160] In one exemplary embodiment, such as Figure 10As shown, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth node N4, and the second electrode of the first transistor T1 is electrically connected to the third node N3; the control electrode of the second transistor T2 is electrically connected to the reset signal line RE, the first electrode of the second transistor T2 is electrically connected to the reference signal line Ref, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first scan signal line Gate1, the first electrode of the third transistor T3 is electrically connected to the first node N1, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected to the second scan signal line Gate2, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the first light emission signal line EM1, the first electrode of the fifth transistor T5 is electrically connected to the fifth node N5, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4. The control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply line VSS; the control electrode of the seventh transistor T7 is electrically connected to the reset signal line RE, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected to the reference signal line Ref; the control electrode of the eighth transistor T8 is electrically connected to the first scan signal line Gate1, the first electrode of the eighth transistor T8 is electrically connected to the second node N2, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the second node N2, and the second plate C12 of the first capacitor is electrically connected to the first power supply line VSS; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the second node N2.

[0161] In one exemplary embodiment, such as Figure 7 As shown, at least one of the transistors from the first transistor T1 to the eighth transistor T8 is an N-type transistor.

[0162] Figure 10 An exemplary structure of a pixel driving circuit is shown. It will be readily understood by those skilled in the art that the implementation of the pixel driving circuit is not limited to this.

[0163] Figure 11 for Figure 10 The provided timing diagram of the pixel driving circuit is shown. Figure 12A This is an equivalent circuit diagram illustrating the working process of a pixel driving circuit. Figure 12BThe equivalent circuit diagram for the second working process of the pixel driving circuit is shown below. Figure 12C The equivalent circuit diagram for the third operation process of the pixel driving circuit is shown below. Figure 12D The equivalent circuit diagram for the fourth step of the pixel driving circuit operation process is shown below. Figure 10 The operation of the pixel driving circuit illustrated in this exemplary embodiment of the disclosure may include:

[0164] Phase 1, P1, is called the initialization phase (also known as the reset phase). The reset signal line RE is high, while the signals of the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first scan signal line Gate1, and the second scan signal line Gate2 are all low. With the reset signal line RE high, the second transistor T2 is turned on, and the reference signal line Ref is provided to the first node N1 to initialize the gate electrode of the first transistor T1 (i.e., the first node N2), for example, by clearing its internal pre-stored voltage. The seventh transistor T7 is turned on, and the reference signal line Ref is provided to the fifth node N5. Meanwhile, the third transistor T3 through the sixth transistor T6, and the eighth transistor T8 are turned off.

[0165] The fifth node N5 is electrically connected to the second electrode (cathode) of the light-emitting device L. When the seventh transistor T7 is turned on, the fifth node N5 provides the initial voltage of the reference signal line Ref to the second electrode of the light-emitting device L, initializing (resetting) the second electrode of the light-emitting device L. For example, it clears the internal pre-stored voltage, completing the initialization and ensuring that the light-emitting device L does not emit light. During this stage, the light-emitting device L does not emit light.

[0166] Phase 2 P2: This is called the compensation phase (also known as the sampling phase of the threshold voltage Vth of the first transistor T1). The signals of the first scan signal line Gate1 and the second light-emitting signal line EM2 are both high-level signals, while the signals of the reset signal line RE, the second scan signal line Gate2, and the first light-emitting signal line EM1 are all low-level signals. When the reset signal line RE is low, the second transistor T2 and the seventh transistor T7 are off. When the signal of the first scan signal line Gate1 is high, the third transistor T3 is on; when the signal of the second light-emitting signal line EM2 is high, the sixth transistor T6 is on. The signal at the first node N1 flows through the on-state third transistor T3, the on-state first transistor T1, and the on-state sixth transistor T6 to the first power supply line VSS. At this time, the voltage at the first node N1 is the sum of the power supply voltage Vs of the first power supply line VSS and the threshold voltage Vth of the first transistor T1, and the power supply voltage Vs of the first power supply line VSS is charged into the second capacitor C2. The eighth transistor T8 is turned on, connecting the second node N2 and the third node N3. The second node N2 and the third node N3 are connected to the power supply voltage of the first power line VSS, meaning that the voltages of the second node N2 and the third node N3 are respectively the power supply voltage Vs of the first power line VSS. Meanwhile, the fourth transistor T4 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0167] In the P2 stage, the difference between the voltage value VD of the second power line VDD and the voltage value Vref of the reference signal line Ref is less than the set light-emitting threshold. The set light-emitting threshold can be in the range of [1V, 2V], which can ensure that the light-emitting device L does not emit light during the sampling or compensation stage of the threshold voltage Vth of the first transistor T1 when the pixel driving circuit is working.

[0168] Phase 3 (P3): This is called the writing phase. The signal on the second scan signal line Gate2 is high, while the signals on the reset signal line RE, the first scan signal line Gate1, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are all low. When the signal on the first scan signal line Gate1 is low, the third transistor T3 and the eighth transistor T8 are off. When the signal on the second light-emitting signal line EM2 is low, the sixth transistor T6 is off. When the signal on the second scan signal line Gate2 is high, the fourth transistor T4 is on, and the data signal line Data is written to the second node N2. At this time, the voltage value V2 of the signal at the second node N2 is the same as the voltage value Vdata of the data signal line Data. Under the action of the second capacitor C2, the voltage value of the signal at the first node N1 in this phase changes compared to the previous phase. The voltage at the first node N1 then changes to Vdata + Vth. During this phase, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 are off. In this phase, the light-emitting device L does not emit light.

[0169] In the P3 phase, the voltage value V2 of the signal at the second node N2 is the voltage value Vdata of the data signal line Data. The voltage of the data signal line Data will not be divided by the first capacitor C1 and the second capacitor C2, which can reduce the voltage drop across the data signal line Data.

[0170] The fourth stage, P4, is called the light-emitting stage. The signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are both high-level signals, while the signals of the reset signal line RE, the first scan signal line Gate1, and the second scan signal line Gate2 are both low-level signals. The signal of the second scan signal line Gate2 is also low-level, and the fourth transistor T4 is off. The signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are both high-level signals, and the fifth transistor T5 and the sixth transistor T6 are turned on. The power supply voltage output from the first power supply line VSS provides a driving voltage to the second terminal of the light-emitting device L through the turned-on sixth transistor T6, the turned-on first transistor T1, and the turned-on fifth transistor T5, driving the light-emitting device L to emit light.

[0171] During the pixel circuit driving process, the driving current flowing through the first transistor T1 (driving transistor) is determined by the voltage difference Vgs between the gate electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the first node N1 is Vdata + Vth, and the voltage value of the third node N3 is the power supply voltage Vs of the first power supply line VSS, the driving current of the first transistor T1 is:

[0172] I = K * (V gs -Vth) 2=K*(Vdata+Vth-Vs-Vth) 2＝ K*(Vdata-Vs) 2

[0173] Where I is the driving current flowing through the first transistor T1, which is also the driving current driving the light-emitting device L, K is a constant, and V gs This is the voltage difference between the gate electrode and the second electrode of the first transistor T1.

[0174] This disclosure also provides a display device, including a pixel driving circuit. The pixel driving circuit is the same as that provided in any of the foregoing embodiments, and its implementation principle and effects are similar, so it will not be described again here.

[0175] This disclosure also provides a method for driving a pixel driving circuit, configured to drive the pixel driving circuit. The method for driving the pixel driving circuit may include:

[0176] The driving sub-circuit, under the control of the signal from the first node, determines the driving current flowing between the third and fourth nodes;

[0177] Under the control of the reset signal line and the first scan signal line, the first control sub-circuit provides the reference signal line or the signal of the fourth node to the first node, and provides the signal of the first node to the second node;

[0178] The second control sub-circuit provides a data signal line or a first power line signal to the second node under the control of the second scan signal line and at least one control signal line.

[0179] The third control sub-circuit provides the reference signal line signal to the fifth node under the control of the reset signal line signal;

[0180] Under the control of the signals from the first and second light-emitting signal lines, the light-emitting control sub-circuit provides the signal from the first power line to the third node and the signal from the fourth node to the fifth node;

[0181] The signal of the first power line is a negative voltage signal.

[0182] The pixel driving circuit is the same as the pixel driving circuit provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0183] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0184] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0185] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel driving circuit, comprising: The driving sub-circuit, the first control sub-circuit, the second control sub-circuit, the third control sub-circuit and the light-emitting control sub-circuit are provided. The driving sub-circuit is electrically connected with the first node, the third node and the fourth node respectively, and is configured to provide a driving current to the fourth node under the control of signals of the first node and the third node. The first control sub-circuit is electrically connected with the reset signal line, the reference signal line, the first scan signal line, the first node, the second node and the fourth node respectively, and is configured to provide a signal of the reference signal line or the fourth node to the first node and a signal of the first node to the second node under the control of signals of the reset signal line and the first scan signal line. The second control sub-circuit is electrically connected with the second scan signal line, the second node, at least one control signal line, the data signal line and the first power supply line respectively, and is configured to provide a signal of the data signal line or the first power supply line to the second node under the control of signals of the second scan signal line and the at least one control signal line. The third control sub-circuit is electrically connected with the reset signal line, the reference signal line and the fifth node respectively, and is configured to provide a signal of the reference signal line to the fifth node under the control of a signal of the reset signal line. The light-emitting control sub-circuit is electrically connected with the first power supply line, the first light-emitting signal line, the second light-emitting signal line, the third node, the fourth node and the fifth node respectively, and is configured to provide a signal of the first power supply line to the third node and a signal of the fourth node to the fifth node under the control of signals of the first light-emitting signal line and the second light-emitting signal line. The signal of the first power supply line is a negative voltage signal.

2. The pixel driving circuit according to claim 1, characterized in that, The fifth node is electrically connected with the second electrode of the light-emitting device, the first electrode of the light-emitting device is electrically connected with the second power supply line, and the signal of the second power supply line is a positive voltage signal.

3. The pixel driving circuit of claim 1, wherein, The at least one control signal line includes a third scan signal line. The second control sub-circuit is electrically connected with the second scan signal line, the second node, the third scan signal line, the data signal line and the first power supply line respectively, and is configured to provide a signal of the data signal line or the first power supply line to the second node under the control of signals of the second scan signal line and the third scan signal line.

4. The pixel driving circuit of claim 3, wherein, The first scan signal line and the third scan signal line are the same signal line.

5. The pixel driving circuit of claim 3, wherein, The second control sub-circuit includes a fourth transistor, an eighth transistor and a first capacitor. The control electrode of the fourth transistor is electrically connected with the second scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the second node. The control electrode of the eighth transistor is electrically connected with the third scan signal line, the first electrode of the eighth transistor is electrically connected with the second node, and the second electrode of the eighth transistor is electrically connected with the first power supply line. The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first power supply line.

6. The pixel driving circuit of claim 1, wherein, The at least one control signal line includes a first scan signal line. The second control sub-circuit is electrically connected with the second scan signal line, the second node, the third node, the first scan signal line, the data signal line and the first power supply line respectively, and is configured to provide the second node with a signal of the data signal line or the first power supply line or the third node under control of signals of the second scan signal line and the first scan signal line.

7. The pixel driving circuit of claim 6, wherein, The second control sub-circuit comprises a fourth transistor, an eighth transistor and a first capacitor. The control electrode of the fourth transistor is electrically connected with the second scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the second node. The control electrode of the eighth transistor is electrically connected with the first scan signal line, the first electrode of the eighth transistor is electrically connected with the second node, and the second electrode of the eighth transistor is electrically connected with the third node. The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first power supply line.

8. The pixel driving circuit of claim 1, wherein, The first control sub-circuit comprises a second transistor, a third transistor and a second capacitor. The control electrode of the second transistor is electrically connected with the reset signal line, the first electrode of the second transistor is electrically connected with the reference signal line, and the second electrode of the second transistor is electrically connected with the first node. The control electrode of the third transistor is electrically connected with the first scan signal line, the first electrode of the third transistor is electrically connected with the first node, and the second electrode of the third transistor is electrically connected with the fourth node. The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the second node.

9. The pixel driving circuit of claim 1, wherein, The third control sub-circuit comprises a seventh transistor. The control electrode of the seventh transistor is electrically connected with the reset signal line, the first electrode of the seventh transistor is electrically connected with the fifth node, and the second electrode of the seventh transistor is electrically connected with the reference signal line.

10. The pixel driving circuit of claim 1, wherein, The driving sub-circuit comprises a first transistor. The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth node, and the second electrode of the first transistor is electrically connected with the third node.

11. The pixel driving circuit of claim 1, wherein, The light-emitting control sub-circuit comprises a fifth transistor and a sixth transistor. The control electrode of the fifth transistor is electrically connected with the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected with the fifth node, and the second electrode of the fifth transistor is electrically connected with the fourth node. The control electrode of the sixth transistor is electrically connected with the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the first power supply line.

12. The pixel driving circuit of claim 1, wherein, The driving sub-circuit comprises a first transistor, the first control sub-circuit comprises a second transistor, a third transistor and a second capacitor, the second control sub-circuit comprises a fourth transistor, an eighth transistor and a first capacitor, the third control sub-circuit comprises a seventh transistor, and the light-emitting control sub-circuit comprises a fifth transistor and a sixth transistor. The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth node, and the second electrode of the first transistor is electrically connected with the third node. The control electrode of the second transistor is electrically connected with the reset signal line, the first electrode of the second transistor is electrically connected with the reference signal line, and the second electrode of the second transistor is electrically connected with the first node; The control electrode of the third transistor is electrically connected with the first scan signal line, the first electrode of the third transistor is electrically connected with the first node, and the second electrode of the third transistor is electrically connected with the fourth node; The control electrode of the fourth transistor is electrically connected with the second scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the second node; The control electrode of the fifth transistor is electrically connected with the first emitting signal line, the first electrode of the fifth transistor is electrically connected with the fifth node, and the second electrode of the fifth transistor is electrically connected with the fourth node; The control electrode of the sixth transistor is electrically connected with the second emitting signal line, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the first power supply line; The control electrode of the seventh transistor is electrically connected with the reset signal line, the first electrode of the seventh transistor is electrically connected with the fifth node, and the second electrode of the seventh transistor is electrically connected with the reference signal line; The control electrode of the eighth transistor is electrically connected with the third scan signal line, the first electrode of the eighth transistor is electrically connected with the second node, and the second electrode of the eighth transistor is electrically connected with the first power supply line; The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first power supply line; The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the second node.

13. The pixel driving circuit of claim 1, wherein, The driving sub-circuit comprises a first transistor, the first control sub-circuit comprises a second transistor, a third transistor and a second capacitor, the second control sub-circuit comprises a fourth transistor, an eighth transistor and a first capacitor, the third control sub-circuit comprises a seventh transistor, and the emitting control sub-circuit comprises a fifth transistor and a sixth transistor; The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth node, and the second electrode of the first transistor is electrically connected with the third node; The control electrode of the second transistor is electrically connected with the reset signal line, the first electrode of the second transistor is electrically connected with the reference signal line, and the second electrode of the second transistor is electrically connected with the first node; The control electrode of the third transistor is electrically connected with the first scan signal line, the first electrode of the third transistor is electrically connected with the first node, and the second electrode of the third transistor is electrically connected with the fourth node; The control electrode of the fourth transistor is electrically connected with the second scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the second node; The control electrode of the fifth transistor is electrically connected with the first emitting signal line, the first electrode of the fifth transistor is electrically connected with the fifth node, and the second electrode of the fifth transistor is electrically connected with the fourth node; The control electrode of the sixth transistor is electrically connected with the second emitting signal line, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the first power supply line; The control electrode of the seventh transistor is electrically connected with the reset signal line, the first electrode of the seventh transistor is electrically connected with the fifth node, and the second electrode of the seventh transistor is electrically connected with the reference signal line. The control electrode of the eighth transistor is electrically connected with the first scanning signal line, the first electrode of the eighth transistor is electrically connected with the second node, and the second electrode of the eighth transistor is electrically connected with the third node. The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the first power supply line. The second capacitor includes a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the second node.

14. The pixel driving circuit according to claim 12 or 13, characterized in that, The type of at least one of the first transistor to the eighth transistor is an N-type transistor.

15. The pixel driving circuit of claim 2, wherein, The difference between the voltage value of the second power supply line and the voltage value of the reference signal line is less than a set light-emitting start threshold value.

16. The pixel driving circuit of claim 15, wherein, The value range of the set light-emitting start threshold value is [1V, 2V].

17. A display device comprising: The pixel driving circuit according to any one of claims 1 to 16.

18. A driving method of a pixel driving circuit configured to drive the pixel driving circuit according to any one of claims 1 to 16, the method comprising: determining, by the driving sub-circuit, a driving current flowing between the third node and the fourth node under the control of the signal of the first node; providing, by the first control sub-circuit, the signal of the reference signal line or the fourth node to the first node and the signal of the first node to the second node under the control of the signals of the reset signal line and the first scanning signal line; providing, by the second control sub-circuit, the signal of the data signal line or the first power supply line to the second node under the control of the signals of the second scanning signal line and at least one control signal line; providing, by the third control sub-circuit, the signal of the reference signal line to the fifth node under the control of the signal of the reset signal line; providing, by the light-emitting control sub-circuit, the signal of the first power supply line to the third node and the signal of the fourth node to the fifth node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line; wherein the signal of the first power supply line is a negative voltage signal.

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