Analog-to-digital conversion circuits, control methods, chips and electronic devices

Abstract

The application provides an analog-digital conversion circuit, a control method, a chip and an electronic device, and belongs to the technical field of electronics. The analog-digital conversion circuit comprises at least a DAC module, a comparison module, a filtering module and a logic module; at the end of the previous conversion, the residual voltage is filtered, and a filtered signal is output; the DAC module comprises a first capacitor module and a second capacitor module, and a first plate is connected with an input end of the comparison module; during sampling, an input signal is connected to a second plate of the first capacitor module; at the start of conversion, the filtered signal is connected to the second plate of the first capacitor module; during conversion, the capacitance of the second capacitor module is switched based on a control signal of the logic module; the voltage on the first plate is compared; based on the comparison result, a control signal is output during conversion, and a digital signal code value is output at the end of conversion. Compared with a traditional successive approximation analog-digital conversion circuit, the application can improve the analog-digital conversion precision.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to an analog-to-digital conversion circuit, a control method, a chip, and an electronic device. Background Technology

[0002] In the field of electronics, analog-to-digital converter (ADC) circuits are used for signal measurement, converting analog signals into digital signals. Successive approximation register (SARADC) ADCs are a type of high-precision analog-to-digital converter.

[0003] Currently, the main problems encountered in achieving high-precision SAR ADCs are comparator noise and capacitor mismatch in the DAC array. Regarding comparator noise, the residual voltage after SAR ADC conversion can be passed to a dual-input path comparator for noise shaping via a loop filter. In a dual-input path comparator, each input path includes a non-inverting input and an inverting input. The residual voltage processed by the loop filter is connected to one input path, and the sampled voltage is connected to the other. Since both input paths contain comparator noise, this noise can be canceled out to reduce the comparator noise problem.

[0004] However, the mismatch between the two pairs of input transistors in the dual-input comparator and the mismatch of the common-mode voltage of the two pairs of input transistors will reduce the noise shaping capability and reduce the effect of noise shaping. Summary of the Invention

[0005] To address the problems of existing technologies, embodiments of this application provide an analog-to-digital conversion circuit, a control method, a chip, and an electronic device that can avoid the use of a dual-input path comparator and improve analog-to-digital conversion accuracy. The technical solution is as follows:

[0006] According to one aspect of this application, an analog-to-digital converter (ADC) circuit is provided, the ADC circuit including at least a digital-to-analog converter (DAC) module, a comparison module, a filtering module, and a logic module. The DAC module includes a first capacitor module and a second capacitor module. The first capacitor module and the second capacitor module each include at least one capacitor unit. The capacitor unit includes a first electrode and a second electrode. The first electrode is connected to the input terminal of the comparison module.

[0007] The filtering module is used to process the residual voltage on the first plate of the first capacitor module and the second capacitor module at the end of the previous analog-to-digital conversion cycle and output a filtered signal.

[0008] The DAC module is configured as follows:

[0009] During the sampling process of the current analog-to-digital conversion cycle, the input signal is connected to the second plate in the first capacitor module;

[0010] At the start of the current analog-to-digital conversion cycle, the filtered signal from the previous analog-to-digital conversion cycle is connected to the second plate in the first capacitor module;

[0011] During the current analog-to-digital conversion cycle, based on the control signal output by the logic module, each capacitor unit in the second capacitor module is controlled to perform a capacitor switching operation.

[0012] The comparison module is used to perform comparison processing based on the voltage on the first plate in the DAC module during the conversion process of the current analog-to-digital conversion cycle, and output a comparison result signal.

[0013] The logic module is configured to output the control signal during the conversion process of the current analog-to-digital conversion cycle based on the comparison result signal, and to output the target digital signal code value corresponding to the input signal at the end of the current analog-to-digital conversion cycle.

[0014] According to another aspect of this application, a control method for an analog-to-digital converter circuit is provided. The analog-to-digital converter circuit includes at least a digital-to-analog converter (DAC) module, a comparison module, a filtering module, and a logic module. The DAC module includes a first capacitor module and a second capacitor module. The first capacitor module and the second capacitor module each include at least one capacitor unit. The capacitor unit includes a first plate and a second plate. The first plate is connected to the input terminal of the comparison module.

[0015] The method includes:

[0016] The filtering module processes the residual voltage on the first plate of the first capacitor module and the second capacitor module at the end of the previous analog-to-digital conversion cycle and outputs a filtered signal.

[0017] The DAC module is controlled to perform the following processes: during the sampling process of the current analog-to-digital conversion cycle, the input signal is connected to the second plate in the first capacitor module; at the start of the conversion of the current analog-to-digital conversion cycle, the filtered signal of the previous analog-to-digital conversion cycle is connected to the second plate in the first capacitor module; during the conversion process of the current analog-to-digital conversion cycle, based on the control signal output by the logic module, each capacitor unit in the first capacitor module and the second capacitor module is controlled to perform a capacitor switching operation.

[0018] The comparison module performs a comparison based on the voltage on the first plate in the DAC module during the current analog-to-digital conversion cycle, and outputs a comparison result signal.

[0019] The logic module outputs the control signal during the current analog-to-digital conversion cycle based on the comparison result signal, and outputs the target digital signal code value corresponding to the input signal at the end of the current analog-to-digital conversion cycle.

[0020] According to another aspect of this application, a chip is provided, including the analog-to-digital conversion circuit described above.

[0021] According to another aspect of this application, an electronic device is provided, including the analog-to-digital conversion circuit described above.

[0022] In this application, the analog-to-digital conversion circuit uses the lower plate of a partial capacitor for sampling during the sampling process. At the start of the conversion, the processed residual voltage is transferred to the lower plate of the first capacitor module used solely for sampling. Based on the principle of charge conservation, the processed residual voltage is summed with the input signal to achieve noise shaping. Furthermore, a single-input path comparator module can be used, avoiding the use of a dual-input path comparator. This avoids the problems introduced by the mismatch between the two pairs of input transistors and the common-mode voltage mismatch between the two pairs of input transistors in a dual-input path comparator. Moreover, lower plate sampling is performed in the DAC module, which, compared to upper plate sampling, avoids the nonlinearity introduced by the parasitic capacitance mismatch of the comparator in different sampling periods. In summary, the analog-to-digital conversion circuit provided in this application improves the accuracy of analog-to-digital conversion. Attached Figure Description

[0023] Further details, features, and advantages of this application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0024] Figure 1 A schematic diagram of an analog-to-digital converter circuit provided according to an exemplary embodiment of this application is shown;

[0025] Figure 2 A schematic diagram of an analog-to-digital converter circuit based on lower plate sampling and MES function is shown according to an exemplary embodiment of this application;

[0026] Figure 3 A schematic diagram of an analog-to-digital converter circuit based on lower plate sampling, MES function and DWA function is shown according to an exemplary embodiment of this application;

[0027] Figure 4 This illustration shows a specific single-ended SARADC provided according to an exemplary embodiment of this application;

[0028] Figure 5 This illustrates another specific single-ended SARADC provided according to an exemplary embodiment of this application;

[0029] Figure 6 A schematic diagram of a comparison module provided according to an exemplary embodiment of this application is shown;

[0030] Figure 7 This illustrates a specific differential SARADC provided according to an exemplary embodiment of this application;

[0031] Figure 8 This diagram illustrates the state of the CDAC module during sampling according to an exemplary embodiment of this application.

[0032] Figure 9 This illustration shows a schematic diagram of the CDAC module state at the start of conversion according to an exemplary embodiment of this application;

[0033] Figure 10 A flowchart of a control method for an analog-to-digital conversion circuit provided according to an exemplary embodiment of this application is shown. Detailed Implementation

[0034] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0035] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the following description. It should be noted that the concepts of "first", "second", etc., mentioned in this application are used only to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies.

[0036] It should be noted that the terms "a" and "a plurality of" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0037] The names of the messages or information exchanged between multiple devices in the embodiments of this application are for illustrative purposes only and are not intended to limit the scope of these messages or information.

[0038] This application provides an analog-to-digital converter circuit that can be integrated into a chip or disposed in an electronic device.

[0039] Reference Figure 1 The schematic diagram of the analog-to-digital converter (ADC) circuit shown includes a digital-to-analog converter (DAC) module, a comparator module, a filter module, and a logic module. The DAC module may include a first capacitor module and a second capacitor module. Each capacitor module may include at least one capacitor unit, and each capacitor unit may include a first plate and a second plate. The first plate is connected to the input terminal of the comparator module. Generally, the capacitor plate connected to the input terminal of the comparator module is called the "upper plate," and the corresponding capacitor plate is called the "lower plate." That is, in this embodiment, the first plate can refer to the upper plate, and the second plate can refer to the lower plate.

[0040] The aforementioned filtering module can be used to process the residual voltage on the first plate of the first capacitor module and the second capacitor module at the end of the previous analog-to-digital conversion cycle, and output a filtered signal.

[0041] The above DAC module can be configured as follows:

[0042] During the sampling process of the current analog-to-digital conversion cycle, the input signal is connected to the second plate in the first capacitor module;

[0043] At the start of the current analog-to-digital conversion cycle, the filtered signal from the previous analog-to-digital conversion cycle is connected to the second plate in the first capacitor module;

[0044] During the current analog-to-digital conversion cycle, based on the control signals output by the logic module, each capacitor unit in the second capacitor module is controlled to perform a capacitor switching operation.

[0045] The aforementioned comparison module can be used to perform comparison processing based on the voltage on the first plate of the DAC module during the conversion process of the current analog-to-digital conversion cycle, and output the comparison result signal.

[0046] The above logic module can be configured to output the control signal during the conversion process of the current analog-to-digital conversion cycle based on the comparison result signal, and output the target digital signal code value corresponding to the input signal at the end of the current analog-to-digital conversion cycle.

[0047] In one possible implementation, the analog-to-digital converter (ADC) circuit measures the input signal and converts it into a digital signal code value. The input signal can be connected to a DAC module for sampling and conversion. For ease of explanation, this embodiment uses a single-ended input as an example.

[0048] Specifically, the DAC module can be divided into a first capacitor module and a second capacitor module, with only the first capacitor module used for sampling the input signal by the next-level board.

[0049] During the sampling process of the current analog-to-digital conversion cycle, the input signal can be connected to the lower plate of the capacitor unit in the first capacitor module for sampling. At this time, the lower plate of the capacitor unit in the second capacitor module does not need to be used for sampling; that is, only a portion of the capacitors are sampled. For the upper plate, the upper plate of each capacitor unit in the DAC module can be connected to the bias signal V. CM .

[0050] When the current analog-to-digital conversion cycle finishes sampling and begins conversion, the bias signal V will be connected to the upper plate. CM Disconnect, and transmit the residual voltage (i.e., the filtered signal) processed by the filter module at the end of the previous analog-to-digital conversion cycle to the lower plate of the first capacitor module.

[0051] Optionally, the residual voltage can be transferred from the upper plate of the DAC module to the filter module. In addition, the DAC module can also be configured to: at the end of the previous analog-to-digital conversion cycle, set the voltage on the first plate of the first capacitor module and the second capacitor module to the residual voltage, where the residual voltage refers to the margin voltage between the input signal and the output signal in the analog-to-digital conversion cycle; and transfer the residual voltage to the filter module.

[0052] In one possible implementation, at the end of the previous analog-to-digital conversion cycle, the analog-to-digital conversion circuit can output the current input signal V. IN The corresponding target digital signal code value D OUT This makes the voltage on the upper plate of the DAC module equal to the residual voltage V. IN -D OUT The input terminal of the filter module is connected to the upper plate of the DAC module, transmitting the residual voltage to the filter module so that the filter module can process the residual voltage.

[0053] When the current analog-to-digital conversion cycle ends and the conversion begins, the output of the filter module is connected to the lower plate of the first capacitor module to transmit the processed residual signal (i.e., the filtered signal) to the lower plate of the first capacitor module.

[0054] At this point, the voltage of the upper plate in the DAC module can be obtained based on the input signal and the residual voltage, and the residual voltage can include the noise level of the comparator module.

[0055] The conversion process then proceeds, quantizing the current voltage of the upper plate in the DAC module and converting it into a digital signal code value. Specifically, the ADC conversion process can include multiple clock cycles. In each clock cycle, the voltage of the upper plate in the DAC module is passed to the comparison module for comparison processing, outputting a comparison result signal, which is then passed to the logic module. The logic module can include a SAR logic array. In the SAR logic module, the comparison result can be processed based on preset SAR logic to generate corresponding control signals, which are then passed to the DAC module. In the next clock cycle, the DAC module can, based on the control signals, control each capacitor unit in the second capacitor module to perform a capacitor switching operation, that is, control the voltage of the lower plate connected to each capacitor unit to a logic high-level voltage (such as the reference voltage V). REF The logic module uses either a low-level logic voltage (such as ground voltage AGND) or a successive approximation method to determine the magnitude of the input signal. After the final comparison, the logic module can output the target digital signal code value corresponding to the input signal as the output signal. This completes one analog-to-digital conversion cycle. In the next analog-to-digital conversion cycle, the above analog-to-digital conversion process is repeated.

[0056] In the aforementioned analog-to-digital conversion process, since the residual voltage contains noise from the comparator module, the residual voltage processed by the filtering module is transmitted to the lower plate of the first capacitor module at the start of the conversion. Based on the principle of charge conservation, the processed residual voltage is summed with the input signal to achieve noise shaping. Therefore, a single-input path comparator module can be used, performing comparison processing only based on the upper plate voltage in the DAC module. This avoids the need for a dual-input path comparator to simultaneously compare the processed residual voltage with the sampled input signal (where the processed residual voltage is connected to one input path and the sampled input signal to the other). This avoids the problems introduced by the mismatch between the two pairs of input transistors and the common-mode voltage mismatch between the two pairs of input transistors in a dual-input path comparator. Furthermore, lower plate sampling is performed in the DAC module, which, compared to upper plate sampling, avoids the nonlinearity introduced by the parasitic capacitance mismatch of the comparator in different sampling periods. In summary, the analog-to-digital conversion circuit provided in this embodiment improves the accuracy of analog-to-digital conversion.

[0057] Optionally, to further improve the accuracy of analog-to-digital conversion, a second capacitor module can be used to retain capacitor mismatch information and perform mismatch error shaping to reduce the mismatch error. Specifically, the second capacitor module may include a first capacitor array. During the sampling process of the current analog-to-digital conversion cycle, the second plate in the first capacitor array can be used to maintain the state at the end of the previous analog-to-digital conversion cycle.

[0058] In one possible implementation, during the sampling process of the current analog-to-digital conversion cycle, the lower-level board of the capacitor unit in the first capacitor array can maintain its current state. If an analog-to-digital conversion has already been performed, the lower-level board of the capacitor unit in the second capacitor module can maintain its state at the end of the previous analog-to-digital conversion to retain the analog quantity containing capacitor mismatch information. Therefore, mismatch error shaping can be performed in the first capacitor array based on the capacitor mismatch information to reduce the mismatch error. Since only the first capacitor module is used for lower-level board sampling of the input signal, the second capacitor module can simultaneously be used to retain capacitor mismatch information, thus jointly achieving both avoiding the nonlinearity introduced by the comparator's parasitic capacitance and mismatch error shaping.

[0059] Optionally, based on this, the MES (Mismatch Error Shaping) function can be used to implement mismatch error shaping. For details, please refer to... Figure 2 The diagram shows a successive approximation analog-to-digital converter circuit based on lower plate sampling and MES function. The logic module of the analog-to-digital converter circuit can include SAR logic and MES logic.

[0060] Correspondingly, the logic module can be configured as follows:

[0061] During the current analog-to-digital conversion cycle, the comparison result signal output by the comparison module is converted into a first control signal. The first control signal is used to control each capacitor unit in the first capacitor array to perform a capacitor switching operation.

[0062] In one possible implementation, during the conversion process of the current analog-to-digital conversion cycle, in the logic module, the comparison result output by the comparison module can be processed based on preset SAR logic and MES logic. This process outputs the target digital signal code value corresponding to the input signal and generates a first control signal, which is then transmitted to the DAC module. The DAC module can then control each capacitor unit in the first capacitor array of the second capacitor module to perform capacitor switching operations based on the first control signal. Specifically, it controls the voltage of the lower plate connected to each capacitor unit to a logic high-level voltage (such as a reference voltage V). REFThe input signal magnitude is determined by a successive approximation method using a logic low-level voltage (such as ground voltage AGND), and mismatch error shaping is performed using the MES method. After the final comparison, the logic module can output the target digital signal code value corresponding to the input signal as the output signal.

[0063] In other words, the analog-to-digital conversion circuit provided in this embodiment can jointly realize partial capacitor lower plate sampling and MES function.

[0064] Furthermore, the analog-to-digital conversion circuit provided in this embodiment can also jointly implement partial capacitor lower plate sampling, MES function, and DWA (Data Weighted Average) function to further improve the accuracy of analog-to-digital conversion. The second capacitor module may also include a second capacitor array, which is a higher-order capacitor relative to the first capacitor array, and the sum of the number of bits of the capacitors in the first and second capacitor arrays is greater than the number of bits of the target digital signal code value corresponding to the input signal. That is to say, the MES method can be used to solve the problem of low-order capacitor mismatch, and the DWA method can be used to solve the problem of high-order capacitor mismatch.

[0065] Based on this, refer to Figure 3 The diagram shows an analog-to-digital converter circuit based on lower plate sampling, MES function and DWA function. The logic module of the analog-to-digital converter circuit can include SAR logic, MES logic and DWA logic.

[0066] Accordingly, the logic module can be configured to convert the comparison result signal output by the comparison module into a first control signal and a second control signal during the conversion process of the current analog-to-digital conversion cycle. The first control signal is used to control each capacitor unit in the first capacitor array to perform a capacitor switching operation, and the second control signal is used to control each capacitor unit in the second capacitor array to perform a capacitor switching operation.

[0067] In one possible implementation, during the conversion process, the logic module can process the comparison result output by the comparison module based on preset SAR logic and MES logic, output the target digital signal code value corresponding to the input signal and generate a first control signal, and then transmit the first control signal to the DAC module. The DAC module can, based on the first control signal, control each capacitor unit in the first capacitor array of the second capacitor module to perform a capacitor switching operation, that is, control the voltage of the lower plate of each capacitor unit connected to the first capacitor array to a logic high-level voltage (such as the reference voltage V). REFThe input signal magnitude is determined by a successive approximation method using a logic low-level voltage (such as ground voltage AGND), and mismatch error shaping is performed using the MES method. After the final comparison, the logic module can output the target digital signal code value corresponding to the input signal and process the additional digital quantity introduced by the MES method, converting it into a second control signal.

[0068] Specifically, the additional digital quantities can be processed based on preset DWA logic to generate a second control signal, which is then transmitted to the DAC module. The DAC module can use this second control signal to control each capacitor unit in the second capacitor array of the second capacitor module to perform capacitor switching operations. That is, it controls the voltage of the lower plate of each capacitor unit in the second capacitor array to be either a logic high-level voltage (such as the reference voltage VREF) or a logic low-level voltage (such as the ground voltage AGND), thus solving the high-level capacitor mismatch problem through the DWA method. Optionally, the size of each capacitor unit in the second capacitor array can be equal to the size of each capacitor unit in the first capacitor array; for example, all units can be 256C0 capacitors. This allows the dynamic range loss introduced by the MES method to be recovered by predicting the magnitude of the next input signal.

[0069] Optionally, during the sampling process of the current analog-to-digital conversion cycle, the voltage on the second plate of the second capacitor array is configured to be connected to a reset voltage; at the start of the conversion of the current analog-to-digital conversion cycle, the voltage on the second plate of the first capacitor array is configured to be connected to a corresponding reset voltage. The reset voltage may include a reference voltage V. REF Or ground voltage AGND. As an example, during the sampling process of the current analog-to-digital conversion cycle, the lower plate of the first capacitor array is used to maintain the state at the end of the previous analog-to-digital conversion cycle, and the voltage of the lower plate of the second capacitor array is reset to the reference voltage V. REF At the start of the current analog-to-digital conversion cycle, the lower plate in the corresponding first capacitor array can be reset from its state at the end of the previous analog-to-digital conversion cycle to the same reference voltage V. REF .

[0070] Optionally, the filtering module may include a buffer and a switched-capacitor integrator.

[0071] As a concrete example, Figure 4A specific single-ended SARADC is shown, which includes a CDAC (charge redistribution DAC, corresponding to the DAC module mentioned above), a comparator (corresponding to the comparison module mentioned above), a logic array containing SAR logic, MES logic and DWA logic (corresponding to the logic module mentioned above), and a filter (composed of a buffer and a switched capacitor integrator, corresponding to the filter module mentioned above).

[0072] This SARADC is based on traditional split-capacitor timing, and its CDAC includes a sampling capacitor C. SAM High-level capacitor C M3 To C M1 Low-side capacitor C L9 To C L1 Terminal capacitor C d Among them, the sampling capacitor C SAM Corresponding to the first capacitor module mentioned above, C SAM Choose a capacitor of 2048C0, where C0 is the unit capacitance; the higher-order capacitance C... M3 To C M1 Corresponding to the second capacitor array in the second capacitor module mentioned above, C M3 There are four 256C0 capacitors, C M2 For two 256C0 capacitors, C M1 One 256C0 capacitor; low-order capacitor C L9 To C L1 and terminal capacitor C d Corresponding to the first capacitor array in the second capacitor module mentioned above, each low-order capacitor is a 256C0 capacitor. Fta<1:17> is the lower plate voltage control signal, where Fta<9:17> corresponds to the first control signal mentioned above, and Fta<2:8> corresponds to the second control signal mentioned above. V IN V is the input signal of the SARADC. REF AGND is the logic high-level voltage in the CDAC, and AGND is the logic low-level voltage in the CDAC. The filter consists of a buffer and an active switched-capacitor integrator, used for traditional first-order noise shaping, and its output is V. INT The signal has a transfer function of z^-1 / (1+z^-1), where z is the input of the filter.

[0073] The specific analog-to-digital conversion process of this SARADC is the same as that described above, and will not be repeated here. After the last comparison, the logic module can output the target digital signal code value D<12:1> corresponding to the input signal. After the normal SAR ADC conversion is completed, the residual voltage of the CDAC top plate is passed to the integrator through the buffer, and the integrator is established during SAR ADC sampling, followed by SAR ADC conversion. In the final output digital code, the additional digital quantity D_3bit introduced by the MES method needs to be processed. The DWA logic converts the above additional digital quantity into the control signal Fta<2:8> and passes it to the CDAC to control the high-order capacitor C. M3 To C M1 The lower electrode plate is connected to V REF Alternatively, AGND can be used to address the high-level capacitor mismatch issue via the DWA method. Furthermore, each capacitor in the high-level capacitors is the same size as the low-level capacitors, both being 256C0. This allows for the recovery of the dynamic range loss introduced by the MES method by predicting the next total system input signal magnitude.

[0074] As another specific example Figure 5 Another specific single-ended SARADC is shown, with Figure 4 Compared to the single-ended SARADC shown, the difference lies in that its CDAC is divided into two capacitor modules, namely C PA C PB Each capacitor module has the same capacitor configuration, meaning each capacitor module is identical to... Figure 4 The single-ended SAR ADC shown has the same CDAC, which is divided into sampling capacitor C. SAM High-level capacitor C M3 To C M1 Low-side capacitor C L9 To C L1 Terminal capacitor C d Fta<1:17> is C PA The lower plate voltage control signal of the capacitor module, where Fta<9:17> corresponds to the first control signal mentioned above, and Fta<2:8> corresponds to the second control signal mentioned above. Ftb<1:17> is C PB The lower plate voltage control signal of the capacitor module, wherein Ftb<9:17> corresponds to the first control signal mentioned above, and Ftb<2:8> corresponds to the second control signal mentioned above. Figure 5 The remaining parts of the single-ended SARADC are shown. Figure 4 The working principle is the same, so it will not be elaborated here.

[0075] Optionally, the DAC module described above is a single-ended DAC. The DAC module can also be a differential DAC. The first capacitor module includes a first-end first capacitor submodule and a second-end first capacitor submodule, and the second capacitor module includes a first-end second capacitor submodule and a second-end second capacitor submodule. For example, the first-end first capacitor submodule can refer to a P-end / N-end first capacitor submodule, and correspondingly, the second-end first capacitor submodule can refer to an N-end / P-end second capacitor submodule; similarly, the first-end second capacitor submodule can refer to a P-end / N-end second capacitor submodule, and correspondingly, the second-end second capacitor submodule can refer to an N-end / P-end second capacitor submodule.

[0076] Reference Figure 6 The schematic diagram of the comparison module shows that the first plate of the first capacitor submodule at the first end and the first plate of the second capacitor submodule at the first end are connected to the first phase input terminal of the comparison module; the first plates of the first capacitor submodule at the second end and the first plates of the second capacitor submodule at the second end are connected to the second phase input terminal of the comparison module. Here, the first phase input terminal can refer to the positive phase input terminal, and the corresponding second phase input terminal can refer to the inverting phase input terminal; conversely, the first phase input terminal can refer to the inverting phase input terminal, and the corresponding second phase input terminal can refer to the positive phase input terminal. Unlike a dual-input path comparator, the comparison module used in this embodiment is a single-input path, and the aforementioned first phase input terminal and second phase input terminal constitute a single input path.

[0077] As a concrete example, Figure 7 A specific differential SARADC is shown, which includes a CDAC (charge redistribution DAC, corresponding to the DAC module mentioned above), a comparator (corresponding to the comparison module mentioned above), a logic array containing SAR logic, MES logic and DWA logic (corresponding to the logic module mentioned above), and a filter (composed of a buffer and a switched capacitor integrator, corresponding to the filtering module mentioned above).

[0078] This noise-shaping SARADC is based on traditional split-capacitor timing, and its CDAC is divided into four capacitor modules, namely C PA C PB C NC C ND Each capacitor module has the same capacitor configuration, consisting of a sampling capacitor C. SAM High-level capacitor C M3 To C M1 Low-side capacitor C L9 To C L1 Terminal capacitor C d Among them, the sampling capacitor C SAM Corresponding to the first capacitor module mentioned above, C SAMChoose a capacitor of 2048C0, where C0 is the unit capacitance; the higher-order capacitance C... M3 To C M1 Corresponding to the second capacitor array in the second capacitor module mentioned above, C M3 There are four 256C0 capacitors, C M2 For two 256C0 capacitors, C M1 One 256C0 capacitor; low-order capacitor C L9 To C L1 and terminal capacitor C d Corresponding to the first capacitor array in the second capacitor module mentioned above, each low-order capacitor is a 256C0 capacitor.

[0079] Fta<1:17> is C PA The lower plate voltage control signal of the capacitor module, where Fta<9:17> corresponds to the first control signal mentioned above, and Fta<2:8> corresponds to the second control signal mentioned above. Ftb<1:17> is C PB The lower plate voltage control signal of the capacitor module, where Ftb<9:17> corresponds to the first control signal mentioned above, and Ftb<2:8> corresponds to the second control signal mentioned above. Fbc<1:17> is C. NC The lower plate voltage control signal of the capacitor module, where Fbc<9:17> corresponds to the first control signal mentioned above, and Fbc<2:8> corresponds to the second control signal mentioned above. Fbd<1:17> is C. ND The lower plate voltage control signal of the capacitor module, wherein Fbd<9:17> corresponds to the first control signal mentioned above, and Fbd<2:8> corresponds to the second control signal mentioned above.

[0080] V INP With V INN V is the input signal of the SARADC. REF AGND is the logic high-level voltage in the CDAC, and AGND is the logic low-level voltage in the CDAC. The filter consists of a buffer and an active switched-capacitor integrator, used for traditional first-order noise shaping, and its output is V. INT_P With V INT_N The signal has a transfer function of z^-1 / (1+z^-1), where z is the input of the filter.

[0081] During sampling, the CDAC module state is as follows: Figure 8 As shown in Figure C. PA Taking the capacitor module as an example, C PA C of capacitor module 2048C0 SAM Capacitor connected to input signal V INP The seven 256C0 capacitors in the high-order capacitor section were reset normally to AGND, while the low-order capacitor section LSBa (i.e., the low-order capacitor C) was reset to AGND.L9 To C L1 and terminal capacitor C d It is only necessary to maintain the state V at the end of the previous cycle. PA_LSB It can remain unchanged. C PB With the above C PA The states are the same, so we won't go into detail here. Similarly, C ND C of capacitor module 2048C0 SAM Capacitor connected to input signal V INN The seven 256C0 capacitors at the high position have been reset to V normally. REF The low-side capacitor portion LSBc (i.e., low-side capacitor C) L9 To C L1 and terminal capacitor C d It is only necessary to maintain the state at the end of the previous cycle. NC_LSB That's all. (C) NC With the above C ND The states are the same, so they will not be described again here. The upper plate of each capacitor module is connected to a bias voltage V. CM .

[0082] If MES operation is not considered, the charge Q on the P-side capacitor is as follows. 1P and the charge Q on the N side 1N as follows:

[0083] Q 1P =(2048*2)C0*(V CM -V INP )+(256*7+256)C0*(V CM -V REF )+(256*7+256)C0*(V CM -0)

[0084] Q 1N =(2048*2)C0*(V CM -V INN )+(256*7+256)C0*(V CM -V REF )+(256*7+256)C0*(V CM -0)

[0085] When sampling ends and conversion begins, the CDAC module state is as follows: Figure 9 As shown. The output voltage V of the loop filter. INT_N Transmit to C PA and C PB C of the capacitor module SAM lower plate of capacitor, V INT_P Transmit to C NC and C ND C of the capacitor moduleSAM lower plate of capacitor, C PA and C NC The voltage at the lower plate of the low-level capacitor in the capacitor module changes from its state at the end of the previous cycle to the same AGND as the high-level capacitor. PB and C ND The voltage of the lower plate of the low-level capacitor in the capacitor module changes from the state at the end of the previous cycle to the same AGND as the high-level capacitor.

[0086] At this time, the charge Q on the capacitor on side P is... 2P and the charge Q on the N side 2N As follows, where V XP It is the voltage on the upper plate of the P side, V XN It is the voltage of the upper plate on the N side:

[0087] Q 2P =(2048*2)C0*(V XP -V INT_P )+(256*7+256)C0*(V XP -V REF )+(256*7+256)C0*(V XP -0)

[0088] Q 2N =(2048*2)C0*(V XN -V INT_N )+(256*7+256)C0*(V XN -V REF )+(256*7+256)C0*(V XN -0)

[0089] The voltage V on the upper plate of side P at the start of the conversion can be obtained. XP and the voltage V on the upper plate of the N side XN They are respectively:

[0090]

[0091]

[0092] The comparator input differential voltage is:

[0093]

[0094] During the subsequent normal SAR ADC quantization process, the comparison result output by the comparator is converted into control signals Fta<9:17>, Ftb<9:17>, Fbc<9:17>, and Fbd<9:17> via the SAR logic array, and then transmitted to the CDAC to control the low-order capacitor C. L9 To C L1and terminal capacitor C d The lower electrode plate is connected to V REF Alternatively, AGND can be used to determine the magnitude of the input signal using a successive approximation method, and mismatch error shaping can be performed using the MES method. Specifically, the analog portion of the LSB from the previous period, containing capacitor mismatch information, is transferred to the current period for mismatch error shaping to reduce the mismatch error. Furthermore, the processed residual signal is transferred to the current period for noise shaping to reduce quantization noise. The input signal is received during partial capacitor sampling, and the processed residual voltage V is received during conversion. INT_P This cleverly achieves the sharing of lower plate sampling and MES method, and avoids the problems caused by mismatch when using a dual-input path comparator. After the last comparison, the logic module can output the target digital signal code value D<12:1> corresponding to the input signal.

[0095] After the normal SAR ADC conversion is completed, the residual voltage of the CDAC top plate is passed to the integrator through a buffer. The integrator is established during SAR ADC sampling, followed by SAR ADC conversion. In the final output digital code, the additional digital quantities introduced by the MES method need to be processed, namely C... PA The corresponding values ​​are D_3bit_a, D_3bit_b for CPB, D_3bit_c for CNC, and D_3bit_d for CND. The DWA logic converts these additional digital values ​​into control signals Fta<2:8>, Ftb<2:8>, Fbc<2:8>, and Fbd<2:8>, which are then passed to CDAC to control the high-order capacitor C. M3 To C M1 The lower electrode plate is connected to V REF Alternatively, AGND can be used to address the high-level capacitor mismatch issue via the DWA method. Furthermore, each capacitor in the high-level capacitors is the same size as the low-level capacitors, both being 256C0. This allows for the recovery of the dynamic range loss introduced by the MES method by predicting the magnitude of the next total system input signal.

[0096] The embodiments of this application can achieve the following beneficial effects:

[0097] (1) In the analog-to-digital converter (ADC) circuit, sampling is performed using the lower plate of a portion of the capacitor. At the start of the conversion, the processed residual voltage is transferred to the lower plate of the first capacitor module used solely for sampling. Based on the principle of charge conservation, the processed residual voltage is summed with the input signal to achieve noise shaping. This allows for the use of a single-input path comparator, avoiding the use of a dual-input path comparator and thus preventing problems caused by mismatches between the two pairs of input transistors and common-mode voltages in a dual-input path comparator. Furthermore, the DAC module uses lower plate sampling, which, compared to upper plate sampling, avoids nonlinearity caused by parasitic capacitance mismatches in different sampling periods. In summary, the ADC circuit provided in this embodiment improves the accuracy of the analog-to-digital conversion.

[0098] (2) The analog-to-digital conversion circuit provided in this embodiment can jointly realize the sampling of the lower plate and the MES function, and further realize the mismatch error shaping.

[0099] (3) The analog-to-digital conversion circuit provided in this embodiment can also jointly realize the lower plate sampling, MES function and DWA function. The MES method is used to solve the problem of low-level capacitor mismatch, and the DWA method is used to solve the problem of high-level capacitor mismatch, which further improves the accuracy of analog-to-digital conversion.

[0100] This application also provides a control method for an analog-to-digital converter (ADC) circuit, which can be used to control the aforementioned ADC circuit. The ADC circuit includes at least a digital-to-analog converter (DAC) module, a comparator module, a filter module, and a logic module. The DAC module includes a first capacitor module and a second capacitor module. The first capacitor module and the second capacitor module each include at least one capacitor unit. Each capacitor unit includes a first electrode and a second electrode. The first electrode is connected to the input terminal of the comparator module. (Refer to...) Figure 10 The flowchart of the control method for the analog-to-digital converter circuit shown is as follows:

[0101] Step 1001: At the end of the previous analog-to-digital conversion cycle, the residual voltage on the first plate of the first capacitor module and the second capacitor module is processed by the filtering module to output a filtered signal.

[0102] Step 1002: Control the DAC module to perform the following processing: During the sampling process of the current analog-to-digital conversion cycle, connect the input signal to the second plate in the first capacitor module; at the start of the conversion of the current analog-to-digital conversion cycle, connect the filtered signal of the previous analog-to-digital conversion cycle to the second plate in the first capacitor module; during the conversion process of the current analog-to-digital conversion cycle, based on the control signal output by the logic module, control each capacitor unit in the first capacitor module and the second capacitor module to perform capacitor switching operation respectively.

[0103] Step 1003: During the current analog-to-digital conversion cycle, the comparison module performs a comparison based on the voltage on the first plate in the DAC module and outputs a comparison result signal.

[0104] Step 1004: Through the logic module, based on the comparison result signal, output the control signal during the conversion process of the current analog-to-digital conversion cycle, and output the target digital signal code value corresponding to the input signal at the end of the current analog-to-digital conversion cycle.

[0105] Optionally, the method further includes:

[0106] The DAC module is controlled to perform the following processing:

[0107] At the end of the previous analog-to-digital conversion cycle, the voltage on the first plate in the first capacitor module and the second capacitor module is set to the residual voltage, which refers to the margin voltage between the input signal and the output signal in the current analog-to-digital conversion cycle.

[0108] The residual voltage is transmitted to the filter module.

[0109] Optionally, the second capacitor module includes a first capacitor array;

[0110] The method further includes:

[0111] During the sampling process of the current analog-to-digital conversion cycle, the second plate in the first capacitor array is used to maintain the state at the end of the previous analog-to-digital conversion cycle.

[0112] Optionally, the step of outputting the control signal during the conversion process of the current analog-to-digital conversion cycle based on the comparison result signal through the logic module includes:

[0113] The logic module performs the following processing: during the conversion process of the current analog-to-digital conversion cycle, the comparison result signal output by the comparison module is converted into a first control signal, which is used to control each capacitor unit in the first capacitor array to perform a capacitor switching operation.

[0114] Optionally, the second capacitor module further includes a second capacitor array, which is a higher-order capacitor relative to the first capacitor array.

[0115] Optionally, the step of outputting the control signal during the conversion process of the current analog-to-digital conversion cycle based on the comparison result signal through the logic module includes:

[0116] The logic module performs the following processing: during the conversion process of the current analog-to-digital conversion cycle, the comparison result signal output by the comparison module is converted into a first control signal and a second control signal. The first control signal is used to control each capacitor unit in the first capacitor array to perform a capacitor switching operation, and the second control signal is used to control each capacitor unit in the second capacitor array to perform a capacitor switching operation.

[0117] Optionally, the method further includes:

[0118] During the sampling process of the current analog-to-digital conversion cycle, the voltage on the second plate in the second capacitor array is configured to be connected to the reset voltage;

[0119] At the start of the current analog-to-digital conversion cycle, the voltage on the second plate in the first capacitor array is configured to be connected to the reset voltage.

[0120] Optionally, the first capacitor module includes a first capacitor submodule at a first end and a first capacitor submodule at a second end, and the second capacitor module includes a second capacitor submodule at a first end and a second capacitor submodule at a second end.

[0121] The first plate in the first capacitor submodule of the first end and the first plate in the second capacitor submodule of the first end are connected to the first phase input terminal of the comparison module;

[0122] The first plate in the first capacitor submodule at the second end and the first plate in the second capacitor submodule at the second end are connected to the second phase input terminal of the comparison module.

[0123] Optionally, the filtering module includes a buffer and a switched-capacitor integrator.

[0124] The embodiments of this application can achieve the following beneficial effects:

[0125] (1) In the analog-to-digital converter (ADC) circuit, sampling is performed using the lower plate of a portion of the capacitor. At the start of the conversion, the processed residual voltage is transferred to the lower plate of the first capacitor module used solely for sampling. Based on the principle of charge conservation, the processed residual voltage is summed with the input signal to achieve noise shaping. This allows for the use of a single-input path comparator, avoiding the use of a dual-input path comparator and thus preventing problems caused by mismatches between the two pairs of input transistors and common-mode voltages in a dual-input path comparator. Furthermore, the DAC module uses lower plate sampling, which, compared to upper plate sampling, avoids nonlinearity caused by parasitic capacitance mismatches in different sampling periods. In summary, the ADC circuit provided in this embodiment improves the accuracy of the analog-to-digital conversion.

[0126] (2) The analog-to-digital conversion circuit provided in this embodiment can jointly realize the sampling of the lower plate and the MES function, and further realize the mismatch error shaping.

[0127] (3) The analog-to-digital conversion circuit provided in this embodiment can also jointly realize the lower plate sampling, MES function and DWA function. The MES method is used to solve the problem of low-level capacitor mismatch, and the DWA method is used to solve the problem of high-level capacitor mismatch, which further improves the accuracy of analog-to-digital conversion.

[0128] An exemplary embodiment of this application also provides a chip including the analog-to-digital conversion circuit provided in the embodiments of this application. In the analog-to-digital conversion circuit, sampling is performed using the lower plate of a partial capacitor. At the start of conversion, the processed residual voltage is transmitted to the lower plate of a first capacitor module used only for sampling. Based on the principle of charge conservation, the processed residual voltage is summed with the input signal to achieve noise shaping. Furthermore, a single-input path comparator module can be used, avoiding the use of a dual-input path comparator. This avoids the problems introduced by the mismatch between the two pairs of input transistors and the mismatch of the common-mode voltage between the two pairs of input transistors in a dual-input path comparator. Moreover, lower plate sampling is performed in the DAC module, which, compared to upper plate sampling, avoids the nonlinearity introduced by the mismatch of the comparator's parasitic capacitance in different sampling periods. This improves the accuracy of the analog-to-digital conversion, thereby improving chip performance.

[0129] An exemplary embodiment of this application also provides an electronic device, including the analog-to-digital conversion circuit provided in the embodiments of this application. In the analog-to-digital conversion circuit, sampling is performed using the lower plate of a partial capacitor. At the start of conversion, the processed residual voltage is transmitted to the lower plate of a first capacitor module used only for sampling. Based on the principle of charge conservation, the processed residual voltage is summed with the input signal to achieve noise shaping. Furthermore, a single-input path comparator module can be used, avoiding the use of a dual-input path comparator, thus avoiding problems introduced by the mismatch between the two pairs of input transistors and the mismatch of the common-mode voltage between the two pairs of input transistors in a dual-input path comparator. Moreover, lower plate sampling is performed in the DAC module, which, compared to upper plate sampling, avoids the nonlinearity introduced by the mismatch of the comparator's parasitic capacitance in different sampling periods. This improves the accuracy of analog-to-digital conversion, thereby improving the performance of the electronic device.

[0130] The foregoing has provided a detailed description of the successive approximation analog-to-digital converter circuit, control method, chip, and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An analog-to-digital conversion circuit, characterized by, The analog-to-digital conversion circuit comprises a digital-to-analog conversion (DAC) module, a comparison module, a filtering module and a logic module, the DAC module comprises a first capacitor module and a second capacitor module, the first capacitor module and the second capacitor module each comprise at least one capacitor unit, the capacitor unit comprises a first plate and a second plate, the first plate is connected with an input end of the comparison module; The filtering module is configured to process a residual voltage on the first plate in the first capacitor module and the second capacitor module at the end of a previous analog-to-digital conversion period, and output a filtering signal; The DAC module is configured to: during sampling in a current analog-to-digital conversion period, input a signal into the second plate in the first capacitor module; at the beginning of conversion in the current analog-to-digital conversion period, input the filtering signal in the previous analog-to-digital conversion period into the second plate in the first capacitor module; during conversion in the current analog-to-digital conversion period, based on a control signal output by the logic module, control each capacitor unit in the second capacitor module to perform a capacitor switching operation; The comparison module is configured to, during conversion in the current analog-to-digital conversion period, perform comparison processing based on a voltage on the first plate in the DAC module, and output a comparison result signal; The logic module is configured to, based on the comparison result signal, output the control signal during conversion in the current analog-to-digital conversion period, and output a target digital signal code value corresponding to the input signal at the end of the current analog-to-digital conversion period.

2. The analog-to-digital conversion circuit of claim 1, wherein, The DAC module is further configured to: at the end of the previous analog-to-digital conversion period, set the voltage on the first plate in the first capacitor module and the second capacitor module as the residual voltage, the residual voltage refers to a residual voltage between an input signal and an output signal in an analog-to-digital conversion period; deliver the residual voltage to the filtering module.

3. The analog-to-digital conversion circuit of claim 1, wherein, The second capacitor module comprises a first capacitor array; during sampling in the current analog-to-digital conversion period, the second plate in the first capacitor array is used to maintain a state at the end of the previous analog-to-digital conversion period.

4. The analog-to-digital conversion circuit of claim 3, wherein, The logic module is configured to: during conversion in the current analog-to-digital conversion period, convert the comparison result signal output by the comparison module into a first control signal, and the first control signal is used to control each capacitor unit in the first capacitor array to perform a capacitor switching operation.

5. The analog-to-digital conversion circuit of claim 3, wherein, The second capacitor module further comprises a second capacitor array, and the second capacitor array is a high-capacitance capacitor array relative to the first capacitor array.

6. The analog-to-digital conversion circuit of claim 5, wherein, The logic module is configured to: during conversion in the current analog-to-digital conversion period, convert the comparison result signal output by the comparison module into a first control signal and a second control signal, the first control signal is used to control each capacitor unit in the first capacitor array to perform a capacitor switching operation, and the second control signal is used to control each capacitor unit in the second capacitor array to perform a capacitor switching operation.

7. The analog-to-digital conversion circuit according to claim 5, wherein, In a sampling process of a current analog-to-digital conversion cycle, the voltage on the second plate in the second capacitor array is configured to access a reset voltage; At the beginning of conversion of the current analog-to-digital conversion cycle, the voltage on the second plate in the first capacitor array is configured to access the reset voltage.

8. The analog-to-digital conversion circuit of claim 1, wherein, The first capacitor module includes a first-end first capacitor submodule and a second-end first capacitor submodule, and the second capacitor module includes a first-end second capacitor submodule and a second-end second capacitor submodule; The first plate in the first-end first capacitor submodule and the first plate in the first-end second capacitor submodule are connected with a first-phase input end of the comparison module; The first plate in the second-end first capacitor submodule and the first plate in the second-end second capacitor submodule are connected with a second-phase input end of the comparison module.

9. The analog-to-digital conversion circuit of claim 1, wherein, The filter module includes a buffer and a switched capacitor integrator.

10. A control method of an analog-digital conversion circuit, characterized by, The analog-to-digital conversion circuit at least includes a digital-to-analog conversion (DAC) module, a comparison module, a filter module and a logic module, the DAC module includes a first capacitor module and a second capacitor module, the first capacitor module and the second capacitor module each include at least one capacitor unit, the capacitor unit includes a first plate and a second plate, and the first plate is connected with an input end of the comparison module; The method includes: At the end of a previous analog-to-digital conversion cycle, the filter module processes residual voltage on the first plate in the first capacitor module and the second capacitor module, and outputs a filtered signal; The DAC module is controlled to perform the following processing: in a sampling process of a current analog-to-digital conversion cycle, an input signal is accessed to the second plate in the first capacitor module; at the beginning of conversion of the current analog-to-digital conversion cycle, the filtered signal of a previous analog-to-digital conversion cycle is accessed to the second plate in the first capacitor module; in a conversion process of the current analog-to-digital conversion cycle, based on a control signal output by the logic module, each capacitor unit in the first capacitor module and the second capacitor module is controlled to perform a capacitor switching operation; In a conversion process of a current analog-to-digital conversion cycle, the comparison module performs comparison processing based on voltage on the first plate in the DAC module, and outputs a comparison result signal; In a conversion process of a current analog-to-digital conversion cycle, the logic module outputs the control signal based on the comparison result signal, and at the end of the current analog-to-digital conversion cycle, outputs a target digital signal code value corresponding to the input signal.

11. A chip, characterized by An analog-to-digital conversion circuit as claimed in any one of claims 1-9.

12. An electronic device, comprising: An analog-to-digital conversion circuit as claimed in any one of claims 1-9.

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