Chip surface morphology simulation method and device and computer readable storage medium

Abstract

The application relates to a chip surface morphology simulation method and device and a computer readable storage medium. Layout information of a chip to be simulated is acquired. Through a physical simulation model, the surface morphology of the chip to be simulated is simulated based on the layout information, and a surface morphology simulation result is obtained. Through a trained surface morphology prediction model, the surface morphology of the chip to be simulated is predicted based on the layout information, and a surface morphology prediction result is obtained. According to the surface morphology simulation result and the surface morphology prediction result, surface morphology data of the chip to be simulated is determined. The surface morphology of the chip to be simulated is predicted by fully considering the surface morphology simulation result and the surface morphology prediction result, the fusion of the physical simulation model and the trained surface morphology prediction model is realized, and the accuracy of surface morphology data prediction of the chip to be simulated is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip surface morphology simulation, in particular to a chip surface morphology simulation method, device and computer readable storage medium. BACKGROUND

[0002] Chemical mechanical polishing (CMP) process is a key technology in semiconductor manufacturing, mainly used for planarizing wafer surface. This process removes the material on the surface of the wafer by combining chemical reaction and physical grinding, achieving a highly uniform and smooth surface. As semiconductor technology enters the deep sub-micron era, the size of circuit elements is constantly shrinking, and the requirement for wafer surface flatness is becoming higher and higher. Through the CMP process, the focal depth problem in the photolithography process can be reduced, and short circuit and open circuit between wires can be avoided, thereby improving the manufacturing success rate and performance of integrated circuits. In addition, the CMP process also helps to reduce interconnection delay and reduce power consumption. In the manufacture of multi-layer metal interconnection, the smooth surface achieved by the CMP process can reduce the capacitive effect between metal lines, thereby reducing signal transmission delay and power consumption. CMP process simulation is crucial for predicting wafer surface topography information after CMP process, supporting analysis and monitoring in process development and production process; therefore, the accuracy of CMP process simulation is of great significance to improve the manufacturing process and quality of integrated circuits.

[0003] The existing process simulation method is based on a physical model, which predicts the chip surface morphology after CMP process through advanced mathematical models and computer simulation. However, the CMP process is affected by many parameters, and the accuracy of the physical model is extremely dependent on the accurate setting of the parameters. In practice, these parameters are often difficult to accurately measure or determine, which will cause a certain deviation between the chip surface morphology prediction result and the actual situation, that is, the process simulation method in the prior art is easily affected by the parameter setting, resulting in low accuracy of the chip surface morphology prediction result.

[0004] At present, there is no effective solution to the problem of low accuracy of chip surface morphology prediction result in the prior art. SUMMARY

[0005] Therefore, it is necessary to provide a chip surface morphology simulation method, device and computer readable storage medium to solve the above technical problems.

[0006] In a first aspect, the present application provides a chip surface morphology simulation method, which comprises:

[0007] obtaining layout information of a chip to be simulated;

[0008] simulate a surface morphology of the chip to be simulated based on the layout information, to obtain a surface morphology simulation result;

[0009] predict a surface morphology of the chip to be simulated based on the layout information by using the trained surface morphology prediction model, to obtain a surface morphology prediction result;

[0010] determine surface morphology data of the chip to be simulated according to the surface morphology simulation result and the surface morphology prediction result.

[0011] In one of the embodiments, before the step of predicting a surface morphology of the chip to be simulated based on the layout information by using the trained surface morphology prediction model, to obtain a surface morphology prediction result, the method further comprises:

[0012] obtain a plurality of random seeds, wherein the random seeds are different from each other;

[0013] based on the plurality of random seeds, establish a plurality of base models corresponding to the plurality of random seeds, to obtain a surface morphology prediction model integrated with the plurality of base models;

[0014] obtain a sample data set;

[0015] train the surface morphology prediction model based on the sample data set, to obtain a trained surface morphology prediction model.

[0016] In one of the embodiments, the step of training the surface morphology prediction model based on the sample data set, to obtain a trained surface morphology prediction model, comprises:

[0017] for each base model, divide the sample data set according to a preset division rule, to determine a training set and a validation set corresponding to each base model;

[0018] train the base model based on the training set and the validation set corresponding to each base model, to obtain a trained base model;

[0019] determine the trained surface morphology prediction model according to a plurality of trained base models.

[0020] In one of the embodiments, the step of obtaining a sample data set comprises:

[0021] obtain grid-based layout information of a test chip and surface morphology representation data of a grid of the test chip after a CMP process;

[0022] standardize the grid-based layout information, to obtain a corresponding layout information tensor;

[0023] obtaining a layout information tensor slice based on a preset sliding sequence and a preset sliding step size by using a preset size sliding window, wherein the preset size sliding window is an m*n grid size sliding window;

[0024] flattening the layout information tensor slice into a one-dimensional vector, and taking the one-dimensional vector as input data of the sample;

[0025] taking surface morphology representation data corresponding to a center grid of the preset size sliding window as a label of the sample;

[0026] constructing a sample data set according to the input data of the sample and the label of the sample.

[0027] In one embodiment, the obtaining of the layout information tensor slice based on the preset sliding sequence and the preset sliding step size by using the preset size sliding window includes:

[0028] taking the layout information tensor in the preset size sliding window as the layout information tensor slice;

[0029] if edge grid information is missing in the preset size sliding window, performing information completion on a position of the missing edge grid information according to a preset completion rule to obtain a corresponding layout information tensor slice.

[0030] In one embodiment, before the simulation of the surface morphology of the chip to be simulated based on the layout information by using the physical simulation model to obtain a surface morphology simulation result, the method further includes:

[0031] obtaining an initial physical simulation model and a simulation process recipe;

[0032] performing model parameter calibration on the initial physical simulation model based on the simulation process recipe, the grid layout information corresponding to the test chip, and surface morphology representation data of the grid of the test chip after the CMP process to obtain a physical simulation model.

[0033] In one embodiment, the obtaining of the layout information of the chip to be simulated includes: obtaining grid layout information of a plurality of to-be-simulated grids in a grid-divided layout of the chip to be simulated;

[0034] The prediction of the surface morphology of the chip to be simulated based on the layout information by using the trained surface morphology prediction model to obtain a surface morphology prediction result includes:

[0035] According to the grid layout information corresponding to each of the to-be-simulated grids, the surface morphology of each of the to-be-simulated grids is predicted by using the plurality of base models in the trained surface morphology prediction model, to obtain a plurality of initial prediction results corresponding to each of the to-be-simulated grids;

[0036] The mean of the plurality of initial prediction results corresponding to each of the to-be-simulated grids is taken as the surface morphology prediction result corresponding to each of the to-be-simulated grids.

[0037] According to the surface morphology prediction results corresponding to all of the to-be-simulated grids, the surface morphology prediction result of the to-be-simulated chip is determined.

[0038] In one of the embodiments, the surface morphology data of the to-be-simulated chip is determined according to the surface morphology simulation result and the surface morphology prediction result, including that the surface morphology simulation result includes the surface morphology simulation result corresponding to each of the to-be-simulated grids.

[0039] Based on the plurality of initial prediction results corresponding to each of the to-be-simulated grids, the difference between the plurality of initial prediction results corresponding to each of the to-be-simulated grids is quantified, to obtain the prediction uncertainty of the surface morphology prediction result corresponding to each of the to-be-simulated grids; wherein the greater the prediction uncertainty is, the greater the difference between the plurality of initial prediction results is.

[0040] According to a preset fusion percentage and the prediction uncertainty of the surface morphology prediction result corresponding to all of the to-be-simulated grids, an uncertainty threshold is determined.

[0041] If the prediction uncertainty is less than the uncertainty threshold, the surface morphology prediction result is used as the surface morphology data of the to-be-simulated grid; otherwise, the surface morphology simulation result is used as the surface morphology data of the to-be-simulated grid.

[0042] In a second aspect, the present application further provides a chip surface morphology simulation device, the device comprising:

[0043] An acquisition module is configured to acquire layout information of a to-be-simulated chip.

[0044] A physical simulation module is configured to simulate the surface morphology of the to-be-simulated chip based on the layout information by using a physical simulation model, to obtain a surface morphology simulation result.

[0045] A model prediction module is configured to predict the surface morphology of the to-be-simulated chip based on the layout information by using a trained surface morphology prediction model, to obtain a surface morphology prediction result.

[0046] a surface morphology determination module configured to determine surface morphology data of the chip to be simulated based on the surface morphology simulation result and the surface morphology prediction result.

[0047] In a third aspect, a computer readable storage medium is provided, which stores a computer program. When the computer program is executed by a processor, the method in any one of the first aspect or the embodiments of the first aspect is implemented.

[0048] The chip surface morphology simulation method, the chip surface morphology simulation device and the computer readable storage medium have the following advantages. Firstly, the layout information of the chip to be simulated is obtained. Then, the surface morphology of the chip to be simulated is simulated and predicted based on the layout information by using the physical simulation model and the trained surface morphology prediction model, so that the corresponding surface morphology simulation result and the surface morphology prediction result are obtained. Finally, the surface morphology data of the chip to be simulated is determined based on the surface morphology simulation result and the surface morphology prediction result. The surface morphology of the chip to be simulated is predicted by fully considering the surface morphology simulation result and the surface morphology prediction result. The fusion of the physical simulation model and the trained surface morphology prediction model is realized, and the accuracy of the surface morphology data prediction of the chip to be simulated is improved. BRIEF DESCRIPTION OF DRAWINGS

[0049] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the embodiments of the present application and, together with the description given below, serve to explain the principles described herein. In the drawings:

[0050] Figure 1 FIG. 1 is a schematic diagram of an application environment of a chip surface morphology simulation method according to an embodiment of the present application;

[0051] Figure 2 FIG. 2 is a schematic diagram of a flow of a chip surface morphology simulation method according to an embodiment of the present application;

[0052] Figure 3 FIG. 3 is a schematic diagram of a construction flow of a trained surface morphology prediction model according to an embodiment of the present application;

[0053] Figure 4 FIG. 4 is a schematic diagram of a flow of a step of obtaining a sample data set according to an embodiment of the present application;

[0054] Figure 5 FIG. 5 is a schematic diagram of a layout information tensor slicing according to an embodiment of the present application;

[0055] Figure 6 FIG. 6 is a schematic diagram of information completion of a position of missing edge grid information according to an embodiment of the present application;

[0056] Figure 7A flowchart of a surface morphology prediction result step of a chip to be simulated obtained by a surface morphology prediction model completed by training in an embodiment;

[0057] Figure 8 A flowchart of a chip surface morphology simulation method in an embodiment;

[0058] Figure 9 A structural block diagram of a chip surface morphology simulation device in an embodiment;

[0059] Figure 10 An internal structure diagram of a computer device in an embodiment.

[0060] Explanation of reference signs:

[0061] 102, terminal; 104, server; 501, grid; 502, sliding window; 601, target test chip; 602, first test chip; 603, second test chip; 604, third test chip; 901, acquisition module; 902, physical simulation module; 903, model prediction module; 904, surface morphology determination module. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0063] The chip surface morphology simulation method provided by the embodiments of the present application can be applied in an application environment as shown in Figure 1 . Among them, the terminal 102 communicates with the server 104 through the network. The data storage system can store the data required to be processed by the server 104. The data storage system can be integrated on the server 104, or placed on the cloud or other network servers. Among them, the terminal 102 can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers. The server 104 can be realized by an independent server or a server cluster composed of multiple servers.

[0064] In an embodiment, as shown in Figure 2 , Figure 2 A flowchart of a chip surface morphology simulation method in an embodiment; this embodiment takes the terminal in Figure 1 as an example to illustrate that the method can also be applied to the server, and can also be applied to a system including the terminal and the server, and is realized through the interaction of the terminal and the server, and the chip surface morphology simulation includes the following steps:

[0065] In step S201, layout information of a chip to be simulated is acquired.

[0066] The layout information of the chip to be simulated includes line width, line spacing, density and line perimeter of the metal lines; the line width is the width of the metal lines; the line spacing is the interval distance between adjacent metal lines; and the density is the density of the metal lines, which is equal to w / (w+space), where w is the line width and space is the line spacing.

[0067] It should be noted that the layout information of the chip to be simulated can be acquired by a feature extraction method, but is not limited thereto. The feature extraction method can be any existing feature extraction method, which is not limited herein.

[0068] In step S202, the surface morphology of the chip to be simulated is simulated based on the layout information by using a physical simulation model to obtain a surface morphology simulation result.

[0069] The physical simulation model refers to a physical simulation model that has been set with a simulation process recipe and calibrated with parameters. It should be noted that the simulation process recipe setting process includes collecting process information of a test chip before a CMP sequence and process settings of a chemical mechanical polishing device; the process information can be, but is not limited to, oxide type and thickness deposited before the CMP process; the process settings can be, but are not limited to, polishing pad type, polishing time, and polishing stop condition; based on the process information of the test chip before the CMP sequence and the process settings of the chemical mechanical polishing device, the simulation process recipe of the physical simulation model is set. The parameter calibration process includes acquiring layout information of a test chip and surface morphology characterization data of the test chip after a CMP process; based on the process recipe, the layout information of the test chip, and the surface morphology characterization data of the test chip after the CMP process, the model parameters of the physical simulation model are calibrated; the surface morphology characterization data can be, but is not limited to, scale information, which can be step height, array height, etching depth, etc., which is not limited herein. It should be noted that the surface morphology characterization data of the test chip can be determined based on measurement of the test chip after the CMP process by a measurement device, which is not limited herein.

[0070] Specifically, the layout information is input into the physical simulation model that has been set with the simulation process recipe and calibrated with the parameters, and the surface morphology of the chip to be simulated is simulated based on the physical simulation model to obtain a surface morphology simulation result of the chip to be simulated.

[0071] Step S203 , predicting the surface morphology of the chip to be simulated based on the layout information using the trained surface morphology prediction model to obtain a surface morphology prediction result.

[0072] The trained surface morphology prediction model can be, but is not limited to, an integrated model of multiple trained base models; the base model can be, but is not limited to, an XGBoost model, which is not specifically limited here. It should be noted that each base model has a corresponding target loss function; the corresponding base model is trained based on the sample data set until the target loss function of the base model converges to a preset threshold, and a trained base model can be obtained; and then the multiple trained base models are integrated to obtain a trained surface morphology prediction model. The preset threshold needs to be set according to the training requirements of the base model and is not specifically limited here.

[0073] Step S204 : determining the surface morphology data of the chip to be simulated according to the surface morphology simulation result and the surface morphology prediction result.

[0074] It should be noted that, by simulating and predicting the chip to be simulated through the physical simulation model and the trained surface morphology prediction model respectively, the surface morphology simulation results and the surface morphology prediction results of the chip to be simulated can be obtained; then, based on the surface morphology simulation results and the surface morphology prediction results, the surface morphology data of the chip to be simulated is determined, which fully considers the relationship between the surface morphology simulation results and the surface morphology prediction results, and can effectively improve the accuracy of the surface morphology prediction of the chip to be simulated.

[0075] In this embodiment, the surface morphology of the chip to be simulated is predicted by fully considering the surface morphology simulation results and the surface morphology prediction results, thereby realizing the fusion of the physical simulation model and the trained surface morphology prediction model, and improving the accuracy of the surface morphology data prediction of the chip to be simulated.

[0076] In one embodiment, Figure 3 As shown, Figure 3 The figure is a schematic diagram of a construction process of a trained surface morphology prediction model in one embodiment; the surface morphology of the chip to be simulated is predicted based on the layout information using the trained surface morphology prediction model. Before obtaining the surface morphology prediction result, the following steps are also included:

[0077] Step S301: Obtain multiple random seeds.

[0078] Step S302: Based on the multiple random seeds, corresponding multiple base models are established to obtain a surface morphology prediction model integrating the multiple base models.

[0079] Step S303: Obtain a sample data set.

[0080] Step S304, based on the sample data set, training the surface morphology prediction model to obtain the trained surface morphology prediction model.

[0081] Wherein, the random seed refers to the value used to initialize the pseudo-random number generator; wherein, the pseudo-random number generator is used to generate a sequence of numbers that appear random but are actually deterministic. The plurality of random seeds are different from each other, so that the initial parameters corresponding to the plurality of base models are different from each other; based on the plurality of base models, the data can be learned from different angles, so that the generalization performance of the trained surface morphology prediction model is better; wherein, the base model can be but is not limited to XGBoost model.

[0082] Wherein, the sample data set includes sample input data and sample labels; the sample input data can be the layout information corresponding to the test chip; the sample labels can be the surface morphology characterization data corresponding to the test chip after the CMP process. Wherein, the surface morphology characterization data corresponding to the test chip after the CMP process can be but is not limited to the measurement of the test chip after the CMP process based on the measurement equipment, which is not limited here; the surface morphology characterization data can be but is not limited to scale information, such as step height, array height, etching depth, etc.

[0083] Specifically, based on a plurality of different random seeds, a plurality of corresponding base models are established, and a surface morphology prediction model integrated with the plurality of base models is obtained; then, based on the sample data set, the surface morphology prediction model integrated with the plurality of base models is trained to obtain the trained surface morphology prediction model.

[0084] In this embodiment, based on a plurality of different random seeds, a plurality of corresponding base models are established, the plurality of base models are integrated to obtain a surface morphology prediction model, and then the surface morphology prediction model is trained based on the sample data set to obtain the trained surface morphology prediction model, which can effectively improve the generalization ability of the surface morphology prediction model, lay a foundation for improving the accuracy of the surface morphology prediction result, and further lay a foundation for improving the accuracy of the surface morphology data prediction of the chip to be simulated.

[0085] In one embodiment, based on the sample data set, the surface morphology prediction model is trained to obtain the trained surface morphology prediction model, including the following steps:

[0086] Step 1, for each base model, the sample data set is divided according to a predetermined division rule to determine the training set and the validation set corresponding to each base model.

[0087] Step 2, based on the training set and the validation set corresponding to each base model, the corresponding base model is trained to obtain the trained base model.

[0088] Step 3, determining the trained surface morphology prediction model according to the plurality of trained base models.

[0089] wherein the preset division rule needs to be set according to the actual training requirement of the model, which is not specifically limited here; for example, the preset division rule can be a division rule of 8:2 of training set: validation set for the sample data set. It should be noted that for each base model, the sample data set needs to be divided according to the same preset division rule to obtain the training set and the validation set corresponding to each base model. It can be understood that assuming that the preset division rule is 8:2 of training set: validation set, for each base model, the data in the sample data set is randomly divided into the corresponding training set and validation set according to the division ratio of 8:2, so that the data in the training set corresponding to each base model is different from each other, and the data in the validation set corresponding to each base model is different from each other.

[0090] It should be noted that each base model has a corresponding target loss function; based on the target loss function and the training set and the validation set corresponding to each base model, the corresponding base model is trained until the target loss function converges to a preset threshold, and the trained base model can be obtained; and the plurality of trained base models are integrated to obtain the trained surface morphology prediction model. The preset threshold needs to be set according to the training requirement of the base model, which is not specifically limited here. In an exemplary embodiment, the target loss function is mean squared error (MSE), and the calculation formula of MSE is shown in formula (1).

[0091] (1)

[0092] wherein, represents the actual value of the i-th observation point, wherein the actual value refers to the surface morphology characterization data corresponding to the test chip after the CMP process; represents the predicted value of the i-th observation point, wherein the predicted value refers to the initial prediction result of the base model; n represents the total number of observation points.

[0093] Exemplarily, the way of determining the trained surface morphology prediction model according to the plurality of trained base models can be that according to the plurality of trained base models, the mean value of the initial prediction results of the plurality of trained base models is taken as the surface morphology prediction result of the trained surface morphology prediction model, to obtain the trained surface morphology prediction model; the surface morphology prediction result of the trained surface morphology prediction model is shown in formula (2).

[0094] (2)

[0095] in, are the horizontal and vertical coordinates of the position to be simulated in the chip to be simulated; , which means the surface morphology prediction model trained is Surface morphology prediction results of the location; , represents the base model pair completed by the i-th training The initial prediction result of the position; n, represents the number of base models that have been trained. It should be noted that when the surface morphology is predicted based on the layout information of each grid in the chip layout to be simulated after grid division, It can also be the horizontal and vertical coordinates of the grid, which is not specifically limited here.

[0096] In this embodiment, for each base model, the sample data set is divided according to the preset division rules to determine the training set and verification set corresponding to each base model; then, based on the training set and verification set corresponding to each base model, the corresponding base model is trained to obtain a trained base model, and then based on multiple trained base models, a trained surface morphology prediction model is determined, which lays the foundation for improving the accuracy of the surface morphology prediction results and the accuracy of the surface morphology data prediction of the chip to be simulated.

[0097] In one embodiment, Figure 4 As shown, Figure 4 The following is a flow chart of the steps for obtaining a sample data set in one embodiment; obtaining a sample data set includes the following steps:

[0098] Step S401 : obtaining gridded layout information corresponding to the test chip and surface morphology characterization data of the grid corresponding to the test chip after the CMP process.

[0099] The gridded layout information refers to the layout information obtained by gridding the test chip layout and performing feature extraction on the gridded layout. It is understood that the gridded layout includes multiple grids, each of which has corresponding layout information. Therefore, the gridded layout information can be understood as the layout information corresponding to all grids. The layout information may include, but is not limited to, layout features such as metal line width, line spacing, density, and line perimeter. It should be noted that the gridding method needs to be set according to the actual layout division requirements and is not specifically limited here.

[0100] The surface morphology characterization data of the grid corresponding to the test chip after the CMP process refers to the surface morphology of the center position of each grid corresponding to the test chip after the CMP process, such as step height, array height, etching depth, and the like. The surface morphology characterization data can be determined based on measurement of the grid position of the test chip after the CMP process by a measurement device, which is not specifically limited herein. It should be noted that the surface morphology characterization data of the grid corresponding to the test chip after the CMP process in this embodiment is the surface morphology characterization data corresponding to the center position of the grid; in other embodiments, the surface morphology characterization data of the grid corresponding to the test chip after the CMP process can be the surface morphology characterization data corresponding to other positions in each grid, or the average of the surface morphology characterization data of multiple positions in the grid, which is not specifically limited herein.

[0101] In step S402, the gridded layout information is standardized to obtain corresponding layout information tensors.

[0102] For example, it is assumed that the layout of the test chip is gridded to obtain MxN grids, where M is the number of rows of the gridded layout, and N is the number of columns of the gridded layout; and it is assumed that the layout information corresponding to each grid includes c layout features, based on which a three-dimensional gridded layout information of cXMxN size can be obtained; based on the three-dimensional gridded layout information of cXMxN, the mean and standard deviation of each layout feature are calculated, and then based on the mean and standard deviation of each layout feature, the layout features corresponding to all grids are standardized according to formula (3) to obtain the layout information tensor corresponding to the test chip, which is a three-dimensional tensor of cXMxN size.

[0103] (3)

[0104] wherein x is a layout feature, is the layout feature after standardization processing; is the mean of the layout feature x of all grids before standardization processing; is the standard deviation of the layout feature x of all grids before standardization processing.

[0105] It can be understood that the layout feature x can include, but is not limited to, line width, line spacing, density, and line perimeter of a metal line; for example, when the line width corresponding to each grid is standardized, the mean of the line width and the standard deviation of the line width are calculated based on the line width x of all grids, and then the standardized line width corresponding to each grid can be calculated according to formula (3). Based on the standardized line width The layout information tensor corresponding to the line width can be obtained.

[0106] In step S403, a layout information tensor slice is obtained based on a preset sliding sequence and a sliding step length by using a sliding window with a preset size.

[0107] The sliding window with the preset size is a sliding window with m*n grid sizes. The preset sliding sequence can be, but is not limited to, a sequence from left to right and from top to bottom according to the grid positions. The sliding step length can be, but is not limited to, a unit grid length. The layout information tensor slice is a three-dimensional tensor with a size of c*m*n. c represents the number of layout features, m represents the number of rows of the layout information tensor slice, and n represents the number of columns of the layout information tensor slice. It can be understood that each grid has a corresponding layout information tensor slice.

[0108] In step S404, the layout information tensor slice is flattened into a one-dimensional vector, and the one-dimensional vector is taken as input data of the sample.

[0109] In step S405, the surface morphology representation data corresponding to the center grid of the sliding window with the preset size is taken as the label of the sample.

[0110] It should be noted that the label of the sample in this embodiment is the surface morphology representation data of the center position of the grid. In other embodiments, the label of the sample can also be the surface morphology representation data of other positions in the grid. It can also be the average of the surface morphology representation data of multiple positions in the grid, which is not limited here.

[0111] It can be understood that each grid can be taken as a sample. The sample includes input data and a label. The input data of the sample is a one-dimensional vector obtained by flattening the three-dimensional layout information tensor slice corresponding to each grid. The label of the sample is the surface morphology representation data corresponding to each grid.

[0112] In step S406, a sample data set is constructed according to the input data of the sample and the label of the sample.

[0113] For example, referring to FIG. 4, the surface morphology representation data of the center grid of the sliding window with the preset size is taken as the label of the sample. Figure 5, assuming that the layout of the test chip is meshed to obtain 5x8 grids, wherein 5 is the number of rows of the layout after meshing, and 8 is the number of columns of the layout after meshing; the layout information corresponding to each grid includes c layout features; the meshed layout information is standardized to obtain a layout information tensor of c*5*8 size; assuming that the preset size of the sliding window is a 3*3 grid size sliding window 502, the preset sliding order is from left to right and from top to bottom according to the grid position, and the sliding step is a unit grid length; taking a sample as a grid 501 as an example, a 3*3 grid size sliding window 502 is used to slide to the grid 501 according to the grid position from left to right and from top to bottom at a unit grid length, and the layout information tensor slice corresponding to the grid 501 is obtained; wherein the size of the layout information tensor slice of the grid 501 is c*3*3; the layout information tensor slice is flattened to a one-dimensional vector, and the one-dimensional vector is used as the input data of the sample; it can be understood that the length of the one-dimensional vector is c*3*3; the surface morphology representation data corresponding to the grid 501 is used as the label of the sample; according to the above implementation manner, the input data of multiple samples and the labels of multiple samples can be obtained, and based on the input data of multiple samples and the labels of multiple samples, a sample data set can be constructed.

[0114] In this embodiment, based on the meshed layout information corresponding to the test chip and the surface morphology representation data of the grid corresponding to the test chip after the CMP process, the meshed layout information is standardized, and the layout information tensor corresponding to the test chip can be obtained; based on the layout information tensor and the sliding window of the preset size, the layout information tensor slice corresponding to each grid can be obtained; based on the layout information tensor slice corresponding to each grid and the surface morphology representation data, the construction of the sample data set is realized, which lays a foundation for improving the generalization ability of the trained surface morphology prediction model.

[0115] In one embodiment, the layout information tensor slice is obtained based on the preset sliding order and the sliding step with the sliding window of the preset size, including the following steps:

[0116] Step 1, the layout information tensor in the preset size sliding window is taken as the layout information tensor slice.

[0117] Step 2, if the edge grid information is missing in the preset size sliding window, the missing edge grid information is completed according to the preset completion rule to obtain the corresponding layout information tensor slice.

[0118] It should be noted that when the preset size of the sliding window is used to obtain the layout information tensor slice, if the center grid of the preset size of the sliding window is located at the edge of the layout, there may be a case of missing grid information, and therefore the position of the missing edge grid information needs to be completed to ensure the integrity of the input data of the sample.

[0119] The preset completion rule needs to be set according to the actual situation of the layout of the test chip, and is not specifically limited here.

[0120] For example, referring to Figure 6 , it is assumed that a plurality of test chips with the same layout information are arranged in a matrix in a preset spatial position, and the plurality of test chips with the same layout information are respectively denoted as a target test chip 601, a first test chip 602, a second test chip 603, and a third test chip 604; taking the target test chip 601 as an example, the layout of the target test chip 601 is divided into grids to obtain 5x7 grids; it is assumed that a sliding window with a 3x3 grid size is used, and the layout information tensor slice corresponding to grid 1 is obtained by sliding from left to right and from top to bottom in unit grid length; because there is missing edge grid information around grid 1, there is a case of missing edge grid information in the sliding window; at this time, because the first test chip 602, the second test chip 603, and the third test chip 604 with the same layout information as the target test chip 601 are arranged in a matrix around the target test chip 601, the preset completion rule can be set as follows: when the position of the missing edge grid information falls into the layout corresponding to the test chip adjacent to the target test chip 601 and having the same layout information as the target test chip 601, the position of the missing edge grid information is completed based on the layout information at the corresponding positions of the target test chip 601 and the adjacent test chip; for example, the layout information of grid 29 is used to complete the information of the position directly above grid 1; the layout information of grid 30 is used to complete the information of the position above and to the right of grid 1; the layout information of grid 35 is used to complete the information of the position above and to the left of grid 1; the layout information of grid 7 is used to complete the information of the position to the left of grid 1; and the layout information of grid 14 is used to complete the information of the position below and to the left of grid 1.

[0121] In this embodiment, when there is missing edge grid information in the preset size of the sliding window, the position of the missing edge grid information is completed based on the preset completion rule to obtain the corresponding layout information tensor slice, which can ensure the integrity of the input data of the sample.

[0122] In one embodiment, before the surface morphology of the to-be-simulated chip is simulated based on the layout information to obtain the surface morphology simulation result, the following steps are further included:

[0123] Step 1, obtaining an initial physical simulation model and a simulation process recipe.

[0124] Step 2, based on the simulation process recipe, the grid layout information corresponding to the test chip and the surface morphology characterization data of the grid corresponding to the test chip after the CMP process, the model parameter calibration is performed on the initial physical simulation model to obtain a physical simulation model.

[0125] The initial physical simulation model refers to a physical simulation model that has not been set by a simulation process recipe and has not been calibrated in parameters. The simulation process recipe needs to be set according to the process information of the test chip before the CMP step and the process setting of the chemical mechanical polishing device, which is not specifically limited herein. The process information can be, but is not limited to, the type and thickness of the oxide deposited before the CMP process. The process setting can be, but is not limited to, the type of polishing pad, polishing time, and polishing stop condition.

[0126] For example, the layout information corresponding to the test chip and the surface morphology characterization data of the test chip after the CMP process are obtained. The initial physical simulation model and the simulation process recipe are obtained. Based on the simulation process recipe, the grid layout information corresponding to the test chip and the surface morphology characterization data of the grid corresponding to the test chip after the CMP process, the model parameter calibration is performed on the initial physical simulation model to obtain a physical simulation model. The surface morphology characterization data can be, but is not limited to, scale information such as step height, array height, and etching depth. It should be noted that the surface morphology characterization data of the test chip can be, but is not limited to, determined based on the measurement of the test chip after the CMP process by a measurement device, which is not specifically limited herein.

[0127] It should be noted that in the present embodiment, the grid layout information corresponding to the test chip and the surface morphology characterization data of the grid corresponding to the test chip after the CMP process used for model parameter calibration of the initial physical simulation model are the same data set as the grid layout information corresponding to the test chip and the surface morphology characterization data of the grid corresponding to the test chip after the CMP process used for training of the surface morphology prediction model. In other embodiments, different data sets can be used to calibrate or train the initial physical simulation model and the surface morphology prediction model, respectively, which is not specifically limited herein.

[0128] In the present embodiment, based on the simulation process recipe, the grid layout information corresponding to the test chip and the surface morphology characterization data of the grid corresponding to the test chip after the CMP process, the model parameter calibration is performed on the initial physical simulation model to obtain a physical simulation model, which can ensure the reliability of the physical simulation model.

[0129] In one embodiment, the layout information of the chip to be simulated is obtained, including: obtaining the grid layout information of a plurality of simulation grids in the grid divided chip layout to be simulated.

[0130] Specifically, obtaining grid layout information of multiple grids to be simulated in the grid-divided chip layout to be simulated includes the following steps:

[0131] Step 1: Obtain the layout of the chip to be simulated.

[0132] Step 2: Divide the layout of the chip to be simulated into grids to generate multiple grids to be simulated.

[0133] Step 3: Obtain the grid layout information corresponding to each grid to be simulated.

[0134] The grid division method needs to be set according to the actual layout division requirements and is not specifically limited here.

[0135] The grid layout information refers to the layout information corresponding to the grid to be simulated; the grid layout information may include, but is not limited to, layout features such as the line width, line spacing, density, and line perimeter of the metal lines.

[0136] Specifically, the layout of the chip to be simulated is obtained; the layout of the chip to be simulated is grid-divided to generate multiple grids to be simulated; based on the feature extraction method, the grid layout information corresponding to each grid to be simulated is obtained respectively, and then the layout information of the chip to be simulated is determined based on the grid layout information corresponding to each grid to be simulated.

[0137] It should be noted that when predicting the surface morphology data of the chip to be simulated, the surface morphology data of each grid to be simulated can be predicted with the grid to be simulated as the minimum prediction unit to obtain the surface morphology data of each grid to be simulated, and then based on the surface morphology data of all grids to be simulated, the surface morphology data of the chip to be simulated can be determined.

[0138] In this embodiment, multiple grids to be simulated can be generated by performing grid division on the layout of the chip to be simulated, thereby laying a data foundation for predicting the surface morphology data of the chip to be simulated.

[0139] In one embodiment, Figure 7 As shown, Figure 7 The present invention is a flow chart illustrating the steps of obtaining a surface morphology prediction result of a chip to be simulated using a trained surface morphology prediction model in one embodiment. The surface morphology prediction result is obtained by predicting the surface morphology of the chip to be simulated based on layout information using the trained surface morphology prediction model, including the following steps:

[0140] Step S701, according to the grid layout information corresponding to each to-be-simulated grid, the surface morphology of each to-be-simulated grid is predicted by the plurality of base models in the trained surface morphology prediction model respectively, and a plurality of initial prediction results corresponding to each to-be-simulated grid are obtained.

[0141] Step S702, the mean of the plurality of initial prediction results corresponding to each to-be-simulated grid is taken as the surface morphology prediction result corresponding to each to-be-simulated grid.

[0142] Step S703, according to the surface morphology prediction results corresponding to all to-be-simulated grids, the surface morphology prediction result of the to-be-simulated chip is determined.

[0143] It should be noted that the plurality of base models in the trained surface morphology prediction model are a plurality of trained base models.

[0144] Exemplarily, according to the grid layout information corresponding to each to-be-simulated grid, the surface morphology of each to-be-simulated grid is predicted by the plurality of base models in the trained surface morphology prediction model respectively, and a plurality of initial prediction results corresponding to each to-be-simulated grid are obtained; based on the plurality of initial prediction results corresponding to each to-be-simulated grid, the mean of the plurality of initial prediction results corresponding to each to-be-simulated grid is calculated, and the mean of the plurality of initial prediction results is taken as the surface morphology prediction result corresponding to each to-be-simulated grid, as shown in formula (4); further, according to the surface morphology prediction results corresponding to all to-be-simulated grids, the surface morphology prediction result of the to-be-simulated chip is determined.

[0145] (4)

[0146] Wherein, x represents the horizontal coordinate of the to-be-simulated grid; y represents the vertical coordinate of the to-be-simulated grid; n represents the number of trained base models; , represents the surface morphology prediction result corresponding to the to-be-simulated grid with coordinates (x, y); , represents the initial prediction result of the i-th trained base model corresponding to the to-be-simulated grid with coordinates (x, y).

[0147] In this embodiment, the surface morphology of each to-be-simulated grid is predicted by the plurality of base models in the trained surface morphology prediction model, a plurality of initial prediction results corresponding to each to-be-simulated grid are obtained, and then the surface morphology prediction result corresponding to each to-be-simulated grid is determined based on the mean of the plurality of initial prediction results corresponding to each to-be-simulated grid, and further, the surface morphology prediction result of the to-be-simulated chip is determined according to the surface morphology prediction results corresponding to all to-be-simulated grids, thereby improving the accuracy and reliability of the surface morphology prediction result of the to-be-simulated chip.

[0148] In one embodiment, the surface morphology simulation result includes a surface morphology simulation result corresponding to each grid to be simulated; and the surface morphology data of the chip to be simulated is determined according to the surface morphology simulation result and the surface morphology prediction result, including the following steps:

[0149] Step 1, based on the plurality of initial prediction results corresponding to each grid to be simulated, quantifying the difference between the plurality of initial prediction results corresponding to each grid to be simulated to obtain the prediction uncertainty of the surface morphology prediction result corresponding to each grid to be simulated.

[0150] Wherein, the prediction uncertainty is used to represent the difference between the plurality of initial prediction results; the greater the prediction uncertainty, the greater the difference between the plurality of initial prediction results; on the contrary, the smaller the prediction uncertainty, the smaller the difference between the plurality of initial prediction results. Based on formula (5), the difference between the plurality of initial prediction results corresponding to each grid to be simulated can be quantified to obtain the prediction uncertainty of the surface morphology prediction result corresponding to each grid to be simulated.

[0151] (5)

[0152] Wherein, x represents the horizontal coordinate of the grid to be simulated; y represents the vertical coordinate of the grid to be simulated; n represents the number of trained base models; represents the prediction uncertainty of the grid to be simulated with coordinates (x, y); represents the initial prediction result of the i-th trained base model corresponding to the grid to be simulated with coordinates (x, y); represents the surface morphology prediction result corresponding to the grid to be simulated with coordinates (x, y).

[0153] Step 2, determining the uncertainty threshold according to the preset fusion percentage and the prediction uncertainty of the surface morphology prediction result corresponding to all grids to be simulated.

[0154] Wherein, the so-called "fusion" refers to the fusion of the physical model and the surface morphology prediction model based on machine learning; the smaller the fusion percentage, the more the surface morphology prediction result depends on the physical model; the greater the fusion percentage, the more the surface morphology prediction result depends on the surface morphology prediction model based on machine learning. The preset fusion percentage needs to be set according to actual needs, but the selection of the preset fusion percentage will affect the surface morphology prediction result of the grid to be simulated; for example, the preset fusion percentage can be set to 50%, which is not limited here.

[0155] Optionally, in an exemplary embodiment, the determination manner of the uncertainty threshold value can be: according to the prediction uncertainty of the surface morphology prediction result corresponding to all the to-be-simulated meshes, sorting the prediction uncertainty of the surface morphology prediction result corresponding to all the to-be-simulated meshes in a preset sorting manner, for example, in an ascending order, and taking the prediction uncertainty at the tth percentile as the uncertainty threshold value according to a preset fusion percentage t; for example, taking the tth prediction uncertainty in the 100 ascending prediction uncertainties as the uncertainty threshold value.

[0156] Step 3: if the prediction uncertainty is less than the uncertainty threshold value, using the surface morphology prediction result as the surface morphology data of the to-be-simulated mesh; otherwise, using the surface morphology simulation result as the surface morphology data of the to-be-simulated mesh.

[0157] It should be noted that, by simulating the surface morphology of each to-be-simulated mesh through the physical simulation model based on the mesh layout information of each to-be-simulated mesh, the surface morphology simulation result corresponding to each to-be-simulated mesh can be obtained.

[0158] Specifically, if the prediction uncertainty is less than the uncertainty threshold value, it indicates that the accuracy of the surface morphology prediction result is high, and the surface morphology prediction result corresponding to the to-be-simulated mesh is taken as the surface morphology data of the to-be-simulated mesh, which can ensure the accuracy of the surface morphology data; if the prediction uncertainty is greater than or equal to the uncertainty threshold value, the surface morphology simulation result corresponding to the to-be-simulated mesh is used as the surface morphology data of the to-be-simulated mesh, which can avoid the problem of low accuracy of surface morphology simulation caused by using the surface morphology prediction result as the surface morphology data corresponding to the to-be-simulated mesh.

[0159] In this embodiment, the uncertainty threshold value can be determined based on the preset fusion percentage and the prediction uncertainty of the surface morphology prediction result corresponding to all the to-be-simulated meshes; and then the fusion of the physical simulation model and the trained surface morphology prediction model can be realized based on the uncertainty threshold value, thereby improving the accuracy of the surface morphology data prediction of the to-be-simulated chip.

[0160] In a specific embodiment, referring to Figure 8 , the chip surface morphology simulation method comprises the following steps:

[0161] Step S801: obtaining the layout of a to-be-simulated chip.

[0162] Step S802: performing mesh division on the layout of the to-be-simulated chip to generate a plurality of to-be-simulated meshes, and obtaining mesh layout information corresponding to each to-be-simulated mesh.

[0163] In step S803, the surface morphology of each to-be-simulated grid is simulated based on the grid layout information corresponding to each to-be-simulated grid by using the physical simulation model, and a surface morphology simulation result of each to-be-simulated grid is obtained.

[0164] In step S804, the surface morphology of each to-be-simulated grid is predicted based on the grid layout information corresponding to each to-be-simulated grid by using the trained surface morphology prediction model, and a surface morphology prediction result of each to-be-simulated grid is obtained.

[0165] In step S805, the prediction uncertainty of the surface morphology prediction result corresponding to each to-be-simulated grid is determined.

[0166] In step S806, the uncertainty threshold is determined according to a preset fusion percentage and the prediction uncertainty of the surface morphology prediction result corresponding to each to-be-simulated grid.

[0167] In step S807, it is determined whether the prediction uncertainty is less than the uncertainty threshold.

[0168] If yes, step S808 is performed; otherwise, step S809 is performed.

[0169] In step S808, the surface morphology prediction result is used as the surface morphology data of the to-be-simulated grid.

[0170] In step S809, the surface morphology simulation result is used as the surface morphology data of the to-be-simulated grid.

[0171] The chip surface morphology simulation method has the following advantages. First, the surface morphology data of the chip to be simulated is determined according to the surface morphology simulation result and the surface morphology prediction result, the fusion of the physical simulation model and the trained surface morphology prediction model is realized, and the accuracy of the surface morphology data prediction of the chip to be simulated is improved. Second, based on a plurality of different random seeds, a plurality of base models are established, the plurality of base models are integrated to obtain a surface morphology prediction model, and then the surface morphology prediction model is trained based on a sample data set to obtain a trained surface morphology prediction model. This can effectively improve the generalization ability of the surface morphology prediction model, lay a foundation for improving the accuracy of the surface morphology prediction result and the accuracy of the surface morphology data prediction of the chip to be simulated. Third, based on the grid-based layout information of the test chip and the surface morphology representation data of the grid of the test chip after the CMP process, the grid-based layout information is standardized to obtain the layout information tensor of the test chip. Based on the layout information tensor and the preset size sliding window, the layout information tensor slice corresponding to each grid can be obtained. Based on the layout information tensor slice corresponding to each grid and the surface morphology representation data, the sample data set is constructed, which lays a foundation for improving the generalization ability of the trained surface morphology prediction model. Fourth, when the edge grid information is missing in the preset size sliding window, the position of the missing edge grid information is completed based on the preset completion rule to obtain the corresponding layout information tensor slice, which can ensure the integrity of the input data of the sample. Fifth, based on the simulation process recipe, the grid-based layout information of the test chip, and the surface morphology representation data of the grid of the test chip after the CMP process, the model parameters of the initial physical simulation model are calibrated to obtain the physical simulation model, which can ensure the reliability of the physical simulation model. Sixth, the surface morphology of each to-be-simulated grid is predicted by using a plurality of trained base models in the trained surface morphology prediction model, a plurality of initial prediction results corresponding to each to-be-simulated grid are obtained, the mean value of the plurality of initial prediction results corresponding to each to-be-simulated grid is used to determine the surface morphology prediction result corresponding to each to-be-simulated grid, and then the surface morphology prediction result of the chip to be simulated is determined based on the surface morphology prediction results of all to-be-simulated grids, which improves the accuracy and reliability of the surface morphology prediction result of the chip to be simulated. Seventh, based on the preset fusion percentage and the prediction uncertainty of the surface morphology prediction result of all to-be-simulated grids, the uncertainty threshold can be determined; then, based on the uncertainty threshold, the fusion of the physical simulation model and the trained surface morphology prediction model is realized, and the accuracy of the surface morphology data prediction of the chip to be simulated is improved.

[0172] It should be understood that although the steps in the flowcharts involved in the embodiments described above are shown in sequence according to the arrows, the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of the steps is not strictly limited in sequence, and the steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the embodiments described above can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of the steps or stages is not necessarily sequential, but can be alternately or alternately executed with at least part of other steps or steps or stages in other steps.

[0173] Based on the same inventive concept, the embodiments of the present application also provide a chip surface morphology simulation device for implementing the chip surface morphology simulation method described above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more chip surface morphology simulation device embodiments provided below can refer to the limitations of the chip surface morphology simulation method described above, which will not be repeated here.

[0174] In one embodiment, as shown in Figure 9 Figure 9 is a structural block diagram of a chip surface morphology simulation device in an embodiment; the chip surface morphology simulation device includes an acquisition module 901, a physical simulation module 902, a model prediction module 903, and a surface morphology determination module 904.

[0175] The acquisition module 901 is configured to acquire layout information of a chip to be simulated.

[0176] The physical simulation module 902 is configured to simulate the surface morphology of the chip to be simulated based on the layout information through a physical simulation model to obtain a surface morphology simulation result.

[0177] The model prediction module 903 is configured to predict the surface morphology of the chip to be simulated based on the layout information through a trained surface morphology prediction model to obtain a surface morphology prediction result.

[0178] The surface morphology determination module 904 is configured to determine surface morphology data of the chip to be simulated according to the surface morphology simulation result and the surface morphology prediction result.

[0179] In one embodiment, the model prediction module 903 is further configured to

[0180] acquire a plurality of random seeds; the plurality of random seeds are different from each other;

[0181] ​Based on a plurality of random seeds, a plurality of base models corresponding to the plurality of random seeds are established, and a surface morphology prediction model integrated with the plurality of base models is obtained.

[0182] A sample data set is obtained.

[0183] Based on the sample data set, the surface morphology prediction model is trained to obtain a trained surface morphology prediction model.

[0184] In one embodiment, the model prediction module 903 is further configured to

[0185] According to a preset division rule, the sample data set is divided for each base model to determine a training set and a validation set corresponding to each base model.

[0186] Based on the training set and the validation set corresponding to each base model, the corresponding base model is trained to obtain a trained base model.

[0187] According to a plurality of trained base models, a trained surface morphology prediction model is determined.

[0188] In one embodiment, the model prediction module 903 is further configured to

[0189] The grid-based layout information corresponding to the test chip and the surface morphology characterization data of the grid corresponding to the test chip after the CMP process are obtained.

[0190] The grid-based layout information is standardized to obtain a corresponding layout information tensor.

[0191] A sliding window of a preset size is used to obtain a layout information tensor slice based on a preset sliding order and a sliding step size. The sliding window of the preset size is an m x n grid size sliding window.

[0192] The layout information tensor slice is flattened to a one-dimensional vector, and the one-dimensional vector is used as input data of a sample.

[0193] The surface morphology characterization data corresponding to the center grid of the sliding window of the preset size is used as the label of the sample.

[0194] According to the input data of the sample and the label of the sample, a sample data set is constructed.

[0195] In one embodiment, the model prediction module 903 is further configured to

[0196] The layout information tensor in the sliding window of the preset size is used as the layout information tensor slice.

[0197] If the edge grid information is missing in the sliding window of the preset size, the missing edge grid information is completed according to a preset completion rule to obtain a corresponding layout information tensor slice.

[0198] In one embodiment, the physical simulation module 902 is further configured to

[0199] obtain an initial physical simulation model and a simulation process recipe;

[0200] calibrate the initial physical simulation model based on the simulation process recipe, the grid layout information of the test chip, and the surface morphology characterization data of the grid of the test chip after the CMP process, to obtain the physical simulation model.

[0201] In one embodiment, the obtaining module 901 is further configured to

[0202] obtain the grid layout information of the plurality of to-be-simulated grids in the to-be-simulated chip layout after the grid division.

[0203] In one embodiment, the model prediction module 903 is further configured to

[0204] predict the surface morphology of each to-be-simulated grid by using the plurality of base models in the trained surface morphology prediction model according to the grid layout information corresponding to each to-be-simulated grid, to obtain a plurality of initial prediction results corresponding to each to-be-simulated grid;

[0205] use the mean value of the plurality of initial prediction results corresponding to each to-be-simulated grid as the surface morphology prediction result corresponding to each to-be-simulated grid;

[0206] determine the surface morphology prediction result of the to-be-simulated chip according to the surface morphology prediction results corresponding to all to-be-simulated grids.

[0207] In one embodiment, the surface morphology determination module 904 is further configured to

[0208] quantify the difference between the plurality of initial prediction results corresponding to each to-be-simulated grid based on the plurality of initial prediction results corresponding to each to-be-simulated grid, to obtain the prediction uncertainty of the surface morphology prediction result corresponding to each to-be-simulated grid; wherein the greater the prediction uncertainty, the greater the difference between the plurality of initial prediction results;

[0209] determine the uncertainty threshold according to the preset fusion percentage and the prediction uncertainty of the surface morphology prediction result corresponding to all to-be-simulated grids;

[0210] if the prediction uncertainty is less than the uncertainty threshold, use the surface morphology prediction result as the surface morphology data of the to-be-simulated grid; otherwise, use the surface morphology simulation result as the surface morphology data of the to-be-simulated grid.

[0211] Each of the modules in the chip surface morphology simulation device can be realized by software, hardware, or a combination thereof, in whole or in part. The modules can be embedded in or independent of a processor in a computer device in hardware form, or stored in a memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to each of the modules.

[0212] In one embodiment, a computer device, which can be a server, has an internal structure diagram as shown in Figure 10 The computer device includes a processor, a memory, and a network interface connected by a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The database of the computer device is configured to store chip surface morphology simulation related data. The network interface of the computer device is configured to communicate with an external terminal through a network connection. The computer program is executed by the processor to implement a chip surface morphology simulation method.

[0213] Those skilled in the art can understand that Figure 10 The structure shown in the above

[0214] In one embodiment, a computer device is also provided, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps in each of the method embodiments.

[0215] In one embodiment, a computer readable storage medium is provided, which stores a computer program. The computer program is executed by a processor to implement the steps in each of the method embodiments.

[0216] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties.

[0217] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0218] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0219] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A chip surface morphology simulation method, characterized in that: The method comprises: Obtain the layout information of the chip to be simulated; The surface morphology of the chip to be simulated is simulated based on the layout information by a physical simulation model to obtain a surface morphology simulation result; the physical simulation model refers to a physical simulation model after simulation process recipe setting and parameter calibration; The surface morphology prediction model is trained to predict the surface morphology of the chip to be simulated based on the layout information to obtain a surface morphology prediction result; the surface morphology prediction result includes a plurality of initial prediction results; Determining surface morphology data of the chip to be simulated according to the surface morphology simulation result and the surface morphology prediction result; Determining the surface morphology data of the chip to be simulated according to the surface morphology simulation result and the surface morphology prediction result includes: Obtaining a prediction uncertainty of the surface morphology prediction result by quantifying the differences between the plurality of initial prediction results; Based on the prediction uncertainty and the uncertainty threshold of the surface morphology prediction result, using the surface morphology simulation result and / or the surface morphology prediction result as the surface morphology data of the chip to be simulated; The surface morphology prediction model completed through training predicts the surface morphology of the chip to be simulated based on the layout information, and before obtaining the surface morphology prediction result, the method further includes: Obtaining multiple random seeds; wherein the multiple random seeds are different from each other; Based on the plurality of random seeds, a corresponding plurality of basis models are established to obtain a surface morphology prediction model integrating the plurality of basis models; Get a sample dataset; The surface morphology prediction model is trained based on the sample data set to obtain a trained surface morphology prediction model.

2. The method according to claim 1, characterized in that The step of training the surface morphology prediction model based on the sample data set to obtain a trained surface morphology prediction model includes: For each base model, the sample data set is divided according to the preset division rules to determine the training set and validation set corresponding to each base model; Based on the training set and the validation set corresponding to each base model, the corresponding base model is trained to obtain a trained base model; A trained surface morphology prediction model is determined based on a plurality of trained base models.

3. The method according to claim 1, characterized in that The obtaining of the sample data set includes: Obtaining gridded layout information corresponding to the test chip and surface morphology characterization data of the grid corresponding to the test chip after the CMP process; Standardizing the gridded layout information to obtain a corresponding layout information tensor; Obtaining a layout information tensor slice using a sliding window of a preset size, based on a preset sliding order and sliding step size; wherein the sliding window of the preset size is a sliding window of an m×n grid size; Flattening the layout information tensor slice into a one-dimensional vector, and using the one-dimensional vector as input data of the sample; Using the surface morphology characterization data corresponding to the center grid of the sliding window of the preset size as a label of the sample; A sample data set is constructed according to the input data of the sample and the label of the sample.

4. The method according to claim 3, characterized in that The method of obtaining a layout information tensor slice using a sliding window of a preset size based on a preset sliding order and sliding step size includes: Using the layout information tensor within the sliding window of the preset size as a layout information tensor slice; If edge grid information is missing in the sliding window of the preset size, the position of the missing edge grid information is supplemented according to the preset supplement rule to obtain the corresponding layout information tensor slice.

5. The method according to claim 3, characterized in that Before simulating the surface morphology of the chip to be simulated based on the layout information using a physical simulation model to obtain a surface morphology simulation result, the method further includes: Obtaining the initial physical simulation model and simulation process recipe; Based on the simulation process recipe, the gridded layout information corresponding to the test chip, and the surface morphology characterization data of the grid corresponding to the test chip after the CMP process, the model parameters of the initial physical simulation model are calibrated to obtain a physical simulation model.

6. The method according to claim 2, characterized in that The obtaining of the layout information of the chip to be simulated includes: obtaining grid layout information of a plurality of grids to be simulated in the grid-divided layout of the chip to be simulated; The surface morphology prediction model completed through training predicts the surface morphology of the chip to be simulated based on the layout information to obtain a surface morphology prediction result, including: According to the grid layout information corresponding to each grid to be simulated, the surface morphology of each grid to be simulated is predicted respectively by using multiple base models in the trained surface morphology prediction model to obtain multiple initial prediction results corresponding to each grid to be simulated; Taking the average of the multiple initial prediction results corresponding to each of the to-be-simulated meshes as the surface morphology prediction result corresponding to each of the to-be-simulated meshes; The surface morphology prediction result of the chip to be simulated is determined according to the surface morphology prediction results corresponding to all the grids to be simulated.

7. The method according to claim 6, characterized in that Determining the surface morphology data of the chip to be simulated according to the surface morphology simulation result and the surface morphology prediction result includes: the surface morphology simulation result includes a surface morphology simulation result corresponding to each mesh to be simulated; quantifying the differences between the multiple initial prediction results corresponding to each of the meshes to be simulated based on the multiple initial prediction results corresponding to each of the meshes to be simulated, to obtain a prediction uncertainty of the surface morphology prediction result corresponding to each of the meshes to be simulated; wherein a greater prediction uncertainty indicates a greater difference between the multiple initial prediction results; Determining an uncertainty threshold according to a preset fusion percentage and prediction uncertainties of surface morphology prediction results corresponding to all the meshes to be simulated; If the prediction uncertainty is less than the uncertainty threshold, the surface morphology prediction result is used as the surface morphology data of the mesh to be simulated; otherwise, the surface morphology simulation result is used as the surface morphology data of the mesh to be simulated.

8. A chip surface morphology simulation device, characterized in that: The device comprises: An acquisition module is used to obtain the layout information of the chip to be simulated; A physical simulation module is configured to simulate the surface morphology of the chip to be simulated based on the layout information using a physical simulation model to obtain a surface morphology simulation result; the surface morphology prediction result includes a plurality of initial prediction results; the physical simulation model refers to a physical simulation model after simulation process recipe setting and parameter calibration; A model prediction module is used to predict the surface morphology of the chip to be simulated based on the layout information using the trained surface morphology prediction model to obtain a surface morphology prediction result; a surface morphology determination module, configured to determine surface morphology data of the chip to be simulated based on the surface morphology simulation result and the surface morphology prediction result; The surface morphology determination module is further configured to obtain a prediction uncertainty of the surface morphology prediction result by quantifying the differences between the plurality of initial prediction results; Based on the prediction uncertainty and the uncertainty threshold of the surface morphology prediction result, using the surface morphology simulation result and / or the surface morphology prediction result as the surface morphology data of the chip to be simulated; The model prediction module is further used to obtain multiple random seeds; the multiple random seeds are different from each other; Based on the plurality of random seeds, a corresponding plurality of basis models are established to obtain a surface morphology prediction model integrating the plurality of basis models; Get a sample dataset; The surface morphology prediction model is trained based on the sample data set to obtain a trained surface morphology prediction model.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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