A flash memory testing system and testing method

Abstract

The present invention provides a flash memory test system and test method, the test system includes a temperature box, a flash memory is arranged in the temperature box, and the temperature box is used to adjust the temperature range around the flash memory; a controller, in a certain group of blocks, the controller performs data processing on the programming / erasing times of different blocks according to the step distribution; wherein, after the step distribution programming and erasing times data processing is performed on a certain group of blocks, the controller first performs a wide temperature test and a data retention test on the certain group of blocks in a first temperature interval, and then performs an erasing process on the certain group of blocks, and then performs a wide temperature test and a data retention test on the certain group of blocks in a second temperature interval, and the second temperature interval includes the first temperature interval. The present invention can obtain the maximum service life of the flash memory under the premise of maintaining the best performance in different temperature intervals.

Description

Technical Field

[0001] The present invention relates to the field of static storage technology, and in particular to a flash memory testing system and a flash memory testing method. Background Art

[0002] Storage media that use flash memory as storage media can be divided into consumer-grade, industrial-grade, and automotive-grade storage media according to different application areas. The main difference is the increasing requirements for stable performance, especially the temperature tolerance. For most small and medium-sized storage manufacturers in the industry, they only verify the functionality of flash memory without performing quality grading. After simply grading the flash memory according to parameter standards, they sell it as industrial-grade flash memory.

[0003] The quality of flash memory will obviously decline with wear and tear, especially for high and low temperature wear and tear, and the durability of data retention in high temperature environment will also decline. Therefore, only testing the industrial-grade performance of flash memory in the early stage of its life cannot take into account the entire life cycle of flash memory. Therefore, there is room for improvement. Summary of the invention

[0004] The present invention provides a flash memory test system and a test method to solve the technical problem that the prior art only performs industrial-grade performance testing in the early life of the flash memory and cannot take into account the entire life cycle of the flash memory.

[0005] The present invention provides a flash memory testing system, comprising:

[0006] A temperature box, wherein a flash memory is arranged in the temperature box, and the temperature box is used to adjust the temperature range around the flash memory, and the flash memory includes a plurality of groups of blocks;

[0007] A controller, in a certain group of blocks, the controller performs data processing on different blocks according to the number of programming and erasing times distributed in a ladder, wherein one number of programming and erasing times indicates that the block has been processed by one writing and erasing;

[0008] After the certain group of blocks is subjected to step-distributed programming and erasure times data processing, the controller firstly performs a wide temperature test and a data retention test on the certain group of blocks in a first temperature interval, then performs an erasure process on the certain group of blocks, and then performs a wide temperature test and a data retention test on the certain group of blocks in a second temperature interval, wherein the second temperature interval includes the first temperature interval;

[0009] The controller generates first test data corresponding to the certain group of blocks in the first temperature range and second test data corresponding to the certain group of blocks in the second temperature range.

[0010] In one embodiment of the present invention, the controller records the maximum number of programming and erasing times of the certain group of blocks without erroneous data under the wide temperature test as the wide temperature number, and records the maximum number of programming and erasing times of the certain group of blocks without erroneous data under the data retention test as the data retention number;

[0011] The controller records the minimum value of the wide temperature times and the data retention times as the maximum service life in the first test data or the second test data.

[0012] In one embodiment of the present invention, the controller performs high-temperature erasing and high-temperature reading, or high-temperature erasing and low-temperature reading, or low-temperature erasing and high-temperature reading, or low-temperature erasing and low-temperature reading tests on the certain group of blocks in the first temperature interval or the second temperature interval;

[0013] The maximum number of programming and erasing times without error data in the above test is recorded as the high temperature write and high temperature read times, the high temperature write and low temperature read times, the low temperature write and high temperature read times, and the low temperature write and low temperature read times respectively;

[0014] The minimum value among the high temperature write and high temperature read times, the high temperature write and low temperature read times, the low temperature write and high temperature read times and the low temperature write and low temperature read times is recorded as the wide temperature times.

[0015] In one embodiment of the present invention, the controller performs high-temperature erasing or low-temperature erasing processing on the certain group of blocks in the first temperature range or the second temperature range, and performs high-temperature read verification and low-temperature read verification on the certain group of blocks at a preset data retention temperature and data retention time;

[0016] The maximum number of programming and erasing times without error data in the above read verification is recorded as the high-temperature erase-retention times and the low-temperature erase-retention times respectively;

[0017] The minimum value of the high-temperature erasing and maintaining times and the low-temperature erasing and maintaining times is recorded as the data maintaining times.

[0018] In one embodiment of the present invention, the certain group of blocks has different data retention times at different data retention temperatures, and the ratio between the different data retention times is the temperature acceleration coefficient. ,satisfy:

[0019] ;

[0020] ;

[0021] in, is the reaction rate constant, is the Arrhenius constant, is the reaction activation energy, is the Boltzmann constant, is the thermodynamic temperature, is the base of natural logarithms;

[0022] is the first temperature, is the second temperature, is the temperature acceleration coefficient, for The corresponding reaction rate constant, for The corresponding reaction rate constant.

[0023] In one embodiment of the present invention, in the step distribution of the programming and erasing times corresponding to the certain group of blocks, the step distribution includes a plurality of step segments;

[0024] In a certain step section, the controller performs data processing on two adjacent blocks according to the difference between the corresponding programming and erasing times as the gradient step number, and the gradient step number is a non-zero constant.

[0025] In one embodiment of the present invention, the controller selects chips at different positions on the wafer surface, or randomly selects chips from different batches and divides them into multiple groups as tested flash memories, and selects blocks of different segments on the flash memories for testing.

[0026] The present invention also provides a flash memory testing method, comprising:

[0027] Placing a flash memory in a temperature box, and adjusting the temperature range around the flash memory by the temperature box, wherein the flash memory includes a plurality of blocks;

[0028] In a certain group of blocks, data processing is performed on different blocks according to the number of programming and erasing times distributed in a ladder, wherein one of the programming and erasing times indicates that the block has been processed by one writing and erasing process;

[0029] After the certain group of blocks is subjected to step-distributed programming and erasing times data processing, the certain group of blocks is subjected to a wide temperature test and a data retention test in a first temperature range;

[0030] Erasing the certain group of blocks, and performing a wide temperature test and a data retention test on the certain group of blocks in a second temperature range, wherein the second temperature range includes the first temperature range;

[0031] First test data corresponding to the certain group of blocks in the first temperature range and second test data corresponding to the certain group of blocks in the second temperature range are generated.

[0032] In one embodiment of the present invention, the step of performing a wide temperature test and a data retention test on the certain group of blocks in the first temperature range includes:

[0033] The maximum number of programming and erasing times of the group of blocks without error data under the wide temperature test is recorded as the wide temperature number;

[0034] The maximum number of programming and erasing times of the group of blocks without error data under the data retention test is recorded as the data retention number;

[0035] The minimum value between the wide temperature times and the data retention times is recorded as the maximum service life in the first test data.

[0036] In one embodiment of the present invention, the step of recording the maximum number of programming and erasing times of the certain group of blocks without erroneous data under the wide temperature test as the wide temperature number includes:

[0037] In the first temperature range, the certain group of blocks are respectively subjected to high-temperature erasing and high-temperature reading, or high-temperature erasing and low-temperature reading, or low-temperature erasing and high-temperature reading, or low-temperature erasing and low-temperature reading tests;

[0038] The maximum number of programming and erasing times without error data in the above test is recorded as the high temperature write and high temperature read times, the high temperature write and low temperature read times, the low temperature write and high temperature read times, and the low temperature write and low temperature read times respectively;

[0039] The minimum value among the high temperature write and high temperature read times, the high temperature write and low temperature read times, the low temperature write and high temperature read times and the low temperature write and low temperature read times is recorded as the wide temperature times.

[0040] Beneficial effects of the present invention: The present invention proposes a flash memory test system and test method, which can obtain the maximum service life of the flash memory under the premise of maintaining the best performance in different temperature ranges. It can also simultaneously realize the wear threshold analysis of "consumer-grade" standard flash memory and the wear threshold analysis of "industrial-grade" standard flash memory, greatly saving the testing and labor costs of the flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 A schematic diagram of the structure of a flash memory testing system provided by an embodiment of the present invention.

[0043] Figure 2 A schematic diagram of selecting the location of flash memory on a wafer provided by an embodiment of the present invention.

[0044] Figure 3 A schematic diagram of processing program / erase count data of multiple groups of blocks in a step-by-step manner according to an embodiment of the present invention.

[0045] Figure 4 A schematic diagram of the steps of a flash memory testing method provided by an embodiment of the present invention.

[0046] Figure 5 An embodiment of the present invention provides Figure 4 Schematic diagram of step S30 in FIG.

[0047] Figure 6 An embodiment of the present invention provides Figure 5 Schematic diagram of step S310 in FIG. DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0049] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0050] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0051] See also Figures 1 to 6The present invention proposes a flash memory test system and a test method, which can be applied to storage devices such as eMMC (Embedded Multi Media Card), SSD (Solid State Disk), and UFS (Univeral Flash Storage). The present invention can obtain the maximum service life of the flash memory 30 under the premise of maintaining the best performance in different temperature ranges. For example, the consumer-grade flash memory 30 is compatible with the industrial-grade standard throughout its life cycle, so that the consumer-grade flash memory 30 can be used to produce industrial-grade products without affecting the yield of the industrial-grade products. The following is a detailed description through specific embodiments.

[0052] See also Figure 1 In one embodiment of the present invention, a flash memory test system is proposed, which may include a controller 10 and a temperature box 20, wherein a flash memory 30 may be provided in the temperature box 20, and the temperature box 20 may adjust the temperature range around the flash memory 30. A bus interface is provided on the flash memory 30, and the flash memory 30 is electrically connected to the controller 10 through the bus interface. The controller 10 may write host data and send instructions to the flash memory 30, or the controller 10 may read host data and receive instructions from the flash memory 30, or the controller 10 may erase the host data in the flash memory 30, and the host data refers to the application data written by the controller 10. The controller 10 may be a processor in a communication device such as a personal computer (PC), a tablet computer (Pad), or a mobile phone (CellPhone).

[0053] See also Figure 1 In one embodiment of the present invention, the flash memory 30 is a non-volatile memory, which is usually used to store host data and system programs, etc. The flash memory 30 can be a NAND flash memory. The flash memory 30 may include a plurality of blocks 31, and the blocks 31 may be used to store the host data written by the controller 10. A block 31 may also include a plurality of pages. The block 31 is the erasing unit of the host data on the flash memory 30, and the page is the reading unit of the host data on the flash memory 30. The storage unit of the block 31 may be a single-level cell (SLC), a double-level cell (MLC), a triple-level cell (TLC), a quad-level cell (QLC), and the like.

[0054] See also Figure 1 and Figure 2In one embodiment of the present invention, on a wafer, chips at different positions on the wafer surface, such as the top, bottom, left, right, and middle positions on the wafer surface, can be selected as the flash memory 30 to be tested. The flash memory 30 at different positions on the wafer is tested to improve the reliability of the test data. If it is impossible to distinguish the specific position of the flash memory 30 on the wafer, multiple flash memories 30 can be randomly selected from three wafer batches each time according to the test standard of Jedec, and the multiple flash memories 30 can be divided into multiple groups as the flash memory 30 to be tested.

[0055] Specifically, 77 flash memories 30 are randomly selected from three wafer batches each time, and a total of 231 flash memories 30 are tested. In order to more comprehensively explore the performance of a batch of flash memories 30 to the industrial standard, blocks 31 of different segments on the flash memory 30, such as the front, middle, and back blocks 31 on the flash memory 30, can be selected for testing.

[0056] See also Figure 1 and Figure 3 In one embodiment of the present invention, in a group of blocks 31 of a flash memory 30, the controller 10 performs data processing on different blocks 31 according to the step-by-step distribution of program and erase cycles (PEC), and one program and erase cycle indicates that the block 31 has undergone one write and erase process.

[0057] See also Figure 1 and Figure 3 In one embodiment of the present invention, in a flash memory 30, after a group of blocks 31 are subjected to step-distributed PEC data processing, the controller 10 first performs a wide temperature test and a data retention test on the group of blocks 31 in a first temperature interval, and then performs an erase process on the group of blocks 31. Then, in a second temperature interval, the controller 10 performs a wide temperature test and a data retention test on the group of blocks 31, and the second temperature interval includes the first temperature interval. The controller 10 generates first test data corresponding to the group of blocks 31 in the first temperature interval, and second test data corresponding to the second temperature interval.

[0058] Specifically, the wide temperature test refers to the test of the stable performance of block 31 in a wide temperature working environment between the minimum and maximum values ​​of a temperature range. For example, the wide temperature working environment corresponding to the consumer-grade block 31 is 0~70℃, and the wide temperature working environment corresponding to the industrial-grade block 31 is -40℃~85℃. The performance can be judged by reading the host data on block 31. When there is no error in the host data on block 31, it can be said that the performance of block 31 is good. When there is an error in the host data on block 31, it can be said that the performance of block 31 is reduced. The data retention test refers to the test of the retention time corresponding to the host data on block 31 without error data under a certain temperature environment.

[0059] Specifically, Figure 1 and Figure 3 As shown, after a group of blocks 31 is processed with the step-by-step distribution of programming and erasure times (PEC) data, the group of blocks 31 can be regarded as having undergone normal use processing corresponding to the step-by-step distribution of programming and erasure times (PEC). This embodiment is described with consumer-grade and industrial-grade flash memory 30, the first temperature range can be 0-70°C, and the second temperature range can be -40°C-85°C. In other embodiments, the corresponding temperature range can be specifically set according to the classification level of the flash memory 30.

[0060] See also Figure 1 and Figure 3 In one embodiment of the present invention, since the lowest temperature in the second temperature interval is -40°C and the highest temperature is 85°C, the temperature condition is more stringent than that in the first temperature interval. After a group of blocks 31 are subjected to step-distributed programming and erasure times (PEC) data processing, with the idea of ​​"raising the light to illustrate the heavy", if a block 31 cannot be used normally in the first temperature interval, then the block 31 cannot be used normally in the second temperature interval. On the contrary, if a block 31 cannot be used normally in the second temperature interval, it is entirely possible that the block 31 can be used normally in the first temperature interval. Therefore, it is possible to consider first performing a wide temperature test and a data retention test on the block 31 in the first temperature interval, and then performing a wide temperature test and a data retention test in the second temperature interval.

[0061] Specifically, for a group of blocks 31, first, the group of blocks 31 can be set to perform a wide temperature test and a data retention test in a first temperature interval. Secondly, after performing a wide temperature test and a data retention test in the first temperature interval on the group of blocks 31, the group of blocks 31 can be erased. Finally, a wide temperature test and a data retention test are performed on the group of blocks 31 in a second temperature interval, and the second temperature interval includes the first temperature interval.

[0062] Specifically, the above process of setting the group of blocks 31 to perform a wide temperature test and a data retention test in the first temperature interval, and erasing the group of blocks 31, only increases the number of programming and erasing times (PEC) by one time, which is negligible compared to the step distribution of programming and erasing times of 500, 1000, 2000, and 3000. In this embodiment, by only adjusting the first temperature interval and the second temperature interval for a group of blocks 31, the wide temperature test and the data retention test of the group of blocks 31 in the first temperature interval can be obtained, and the wide temperature test and the data retention test of the group of blocks 31 in the second temperature interval can also be obtained. The controller 10 can generate the first test data corresponding to the group of blocks 31 in the first temperature interval, and the second test data corresponding to the second temperature interval. The present invention can obtain the maximum service life of the flash memory 30 under the premise of maintaining the best performance in different temperature intervals.

[0063] In addition, there are slight differences between different blocks 31 . In this embodiment, there is no need to set up multiple groups of control blocks 31 for testing, that is, there is no need to set a first temperature range for testing the first group of blocks 31 , and there is no need to set a second temperature range for testing the second group of blocks 31 .

[0064] See also Figure 1 and Figure 3 In one embodiment of the present invention, in a certain group of blocks 31, the controller 10 performs data processing on different blocks 31 according to the number of programming and erasing times of step distribution, which can be specifically described as follows.

[0065] Specifically, Figure 3 As shown, blocks 31 of the front, middle and rear parts can be selected on a flash memory 30, and they can be recorded as three groups of blocks 31. In the step distribution of the number of programming and erasing times corresponding to a certain group of blocks 31, the step distribution includes a plurality of step sections. In a certain step section, the controller 10 processes data for two adjacent blocks 31 according to the difference between the number of programming and erasing times as the gradient step number, and the gradient step number is a non-zero constant.

[0066] Specifically, in a step section where the number of programming and erasure times (PEC) in a certain group of blocks 31 is 1 to 1000, the controller 10 processes data on multiple blocks 31 according to a programming and erasure times (PEC) with a gradient step number of 500. In a step section where the number of programming and erasure times (PEC) in a certain group of blocks 31 is 1000 to 2000, the controller 10 processes data on multiple blocks 31 according to a programming and erasure times (PEC) with a gradient step number of 200. In a step section where the number of programming and erasure times (PEC) in a certain group of blocks 31 is 2000 to 3000, the controller 10 processes data on multiple blocks 31 according to a programming and erasure times (PEC) with a gradient step number of 500.

[0067] Specifically, in each group of blocks 31, the number of programming and erasing times (PEC) of the first block 31 worn out is 3000, the number of programming and erasing times (PEC) of the second block 31 worn out is 2500, and the number of programming and erasing times (PEC) of the third block 31 worn out is 2000. The number of programming and erasing times (PEC) of the fourth block 31 worn out is 1800, and the subsequent blocks 31 are worn out with a gradient step number of 200 until the number of programming and erasing times (PEC) of the eighth block 31 worn out is 1000. The number of programming and erasing times (PEC) of the ninth block 31 worn out is 500, and the subsequent blocks 31 are worn out with a gradient step number of 500 until the number of programming and erasing times (PEC) of the tenth block 31 worn out is 1.

[0068] See also Figure 1 In one embodiment of the present invention, in the first temperature interval or the second temperature interval, the controller 10 records the maximum number of programming and erasing times (PEC) of a certain group of blocks 31 under the wide temperature test without erroneous data as the wide temperature number. In the first temperature interval or the second temperature interval, the controller 10 records the maximum number of programming and erasing times (PEC) of a certain group of blocks 31 under the data retention test without erroneous data as the data retention number. In addition, the controller 10 compares the wide temperature number with the data retention number, and records the minimum value of the wide temperature number and the data retention number as the maximum service life in the first test data or the second test data.

[0069] See also Figure 1 In one embodiment of the present invention, the controller 10 performs high-temperature erasing and high-temperature reading, or high-temperature erasing and low-temperature reading, or low-temperature erasing and high-temperature reading, or low-temperature erasing and low-temperature reading, or low-temperature erasing and low-temperature reading tests on a group of blocks 31 in the first temperature interval or the second temperature interval. The maximum number of programming and erasing times without erroneous data in the above tests is recorded as the high-temperature writing and high-temperature reading times, the high-temperature writing and low-temperature reading times, the low-temperature writing and high-temperature reading times, and the low-temperature writing and low-temperature reading times. The minimum value among the high-temperature writing and high-temperature reading times, the high-temperature writing and low-temperature reading times, the low-temperature writing and high-temperature reading times, and the low-temperature writing and low-temperature reading times is recorded as the wide temperature times.

[0070] Specifically, the first temperature range is 0-70°C, and the second temperature range is -40°C-85°C. Since the processing procedures of the wide temperature test corresponding to the first temperature range and the second temperature range are the same, the only difference is the difference in the maximum temperature value and the minimum temperature value, the wide temperature test of the second temperature range is taken as an example for specific description below.

[0071] High temperature erase and read test: After the step-distributed programming and erasure times (PEC) data processing is performed on a certain group of blocks 31, first, the group of blocks 31 is placed in an 85°C temperature box 20, and 10 minutes later, the high temperature erase is performed at 85°C, and the test data is 0x3CC35AA5. Secondly, the number of error bits (Error Bit Count) in the group of blocks 31 is read and detected, and it is determined whether the number of error bits exceeds the error correction threshold of the controller 10. When the number of error bits in the block 31 exceeds the error correction threshold, it is recorded as an error correction code (UECC, Uncorrectable Error Correction Code). If an error correction code appears in a certain block 31, it means that the programming and erase times (PEC) corresponding to the block 31 cannot withstand the high temperature erase and high temperature read test. On the contrary, if an error correction code does not appear in a certain block 31, it means that the programming and erase times (PEC) corresponding to the block 31 can withstand the high temperature erase and high temperature read test. In this test, the maximum number of program and erase times (PEC) without error correction code is the maximum service life in this scenario.

[0072] Low temperature erase and read test: After the step-distributed programming and erasure times (PEC) data processing is performed on a certain group of blocks 31, first, the group of blocks 31 is placed in a -40°C incubator 20, and after 10 minutes, the low temperature erase is performed at -40°C, and the test data is 0x3CC35AA5. Secondly, the number of error bits (Error Bit Count) in the group of blocks 31 is read and detected, and it is determined whether the number of error bits exceeds the error correction threshold of the controller 10. When the number of error bits in the block 31 exceeds the error correction threshold, it is recorded as an error correction code (UECC, Uncorrectable Error Correction Code). If an error correction code appears in a certain block 31, it means that the programming and erasure times (PEC) corresponding to the block 31 cannot withstand the low temperature erase and low temperature read test. On the contrary, if an error correction code does not appear in a certain block 31, it means that the programming and erasure times (PEC) corresponding to the block 31 can withstand the low temperature erase and low temperature read test. In this test, the maximum number of program and erase times (PEC) without error correction code is the maximum service life in this scenario.

[0073] High temperature erase and low temperature read test: After the step-distributed programming and erasure times (PEC) data processing is performed on a certain group of blocks 31, first, the group of blocks 31 is placed in an 85°C incubator 20, and 10 minutes later, a high temperature erase is performed at 85°C, and the test data is 0x3CC35AA5. Secondly, the group of blocks 31 is placed in a -40°C incubator 20, and the number of error bits (Error Bit Count) that appear in the group of blocks 31 is read and detected, and it is determined whether the number of error bits exceeds the error correction threshold of the controller 10. When the number of error bits in the block 31 exceeds the error correction threshold, it is recorded as an error correction code (UECC, Uncorrectable ErrorCorrection Code). If an error correction code appears in a certain block 31, it means that the programming and erasure times (PEC) corresponding to the block 31 cannot withstand the high temperature erase and low temperature read test. On the contrary, if no error correction code appears in a block 31, it means that the program and erase times (PEC) corresponding to the block 31 can withstand the high temperature erase and low temperature read test. In this test, the maximum program and erase times (PEC) without error correction code is the maximum service life in this scenario.

[0074] Low temperature erase and read test: After the step-distributed programming and erasure times (PEC) data processing is performed on a certain group of blocks 31, first, the group of blocks 31 is placed in a -40°C incubator 20, and after 10 minutes, a -40°C low temperature erase is performed, and the test data is 0x3CC35AA5. Secondly, the group of blocks 31 is placed in an 80°C incubator 20, and the number of error bits (Error Bit Count) that appear in the group of blocks 31 is read and detected, and it is determined whether the number of error bits exceeds the error correction threshold of the controller 10. When the number of error bits in the block 31 exceeds the error correction threshold, it is recorded as an error correction code (UECC, Uncorrectable ErrorCorrection Code). If an error correction code appears in a certain block 31, it means that the programming and erasure times (PEC) corresponding to the block 31 cannot withstand the low temperature erase and high temperature read test. On the contrary, if no error correction code appears in a block 31, it means that the program and erase times (PEC) corresponding to the block 31 can withstand the low-temperature erase and high-temperature read test. In this test, the maximum program and erase times (PEC) without the occurrence of error correction code is the maximum service life in this scenario.

[0075] In the second temperature range, after the above-mentioned high temperature erase and high temperature read test, high temperature erase and low temperature read test, high temperature erase and low temperature read test, low temperature erase and low temperature read test, the minimum programming and erasure times (PEC) without error correction code appearing in each scenario are selected, which are recorded as high temperature write high temperature read times, high temperature write low temperature read times, low temperature write high temperature read times, and low temperature write low temperature read times. The controller 10 compares the magnitudes of the high temperature write high temperature read times, the high temperature write low temperature read times, the low temperature write high temperature read times, and the low temperature write low temperature read times, and records the minimum value among the high temperature write high temperature read times, the high temperature write low temperature read times, the low temperature write high temperature read times, and the low temperature write low temperature read times as the wide temperature times of the second temperature range.

[0076] See also Figure 1 In one embodiment of the present invention, the controller 10 performs high-temperature erasing or low-temperature erasing processing on a certain group of blocks 31 in the first temperature interval or the second temperature interval, and performs high-temperature read verification and low-temperature read verification on a certain group of blocks 31 at a preset data retention temperature and data retention time. The maximum number of programming and erasing times (PEC) without erroneous data in the above read verification is recorded as the high-temperature erase retention number and the low-temperature erase retention number. The minimum value of the high-temperature erase retention number and the low-temperature erase retention number is recorded as the data retention number.

[0077] Specifically, after high-temperature erasing, the high-temperature read verification and low-temperature read verification are performed at the data retention temperature and data retention time as follows. After a certain group of blocks 31 is subjected to step-distributed programming and erasure times (PEC) data processing, first, the group of blocks 31 is placed in an 85°C incubator 20, and 85°C high-temperature erasing is performed after 10 minutes, and the test data is 0x3CC35AA5. Secondly, the group of blocks 31 is placed in a 125°C incubator 20 for power-off baking, and the duration can be determined based on the time calculated by the temperature acceleration coefficient. After the accelerated baking is completed, it is placed in an 85°C incubator 20, and a read verification is performed after 10 minutes to detect whether an error correction code appears in the group of blocks 31. Finally, the group of blocks 31 is placed in a -40°C incubator 20 again, and a read verification is performed after 10 minutes to detect whether an error correction code appears in the group of blocks 31. The read verification is performed in the temperature chamber 20 at -40°C and 85°C. The maximum programming and erasure times (PEC) when no error correction code occurs in the two read tests are recorded as the high-temperature erase retention times.

[0078] Specifically, after low-temperature erasing, the high-temperature read verification and low-temperature read verification are performed at the data retention temperature and data retention time as follows. After a certain group of blocks 31 are subjected to step-distributed programming and erasure times (PEC) data processing, first, the group of blocks 31 is placed in a -40°C incubator 20, and a low-temperature erase at -40°C is performed after 10 minutes, and the test data is 0x3CC35AA5. Secondly, the group of blocks 31 is placed in a 125°C incubator 20 for power-off baking, and the duration can be determined based on the time calculated by the temperature acceleration coefficient. After the accelerated baking is completed, it is placed in a -40°C incubator 20, and a read verification is performed after 10 minutes to detect whether an error correction code appears in the group of blocks 31. Finally, the group of blocks 31 is placed in an 85°C incubator 20 again, and a read verification is performed after 10 minutes to detect whether an error correction code appears in the group of blocks 31. The read verification is performed in the temperature chamber 20 at -40°C and 85°C. The maximum programming and erasure times (PEC) when no error correction code occurs in the two read tests are recorded as the low-temperature erase retention times.

[0079] Specifically, the controller 10 compares the high-temperature erasing and maintaining times and the low-temperature erasing and maintaining times, and records the minimum value of the high-temperature erasing and maintaining times and the low-temperature erasing and maintaining times as the data retention times, which is the maximum service life in this scenario.

[0080] See also Figure 1 In one embodiment of the present invention, a group of blocks 31 has different data retention times at different data retention temperatures, and the ratio between the different data retention times is the temperature acceleration coefficient ,satisfy:

[0081] ;

[0082] ;

[0083] in, is the reaction rate constant, is the Arrhenius constant, is the reaction activation energy, The value is 1.1 , is the Boltzmann constant, The numerical value is 8.62×10 -5 , is the thermodynamic temperature, is the base of natural logarithms. is the first temperature, is the second temperature, is the temperature acceleration coefficient, for The corresponding reaction rate constant, for The corresponding reaction rate constant.

[0084] Specifically, when At 30°C, Table 1 can be obtained by calculation.

[0085] Table 1. Temperature acceleration coefficient table corresponding to data retention temperature and data retention time

[0086]

[0087] As can be seen from Table 1, the data retention time can be tested at high temperature, and then the data retention time at room temperature can be calculated using the formula above. In this way, the corresponding data retention time at each temperature can be quickly obtained without the need to actually test it at room temperature, greatly shortening the test time required for different data retention temperatures. According to Table 1, the corresponding data retention time at 30°C is calculated to be one year, and it can be accelerated by baking in a 125°C high temperature oven 20. The time required for the accelerated test can be specifically calculated using the formula above.

[0088] After a group of blocks 31 are subjected to the above-mentioned wide temperature test and data retention test in the first temperature range or the second temperature range, the controller 10 compares the wide temperature times and the data retention times, and records the minimum value between the wide temperature times and the data retention times as the maximum service life in the first test data or the second test data.

[0089] It can be seen that the biggest differences between consumer-grade flash memory 30 and industrial-grade flash memory 30 are the following two points. First, the operating temperature range is different. Consumer-grade flash memory 30 is 0~70℃, and industrial-grade flash memory 30 is -40~85℃. Second, the requirements for data retention time are different. Consumer-grade flash memory 30 is mostly stored at 30℃ for one year, and industrial-grade flash memory 30 is mostly required to be stored at 55℃ for one year. Among them, the quality of flash memory 30 is mainly affected by the number of programming and erasing times (PEC). When the number of programming and erasing times (PEC) is small, that is, when the flash memory 30 is new, the storage capacity of charge is strong, which is why the consumer-grade flash memory 30 can pass the wide temperature test in the early stage of its service life. However, as the number of programming and erasing times (PEC) increases, the storage capacity of flash memory 30 for charge decreases, and this effect is irreversible and will seriously affect the tolerance of wide temperature test and data retention test.

[0090] Therefore, the present invention can obtain the maximum service life of the flash memory 30 under the premise of maintaining the best performance in different temperature ranges. This embodiment can quickly determine the life range of the consumer-grade flash memory 30 as the industrial-grade flash memory 30. Thereby solving the problem of the performance degradation caused by using the consumer-grade flash memory 30 as the industrial-grade flash memory 30. This embodiment sacrifices the service life of the consumer-grade flash memory 30 in exchange for the requirement of supporting the industrial-grade flash memory 30 during the entire use cycle, and can control the yield of the flash memory 30. This embodiment can simultaneously realize the wear threshold analysis of the "consumer-grade" standard flash memory 30 and the wear threshold analysis of the "industrial-grade" standard flash memory 30, which greatly saves the testing and manpower costs of the flash memory 30.

[0091] See also Figure 4 In one embodiment of the present invention, a flash memory testing method is proposed, which may include the following steps.

[0092] Step S10, placing the flash memory in a temperature box, and adjusting the temperature range around the flash memory by using the temperature box, the flash memory includes a plurality of blocks.

[0093] In one embodiment of the present invention, a flash memory 30 may be provided in the temperature box 20, and the temperature box 20 may adjust the temperature range around the flash memory 30. The flash memory 30 may be a flash memory particle, which is a non-volatile memory, usually used to store host data and system programs. The flash memory 30 may include a plurality of blocks 31, and the blocks 31 may be used to store the host data written by the controller 10. A block 31 may also include a plurality of pages. The block 31 is the erasing unit of the host data on the flash memory 30, and the page is the reading unit of the host data on the flash memory 30.

[0094] Step S20: In a certain group of blocks, data processing is performed on different blocks according to the programming and erasing times of step distribution. One programming and erasing time indicates that the block has been processed once for writing and erasing.

[0095] In one embodiment of the present invention, in a step distribution of programming and erasure times (PEC) of 1 to 1000 in a certain group of blocks 31, the controller 10 performs data processing on some blocks 31 according to the programming and erasure times (PEC) of the first gradient. In a step distribution of programming and erasure times (PEC) of 1000 to 2000 in a certain group of blocks 31, the controller 10 performs data processing on some blocks 31 according to the programming and erasure times (PEC) of the second gradient. In a step distribution of programming and erasure times (PEC) of 2000 to 3000 in a certain group of blocks 31, the controller 10 performs data processing on some blocks 31 according to the programming and erasure times (PEC) of the third gradient.

[0096] Step S30 , after performing step-distributed programming and erasing times data processing on a group of blocks, performing a wide temperature test and a data retention test on the group of blocks in a first temperature range.

[0097] In one embodiment of the present invention, since the lowest temperature in the second temperature interval is -40°C and the highest temperature is 85°C, the temperature condition is more stringent than that in the first temperature interval. After a group of blocks 31 are subjected to step-distributed programming and erasure times (PEC) data processing, with the idea of ​​"raising the light to illustrate the heavy", if a block 31 cannot be used normally in the first temperature interval, then the block 31 cannot be used normally in the second temperature interval. On the contrary, if a block 31 cannot be used normally in the second temperature interval, it is entirely possible that the block 31 can be used normally in the first temperature interval. Therefore, it is possible to consider first performing a wide temperature test and a data retention test on the block 31 in the first temperature interval, and then performing a wide temperature test and a data retention test in the second temperature interval.

[0098] Step S40: performing an erasing process on a group of blocks, and performing a wide temperature test and a data retention test on the group of blocks in a second temperature range, wherein the second temperature range includes the first temperature range.

[0099] In one embodiment of the present invention, for a group of blocks 31, first, the group of blocks 31 can be set to perform a wide temperature test and a data retention test in a first temperature interval. Secondly, after performing a wide temperature test and a data retention test in the first temperature interval on the group of blocks 31, the group of blocks 31 can be erased. Finally, a wide temperature test and a data retention test are performed on the group of blocks 31 in a second temperature interval, and the second temperature interval includes the first temperature interval.

[0100] Step S50: generating first test data corresponding to a group of blocks in a first temperature range and second test data corresponding to a second temperature range.

[0101] In one embodiment of the present invention, the above process of setting the group of blocks 31 to perform a wide temperature test and a data retention test in the first temperature interval, and erasing the group of blocks 31, only increases the number of programming and erasing times (PEC) by one time, which is negligible compared to the step distribution of the number of programming and erasing times of 500, 1000, 2000, and 3000. In this embodiment, only by adjusting the first temperature interval and the second temperature interval for a group of blocks 31, the wide temperature test and the data retention test of the group of blocks 31 in the first temperature interval can be obtained, and the wide temperature test and the data retention test of the group of blocks 31 in the second temperature interval can also be obtained. The controller 10 can generate the first test data corresponding to the group of blocks 31 in the first temperature interval, and the second test data corresponding to the second temperature interval.

[0102] In addition, there are slight differences between different blocks 31 . In this embodiment, there is no need to set up multiple groups of control blocks 31 for testing, that is, there is no need to set a first temperature range for testing the first group of blocks 31 , and there is no need to set a second temperature range for testing the second group of blocks 31 .

[0103] See also Figure 5 In one embodiment of the present invention, step S30 may include step S310, step S320 and step S330. Step S310 may be expressed as recording the maximum number of programming and erasing times of a certain group of blocks 31 under a wide temperature test without erroneous data as the wide temperature number. Step S320 may be expressed as recording the maximum number of programming and erasing times of a certain group of blocks 31 under a data retention test without erroneous data as the data retention number. Step S330 may be expressed as recording the minimum value between the wide temperature number and the data retention number as the maximum service life in the first test data.

[0104] See also Figure 6 In one embodiment of the present invention, step S310 may include step S311, step S312 and step S313, wherein step S311 may be represented as testing a group of blocks 31 with high temperature erasing and high temperature reading, or high temperature erasing and low temperature reading, or low temperature erasing and high temperature reading, or low temperature erasing and low temperature reading within the first temperature range. Step S312 may be represented as recording the maximum number of programming and erasing times without erroneous data in the above tests as high temperature writing and high temperature reading times, high temperature writing and low temperature reading times, low temperature writing and high temperature reading times, and low temperature writing and low temperature reading times, respectively. Step S313 may be represented as recording the minimum value among the high temperature writing and high temperature reading times, the high temperature writing and low temperature reading times, the low temperature writing and high temperature reading times, and the low temperature writing and low temperature reading times as the wide temperature times.

[0105] In summary, the present invention proposes a flash memory test system and test method, which can obtain the maximum service life of the flash memory under the premise of maintaining the best performance in different temperature ranges. This embodiment can generate first test data corresponding to the block in the first temperature range, and second test data corresponding to the second temperature range. Between the first test data and the second test data, only one programming and erasing number is added, and the impact is minimal. The present invention can simultaneously realize the wear threshold analysis of "consumer-grade" standard flash memory and the wear threshold analysis of "industrial-grade" standard flash memory, which greatly saves the testing and manpower costs of the flash memory.

[0106] The flow chart and block diagram in the accompanying drawings illustrate the possible implementation architecture, function and operation of the method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

Claims

1. A flash memory testing system, It is characterized in that include: A temperature box, wherein a flash memory is arranged in the temperature box, and the temperature box is used to adjust the temperature range around the flash memory, and the flash memory includes a plurality of groups of blocks; A controller, in a certain group of blocks, the controller performs data processing on different blocks according to the number of programming and erasing times distributed in a ladder, wherein one number of programming and erasing times indicates that the block has been processed by one writing and erasing; After the certain group of blocks is subjected to step-distributed programming and erasure times data processing, the controller firstly performs a wide temperature test and a data retention test on the certain group of blocks in a first temperature interval, then performs an erasure process on the certain group of blocks, and then performs a wide temperature test and a data retention test on the certain group of blocks in a second temperature interval, wherein the second temperature interval includes the first temperature interval; The controller generates first test data corresponding to the certain group of blocks in the first temperature range and second test data corresponding to the second temperature range; The wide temperature test refers to a test of the stability of the performance of a group of blocks in a wide temperature working environment between a minimum value and a maximum value of a temperature range.

2. The flash memory testing system according to claim 1, It is characterized in that The controller records the maximum programming and erasing times of the certain group of blocks without erroneous data under the wide temperature test as the wide temperature times, and records the maximum programming and erasing times of the certain group of blocks without erroneous data under the data retention test as the data retention times; The controller records the minimum value of the wide temperature times and the data retention times as the maximum service life in the first test data or the second test data.

3. The flash memory testing system according to claim 2, It is characterized in that The controller performs high-temperature erasing and high-temperature reading, or high-temperature erasing and low-temperature reading, or low-temperature erasing and high-temperature reading, or low-temperature erasing and low-temperature reading tests on the group of blocks in the first temperature interval or the second temperature interval; The maximum number of programming and erasing times without error data in the above test is recorded as the high temperature write and high temperature read times, the high temperature write and low temperature read times, the low temperature write and high temperature read times, and the low temperature write and low temperature read times respectively; The minimum value among the high temperature write and high temperature read times, the high temperature write and low temperature read times, the low temperature write and high temperature read times and the low temperature write and low temperature read times is recorded as the wide temperature times.

4. The flash memory testing system according to claim 2, It is characterized in that The controller performs high-temperature erasing or low-temperature erasing processing on the certain group of blocks in the first temperature range or the second temperature range, and performs high-temperature read verification and low-temperature read verification on the certain group of blocks at a preset data retention temperature and data retention time; The maximum number of programming and erasing times without error data in the above read verification is recorded as the high-temperature erase-retention times and the low-temperature erase-retention times respectively; The minimum value of the high-temperature erasing and maintaining times and the low-temperature erasing and maintaining times is recorded as the data maintaining times.

5. The flash memory testing system according to claim 4, It is characterized in that The certain group of blocks has different data retention times at different data retention temperatures, and the ratio between the different data retention times is the temperature acceleration coefficient. ,satisfy: ； ； in, is the reaction rate constant, is the Arrhenius constant, is the reaction activation energy, is the Boltzmann constant, is the thermodynamic temperature, is the base of natural logarithms; is the first temperature, is the second temperature, is the temperature acceleration coefficient, for The corresponding reaction rate constant, for The corresponding reaction rate constant.

6. The flash memory testing system according to claim 1, It is characterized in that In the step distribution of the programming and erasing times corresponding to the certain group of blocks, the step distribution includes a plurality of step segments; In a certain step section, the controller processes data for two adjacent blocks according to a gradient step number corresponding to a difference between the number of programming and erasing times, and the gradient step number is a non-zero constant.

7. The flash memory testing system according to claim 1, It is characterized in that The controller selects chips at different positions on the wafer surface, or randomly selects chips from different batches and divides them into multiple groups as the flash memory for testing, and selects blocks of different segments on the flash memory for testing.

8. A flash memory testing method, It is characterized in that include: Placing a flash memory in a temperature box, and adjusting the temperature range around the flash memory by the temperature box, wherein the flash memory includes a plurality of blocks; In a certain group of blocks, data processing is performed on different blocks according to the number of programming and erasing times distributed in a ladder, wherein one of the programming and erasing times indicates that the block has been processed by one writing and erasing process; After the certain group of blocks is subjected to step-distributed programming and erasing times data processing, a wide temperature test and a data retention test are performed on the certain group of blocks in a first temperature range, wherein the wide temperature test refers to a test of the stability of the performance of the certain group of blocks in a wide temperature working environment between a minimum value and a maximum value of a temperature range; Erasing the certain group of blocks, and performing a wide temperature test and a data retention test on the certain group of blocks in a second temperature range, wherein the second temperature range includes the first temperature range; First test data corresponding to the certain group of blocks in the first temperature range and second test data corresponding to the certain group of blocks in the second temperature range are generated.

9. The flash memory testing method according to claim 8, It is characterized in that The step of performing a wide temperature test and a data retention test on the certain group of blocks in the first temperature range includes: The maximum number of programming and erasing times of the group of blocks without error data under the wide temperature test is recorded as the wide temperature number; The maximum number of programming and erasing times of the group of blocks without error data under the data retention test is recorded as the data retention number; The minimum value between the wide temperature times and the data retention times is recorded as the maximum service life in the first test data.

10. The flash memory testing method according to claim 9, It is characterized in that The step of recording the maximum number of programming and erasing times of the certain group of blocks without erroneous data under the wide temperature test as the wide temperature times includes: In the first temperature range, the certain group of blocks are respectively subjected to high-temperature erasing and high-temperature reading, or high-temperature erasing and low-temperature reading, or low-temperature erasing and high-temperature reading, or low-temperature erasing and low-temperature reading tests; The maximum number of programming and erasing times without error data in the above test is recorded as the high temperature write and high temperature read times, the high temperature write and low temperature read times, the low temperature write and high temperature read times, and the low temperature write and low temperature read times respectively; The minimum value among the high temperature write and high temperature read times, the high temperature write and low temperature read times, the low temperature write and high temperature read times and the low temperature write and low temperature read times is recorded as the wide temperature times.

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