A multi-channel trench MOSFET and a method for manufacturing the same

Abstract

The application relates to a multi-channel trench type MOSFET and a preparation method thereof, and belongs to the technical field of semiconductors. The application forms a structure of a P+ channel region, an N-resistance region and a P+ channel region in a groove spacing region through special structural design without increasing additional process steps. The width and the doping concentration of the P+ channel region, the N-resistance region and the P+ channel region in the structure are controlled, the N-resistance region is completely depleted by the P+ channel regions on both sides without voltage of a device gate, and the device gate is in a blocking state. When a positive voltage is applied to the device gate, the N-resistance region is changed from the completely depleted state to a normal conduction state, an additional conductive channel is formed in addition to a reverse type layer conductive channel below a gate oxide, and the unit area conduction resistance of the trench type MOSFET is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a multi-channel trench MOSFET and a preparation method thereof. BACKGROUND

[0002] In the technical field of power electronics, MOSFET as a commonly used power semiconductor has replaced triode to become one of the most commonly used switching devices in the field of power semiconductors.

[0003] In the iterative process of MOSFET in the past decades, improving power density has always been one of the main directions of development, and reducing the on-resistance value per unit area is the most effective method to improve the power density of the device and is one of the main research and development directions of MOSFET.

[0004] For the trench MOSFET, reducing the trench width and adopting the shield gate structure are the most important measures to reduce the on-resistance per unit area at present, but with the continuous improvement of the process technology level, the trench width of the high-performance trench MOSFET has been reduced to the sub-micron level, and the space for further reducing the trench width is limited, and the shield gate structure technology has been very mature after development for more than ten years, so it is necessary to adopt new structures and new technologies to continuously reduce the on-resistance per unit area of the trench MOSFET. SUMMARY

[0005] The present application provides a multi-channel trench MOSFET and a preparation method thereof aiming at the research and development direction of reducing the on-resistance per unit area of MOSFET.

[0006] The technical scheme of the present application is as follows:

[0007] A preparation method of a multi-channel trench MOSFET, comprising the following steps:

[0008] Step S100, a plurality of spaced P+ channel layers are prepared in an epitaxial wafer, and the N-resistance layer in the spaced area of the P+ channel layer is completely depleted;

[0009] Step S200, an N+ layer is prepared in the epitaxial wafer;

[0010] Step S300, a plurality of trenches are prepared in the epitaxial wafer;

[0011] Step S400, a gate dielectric and a polysilicon are sequentially prepared in the trench;

[0012] Step S500, an isolation layer is deposited on the epitaxial wafer, and a window is opened at the N+ layer and the polysilicon to respectively prepare an S electrode and a G electrode;

[0013] Step S600, a D electrode is prepared at the bottom of the epitaxial wafer, and the whole device is prepared.

[0014] Specifically, step S100 comprises:

[0015] Step S110, using a photolithography process, using a mask to protect the outside area of the P+ channel layer; through diffusion process or ion implantation process, forming the spaced P+ channel layer;

[0016] The spaced P+ channel layer completely depletes the N-resistance layer in the spaced area along the horizontal direction.

[0017] Specifically, step S200 comprises:

[0018] Step S210, using a photolithography process, using a mask to protect the outside area of the N+ layer; through diffusion process or ion implantation process, forming the N+ layer.

[0019] Specifically, step S300 comprises:

[0020] Step S310, using a photolithography process, using a mask to protect the outside area of the trench; through etching process, forming the trench;

[0021] The trench extends downward from the top surface of the epitaxial wafer, the bottom surface is lower than the bottom surface of the P+ channel layer and higher than the bottom surface of the N-resistance layer, and the width ranges from 1 to 10 um.

[0022] Specifically, step S400 comprises:

[0023] Step S410, through a photolithography process, using a mask to protect the outside area of the trench, using a thermal oxidation technology to prepare a gate medium in the trench;

[0024] Step S420, through chemical vapor deposition, preparing polysilicon in the trench.

[0025] Specifically, step S500 comprises:

[0026] Step S510, through chemical vapor deposition to prepare an isolation layer, through a photolithography process, using a mask to protect the outside area of the N+ layer and the polysilicon, through etching process to open a window at the N+ layer and the polysilicon;

[0027] Step S520, through a stripping process or etching process, preparing a corresponding S-pole electrode and G-pole electrode at the N+ layer and the polysilicon window.

[0028] Specifically, step S600 comprises:

[0029] Step S610, through a thinning process and a back gold process to prepare a D-pole electrode at the bottom of the epitaxial wafer, and the whole device is prepared.

[0030] A multi-channel trench MOSFET, comprising a D electrode, an epitaxial wafer and an isolation layer arranged in sequence from bottom to top;

[0031] The epitaxial wafer is internally provided with:

[0032] P+ channel layers are provided in several numbers and are spaced apart, the top surface of the P+ channel layers is lower than the top surface of the epitaxial wafer, and the bottom surface of the P+ channel layers is higher than the bottom surface of the N-resistance layer, and the spaced-apart P+ channel layers completely deplete the N-resistance layer in the spacing area in the horizontal direction;

[0033] An N+ layer extends downward from the top surface of the epitaxial wafer and is connected to the top surface of the P+ channel layer;

[0034] Trenches are provided in several numbers and extend downward from the top surface of the N+ layer, pass through the P+ channel layer and extend into the N-resistance layer;

[0035] Gate dielectric is arranged on the inner side wall of the trench and is connected to the N+ layer, the P+ channel layer and the N-resistance layer, respectively;

[0036] Polysilicon extends downward from the top of the trench and is filled in the gate dielectric;

[0037] The isolation layer is internally provided with:

[0038] An S electrode extends downward from the top surface of the isolation layer, passes through the N+ layer and extends into the P+ channel layer;

[0039] A G electrode extends downward from the top surface of the isolation layer and extends into the polysilicon to form an ohmic contact with the polysilicon.

[0040] Specifically, the epitaxial wafer comprises an N+ substrate layer and an N-resistance layer connected in sequence from bottom to top.

[0041] Specifically, the S electrode is connected to the N+ layer, the P+ channel layer and the N-resistance layer to form an ohmic contact.

[0042] The present application has the following beneficial effects:

[0043] The trench MOSFET, the reduction of the trench width and the adoption of the shielded gate structure are the main measures for reducing the on-resistance per unit area at present, but with the continuous improvement of the process technology level, the trench width of the high-performance trench MOSFET has been reduced to the sub-micron level, and the space for further reducing the trench width is limited, and the shielded gate structure technology has been very mature after development for more than ten years, so it is necessary to adopt new structures and new technologies to continuously reduce the on-resistance per unit area of the trench MOSFET. The present application forms a P+ channel region, an N-resistance region and a P+ channel region in the trench spacing area through special structure design without increasing additional process steps, and by controlling the width and doping concentration of the P+ channel region, the N-resistance region and the P+ channel region in the structure, the device gate is not added voltage, the N-resistance region is completely depleted by the P+ channel region on both sides, and the device gate is in a blocking state, the N-resistance region is changed from the completely depleted state to the normal conduction state when the device gate is added with a positive voltage, forming an additional conductive channel in addition to the inversion layer conductive channel under the gate oxide, thereby reducing the on-resistance per unit area of the trench MOSFET. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 It is a process flow chart of the present application;

[0045] Figure 2 It is a device cross-section structure schematic diagram in step S100;

[0046] Figure 3 It is a device cross-section structure schematic diagram in step S200;

[0047] Figure 4 It is a device cross-section structure schematic diagram in step S300;

[0048] Figure 5 It is a structure schematic diagram of preparing gate medium in the trench;

[0049] Figure 6 It is a structure schematic diagram of preparing polysilicon in the trench;

[0050] Figure 7 It is a structure schematic diagram of depositing an isolation layer on an epitaxial wafer and windowing at an N+ layer and a polysilicon;

[0051] Figure 8 It is a structure schematic diagram of preparing S electrode and G electrode;

[0052] Figure 9 It is a device cross-section structure schematic diagram in step S600;

[0053] Fig. 1 is an epitaxial wafer, 2 is a P+ channel layer, 3 is an N+ layer, 4 is a trench, 5 is a gate dielectric, 6 is polysilicon, 7 is an isolation layer, 8 is an S electrode, 9 is a G electrode, 10 is a D electrode, 11 is an N+ substrate layer, and 12 is an N- withstand voltage layer. DETAILED DESCRIPTION

[0054] Embodiments of the present application are described in detail below with reference to the attached drawing figures, wherein the same or like reference numerals and characters are used throughout the drawing figures to designate the same or like components. The embodiments described below are illustrative only, and are not intended to be limiting on the present application.

[0055] In the description of the present application, it is necessary to point out that unless explicitly defined and limited, the terms "mounting", "connection", and "linking" should be understood in a broad sense, for example, they can be fixed connection, detachable connection, or integral connection; they can be mechanical connection, or electrical connection; they can be direct connection, or indirect connection through an intermediate medium; and they can be internal connection of two elements. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0056] The present application is described below with reference to Figs. 1-9;

[0057] A method for manufacturing a multi-channel trench MOSFET includes the following steps:

[0058] Step S100, a plurality of spaced P+ channel layers 2 are prepared in an epitaxial wafer 1; as shown in Figure 2 ;

[0059] Step S110, using a photolithography process, the P+ channel layer 2 is protected outside the region using a mask; through a diffusion process or an ion implantation process, the spaced P+ channel layer 2 is formed;

[0060] The spaced P+ channel layer 2 completely depletes the N- withstand voltage layer 12 in the spaced region along the horizontal direction;

[0061] Correspondingly, the epitaxial wafer 1 is an N-type epitaxial wafer, which is composed of an N+ substrate layer 11 and an N- withstand voltage layer 12 from bottom to top, the thickness of the epitaxial wafer 1 is 100-2000 um, the thickness of the N+ substrate layer 11 is 90-1500 um, the thickness of the N- withstand voltage layer 12 is 10-500 um, the thickness of the P+ channel layer 2 is 1-5 um, the spacing distance is set to 0.01-10 um, the doping concentration range of N-type doping is 1e 14 .cm -3 -1e 20 .cm -3 , and the doping concentration range of P-type doping is 1e15 .cm -3 -1e 20 .cm -3 , the related parameters are related to the electrical design of the device;

[0062] In this embodiment, the thickness of the epitaxial wafer 1 is 350 um, the thickness of the N+ substrate layer 11 is 330 um, and the doping concentration is 1e 19 .cm -3 , the thickness of the N- voltage resistance layer 12 is 20 um, and the doping concentration is 1e 16 .cm -3 , the thickness of the P+ channel layer 2 is 2 um, the interval distance is 0.1 um, and the doping concentration is 3e 18 .cm -3 , which ensures that the P+ channel layer 2 along the horizontal direction completely depletes the N- voltage resistance layer 12 in the interval area, and the interval P+ channel layer 2 is prepared by using an ion implantation process.

[0063] Step S200, preparing an N+ layer 3 in the epitaxial wafer 1; as Figure 3 shown;

[0064] Step S210, using a photolithography process, using a mask to protect the external area of the N+ layer 3; forming the N+ layer 3 by a diffusion process or an ion implantation process;

[0065] Correspondingly, the N+ layer 3 extends downward from the top surface of the P+ channel layer 2, the bottom surface is higher than the bottom surface of the P+ channel layer 2, the thickness is set to 0.5-3 um, and the doping concentration range is 1e 18 .cm -3 -1e 20 .cm -3 , the related parameters are related to the electrical design of the device;

[0066] In this embodiment, the thickness of the N+ layer 3 is 1 um, the doping concentration is 1e 19. cm -3 , and the N+ layer 3 is prepared by using an ion implantation process.

[0067] Step S300, preparing a plurality of grooves 4 in the epitaxial wafer 1; as Figure 4 shown;

[0068] Step S310, using a photolithography process, using a mask to protect the external area of the groove 4; forming the groove 4 by an etching process;

[0069] Correspondingly, the groove 4 extends downward from the top surface of the epitaxial wafer 1, the bottom surface is lower than the bottom surface of the P+ channel layer 2, and higher than the bottom surface of the N- voltage resistance layer 12, the width range is set to 1-10 um, and the related parameters are related to the electrical design of the device;

[0070] In this embodiment, the groove 4 has a depth of 4 um and a width of 2 um, and is prepared by using the ICP dry etching process.

[0071] In step S400, the gate dielectric 5 and the polysilicon 6 are sequentially prepared in the groove 4. Figure 5 、 Figure 6 as shown in the figure.

[0072] In step S410, the gate dielectric 5 is prepared in the groove 4 by using the thermal oxidation technology after the external area of the groove 4 is protected by using the mask through the photolithography process.

[0073] In step S420, the polysilicon 6 is prepared in the groove 4 by using the chemical vapor deposition.

[0074] Correspondingly, the gate dielectric 5 is located in the groove 4 and contacts the N+ layer 3, the P+ channel layer 2 and the N- withstand voltage layer 12 respectively, the polysilicon 6 is located in the groove 4, fills the groove 4 and contacts the gate dielectric 5, the upper surface of the polysilicon 6 is horizontal with the upper surface of the groove 4, the material of the gate dielectric 5 is SiO2, and the thickness is set to 40-500 nm.

[0075] In this embodiment, the SiO2 with a thickness of 80 nm is prepared as the gate dielectric 5 by using the thermal oxidation technology, and the polysilicon 6 is prepared by using the chemical vapor deposition.

[0076] In step S500, the isolation layer 7 is deposited on the epitaxial wafer 1, and the S pole electrode 8 and the G pole electrode 9 are respectively prepared by windowing at the N+ layer 3 and the polysilicon 6. Figure 7 、 Figure 8 as shown in the figure.

[0077] In step S510, the isolation layer 7 is prepared by using the chemical vapor deposition, the external area of the N+ layer 3 and the polysilicon 6 is protected by using the mask through the photolithography process, and the S pole electrode 8 and the G pole electrode 9 are respectively prepared by windowing at the N+ layer 3 and the polysilicon 6 through the etching process.

[0078] In step S520, the S pole electrode 8 and the G pole electrode 9 are respectively prepared by using the stripping process or the etching process at the windowed N+ layer 3 and the polysilicon 6.

[0079] Correspondingly, the isolation layer 7 has a protective effect, the material is SiO2 or Si3N4, the thickness is set to 10-5000 nm, the windowing is performed by using the ICP dry etching, the windowing depth is greater than the sum of the thicknesses of the isolation layer 7 and the N+ layer 3, the S pole electrode 8 extends downward from the top surface of the isolation layer 7, and connects and forms an ohmic contact with the N+ layer 3, the P+ channel layer 2 and the N- withstand voltage layer 12, and the G pole electrode 9 extends downward from the top surface of the isolation layer 7, and connects and forms an ohmic contact with the polysilicon 6.

[0080] In this embodiment, Si3N4 is used as the isolation layer 7, the thickness is set to 200 nm, ICP dry etching is used for windowing, the windowing depth is 1.3 um, and the S-pole electrode 8 and the G-pole electrode 9 are prepared by using Al / Ti two-layer metal.

[0081] In step S600, the D-pole electrode 10 is prepared at the bottom of the epitaxial wafer, and the whole device is prepared. Figure 9

[0082] In step S610, the D-pole electrode 10 is prepared at the bottom of the epitaxial wafer 1 by thinning process and back plating process, and the whole device is prepared.

[0083] Correspondingly, the epitaxial wafer 1 is thinned by the thinning process, the D-pole electrode 10 is prepared by the back plating process, and the D-pole electrode 10 and the N+ substrate layer 11 are connected and form an ohmic contact.

[0084] In this embodiment, the 350 um thick epitaxial wafer 1 is thinned to 180 um by the thinning process, the D-pole electrode 10 is prepared by using Al / Ti two-layer metal, and the whole device is prepared.

[0085] A multi-channel trench MOSFET includes a D-pole electrode 10, an epitaxial wafer 1 and an isolation layer 7 arranged in sequence from bottom to top.

[0086] The epitaxial wafer 1 is provided with:

[0087] P+ channel layer 2, provided with several and spaced from each other, the top surface is lower than the top surface of the epitaxial wafer 1, and the bottom surface is higher than the bottom surface of the N-resistance layer 12, the P+ channel layer 2 completely depletes the N-resistance layer 12 in the spaced area along the horizontal direction;

[0088] N+ layer 3, extending downward from the top surface of the epitaxial wafer 1 and connected with the top surface of the P+ channel layer 2;

[0089] Trench 4, provided with several, respectively extending downward from the top surface of the N+ layer 3, passing through the P+ channel layer 2 and extending into the N-resistance layer 12; that is, the bottom surface is lower than the bottom surface of the P+ channel layer 2 and higher than the bottom surface of the N-resistance layer 12;

[0090] Gate dielectric 5, arranged on the inner side wall of the trench 4 and connected with the N+ layer 3, the P+ channel layer 2 and the N-resistance layer 12 respectively;

[0091] Poly 6, extending downward from the top of the trench 4 and filled in the gate dielectric 5; in contact with the gate dielectric 5, the upper surface is horizontal with the upper surface of the trench 4;

[0092] The isolation layer 7 is provided with:

[0093] ​The S electrode 8 extends downward from the top surface of the isolation layer 7 to the P+ channel layer 2 through the N+ layer 3, i.e., is connected with the N+ layer 3, the P+ channel layer 2 and the N- voltage-resisting layer 12 to form an ohmic contact;

[0094] The G electrode 9 extends downward from the top surface of the isolation layer 9 to the polysilicon 6, i.e., is connected with the polysilicon 6 to form an ohmic contact.

[0095] Further, the epitaxial wafer 1 comprises the N+ substrate layer 11 and the N- voltage-resisting layer 12 connected from bottom to top; the D electrode 10 is connected with the N+ substrate layer 11 to form an ohmic contact.

[0096] The present application has the following advantages:

[0097] The trench type MOSFET, the reduction of the trench width and the adoption of the shield gate structure are the most important measures for reducing the on-resistance per unit area at present, but with the continuous improvement of the process technology level, the trench width of the high-performance trench type MOSFET has been reduced to the sub-micron level, and the space for further reducing the trench width is limited, and the shield gate structure technology has been very mature after development for more than ten years, so it is necessary to adopt new structures and new technologies to continuously reduce the on-resistance per unit area of the trench type MOSFET. The present application forms a structure of P+ channel region, N- voltage-resisting region and P+ channel region in the trench spacing area under the condition of not increasing additional process steps, by controlling the width and doping concentration of the P+ channel region, N- voltage-resisting region and P+ channel region in the structure, the device gate is not applied with voltage, the N- voltage-resisting region is completely depleted by the P+ channel regions on both sides, and is in a blocking state, the device gate is applied with positive voltage, the N- voltage-resisting region changes from the completely depleted state to the normal conduction state, forming an additional conduction channel in addition to the inversion layer conduction channel below the gate oxide, thereby reducing the on-resistance per unit area of the trench type MOSFET. Compared with the conventional structure of the trench type MOSFET, under the same process conditions, the on-resistance of the multi-channel trench type MOSFET prepared by the present application is reduced by 10%-20%.

[0098] For the content disclosed in the present case, the following points need to be explained:

[0099] (1) The embodiment disclosed in the present case only relates to the structure involved in the embodiment disclosed in the present case, and other structures can be referred to the general design;

[0100] (2) In the case of no conflict, the embodiments disclosed in the present case and the features in the embodiments can be combined to obtain new embodiments;

[0101] The above is only a specific embodiment disclosed in the present case, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for fabricating a multi-channel trench MOSFET, characterized in that, Includes the following steps: Step S100, the epitaxial wafer (1) includes an N+ substrate layer (11) and an N- withstand voltage layer (12) stacked sequentially from bottom to top, and a plurality of P+ channel layers (2) spaced horizontally are formed in the N- withstand voltage layer (12), and the N- withstand voltage layer (12) in the spaced region of the P+ channel layer (2) is completely depleted; Step S200: An N+ layer (3) is prepared by extending downward from the top surface of the N-pressure-resistant layer (12) between the P+ channel layer (2) and the P+ channel layer (2), wherein the bottom surface of the N+ layer (3) is higher than the bottom surface of the P+ channel layer (2); Step S300: A plurality of trenches (4) are prepared in the epitaxial wafer (1) through the P+ channel layer (2), wherein the bottom surface of the trenches (4) is lower than the bottom surface of the P+ channel layer (2) and higher than the bottom surface of the N-pressure resistant layer (12); Step S400: Gate dielectric (5) and polysilicon (6) are sequentially prepared in the trench (4). Step S500: Deposit an isolation layer (7) on the epitaxial wafer (1), and open windows at the N- withstand layer (12) between two adjacent N+ layers (3) and at the polysilicon (6) to prepare the S electrode (8) and G electrode (9) respectively. Step S600: D electrode (10) is prepared on the bottom of the epitaxial wafer, and the entire device is prepared.

2. The method for fabricating a multi-channel trench MOSFET according to claim 1, characterized in that, Step S100 includes: Step S110: Using photolithography, a mask is used to protect the external region of the P+ channel layer (2); and spaced P+ channel layers (2) are formed by diffusion or ion implantation. The P+ channel layer (2) in the interval completely depletes the N-pressure-resistant layer (12) in the interval region in the horizontal direction.

3. The method for fabricating a multi-channel trench MOSFET according to claim 1, characterized in that, Step S200 includes: Step S210: Using photolithography, a mask is used to protect the outer region of the N+ layer (3); the N+ layer (3) is formed by diffusion or ion implantation.

4. The method for fabricating a multi-channel trench MOSFET according to claim 1, characterized in that, Step S300 includes: Step S310: Using photolithography, a mask is used to protect the outer area of ​​the trench (4); the trench (4) is formed by etching. The trench (4) extends downward from the top surface of the epitaxial wafer (1), with its bottom surface lower than the bottom surface of the P+ channel layer (2) and higher than the bottom surface of the N- pressure-resistant layer (12), and its width ranges from 1 to 10 μm.

5. The method for fabricating a multi-channel trench MOSFET according to claim 1, characterized in that, Step S400 includes: Step S410: Using photolithography, a mask is used to protect the outer area of ​​the trench (4), and a gate dielectric (5) is prepared in the trench (4) using thermal oxidation technology. In step S420, polycrystalline silicon (6) is prepared in the trench (4) by chemical vapor deposition.

6. The method for fabricating a multi-channel trench MOSFET according to claim 1, characterized in that, Step S500 includes: Step S510: Prepare an isolation layer (7) by chemical vapor deposition, protect the outer area of ​​the N+ layer (3) and polysilicon (6) by photolithography using a mask, and open windows at the N+ layer (3) and polysilicon (6) by etching. In step S520, the corresponding S electrode (8) and G electrode (9) are prepared at the openings in the N+ layer (3) and polysilicon (6) by a stripping process or an etching process.

7. The method for fabricating a multi-channel trench MOSFET according to claim 1, characterized in that, Step S600 includes: In step S610, the D electrode (10) is prepared on the bottom of the epitaxial wafer (1) by thinning and back gold processing, and the entire device is prepared.

8. A multi-channel trench MOSFET, fabricated by the method for fabricating a multi-channel trench MOSFET according to claim 1, characterized in that, It includes a D electrode (10), an epitaxial wafer (1), and an isolation layer (7) arranged sequentially from bottom to top. The epitaxial wafer (1) contains: The P+ channel layer (2) is provided in several layers and is spaced apart from each other. Its top surface is lower than the top surface of the epitaxial wafer (1) and its bottom surface is higher than the bottom surface of the N-pressure resistant layer (12). The spaced P+ channel layers (2) completely deplete the N-pressure resistant layer (12) in the spaced area in the horizontal direction. The N+ layer (3) extends downward from the top surface of the epitaxial wafer (1) and is connected to the top surface of the P+ channel layer (2); The trench (4) is provided in several ways, which extend downward from the top surface of the N+ layer (3), pass through the P+ channel layer (2), and extend into the N- pressure-resistant layer (12); The gate dielectric (5) is disposed on the inner sidewall of the trench (4) and is connected to the N+ layer (3), the P+ channel layer (2) and the N- pressure-resistant layer (12) respectively; Polycrystalline silicon (6) extends downward from the top of the trench (4) and fills the gate dielectric (5); The isolation layer (7) contains: The S electrode (8) extends downward from the top surface of the isolation layer (7), through the N+ layer (3), into the P+ channel layer (2); The G electrode (9) extends downward from the top surface of the isolation layer (7) into the polysilicon (6) and forms an ohmic contact with the polysilicon (6).

9. A multi-channel trench MOSFET according to claim 8, characterized in that, The epitaxial wafer (1) includes an N+ substrate layer (11) and an N- withstand layer (12) connected from bottom to top.

10. A multi-channel trench MOSFET according to claim 8, characterized in that, The S electrode (8) is connected to the N+ layer (3), the P+ channel layer (2) and the N- withstand layer (12) to form an ohmic contact.

Images