Manufacturing method for improving anti-single event burnout of trench MOSFET

Abstract

The application discloses a manufacturing method for improving the anti-single-particle burnout of a trench type MOSFET, and belongs to the technical field of semiconductor power devices. On the basis of a trench type MOSFET process, the anti-radiation performance of a device product is improved through process optimization, so that the device product is adapted to the space environment of ionizing radiation in space, and the high reliability index of the device product is improved. The process features of the application are as follows: the well region is implanted before trench etching, so as to avoid affecting the gate oxide process; deep hole implantation is realized by using TC photoetching, so as to improve the ability of the body region to extract holes under heavy ion radiation; local oxidation thickening is performed at the bottom of the gate trench, so as to increase the ability of the device to resist single-particle gate penetration; and a low-temperature wet oxygen process is adopted for the gate oxidation process, so as to improve the total dose resistance of the device. Through modification of process steps and process conditions, the application realizes deep hole implantation to increase the anti-single-particle burnout ability, meets the anti-radiation performance index of the MOSFET device, and meets the environmental requirements in the field of spaceflight.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor power devices, in particular to a manufacturing method for improving the anti-single-particle burnout of a trench MOSFET. BACKGROUND

[0002] The trench MOSFET is a new type of discrete power MOSFET power device, and compared with the performance of bipolar power devices, has the advantages of low conduction loss, high working frequency, voltage control type device, simple control circuit and the like, and is more and more valued by the industry. Compared with the planar MOSFET, the trench MOSFET can realize smaller cell size and higher current density, improve the current capacity and switching performance of the device, and has more obvious advantages in the field of medium and low voltage power MOSFET.

[0003] With the exploration of human beings in the field of space, electronic components not only need excellent electrical performance, but also need to cope with the harsh environment in space, such as gamma rays, solar wind, etc. In the space ionizing radiation environment, the irradiation effects of the device mainly include total dose irradiation effect, single-particle burnout and single-particle gate penetration, so the device needs to be designed for radiation hardening. SUMMARY

[0004] The purpose of the present application is to provide a manufacturing method for improving the anti-single-particle burnout of a trench MOSFET to solve the problems in the background art.

[0005] To solve the above technical problems, the present application provides a manufacturing method for improving the anti-single-particle burnout of a trench MOSFET, comprising:

[0006] Growth of a first silicon oxide layer on a silicon epitaxial wafer, P-well is realized by ion implantation, and high temperature push joint is performed on the P-well; then a first silicon nitride layer is deposited;

[0007] Dig out the trench structure on the wafer, and perform silicon dioxide filling and grinding on the trench structure;

[0008] Etch to the silicon epitaxial wafer at the position on the wafer which needs to be used as a gate trench to form a gate trench;

[0009] Depositing a layer of silicon oxide and silicon nitride in the gate trench, etching off the silicon nitride on the surface of the wafer and the bottom of the gate trench, growing silicon oxide at the bottom of the gate trench to realize local thickening of the bottom;

[0010] Removing the silicon nitride layer of the side wall of the gate trench, controlling the wet etching time of the oxide layer, and only retaining the thickened silicon oxide layer at the bottom of the gate trench;

[0011] The gate oxide is grown by low-temperature wet oxygen process, the in-situ polycrystal is deposited in the gate trench, and the polycrystal on the silicon surface is etched away by a gate polycrystal etching process;

[0012] The source injection is realized and activated by N+ photolithography and ion implantation, a medium layer is deposited on the surface and is subjected to planarization treatment;

[0013] The first medium hole etching and silicon hole etching are performed by hole photolithography, P-type high-concentration impurities are implanted into the silicon surface at the bottom of the hole by hole implantation, P-type medium-concentration doped impurities are implanted into the deep body region, and the body region is led out by heat activation in the form of rapid annealing;

[0014] The contact hole metal lead-out is realized by tungsten filling and grinding, the metal interconnection is realized by metal deposition, photolithography and etching, and the overall device is completed.

[0015] In an embodiment, the trench structure has an inclination angle, includes a strip-shaped gate structure and a pin-shaped gate structure, and has a depth ranging from 0.5 to 1 µm.

[0016] In an embodiment, the first silicon nitride layer has a thickness ranging from 1000 Å to 2000 Å.

[0017] In an embodiment, the ion implantation of the P well is B element, the implantation energy is 50-120 Kev, and the dose is 1E13-5E13 / cm 2 .

[0018] In an embodiment, the gate trench has a depth ranging from 1 to 2 µm.

[0019] In an embodiment, when the silicon oxide is grown at the bottom of the gate trench to locally thicken the bottom, a part of the silicon oxide layer is formed on the sidewall of the gate trench, and the silicon oxide layer on the sidewall of the gate trench is removed by a phosphoric acid process.

[0020] In an embodiment, in the process of realizing the source injection and activation, the implantation element is As / P, the implantation energy is 60-100 Kev, and the implantation dose is 5E15-1E16 / cm 2 .

[0021] The application provides a manufacturing method for improving the anti-single-particle burnout of a trench type MOSFET, wherein the well region injection and the push joint process are advanced to avoid affecting the gate oxide process; the first photoetching and etching are used to define the gate trench and the hole contact area, and realize the self-alignment of the two positions; the first trench etching is used to finally realize the deep hole process, and improve the extraction capacity of holes under the heavy ion radiation; the gate trench bottom oxidation is thickened according to the requirement of anti-single-particle gate penetration; and the low-temperature wet oxygen process is used in the process according to the requirement of the anti-total dose of the gate oxide itself. The process steps and the process flow are optimized, the process difficulty and the manufacturing cost are increased within a limited range, and the product with the improved anti-single-particle burnout capacity of the trench type MOSFET can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a P well injection and push joint schematic diagram;

[0023] Figure 2 is a TC photoetching and etching structure schematic diagram;

[0024] Figure 3 is a surface mechanical grinding structure schematic diagram;

[0025] Figure 4 is a GT photoetching and etching structure schematic diagram;

[0026] Figure 5 is a trench bottom thickening process structure schematic diagram;

[0027] Figure 6 is a gate oxide growth and gate polycrystal etching schematic diagram;

[0028] Figure 7 is an N+ injection and activation schematic diagram;

[0029] Figure 8 is a dielectric deposition and surface planarization schematic diagram;

[0030] Figure 9 is a hole etching and hole injection activation structure schematic diagram;

[0031] Figure 10 is a metal photoetching and etching completed device interconnection schematic diagram. DETAILED DESCRIPTION

[0032] The application provides a manufacturing method for improving the anti-single-particle burnout of a trench type MOSFET, wherein the well region injection and the push joint process are advanced to avoid affecting the gate oxide process; the first photoetching and etching are used to define the gate trench and the hole contact area, and realize the self-alignment of the two positions; the first trench etching is used to finally realize the deep hole process, and improve the extraction capacity of holes under the heavy ion radiation; the gate trench bottom oxidation is thickened according to the requirement of anti-single-particle gate penetration; and the low-temperature wet oxygen process is used in the process according to the requirement of the anti-total dose of the gate oxide itself. The process steps and the process flow are optimized, the process difficulty and the manufacturing cost are increased within a limited range, and the product with the improved anti-single-particle burnout capacity of the trench type MOSFET can be realized.

[0033] The anti-radiation trench MOSFET device is a three-terminal discrete device, and the front surface of the wafer is divided into a source area and a gate area, which are isolated from the outside by a trench method or field oxidation. The drain area of the device is on the back surface of the wafer. The process method of the present application is mainly for the wafer source; the gate is led out to the edge of the die through the polycrystalline in the trench, and then connected through the contact hole and the metal interconnection on it; the drain only needs to be thinned on the back surface and plated with metal to be led out, which is understood by those skilled in the art, so the present application will not be described. The present application mainly proposes a process processing technology for the cell area, and a trench isolation ring is used to realize the junction termination in the whole die peripheral area.

[0034] The present application provides a manufacturing method for anti-single-particle burnout of a trench MOSFET, which realizes the performance of reducing on-state resistance and the performance of anti-radiation performance reinforcement, effectively improves the quality of anti-single-particle burnout of the trench MOSFET through improvement of part of the design and process.

[0035] The anti-radiation trench MOSFET process is completed through the following method:

[0036] Taking an N-type device as an example, a P-type device can be obtained by the corresponding method. First, a first silicon oxide layer 2 is grown on a silicon epitaxial wafer 1, wherein the thickness of the first silicon oxide layer 2 is 200Å~500Å; a P-well (PW) implantation is realized through an ion implantation process, wherein B elements are implanted, the energy is 50~120Kev, and the dose is 1E13~5E13 / cm 2 ; a high-temperature push junction process is performed on the P-type well implantation; a first silicon nitride layer 3 is formed by chemical vapor deposition to form an epitaxial silicon-silicon oxide-silicon nitride three-layer thin film structure, and the thickness of the first silicon nitride layer 3 is 1000Å~2000Å, as shown in Figure 1 .

[0037] A trench structure with a certain inclination angle and a certain depth is dug out on the wafer through a TC trench photoetching and etching process, and the depth of the trench structure is 0.5~1µm, as shown in Figure 2 .

[0038] After the first trench process is completed, the trench structure is filled with silicon dioxide 4 by using a high-density plasma chemical vapor deposition method, and then the surface silicon dioxide layer is removed by chemical mechanical grinding, as shown in Figure 3 .

[0039] GT trench lithography and etching process is used to etch into the silicon epitaxial wafer 1 at the place where the gate trench is needed, to form a gate trench 5 (longitudinal channel region) with a certain depth and morphology, the total depth is in the range of 1-2 pm, as shown in Figure 4 ; wherein the GT trench is: etching off the oxide layer in the shallow trench first, and then further etching off the silicon to deepen the trench and form the gate trench.

[0040] After the gate trench etching is completed, the GT photoresist is removed, and a layer of silicon oxide and silicon nitride is deposited in the gate trench 5. Using dry etching anisotropy, the silicon nitride layer on the surface of the wafer and the bottom of the gate trench 5 is etched off, and the sidewall of the gate trench 5 still retains the silicon nitride. Then, through a thermal oxidation process, a silicon oxide layer is grown at the bottom of the gate trench to achieve local thickening of the bottom, and the trench type single particle gate penetration resistance is improved. At this time, the sidewall of the gate trench also forms a part of the silicon oxide layer. Using phosphoric acid and hydrofluoric acid process, the silicon nitride layer and the thin silicon oxide layer on the sidewall of the gate trench 5 are removed, and the wet etching time of the oxide layer is controlled, as shown in Figure 5 , only the thickened silicon oxide layer at the bottom of the gate trench 5 is retained.

[0041] The gate oxide is grown by using a low-temperature wet oxygen process. Considering the requirement of radiation resistance, the gate oxide layer is generally grown by using a low-temperature wet oxygen process, with a thickness of 300-800 Å and a growth temperature of 700-1000 °C. This step forms a silicon oxide layer on the sidewall of the gate trench 5; in-situ polycrystalline 6 is deposited in the gate trench 5 by chemical vapor deposition. The polycrystalline on the silicon surface is etched off by a gate polycrystalline etching process, as shown in Figure 6 .

[0042] The source electrode is implanted and activated by N+ lithography and ion implantation, and the source contact area of the cell region is realized. The implanted element is As / P, the implantation energy is 60-100 Kev, and the implantation dose is 5E15-1E16 per / cm 2 , as shown in Figure 7 .

[0043] The front-end device process has been completed, and then a dielectric layer 7 is deposited on the surface by chemical vapor deposition and planarization treatment, as shown in Figure 8 .

[0044] Using hole lithography, the first step of dielectric hole etching and silicon hole etching is performed. P-type high-concentration impurities are implanted into the silicon surface at the bottom of the hole by hole implantation, and P-type medium-concentration doping is implanted into the deep body region. Finally, the body region is formed by rapid annealing, as shown in Figure 9As shown in the figure. Since the shallow trench is etched out by the first TC silicon corrosion, the self-alignment of the shallow trench and the deep trench etched twice is ensured, and the control precision is improved; when the hole injection is performed, a deeper ion injection depth can be achieved, thereby improving the hole extraction capability under heavy ion radiation; secondly, the silicon groove is defined by the lithography plate, and is located at the center position of the left and right gate trenches, and the extraction effect is best.

[0045] The contact hole metal is led out by filling and grinding of tungsten 8. The metal interconnection is realized by metal 9 deposition, lithography and etching, and the overall device such as Figure 10 is completed.

[0046] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any modification or modification made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A manufacturing method of improving single event burnout resistance of a trench MOSFET, characterized by, The application relates to a method for manufacturing a silicon-on-insulator (SOI) transistor, and belongs to the field of semiconductor manufacturing. A first silicon oxide layer is grown on a silicon epitaxial wafer, a P well is formed by ion implantation, and the P well is subjected to high-temperature annealing; A first silicon nitride layer is deposited; A trench structure is formed on the wafer, and the trench structure is filled with silicon dioxide and polished; A GT trench is etched into the silicon epitaxial wafer at a position required as a gate trench on the wafer by using a GT trench photolithography and etching process, so that the gate trench is formed; wherein the GT trench is: the oxide layer in the shallow trench is etched first, and then the silicon is etched further to deepen the trench and form the gate trench; A layer of silicon oxide and silicon nitride is deposited in the gate trench, the silicon nitride on the wafer surface and the bottom of the gate trench is etched, the silicon oxide is grown at the bottom of the gate trench, and local thickening of the bottom is realized; The silicon nitride layer on the side wall of the gate trench is removed, and the wet etching time of the oxide layer is controlled to only keep the thickened silicon oxide layer at the bottom of the gate trench; Gate oxide is grown by using a low-temperature wet oxygen process, in-situ polysilicon is deposited in the gate trench, and the polysilicon on the wafer surface is etched by using a gate polysilicon etching process; Source implantation and activation are realized by using N+ photolithography and ion implantation, a dielectric layer is deposited on the wafer surface and is subjected to planarization treatment; A first dielectric hole etching and a silicon hole etching are performed by using hole photolithography, P-type high-concentration impurities are implanted into the silicon surface at the bottom of the hole by using hole implantation, P-type medium-concentration impurities are implanted into a deep body region, and the body region is led out by forming a body region through rapid annealing and heat activation. Contact hole metal leading-out is realized by using tungsten filling and polishing, and metal interconnection is realized by metal deposition, photolithography and etching, so that the whole device is completed.

2. The manufacturing method of a trench-MOSFET against single event burnout according to claim 1, wherein The trench structure has an inclination angle and a depth ranging from 0.5 to 1 mu m.

3. The manufacturing method of a trench-MOSFET against single event burnout according to claim 1, wherein The thickness of the first silicon nitride layer ranges from 1000 angstroms to 2000 angstroms.

4. The fabrication method of a trench-type MOSFET against single event burnout according to claim 1, wherein The ion implantation of the P well is B element, the implantation energy is 50-120 Kev, and the dose is 1E13-5E13 per / cm 2 .

5. The fabrication method of a trench-type MOSFET against single event burnout according to claim 1, wherein The depth of the gate trench ranges from 1 to 2 mu m.

6. The fabrication method of a trench-type MOSFET against single event burn-out according to claim 1, wherein When the silicon oxide is grown at the bottom of the gate trench to locally thicken the bottom, the silicon nitride on the side wall of the gate trench is protected, only the bottom is thickened, the silicon oxide layer at the bottom of the trench is formed, and then the silicon nitride layer and the thin silicon oxide layer on the side wall of the gate trench are removed by using a phosphoric acid and hydrofluoric acid process, and most of the bottom oxide layer is kept.

7. The fabrication method of a trench-type MOSFET against single event burn-out according to claim 1, wherein In the process of realizing source injection and activation, the injection element is As / P, the injection energy is 60-100 Kev, and the injection dose is 5E15-1E16 / cm 2 .

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