Shield gate groove type MOSFET four-terminal device and preparation method thereof

Abstract

The invention discloses a shield gate groove type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) four-terminal device and a preparation method thereof. The shield gate trench type MOSFET four-terminal device comprises a substrate and an epitaxial layer, a trench is arranged in the epitaxial layer, gates are arranged in the trench in a segmented manner, the gates arranged in the segmented manner comprise a first shield gate, a second shield gate and a control gate, the first shield gate is connected with an independent bias power supply to form a fourth terminal, oxide layers are arranged among the gates arranged in the segmented manner, and the second shield gate is connected with the control gate. A P-type heavily-doped region is arranged on the top of the epitaxial layer, an N-type heavily-doped region is arranged on the P-type heavily-doped region, an interlayer dielectric layer is arranged on the N-type heavily-doped region and the control gate, contact holes are formed among the interlayer dielectric layer, the P-type heavily-doped region and the N-type heavily-doped region, the contact holes are fixedly connected with source metal, and the control gate is connected with the P-type heavily-doped region and the N-type heavily-doped region. And drain electrode metal is arranged on the back surface of the substrate. According to the invention, the specific on-resistance of the MOSFET device can be reduced, so that the on-loss of the MOSFET device is reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power MOSFET devices, and particularly relates to a shielded gate trench MOSFET four-terminal device and a preparation method thereof. BACKGROUND

[0002] The shielded gate trench MOSFET (SGT MOSFET) can improve the breakdown voltage (BV) and specific on-resistance (Ron,sp) of the MOSFET device by introducing a shielded gate structure. The specific on-resistance can reflect the power loss capability of the device. For a given breakdown voltage, the SGT MOSFET with lower specific on-resistance has always been the focus of research. The drift region of the SGT MOSFET device is the region that is most affected by the voltage withstand capability and on-resistance. By reasonably designing the shielded gate structure, the electric field of the drift region can be flattened, and the breakdown voltage of the device can be effectively improved and the specific on-resistance can be reduced.

[0003] At present, the SGT MOSFET generally has only three electrodes, namely a source electrode, a drain electrode and a gate electrode, and is usually referred to as a three-terminal device. The methods for improving the breakdown voltage and reducing the specific on-resistance of the MOSFET device mainly include: using high-K dielectric material as the dielectric layer of the trench, setting floating gates on both sides of the shielded gate, setting a multi-section floating shielded gate and a T-shaped shielded gate.

[0004] A Chinese invention patent application with the publication number CN116093146A discloses a segmented separated gate SGT MOSFET structure. By setting one or two columns of segmented separated gates, the device can reduce the output capacitance Coss and the input capacitance Ciss simultaneously under the premise of ensuring the same voltage withstand capability and specific on-resistance. However, due to the segmented floating gate potential, the electric field improvement effect on the drift region is not good, and the breakdown voltage of the device cannot be effectively improved and the specific on-resistance cannot be reduced.

[0005] A Chinese invention patent application with the publication number CN116565002A discloses a high-gate-lock-threshold split-gate power MOSFET structure and manufacturing method. By setting the shielded gate into a T-shaped structure, the on-resistance can be further reduced under the condition of obtaining the same reverse voltage. However, this structure is mainly used to improve the anti-gate-lock capability of the device, and the optimization effect on the electric field distribution in the middle part of the drift region is limited. The electric field flattening design of the drift region cannot be achieved, and the breakdown voltage of the device cannot be effectively improved and the specific on-resistance cannot be significantly reduced.

[0006] At present, power devices also need to continue to reduce the on-state loss to meet the green energy-saving requirements. This requires the power device to reduce the on-state resistance as much as possible while meeting the withstand voltage, so as to reduce the on-state loss. SUMMARY

[0007] The present application aims to provide a shielded gate trench MOSFET four-terminal device and a preparation method thereof. On the basis of the existing SGT MOSFET device structure, a shielded gate structure controlled by an independent electrode is designed. The charge coupling effect between the shielded gate biased by an independent power supply and another segment of the wide shielded gate realizes the regulation of the electric field in the drift region. Because an independent power supply bias is introduced, the shielded gate trench MOSFET device of the present application has four electrodes, so it is called a four-terminal device. The present application can realize the flattening of the electric field distribution in the device drift region to a great extent, so that the MOSFET device can realize a significant reduction in the specific on-state resistance under the same withstand voltage, thereby reducing the on-state loss of the MOSFET device.

[0008] In a first aspect, the present application provides a shielded gate trench MOSFET four-terminal device, comprising: a substrate 1, an epitaxial layer 2 located on the substrate 1, a trench 3 provided in the epitaxial layer, and a segmented gate provided in the trench 3, wherein the segmented gate comprises a first shielded gate 5, a second shielded gate 8, and a control gate 11, the first shielded gate 5 is connected to an independent bias power supply, an oxide layer is provided between each of the segmented gates, a P-type heavily doped region 12 is provided on the top of the epitaxial layer, an N-type heavily doped region 13 is provided on the P-type heavily doped region 12, an interlayer dielectric layer 14 is provided on the N-type heavily doped region 13 and the control gate 11, a source metal 16 penetrates through the interlayer dielectric layer 14 and the P-type heavily doped region 11 via a contact hole 15, the bottom of the source metal 16 is provided on the N-type heavily doped region 13, and a drain metal 17 is provided on the back of the substrate.

[0009] Further, the potential of the independent bias power supply is a positive potential relative to the source, and the potential is less than the drain potential.

[0010] Further, the segmented gate is specifically provided at the following positions: the first shielded gate 5 is provided at a position close to the bottom of the trench, the second shielded gate 8 is provided at the middle of the trench, and the control gate 11 is provided at the top of the trench.

[0011] Further, an oxide layer is provided between each of the segmented gates, and specifically, a second oxide layer 6 and a third oxide layer 7 are sequentially provided between the first shielded gate 5 and the second shielded gate 8, and a fourth oxide layer 9 and a fifth oxide layer 10 are sequentially provided between the second shielded gate 8 and the control gate 11.

[0012] Further, the depth of the first shielded gate 5 is 2.3-2.5 μm.

[0013] Furthermore, a first oxide layer 4 is provided on the surface of the trench 3.

[0014] Furthermore, the width of the second shielding gate 8 is 1-1.2 μm.

[0015] Secondly, the present invention provides a method for fabricating a shielded gate trench MOSFET four-terminal device, comprising:

[0016] An epitaxial layer is formed on the substrate, and trenches are etched in the epitaxial layer;

[0017] Thermal growth and chemical vapor deposition are performed on the inner surface of the trench to form the first oxide layer;

[0018] Near the bottom of the trench, polysilicon is deposited by chemical vapor deposition and then etched to form the first shielding gate.

[0019] A second oxide layer is formed between the first oxide layer and the first shielding gate by chemical vapor deposition and etching;

[0020] The first oxide layer and the second oxide layer are etched, the third oxide layer is thermally grown above the second oxide layer, conductive polysilicon is deposited on the third oxide layer, and the second shielding gate is formed by etching back.

[0021] A fourth oxide layer is formed by depositing polysilicon on the second shielding gate, and the third oxide layer and the fourth oxide layer are etched to the top of the second shielding gate.

[0022] A fifth oxide layer is formed by thermal growth of the fourth oxide layer, and a control gate is formed by depositing conductive polysilicon on the fifth oxide layer.

[0023] The active region is defined by photoresist, boron ion implantation is performed to form a P-type heavily doped region, and after high-temperature annealing, arsenic ion implantation is performed again to form an N-type doped region.

[0024] An interlayer dielectric layer is deposited on top of the N-type heavily doped region and trench;

[0025] The contact hole area is defined by photoresist, and the interlayer dielectric layer, N-type heavily doped region and P-type heavily doped region are etched to form the contact hole.

[0026] Boron fluoride (BF2) is injected into the bottom of the contact hole and metal is deposited to form an ohmic contact and source electrode. Metal is deposited on the back side of the substrate to form a drain electrode.

[0027] Beneficial effects of the present invention: The shielded gate trench MOSFET four-terminal device proposed in this invention is an optimized design of the shielded gate of the traditional SGTMOSFET.

[0028] First, the shielding gate of a traditional SGT MOSFET is designed in segments as a first shielding gate 5 and a second shielding gate 8. The second shielding gate 8, like the traditional shielding gate, is connected to the source potential; the first shielding gate 5 is externally biased by an independent power supply, requiring an independent bias power supply electrode pad to be led out on the chip surface. Then, the second shielding gate 8 is wider than the first shielding gate 5, ranging from 1-1.2 μm. During reverse breakdown, the electric field of the second shielding gate 8 can be superimposed with that of the first shielding gate 5, modulating the electric field in the drift region. Because the second shielding gate 8 is wider, it is closer to the drift region, increasing the charge coupling strength and thus improving the electric field strength in the middle of the drift region. During forward conduction, the second shielding gate 8 can reduce the gate-drain facing area, thereby suppressing parasitic capacitance Coss and improving frequency response.

[0029] Secondly, the independent power supply biased by the first shielding gate 5 is positive relative to the source, and its potential is lower than that of the drain. In reverse blocking mode, because the first shielding gate 5 is connected to a positive potential relative to the source, the voltage drop at the bottom of the trench decreases accordingly, reducing the peak electric field at the bottom of the trench and raising the electric field in the middle of the drift region and near the PN junction. This achieves the goal of flattening the electric field in the drift region and improving the device's breakdown voltage. In forward conduction mode, the potential of the first shielding gate 5 can be adjusted by applying an external independent bias power supply to generate a transverse electric field pointing from the first shielding gate 5 to the drift region, thereby widening the conduction current path and reducing the on-resistance. Under different voltage conditions, appropriately adjusting the potential of the bias power supply can keep the device's losses in an optimal state.

[0030] Furthermore, since the first shielding gate 5 can regulate the electric field strength of the drift region to improve the breakdown voltage of the device, the light doping concentration of the epitaxial layer 2 can be adjusted within a certain range according to the design requirements when designing the unit cell structure, so that the designed unit cell structure can meet the breakdown voltage requirements while having a lower on-resistance. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the structure of the shielded gate trench MOSFET four-terminal device according to Embodiment 1 of the present invention;

[0032] Figure 2 This is a schematic diagram of the structure of the epitaxial layer formed on the substrate in Embodiment 2 of the present invention;

[0033] Figure 3 This is a schematic diagram of the structure in Embodiment 2 of the present invention where a trench is formed in the epitaxial layer;

[0034] Figure 4 This is a schematic diagram of the structure in Embodiment 2 of the present invention showing the formation of the first oxide layer in the trench;

[0035] Figure 5 This is a schematic diagram of the structure in Embodiment 2 of the present invention, in which polysilicon is deposited near the bottom of the trench to form a first shielding gate;

[0036] Figure 6 This is a schematic diagram of the structure in Embodiment 2 of the present invention in which a second oxide layer is deposited on the first shielding gate;

[0037] Figure 7 This is a schematic diagram of the structure after etching the first oxide layer and the second oxide layer in Embodiment 2 of the present invention;

[0038] Figure 8 This is a schematic diagram of the structure of the thermally grown third oxide layer in Embodiment 2 of the present invention;

[0039] Figure 9 This is a schematic diagram of the structure in Embodiment 2 of the present invention, in which polysilicon is deposited on the third oxide layer to form a second shielding gate;

[0040] Figure 10 This is a schematic diagram of the structure in Embodiment 2 of the present invention, showing the deposition and etching of a fourth oxide layer on the second shielding gate;

[0041] Figure 11 This is a schematic diagram of the structure in Embodiment 2 of the present invention, in which a fifth oxide layer is formed by thermal growth on the fourth oxide layer;

[0042] Figure 12 This is a schematic diagram of the structure in Embodiment 2 of the present invention in which polysilicon is deposited on the fifth oxide layer to form a control gate;

[0043] Figure 13 This is a schematic diagram of the structure formed after ion implantation in the active region in Embodiment 2 of the present invention, showing the formation of P-type doped and N-type doped regions.

[0044] Figure 14 This is a schematic diagram of the structure of the interlayer dielectric layer formed by depositing USG and BPSG in Embodiment 2 of the present invention;

[0045] Figure 15 This is a schematic diagram of the structure of etching contact holes and forming ohmic contacts by ion implantation in Embodiment 2 of the present invention, and depositing source metal to form source electrodes;

[0046] Figure 16 This is a schematic diagram of the structure in Embodiment 2 of the present invention in which a drain electrode is formed on the back side of the substrate;

[0047] Figure 17 This is a schematic diagram of the layout of Embodiment 1 of the present invention;

[0048] Figure 18 This is a schematic diagram of the shielded gate charge coupling principle in Embodiment 1 of the present invention;

[0049] Figure 19This is a comparison diagram of the current distribution of a conventional SGT MOSFET and the current distribution of the embodiment of the present invention when the device is forward-biased during simulation verification.

[0050] Figure 20 This is a comparison of the electric field distribution curves of Embodiment 1 of the present invention and a traditional shielded gate trench MOSFET device during simulation verification;

[0051] In the attached figures, 1 is the substrate, 2 is the epitaxial layer, 3 is the trench, 4 is the first oxide layer, 5 is the first shielding gate, 6 is the second oxide layer, 7 is the third oxide layer, 8 is the second shielding gate, 9 is the fourth oxide layer, 10 is the fifth oxide layer, 11 is the control gate, 12 is the P-type heavily doped region, 13 is the N-type heavily doped region, 14 is the interlayer dielectric layer, 15 is the contact hole, 16 is the source metal, and 17 is the drain metal. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] Embodiment 1 of the present invention provides a shielded gate trench type MOSFET four-terminal device.

[0054] like Figure 1As shown, a shielded gate trench MOSFET four-terminal device includes: a substrate 1, an epitaxial layer 2 on the substrate 1, a trench 3 formed in the epitaxial layer 2, a first oxide layer 4 on the surface of the trench 3, and gates segmented within the trench 3. The segmented gates include a first shielding gate 5, a second shielding gate 8, and a control gate 11. The first shielding gate 5 is connected to an independent bias power supply. The first shielding gate 5 is located near the bottom of the trench 3, the second shielding gate 8 is located in the middle of the trench 3, and the control gate 11 is located at the top of the trench 3. Oxide layers are provided between each segmented gate, and a second oxide layer 6 is sequentially disposed between the first shielding gate 5 and the second shielding gate 8. A third oxide layer 7 and a fourth oxide layer 9 and a fifth oxide layer 10 are sequentially disposed between the second shielding gate 8 and the control gate 11. A P-type heavily doped region 12 is provided on the top of the epitaxial layer 2, and an N-type heavily doped region 13 is provided on the P-type heavily doped region 12. An interlayer dielectric layer 14 is disposed above the N-type heavily doped region 13 and the trench 3. A contact hole 15 is provided between the interlayer dielectric layer 14, the P-type heavily doped region 12 and the N-type heavily doped region 13. The contact hole 15 penetrates the interlayer dielectric layer 14 and the P-type heavily doped region, and its bottom is on the N-type heavily doped region 13. The contact hole 15 is fixedly connected to the source metal 16. A drain metal 17 is disposed on the back side of the substrate 1.

[0055] Specifically, refer to Figure 1 As shown, the substrate 1 is made of, but is not limited to, a silicon substrate doped with impurities such as arsenic, red phosphorus, or antimony. The epitaxial layer 2 is a lightly doped epitaxial layer of the first conductivity type, and its material includes, but is not limited to, silicon. The trench 3 is located inside the epitaxial layer 2. The first oxide layer 4 is a field oxide layer formed by thermal growth and is grown on the surface of the trench.

[0056] Specifically, the thickness of the first oxide layer 4 is 0.5-0.6 μm. The trench oxide layer thickness within this range can ensure good isolation characteristics, and will not break down even under high electric field conditions. It also ensures charge coupling capability during forward conduction, giving the device a low on-resistance.

[0057] Specifically, refer to Figure 1 As shown, the first shielding gate 5 is located near the bottom of the trench 3 and within the first oxide layer 4.

[0058] Preferably, the depth of the first shielding gate 5 is 2.3-2.5 μm. The depth range of the first shielding gate 5 is related to the distance from the top of the first shielding gate 5 to the bottom of the control gate 11. Experimental simulations have verified that the depth of the first shielding gate 5 must be 1.54 to 1.67 times the distance from the top of the first shielding gate 5 to the bottom of the control gate 11 to maximize the electric field enhancement in the middle of the drift region, thereby achieving the optimal electric field distribution in the drift region.

[0059] Specifically, a second oxide layer 6 and a third oxide layer 7 are sequentially disposed between the first shielding gate 5 and the second shielding gate 8, and a fourth oxide layer 9 and a fifth oxide layer 10 are sequentially disposed between the second shielding gate 8 and the control gate 11. Because there are strict requirements for preventing leakage current and breakdown between the shielding gates, the oxide layers between the shielding gates require high quality. Therefore, the second oxide layer 6, the third oxide layer 7, the fourth oxide layer 9, and the fifth oxide layer 10 are all high-quality silicon dioxide layers. Their function is to prevent leakage current between the first shielding gate 5 and the second shielding gate 8, and between the second shielding gate 8 and the control gate 11, thereby preventing breakdown.

[0060] The second shielding gate 8 is connected to the source potential, just like the traditional shielding gate; while the first shielding gate 5 is externally biased by an independent power supply, requiring an independent bias power supply electrode pad to be led out on the chip surface.

[0061] Preferably, the width of the second shielding gate (8) is wider than the width of the first shielding gate (5). The wider second shielding gate (8) brings it closer to the drift region, increasing the charge coupling strength during reverse breakdown and thus enhancing the electric field strength in the middle of the drift region, achieving electric field flattening in the drift region and improving the device's breakdown voltage. During forward conduction, the wider second shielding gate (8) reduces the gate-drain facing area, thereby suppressing parasitic capacitance Coss and improving frequency response.

[0062] Preferably, the width of the second shielding gate (8) is 1-1.2 μm. Within this design range, the following beneficial effects can be achieved: First, while increasing the width of the second shielding gate 8, the thickness of the oxide layer 7 that isolates the second shielding gate 8 and the drift region will be reduced accordingly, which may lead to the risk of leakage current. This design size can ensure that the electric field in the middle of the drift region is maximized during reverse withstand voltage and that there is good isolation characteristics (i.e., no leakage current from the drift region to the second shielding gate 8 is generated); Second, this design size can make the electric field between the second shielding gate 8 and the first shielding gate 5 superimpose, further enhancing the electric field in the middle of the drift region, thereby better achieving the flattening of the electric field in the drift region and increasing the breakdown voltage of the device.

[0063] The first shielding gate 5 is externally biased by an independent power supply, requiring an independent bias power supply electrode pad to be led out on the chip surface.

[0064] Preferably, the independent bias power supply has a positive potential relative to the source, and its potential is lower than the drain potential. The potential range of the independent bias power supply is: source potential (Vs) to one-third of the drain potential (1 / 3Vd). Under different voltage conditions, appropriately adjusting the bias power supply potential can keep the device losses in an optimal state. It should be noted that during reverse blocking, an excessively high bias power supply potential will reduce the electric field strength near the bottom of the trench, preventing the drift region from being exhausted and thus reducing the breakdown voltage. Therefore, setting the upper limit of the bias power supply potential to no more than one-third of the drain potential can avoid the above situation.

[0065] Specifically, the second oxide layer 6 is a high-quality oxide layer deposited by HDP-CVD process, used to fill the gap above the first shielding gate 5. The thickness of the second oxide layer 6 is 0.25-0.3 μm, and its beneficial effect is to ensure good isolation characteristics between the shielding gates.

[0066] Specifically, the third oxide layer 7 is an oxide layer formed by thermal growth after etching an oxide layer to a certain distance from the surface of the first shielding gate 5, and is located on the trench sidewall. The second shielding gate 8 is located above the first shielding gate 5.

[0067] Specifically, the fourth oxide layer 9 is a high-quality oxide layer deposited by HDP-CVD process, used to fill the void above the second shielding gate 5. The fifth oxide layer 10 is a thermally grown gate oxide layer.

[0068] Specifically, the interlayer dielectric layer 14 is located between the N-type heavily doped region 13 and the source metal 16, serving to insulate the source metal and block mobile ions from entering the drift region. The contact hole 15 extends through the interlayer dielectric layer 14 and the N-type heavily doped region 13, with the bottom of the contact hole 15 located in the P-type heavily doped region 12.

[0069] It should be noted that the materials of the first shielding gate 5, the second shielding gate 8, and the control gate 11 include, but are not limited to, polysilicon doped with the first conductivity type. The materials of the first oxide layer 4, the second oxide layer 6, the third oxide layer 7, the fourth oxide layer 9, and the fifth oxide layer 10 include, but are not limited to, silicon dioxide; silicon dioxide is selected as an example in this embodiment.

[0070] It should be noted that, typically, the source metal 16 of a MOSFET is called the first terminal, the drain metal 17 is the second terminal, and the gate is the third terminal. However, in this embodiment of the invention, the gate is segmented within the trench 3 of the epitaxial layer 2, including a first shielding gate 5, a second shielding gate 8, and a control gate 11. The first shielding gate 5 is connected to an independent bias power supply. Therefore, in this embodiment, the control gate 11 is the third terminal, and the first shielding gate 5 is the fourth terminal. Thus, the shielded-gate trench MOSFET of this embodiment is a four-terminal device, with a separate independent bias power supply. The electric field in the drift region is controlled through the charge coupling effect between the first shielding gate 5, connected to the independent bias power supply, and another wider section of the second shielding gate 8.

[0071] When the shielded-gate trench MOSFET four-terminal device is operating, the second shielded gate 8 is electrically connected to the source. When the shielded-gate trench MOSFET four-terminal device is forward-biased, an electric field is introduced from the shielded gate 5 to the drift region due to the potential difference between the first shielded gate 5 and the drift region. (Refer to...) Figure 18 As shown, according to the charge coupling principle, when the shielded-gate trench MOSFET four-terminal device is forward-biased, electrons flowing through the drift region will move towards the first shielded gate 5 due to the transverse electric field force, thereby widening the conduction current path and reducing the on-resistance. When the shielded-gate trench MOSFET four-terminal device is reverse-biased, due to the potential difference between the first shielded gate 5, the second shielded gate 8 and the drift region, two transverse electric fields will be introduced, one pointing from the shielded gate 5 to the drift region and the other pointing from the shielded gate 8 to the drift region. Since the shielded gate 5 is connected to an independent bias power supply, the potential difference at the bottom of the trench decreases (the potential difference at the bottom of the trench is the drain potential minus the independent bias power supply potential). The decrease in potential difference leads to a decrease in electric field strength, which in turn reduces the peak electric field at the bottom of the trench, increases the electric field strength in the middle of the drift region, flattens the electric field of the entire drift region, and thus improves the overall withstand voltage of the shielded-gate trench MOSFET four-terminal device of this embodiment.

[0072] Embodiment 2 of the present invention provides a method for manufacturing a shielded gate trench MOSFET four-terminal device.

[0073] Reference Figures 2-16 As shown, the manufacturing method of a shielded gate trench MOSFET four-terminal device includes:

[0074] S1: An epitaxial layer 2 is formed on substrate 1, and trenches 3 are etched in the epitaxial layer 2. For details, refer to... Figure 2 As shown, in this embodiment of the invention, silicon (Si) of suitable size and resistivity is selected as substrate 1, and a lightly doped epitaxial structure, namely epitaxial layer 2, is formed on the Si substrate by an epitaxial process.

[0075] It should be noted that in chip manufacturing, epitaxy is the process of growing a new single-crystal layer with the same or different crystal structure as the substrate on a single-crystal silicon substrate that has undergone fine processing such as cutting, grinding, and polishing, using chemical or physical methods. By growing an epitaxial layer on the substrate, the doping concentration and type of silicon can be precisely controlled, optimizing the electrical performance of the device. The epitaxial layer can also be designed to have a high breakdown voltage resistance.

[0076] Furthermore, a masking and etching process is performed on the epitaxial layer 2 to form the first hard mask layer of the trench 3. This mask layer serves as an etching barrier layer, and the trench 3 is formed by etching within the epitaxial layer 2. Specifically, refer to... Figure 3 As shown, a silicon dioxide layer, a silicon nitride layer, and another silicon dioxide layer are sequentially grown on epitaxial layer 2, followed by masking and etching processes to form the first hard mask layer of the etching trench 3. Using the first hard mask layer as an etching barrier layer, the trench 3 is etched in epitaxial layer 2. The function of the trench 3 is that both the shielding gate and the control gate structure must be recessed into the device through trenching to achieve the effect of controlling the device current.

[0077] It should be noted that in chip manufacturing, etching is a key step in forming three-dimensional structures by selectively removing material from specific areas using physical or chemical methods to transfer the pattern defined by the photoresist to the wafer surface.

[0078] It should be noted that in chip manufacturing, the mask process is a key step that uses a photomask (photomask) to precisely transfer the chip design pattern to the wafer surface using photolithography.

[0079] S2: Thermal growth and chemical vapor deposition are performed on the inner surface of trench 3 to form the first oxide layer 4. For details, refer to... Figure 4 As shown, thermal growth and chemical vapor deposition (CVD) are performed on the inner surface of trench 3 to form a first oxide layer 4. The main component of the first oxide layer 4 is silicon dioxide (SiO2). The function of the first oxide layer 4 is to isolate the drift region from the shielding gate and the control gate, and to prevent leakage current from forming between the control gate, the shielding gate and the drain.

[0080] It should be noted that chemical vapor deposition (CVD) is a process for depositing thin film materials on solid surfaces through chemical reactions. The basic process involves introducing one or more gaseous precursors into a reaction chamber, where a chemical reaction occurs on a heated substrate surface, generating a solid thin film product while releasing gaseous byproducts. These byproducts are then discharged from the chamber through an exhaust system. For example, in the preparation of silica thin films, commonly used precursors are silane (SiH4) and oxygen (O2), which react at high temperatures to generate silica (SiO2) and release water vapor (H2O).

[0081] S3: Near the bottom of trench 3, polysilicon is deposited by chemical vapor deposition and then etched to form the first shielding gate 5. For details, refer to... Figure 5 As shown, conductive polysilicon shielding gate is deposited in the first oxide layer by chemical vapor deposition (CVD), and the first shielding gate 5 is formed near the bottom in the trench 3 by etching back the polysilicon.

[0082] In terms of process, this step is a simple polysilicon deposition, consistent with the shielded gate deposition process of ordinary SGTs. In terms of details, the depth of the first shielded gate 5 is between 2.3-2.5 μm; within this range, its effect is better. If the depth of the first shielded gate 5 is too deep or too shallow, it is difficult to achieve the desired effect. The functions of the shielded gate 5 are: 1. To introduce a lateral electric field in the drift region through charge coupling, thereby reducing the on-resistance; 2. To adjust the depletion state of the drift region at the bottom of the trench by applying an independent power supply bias, thereby adjusting the peak electric field at the bottom of the trench, making the electric field distribution of the entire drift region flatter, achieving a better BV and Ron trade-off design under the same device structure conditions.

[0083] S4: A second oxide layer 6 is formed between the first oxide layer and the first shielding gate 5 by chemical vapor deposition and etching. For details, refer to... Figure 6 As shown, a second oxide layer 6 is formed by filling high-quality silicon oxide between the first oxide layer and the first shielding gate 5 through high-density plasma chemical vapor deposition, and the first oxide layer 4 and the second oxide layer 6 are etched above the first shielding gate 5.

[0084] It's important to note that High-Density Plasma Chemical Vapor Deposition (HDP-CVD) is a variant of Chemical Vapor Deposition (CVD) technology. It uses high-frequency radio frequency or microwave excitation sources to generate high-density plasma in a gas, ionizing the material and depositing it onto the substrate surface to form a thin film. Specifically, HDP-CVD utilizes an inductively coupled plasma (ICP) source to produce higher plasma density and mass than traditional PECVD equipment at relatively low deposition temperatures. When the gas is heated to a plasma state, molecules dissociate into atoms and ions. These ions are attracted by an electric field and deposit on the substrate surface, forming a uniform and dense thin film.

[0085] S5: Etch the first oxide layer and the second oxide layer, thermally grow the third oxide layer 7 on the second oxide layer, deposit conductive polysilicon on the third oxide layer 7, and form the second shielding gate 8 by etching back.

[0086] Reference Figure 8 , 9As shown, the first oxide layer and the second oxide layer are etched, and the third oxide layer 7 is thermally grown on the second oxide layer. Conductive polysilicon is deposited by CVD and etched back to form the second shielding gate 8. The functions of the second shielding gate 8 are: 1. To reduce the area of ​​the control gate and the drain facing each other, thereby reducing the gate-drain capacitance (COSS); 2. To introduce a lateral electric field in the drift region through charge coupling, thereby reducing the on-resistance; 3. To introduce an electric field spike in the middle of the drift region, enhancing the electric field in the middle of the drift region; 4. To modulate the electric field with the first shielding gate, thereby better achieving the planarization of the electric field in the drift region.

[0087] S6: A fourth oxide layer 9 is formed by depositing polysilicon on the second shielding gate 8, and the third oxide layer 7 and the fourth oxide layer 9 are etched above the second shielding gate 8. For details, refer to... Figure 10 As shown, high-quality silicon oxide is filled using HDP-CVD process to form the fourth oxide layer 9, and the third and fourth oxide layers 7 and 9 are etched above the second shielding gate 8.

[0088] S7: A fifth oxide layer 10 is formed by thermal growth on the fourth oxide layer 9, and a conductive polysilicon gate is deposited on the fifth oxide layer to form the control gate. For details, refer to... Figure 11 As shown, a fifth oxide layer 10, i.e., the gate oxide layer, is formed by thermal growth on the fourth oxide layer 9. (Refer to...) Figure 12 As shown, conductive polysilicon is deposited on the fifth oxide layer by CVD and then etched back to form the control gate 11.

[0089] S8: The active region is defined using photoresist, followed by boron ion implantation to form a heavily p-type doped region. After high-temperature annealing, arsenic ion implantation is performed again to form an n-type doped region. For details, refer to... Figure 13 As shown, since ion implantation can damage the crystal structure, a sacrificial oxide layer needs to be grown first to protect the crystal lattice. Then, the active region is defined using photoresist and boron ions are implanted to form a heavily doped P-type region (P-type body region) 12. High-temperature annealing ensures sufficient junction depth for the heavily doped P-type region 12. Arsenic ion implantation is then performed again to form a heavily doped N-type region (N-type source region) 13. High-temperature annealing ensures sufficient junction depth for the heavily doped N-type region 13.

[0090] S9: An interlayer dielectric layer 14 is deposited over the N-type heavily doped region 13, the control gate 11, and the trench 3. See details below. Figure 14 As shown, a silicon dioxide layer (USG) and a borosilicate glass layer (BPSG) are sequentially deposited on the N-type heavily doped region 13, the control gate 11, and the trench 3 to form an interlayer dielectric layer 14.

[0091] S10: Define the area of ​​contact hole 15 using photoresist, and etch the interlayer dielectric layer 14, the N-type heavily doped region 13, and the P-type heavily doped region 12 to form contact hole 15. For details, refer to... Figure 15 As shown, the area of ​​contact hole 15 is defined by photoresist, and the interlayer dielectric layer 14, N-type heavily doped region 13 and P-type heavily doped region 12 are etched to form contact hole 15.

[0092] S11: Boron fluoride (BF2) is injected into the bottom of contact hole 15 and metal is deposited to form an ohmic contact and source electrode 16. Metal is deposited on the back side of the substrate to form a drain electrode 17. For details, refer to... Figure 16 As shown, boron fluoride (BF2) is injected into the bottom of the contact hole 15 and metal is deposited to form an ohmic contact and a source electrode 16, while metal is deposited on the back side of the substrate to form a drain electrode 17.

[0093] Figure 17 This is a schematic diagram of the layout of Embodiment 1 of the present invention. In actual implementation of this embodiment, the layout can be referred to... Figure 17 As shown. Figure 17 In this context, "Gate bus" refers to the control gate electrode trace on the chip surface. The gate strip inside the chip is electrically connected to the gate trace on the chip surface through perforation and metal deposition, ultimately converging on the control gate electrode. "Shield gate exit area" refers to the area where the second shield gate is led out through perforation. In this area, perforation and metal deposition are performed to electrically connect the second shield gate inside the chip to the source electrode on the surface. "Active region" refers to the active region of the chip, which is the region composed of unit cell structures and is responsible for controlling the current. The area surrounding the active region is the termination region, which isolates interference from external electric fields. "IB pad" refers to the external independent power supply bias electrode. The first shield gate inside the chip is electrically connected to the independent bias power supply electrode and its traces on the chip surface through perforation and metal deposition. "Gate Pad" refers to the control gate electrode. "Sealring" refers to the sealing ring of the chip. The sealing ring is a continuous ring structure integrated within the outermost scribe line of the chip, composed of multiple layers of metal and through-holes. Its main function is to act as a mechanical crack termination zone and an environmental pollution barrier to protect the internal circuitry of the chip from mechanical stress damage and the intrusion of moisture and impurities during wafer dicing, subsequent packaging, and use, thereby ensuring the long-term reliability of the chip.

[0094] Figure 18 This is a schematic diagram of the shielded gate charge coupling principle in Embodiment 1 of the present invention. Figure 18 In this context, "source" represents the source electrode, "gate" represents the control gate, "sg1" indicates that the first shielded gate is connected to an independent power supply bias, and "sg2" represents the second shielded gate connected to the source potential. P +This indicates the P-type heavily doped region at the bottom of the contact hole, used to achieve better ohmic contact. N + This represents the N-type doped region located on top of the P-based region. p-body represents the P-type doped P-based region, N-drifit represents the drift region (the path through which current flows), E represents the electric field (vector, including magnitude and direction), sub represents the substrate, and drain represents the drain electrode. For example... Figure 18 As shown, during forward conduction, because sg1 is connected to an independent bias voltage, the potential of sg1 is greater than the potential of the drift region (which is typically only a few volts during forward conduction). This generates an electric field pointing from sg1 towards the drift region. Electrons flowing through the drift region are drawn towards sg1 by this electric field, thus widening the current path. The magnitude of the electric field is determined by the potential difference between sg1 and the drift region. The higher the independent bias voltage, the stronger the electric field, the wider the electron path, and the lower the on-resistance.

[0095] Simulation verification: Simulation verification platform or software: Sentaurus. Simulation verification results:

[0096] Figure 19 In this context, Abs indicates taking the absolute value, and Total Current Density-V represents the total current density in A*cm^2. -2 It is a unit of total current density, representing the amount of current flowing through each square centimeter. A is the international unit of electric current, the ampere (cm²). -2 This represents the cross-sectional area of ​​the current; 5e16 represents 5 × 10⁻¹⁶ in scientific notation. 16 .

[0097] Figure 20 In this context, Electric Field represents the electric field. Figure 20 In the diagram, the blue curve represents the electric field distribution curve of the traditional SGT MOSFET unit cell structure, while the red curve represents the electric field distribution curve of the unit cell structure in the embodiment of this invention.

[0098] 1. Simulation comparison of electric field distribution between traditional SGT MOSFET and the embodiment of this invention. (Refer to...) Figure 20 As shown, compared with the traditional SGT MOSFET, the electric field distribution of the structure in this embodiment of the invention is more flattened. The area enclosed by the electric field lines is the size of the reverse breakdown voltage. Therefore, the flattened design can enable the MOSFET device to have a higher breakdown voltage.

[0099] 2. Comparison of the current path during forward conduction between the cell structure of a traditional SGT MOSFET and the cell structure of this embodiment. (Refer to...) Figure 18As shown, during forward conduction, because the shielding gate of a traditional unit cell structure is connected to the source potential, the potential of the shielding gate is zero. The potential of the drift region is greater than that of the shielding gate, thus generating an electric field from the drift region towards the shielding gate. When current flows near the shielding gate, electrons are driven away from the shielding gate by the electric field, resulting in a narrower current path and increased on-resistance. When the source-drain voltage is even higher, the potential of the drift region is even greater, and the repulsive effect of the shielding gate on electrons in the drift region will be further enhanced, leading to a further increase in on-resistance. In the structure of this embodiment, because the shielding gate is connected to an independent electrode, the applied potential is positive relative to the source potential, which attracts electrons in the drift region, widening the current conduction path and reducing on-resistance.

[0100] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A shielded gate trench type MOSFET four-terminal device, characterized in that, include: Substrate (1), epitaxial layer (2) located on substrate (1), trench (3) is provided in epitaxial layer, gate is provided in segmented form in trench (3), gate is provided in segmented form including first shield gate (5), second shield gate (8) and control gate (11), first shield gate (5) is connected to independent bias power supply, oxide layer is provided between each segmented gate, P-type heavily doped region (12) is provided on top of epitaxial layer, N-type heavily doped region (13) is provided on P-type heavily doped region (12), interlayer dielectric layer (14) is provided on N-type heavily doped region (13) and control gate (11), source metal (16) penetrates through interlayer dielectric layer (14) and P-type heavily doped region (11) through contact hole (15), bottom of source metal (16) is provided in N-type heavily doped region (13), drain metal (17) is provided on back side of substrate.

2. The shielded gate trench MOSFET four-terminal device according to claim 1, characterized in that, The potential of the independent bias power supply is positive relative to the source, and its potential is less than that of the drain.

3. The shielded gate trench MOSFET four-terminal device according to claim 1, characterized in that, The specific positions of the segmented gates are as follows: the first shielding gate (5) is located near the bottom of the trench, the second shielding gate (8) is located in the middle of the trench, and the control gate (11) is located at the top of the trench.

4. A shielded gate trench MOSFET four-terminal device according to claim 1 or 2, characterized in that, An oxide layer is provided between the gates of each segment, specifically: a second oxide layer (6) and a third oxide layer (7) are provided sequentially between the first shielding gate (5) and the second shielding gate (8), and a fourth oxide layer (9) and a fifth oxide layer (10) are provided sequentially between the second shielding gate (8) and the control gate (11).

5. A shielded gate trench MOSFET four-terminal device according to claim 1, characterized in that, The epitaxial layer (2) is a lightly doped epitaxial layer of the first conductivity type, and its material includes, but is not limited to, silicon.

6. A shielded gate trench MOSFET four-terminal device according to claim 1, characterized in that, The depth of the first shielding gate (5) is 2.3-2.5 μm.

7. A shielded gate trench MOSFET four-terminal device according to claim 1, characterized in that, A first oxide layer (4) is provided on the surface of the trench (3).

8. A shielded gate trench MOSFET four-terminal device according to claim 1, characterized in that, The width of the second shielding gate (8) is 1-1.2 μm.

9. A shielded gate trench MOSFET four-terminal device according to claim 1, characterized in that, The width of the second shielding gate (8) is wider than the width of the first shielding gate (5).

10. A method for fabricating a shielded gate trench MOSFET four-terminal device, characterized in that, include: An epitaxial layer is formed on the substrate, and trenches are etched in the epitaxial layer; Thermal growth and chemical vapor deposition are performed on the inner surface of the trench to form the first oxide layer; Near the bottom of the trench, polysilicon is deposited by chemical vapor deposition and then etched to form the first shielding gate. A second oxide layer is formed between the first oxide layer and the first shielding gate by chemical vapor deposition and etching; The first oxide layer and the second oxide layer are etched, the third oxide layer is thermally grown above the second oxide layer, conductive polysilicon is deposited on the third oxide layer, and the second shielding gate is formed by etching back. A fourth oxide layer is formed by depositing polysilicon on the second shielding gate, and the third oxide layer and the fourth oxide layer are etched to the top of the second shielding gate. A fifth oxide layer is formed by thermal growth of the fourth oxide layer, and a control gate is formed by depositing conductive polysilicon on the fifth oxide layer. The active region is defined by photoresist, boron ion implantation is performed to form a P-type heavily doped region, and after high-temperature annealing, arsenic ion implantation is performed again to form an N-type doped region. An interlayer dielectric layer is deposited on top of the N-type heavily doped region and trench; The contact hole area is defined by photoresist, and the interlayer dielectric layer, N-type heavily doped region and P-type heavily doped region are etched to form the contact hole. Boron fluoride (BF2) is injected into the bottom of the contact hole and metal is deposited to form an ohmic contact and source electrode. Metal is deposited on the back side of the substrate to form a drain electrode.

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