Shield gate trench MOSFET device and preparation method thereof

Abstract

The invention provides a shield gate trench MOSFET device and a preparation method thereof, a first contact hole and a second contact hole which are strip-shaped, continuous, alternately arranged and different in transverse width are formed in an interlayer dielectric layer, the transverse width of the second contact hole is larger than that of the first contact hole, and the first contact hole and the second contact hole are communicated with each other. The ion concentration of the channel region of the cell where the second contact hole is located is relatively high, so that the threshold voltage is relatively high; the channel ion concentration of the cell where the first contact hole is located is low, so that the threshold voltage is low, when the MOS device works, the channel of the cell with the low threshold voltage is firstly started for conduction, the channel of the cell with the high threshold voltage is then started for conduction, the cell which is started later can serve as a heat dissipation channel through the time-sharing starting mechanism, heat is dissipated for the cell which is started firstly, and the heat dissipation efficiency is improved. Therefore, the SOA and the heat dissipation capability of the device are remarkably improved, only the shape of the contact hole mask layout needs to be adjusted, additional process steps do not need to be added, the reliability of the MOS device is improved, and the application range of the MOS device is widened with extremely low cost.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor integrated circuit manufacturing, and particularly relates to a shielding gate trench MOSFET device and a preparation method thereof. BACKGROUND

[0002] Power devices are used in the fields of power management, power transmission and high-speed switching control, and can be divided into junction field effect transistor (JFET), metal oxide semiconductor field effect transistor (MOSFET), bipolar transistor (BJT), thyristor (SCR) and the like according to the operating principle. The shielding gate trench MOS device (Shielding Gate Trench MOSFET, SGT MOS) in the metal oxide semiconductor field effect transistor is an improvement of the traditional deep trench MOS, which reduces the gate-drain overlap area of the MOS device by adding a polysilicon electrode (called shielding gate) below the gate electrode, reduces the gate-drain capacitance, improves the switching speed, reduces the dynamic loss of the MOSFET device, and increases the cell density and reduces the on-resistance, so that it is widely used in low-voltage fields such as motor drive, power management, synchronous rectification, energy storage control and the like.

[0003] Due to the existence of chip area, cell design and packaging performance and other factors, the shielding gate trench MOS device has an energy range that can safely handle the drain-source voltage and drain current, i.e. SOA (Safe Operating Aera, safe operating area). However, with the continuous change and development of the application environment of the shielding gate trench MOS device, on the one hand, it is required that the shielding gate trench MOS device has lower on-state loss; on the other hand, it is required that the shielding gate trench MOS device can work for a longer time under high voltage and large current, i.e. it is required that the shielding gate trench MOS device has better SOA performance.

[0004] The SOA performance of the shielding gate trench MOS device in the prior art is poor, and only has one shape type of source contact hole, and the source contact hole is generally arranged on the center area between adjacent trenches, so that different cells in the shielding gate trench MOS device only have one threshold voltage, which leads to the fact that the shielding gate trench MOS device can only be applied to one corresponding required circuit, and the application range is small; further, the change of environmental temperature and the heat generated during work will cause the working resistance of the shielding gate trench MOS device to increase, generate more heat, and eventually the shielding gate trench MOS device may be burned due to poor heat dissipation effect.

[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application and facilitating the understanding of the skilled in the art. The above technical scheme cannot be considered as known to the skilled in the art only because it is described in the background section of the present application. SUMMARY

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a shield gate trench MOSFET device and a preparation method thereof, which are used to solve the problems of poor SOA performance, small application range and poor heat dissipation effect of the shield gate trench MOSFET device in the prior art, which leads to the burning of the shield gate trench MOS device.

[0007] To achieve the above-mentioned purpose and other related purposes, the present application provides a preparation method of a shield gate trench MOSFET device, comprising the following steps:

[0008] providing a semiconductor substrate with an epitaxial layer, and forming trenches arranged at intervals in a horizontal direction in the epitaxial layer, the trenches being open from the upper surface of the epitaxial layer and extending downward;

[0009] forming a dielectric material layer and a conductive material layer in the trenches in sequence, the dielectric material layer being located on the inner wall and bottom surface of the trench and wrapping the side wall and bottom surface of the conductive material layer, and the upper surface of the dielectric material layer being lower than the upper surface of the epitaxial layer;

[0010] forming a gate dielectric layer and a gate conductive layer on the surface of the dielectric material layer in sequence, the gate dielectric layer covering the side wall of the trench and wrapping the side wall and bottom surface of the gate conductive layer;

[0011] performing ion implantation on the upper surface of the epitaxial layer on both sides of the trench to form a body region, and performing ion implantation on the upper surface of the body region to form a source region;

[0012] forming an interlayer dielectric layer on the source region, and etching the interlayer dielectric layer, the source region and the body region to form a first contact hole and a second contact hole penetrating through the interlayer dielectric layer and the source region and exposing the body region, the first contact hole and the second contact hole being distributed on both sides of the trench;

[0013] depositing metal on the interlayer dielectric layer to form a source electrode filling the first contact hole and the second contact hole.

[0014] Optionally, the first contact hole and the second contact hole are both located in the central region of two adjacent trenches, and the first contact hole and the second contact hole are arranged alternately in the horizontal direction.

[0015] Optionally, the lateral width of the second contact hole is greater than the lateral width of the first contact hole.

[0016] Optionally, the lateral width of the first contact hole is 0.2~0.3μm, and the lateral width of the second contact hole is 0.4~0.6μm.

[0017] Optionally, the upper surfaces of the gate dielectric layer, the gate conductive layer, and the source region are flush.

[0018] Optionally, after forming the source, the method further includes forming a passivation layer, etching the passivation layer to form metal leads, and forming a drain, wherein the passivation layer is located on the surface of the source, and the drain is electrically connected to the back side of the semiconductor substrate.

[0019] Optionally, the width of the trench is 0.8~1.2μm, and the ratio of the lateral width of the conductive material layer to the lateral width of the dielectric material layer is 0.5~3.

[0020] The present invention also provides a shielded gate trench MOSFET device, comprising:

[0021] A semiconductor substrate and an epitaxial layer disposed on the semiconductor substrate;

[0022] At least one cell unit is located in the epitaxial layer, the cell unit including trenches spaced apart in the horizontal direction;

[0023] A shielding grid, comprising a dielectric material layer and a conductive material layer, wherein the dielectric material layer is located on the inner wall and bottom surface of the trench, the dielectric material layer wraps around the sidewall and bottom surface of the conductive material layer, and the upper surface of the dielectric material layer is lower than the upper surface of the epitaxial layer;

[0024] A trench gate structure, comprising a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer is located on the inner wall of the trench and the upper surface of the dielectric material layer and wraps the sidewalls and bottom surface of the gate conductive layer;

[0025] A second conductivity type body region and a first conductivity type source region, wherein the body region is located on the upper surface of the epitaxial layer, and the source region is located on the upper surface of the body region and is flush with the upper surface of the trench gate structure;

[0026] An interlayer dielectric layer is located on the upper surface of the source region. The interlayer dielectric layer has a first contact hole and a second contact hole that penetrate the source region and expose the body region. The first contact hole and the second contact hole are distributed on both sides of the trench.

[0027] The source electrode is located on the interlayer dielectric layer and fills the first contact hole and the second contact hole.

[0028] Optionally, the first contact hole and the second contact hole are both located in the central region of two adjacent grooves, and the first contact hole and the second contact hole are arranged alternately in the horizontal direction.

[0029] Optionally, the lateral width of the second contact hole is greater than the lateral width of the first contact hole, and the lateral width of the first contact hole is 0.2~0.3μm, while the lateral width of the second contact hole is 0.4~0.6μm.

[0030] As described above, the shielded gate trench MOSFET device and its fabrication method of the present invention fabricate first and second contact holes, both of which are elongated and continuous in shape, arranged alternately in the horizontal direction with different lateral widths, in the interlayer dielectric layer of the cell region. The lateral width of the second contact hole is greater than that of the first contact hole, resulting in a higher ion concentration in the channel region of the cell containing the second contact hole, and thus a higher threshold voltage. Conversely, the ion concentration in the channel of the cell containing the first contact hole is lower, resulting in a lower threshold voltage. This allows the channel of the cell with the lower threshold voltage to turn on and conduct first when the shielded gate trench MOSFET device is in operation, while the channel of the cell with the higher threshold voltage turns on and conducts later. The time-division multiplexing mechanism allows the later-turned-on cells to act as heat dissipation channels to disperse heat from the earlier-turned cells, thereby significantly improving the safe operating area (SOA) and heat dissipation capability of the device. Moreover, this fabrication method only requires adjusting the shape of the contact hole mask pattern without adding any additional process steps, achieving improved reliability and application range of the MOSFET device at extremely low cost, and has high industrial application value. Attached Figure Description

[0031] Figure 1 The diagram shows the process flow of the fabrication method of the shielded gate trench MOSFET device of the present invention.

[0032] Figure 2 The diagram shows a cross-sectional structure after a trench is formed in the epitaxial layer according to the present invention.

[0033] Figure 3 The diagram shows a cross-sectional structure after a dielectric material layer and a conductive material layer are formed in the trench according to the present invention.

[0034] Figure 4 The diagram shows a cross-sectional structure after etching the dielectric and conductive material layers.

[0035] Figure 5 The diagram shows a cross-sectional structure after the gate dielectric layer and the gate conductive layer are formed in the trench according to the present invention.

[0036] Figure 6 The diagram shows a cross-sectional structure after etching the gate dielectric layer and the gate conductive layer.

[0037] Figure 7 The diagram shows a cross-sectional structure after the body region and the source region are formed on the epitaxial layer in this invention.

[0038] Figure 8 The diagram shown is a cross-sectional view of the structure after the interlayer dielectric layer is formed in this invention.

[0039] Figure 9 The diagram shows a cross-sectional structure after the formation of the first and second contact holes in this invention.

[0040] Figure 10 The diagram shown is a top view of the structure after the first and second contact holes are formed in this invention.

[0041] Figure 11 The diagram shown is a cross-sectional view of the source electrode after it has been formed in this invention.

[0042] Figure 12 The diagram shown is a cross-sectional view of the structure after the passivation layer and drain electrode are formed in this invention.

[0043] Explanation of icon numbers

[0044] 110. Semiconductor substrate; 111. Epitaxial layer; 112. Trench; 113. Dielectric material layer; 114. Conductive material layer; 115. Gate dielectric layer; 116. Gate conductive layer; 117. Body region; 118. Source region; 119. Interlayer dielectric layer; 120. First contact hole; 121. Second contact hole; 124. Source electrode; 125. Passivation layer; 126. Drain electrode; S1~S6. Steps. Detailed Implementation

[0045] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0047] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0048] Please see Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0049] Example 1

[0050] This embodiment provides a method for fabricating a shielded gate trench MOSFET device, such as... Figure 1 The diagram shown illustrates the process flow of the fabrication method for the shielded gate trench MOSFET device, including the following steps:

[0051] S1: A semiconductor substrate 110 having an epitaxial layer 111 is provided, wherein trenches 112 are formed in the epitaxial layer 111 at intervals in the horizontal direction, the trenches 112 opening from the upper surface of the epitaxial layer 111 and extending downward.

[0052] S2: A dielectric material layer 113 and a conductive material layer 114 are sequentially formed in the trench 112. The dielectric material layer 113 is located on the inner wall and bottom surface of the trench 112 and wraps around the side wall and bottom surface of the conductive material layer 114. The upper surface of the dielectric material layer 113 is lower than the upper surface of the epitaxial layer 111.

[0053] S3: A gate dielectric layer 115 and a gate conductive layer 116 are sequentially formed on the surface of the dielectric material layer 113. The gate dielectric layer 115 covers the sidewall of the trench 112 and wraps the sidewall and bottom surface of the gate conductive layer 116.

[0054] S4: Ion implantation is performed on the trench 112 and the upper surface of the epitaxial layer 111 on both sides to form a body region 117, and ion implantation is performed on the upper surface of the body region 117 to form a source region 118.

[0055] S5: An interlayer dielectric layer 119 is formed on the source region 118, and the interlayer dielectric layer 119, the source region 118 and the body region 117 are etched to form a first contact hole 120 and a second contact hole 121 that penetrate the interlayer dielectric layer 119 and the source region 118 and expose the body region 117. The first contact hole 120 and the second contact hole 121 are distributed on both sides of the trench 112.

[0056] S6: Deposit metal on the interlayer dielectric layer 119 to form a source 124 that fills the first contact hole 120 and the second contact hole 121.

[0057] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite. In this embodiment, a shielded gate trench MOSFET device is used as an example of an N-type device for detailed explanation; that is, in this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. When the shielded gate trench MOSFET device is a P-type device, it is only necessary to interchange the corresponding N-type and P-type types.

[0058] The fabrication method of the shielded gate trench MOSFET device of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0059] like Figure 2 As shown, in step S1, a semiconductor substrate 110 having an epitaxial layer 111 is provided, and trenches 112 spaced apart along the X direction are formed in the epitaxial layer 111, the trenches 112 extending downward from the upper surface of the epitaxial layer 111 along the Y direction.

[0060] Specifically, such as Figure 2 The diagram shows a cross-sectional view of the semiconductor substrate 110. In this embodiment, the semiconductor substrate 110 is an N-type semiconductor substrate 110, and an N-type epitaxial layer 111 is formed on the front side of the semiconductor substrate 110. While ensuring device performance, the thickness, size, doping concentration, and shape of the semiconductor substrate 110 can be selected according to actual conditions and are not limited here. The thickness, size, doping concentration, and shape of the epitaxial layer 111 can be selected according to actual conditions and are not limited here.

[0061] Optionally, in this embodiment, the semiconductor substrate 110 can be an N+ type doped silicon substrate, a germanium silicon substrate, a silicon carbide substrate, etc., and the epitaxial layer 111 is selected as a single-crystal silicon epitaxial layer 111 of the first conductivity type. Before performing subsequent processes, the semiconductor substrate 110 can be cleaned, for example, by sequentially cleaning with an organic solvent such as acetone and deionized water to remove contaminants from the surface of the semiconductor substrate 110, followed by drying; or by first removing the natural oxide layer on the surface of the semiconductor substrate 110 with a diluted acid solution, then cleaning with deionized water, and finally drying; or by performing multiple cleanings using the aforementioned methods.

[0062] Furthermore, such as Figure 2 As shown, a plurality of trenches 112 are formed in the epitaxial layer 111 at intervals along the X direction. The trenches 112 extend downward from the upper surface of the epitaxial layer 111 along the Y direction. The number and depth of the trenches 112 can be selected according to actual conditions while ensuring device performance, and are not limited here. The width of the trenches 112 is 0.8~1.2μm, for example, the width of the trenches 112 is 0.8μm, 1μm or 1.2μm. The spacing between adjacent trenches 112 is 2.4~3μm, for example, the spacing between adjacent trenches 112 is 2.4μm, 2.6μm or 3μm. The specific steps for forming multiple trenches 112 spaced apart along the X-direction are as follows: First, a hard mask layer is formed on the upper surface of the epitaxial layer 111. The mask layer includes, but is not limited to, an oxide layer, a silicon nitride layer, or other suitable film layers. Using the hard mask layer, the regions where the trenches 112 to be formed are defined by photolithography, thereby etching out the desired trenches 112. After forming the trenches 112, residual hard mask layers are removed using processes including, but not limited to, etching. Specific implementation methods of the photolithography and etching processes can be achieved using conventional methods known to those skilled in the art, and are not specifically limited here.

[0063] like Figure 3 and Figure 4 As shown, in step S2, a dielectric material layer 113 and a conductive material layer 114 are sequentially formed in the trench 112. The dielectric material layer 113 is located on the inner wall and bottom surface of the trench 112 and wraps around the side wall and bottom surface of the conductive material layer 114. The upper surface of the dielectric material layer 113 is lower than the upper surface of the epitaxial layer 111.

[0064] Specifically, such as Figure 3The diagram shows a cross-sectional structure after a dielectric material layer 113 and a conductive material layer 114 of a certain thickness have been grown on the surface of the epitaxial layer 111 and the inner wall of the trench 112. The ratio of the lateral width of the conductive material layer 114 to the lateral width of the dielectric material layer 113 is 0.5 to 3. For example, the ratio of the lateral width of the conductive material layer 114 to the lateral width of the dielectric material layer 113 is 0.5, 1.5, 2.5 or 3. No specific limitation is made here. The method for forming the dielectric material layer 113 and the conductive material layer 114 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0065] Specifically, the dielectric material layer 113 can be a high-k dielectric layer, including but not limited to silicon oxide, silicon nitride, aluminum oxide or other suitable dielectric materials, and the conductive material layer 114 is made of polycrystalline silicon.

[0066] Specifically, while ensuring device performance, the thickness of the dielectric material layer 113 covering the inner wall of the trench 112 can be selected according to the actual situation, and is not limited here.

[0067] like Figure 4 As shown, the dielectric material layer 113 and the conductive material layer 114 within the trench 112 are etched to obtain the shielding gate layer of a preset height. Specifically, while ensuring device performance, the height of the shielding gate layer can be selected according to actual conditions, and is not limited here. The height here refers to the distance between the bottom surface of the shielding gate layer and the top surface of the shielding gate layer.

[0068] Specifically, such as Figure 4 As shown, anisotropic etching is performed on the dielectric material layer 113 and the conductive material layer 114 so that the upper surface of the dielectric material layer 113 is lower than the upper surface of the epitaxial layer 111. Then, the dielectric material layer 113 and the conductive material layer 114 are planarized, or CMP process is directly used to make the dielectric material layer 113 and the conductive material layer 114 located in the trench 112 have the same height. Both of the above processing methods can make the dielectric material layer 113 and the conductive material layer 114 have flush surfaces. The planarization process can include mechanical polishing or CMP, which is not excessively limited here.

[0069] Optionally, after anisotropic etching and planarization of the dielectric material layer 113 and the conductive material layer 114, the dielectric material layer 113 needs to be deposited again on the surface of the dielectric material layer 113 and the conductive material layer 114, so that the dielectric material layer 113 is located on the inner wall and bottom surface of the trench 112 and wraps the side wall and bottom surface of the conductive material layer 114.

[0070] like Figure 5 and Figure 6 As shown, in step S3, a gate dielectric layer 115 and a gate conductive layer 116 are sequentially formed on the surface of the dielectric material layer 113. The gate dielectric layer 115 covers the sidewall of the trench 112 and wraps the sidewall and bottom surface of the gate conductive layer 116.

[0071] Specifically, such as Figure 5 The diagram shows a cross-sectional structure after the gate dielectric layer 115 and the gate conductive layer 116 of a certain thickness are grown on the surface of the epitaxial layer 111 and the inner wall of the trench 112. The methods for forming the gate dielectric layer 115 and the gate conductive layer 116 include thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0072] Specifically, the gate dielectric layer 115 can be a high-k dielectric layer, including but not limited to silicon oxide, silicon nitride, aluminum oxide or other suitable dielectric materials, and the gate conductive layer 116 is made of polycrystalline silicon.

[0073] Specifically, forming the gate dielectric layer 115 and the gate conductive layer 116 includes the following steps: forming a gate dielectric layer 115 covering the surface of the dielectric material layer 113, the sidewalls of the trench 112, and the upper surface of the epitaxial layer 111; and then forming the gate conductive layer 116 in the trench 112 in the middle of the gate dielectric layer 115 and on the upper surface of the epitaxial layer 111; as shown Figure 6 As shown, the gate dielectric layer 115 and the gate conductive layer 116 are subjected to anisotropic etching and planarization to obtain a trench gate structure located in the trench 112.

[0074] Specifically, the planarization methods for the gate dielectric layer 115 and the gate conductive layer 116 include chemical mechanical polishing, dry etching, wet etching, or other suitable methods.

[0075] Specifically, while ensuring device performance, the thickness of the gate dielectric layer 115 covering the inner wall of the trench 112 can be selected according to the actual situation, and is not limited here.

[0076] like Figure 7 As shown, step S4 is performed, ion implantation is performed on the trench 112 and the upper surface of the epitaxial layer 111 on both sides to form a body region 117, and ion implantation is performed on the upper surface of the body region 117 to form a source region 118.

[0077] Specifically, in this embodiment, such as Figure 7As shown, the body region 117 is a body region of the second conductivity type. The method for forming the body region 117 of the second conductivity type includes ion implantation and high-temperature annealing. For example, ion implantation can be used to implant second conductivity type impurities into the top of the epitaxial layer 111 doped with the first conductivity type on both sides of the trench 112, and then a high-temperature annealing process can be performed to invert the top of the epitaxial layer 111 doped with the first conductivity type into the body region 117 of the second conductivity type. The body region 117 is isolated from the gate conductive layer 116 through the gate dielectric layer 115.

[0078] Specifically, while ensuring device performance, the doping concentration and thickness of the body region 117 can be selected according to actual conditions, and are not limited here. The thickness here refers to the distance between the lower surface and the upper surface of the body region 117.

[0079] Specifically, the source region 118 is a first conductivity type source region 118. The method for forming the first conductivity type source region 118 includes ion implantation and high-temperature annealing. For example, ion implantation can be used to implant first conductivity type impurities into the top of the second conductivity type body region 117, followed by a high-temperature annealing process to reverse the top of the second conductivity type body region 117 back into the first conductivity type source region 118, making the upper surfaces of the gate dielectric layer 115, the gate conductive layer 116, and the source region 118 flush. The source region 118 and the gate conductive layer 116 are isolated by the gate dielectric layer 115.

[0080] Specifically, while ensuring device performance, the doping concentration, size, thickness, and shape of the source region 118 can be selected according to actual conditions, and are not limited here. The thickness here refers to the distance between the lower surface and the upper surface of the source region 118.

[0081] Specifically, such as Figure 7 As shown, the lower surface of the gate conductive layer 116 is lower than the upper surface of the source region 118, so that the gate conductive layer 116 can control the opening and closing of the conductive channel.

[0082] like Figures 8 to 10 As shown, in step S5, an interlayer dielectric layer 119 is formed on the source region 118, and the interlayer dielectric layer 119, the source region 118 and the body region 117 are etched to form a first contact hole 120 and a second contact hole 121 that penetrate the interlayer dielectric layer 119 and the source region 118 and expose the body region 117. The first contact hole 120 and the second contact hole 121 are distributed on both sides of the trench 112.

[0083] Specifically, such as Figure 8As shown, an interlayer dielectric layer 119 is formed on the source region 118. The method for forming the interlayer dielectric layer 119 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. Optionally, the interlayer dielectric layer 119 includes one or a combination of silicon oxide layer, silicon nitride layer, and silicon phosphate glass layer.

[0084] Specifically, a photoresist mask layer is formed on the interlayer dielectric layer 119. The photoresist mask layer is exposed using a mask, and a first contact hole 120 region and a second contact hole 121 region are defined in the developed photoresist mask layer. The first contact hole 120 and the second contact hole 121 are formed through the interlayer dielectric layer 119 and the source region 118, with the bottom surface exposing the body region 117, using a dry etching process. In this embodiment, dry etching offers good anisotropy, thus saving costs. Furthermore, compared to the traditional mask-based contact hole fabrication process, this process only requires changing the mask pattern design for forming the first contact hole 120 and the second contact hole 121, without adding additional photolithography steps or complex processes, resulting in almost no increase in manufacturing costs.

[0085] Specifically, such as Figure 9 As shown, the first contact hole 120 and the second contact hole 121 are distributed on both sides of the groove 112. That is, the first contact hole 120 is located in the central region between two adjacent grooves 112, and the second contact hole 121 is located in the central region between two adjacent grooves 112. The first contact hole 120 and the second contact hole 121 are arranged alternately in the horizontal direction. The lateral width of the second contact hole 121 is equal to the lateral width of the first contact hole 120. The lateral width of the first contact hole 120 is 0.2~0.3μm, and the lateral width of the second contact hole 121 is 0.4~0.6μm. For example, the lateral width of the first contact hole 120 is 0.2μm, 0.25μm, or 0.3μm, and the lateral width of the second contact hole 121 is 0.4μm, 0.5μm, or 0.6μm. There is no limitation here.

[0086] Specifically, such as Figure 10The diagram shows a top view of the structure after the formation of the first contact hole 120 and the second contact hole 121. In this embodiment, both the second contact hole 121 and the first contact hole 120 are elongated continuous shapes. This configuration results in a higher ion concentration in the channel region of the cell containing the second contact hole 121, leading to a higher threshold voltage; conversely, a lower ion concentration in the channel of the cell containing the first contact hole 120, resulting in a lower threshold voltage. Based on the different threshold voltages between different cells of the shielded gate trench MOSFET device, the device can have sequential turn-on functionality. Furthermore, the later-turned channel can serve as a heat dissipation channel for the earlier-turned channel, thereby improving the SOA performance of the shielded gate trench MOSFET device and enhancing its processing power and reliability.

[0087] like Figure 11 As shown, step S6 is performed to deposit metal on the interlayer dielectric layer 119 to form a source 124 that fills the first contact hole 120 and the second contact hole 121.

[0088] Specifically, such as Figure 11 The diagram shown is a cross-sectional view of the source electrode 124 after it has been formed. The methods for forming the source electrode 124 include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0089] Specifically, in order to ensure that the exposed body area 117 at the bottom of the first contact hole 120 and the second contact hole 121 has a good metal connection with the outside, this embodiment uses metal to fill the first contact hole 120 and the second contact hole 121. The metal material forming the source electrode 124 includes titanium, titanium nitride, silver, gold, copper, aluminum, tungsten or other suitable conductive materials.

[0090] Specifically, the source 124 also covers the upper surface of the interlayer dielectric layer 119 above the gate conductive layer 116.

[0091] As an example, such as Figure 12 As shown, after forming the source 124, the process further includes forming a passivation layer 125, etching the passivation layer 125 to form metal leads, and forming a drain 126. The passivation layer 125 is located on the surface of the source 124, and the drain 126 is electrically connected to the back side of the semiconductor substrate 110.

[0092] Optionally, the passivation layer 125 can be a single-layer or multi-layer stacked structure. For example, the passivation layer 125 may consist only of a silicon nitride layer, or it may consist of a silicon nitride layer and a polymer layer located on the silicon nitride layer. Preferably, in this embodiment, the passivation layer 125 is selected to include a silicon nitride layer and a polyimide layer. The silicon nitride layer can be formed by chemical vapor deposition, and the polyimide layer can be formed by spin coating, so that the passivation layer 125 can better protect the underlying structure.

[0093] Specifically, the MOS device also includes a drain 126, which is located on the back side of the semiconductor substrate 110 and forms an electrical connection with the semiconductor substrate 110.

[0094] Example 2

[0095] This embodiment also provides a shielded gate trench MOSFET device, which is fabricated using the preparation method described in Embodiment 1 or other suitable similar methods. For details regarding the fabrication method, materials, and structure of the shielded gate trench MOSFET device, please refer to Embodiment 1. Specifically, since the shielded gate trench MOSFET device can be an N-type device or a P-type device, this embodiment uses an N-type device as an example for detailed explanation. See [link to previous embodiment]. Figure 12 The diagram shows a cross-sectional view of the shielded gate trench MOSFET device, wherein the shielded gate trench 112 type MOSFET device includes:

[0096] A semiconductor substrate 110 and an epitaxial layer 111 disposed on the semiconductor substrate 110; at least one cell unit located in the epitaxial layer 111, the cell unit including trenches 112 spaced apart in a horizontal direction; a shielding gate, the shielding gate including a dielectric material layer 113 and a conductive material layer 114, the dielectric material layer 113 being located on the inner wall and bottom surface of the trench 112, the dielectric material layer 113 wrapping the sidewalls and bottom surface of the conductive material layer 114, the upper surface of the dielectric material layer 113 being lower than the upper surface of the epitaxial layer 111; a trench gate structure, the trench gate structure including a gate dielectric layer 115 and a gate conductive layer 116, the gate dielectric layer 115 being located on the inner wall of the trench 112 and the upper surface of the dielectric material layer 113 and... The trench 112 includes the following components: a sidewall and a bottom surface of the gate conductive layer 116; a second conductivity type body region 117 and a first conductivity type source region 118, wherein the body region 117 is located on the upper surface of the epitaxial layer 111, and the source region 118 is located on the upper surface of the body region 117 and is flush with the upper surface of the trench gate structure; an interlayer dielectric layer 119, located on the upper surface of the source region 118, having a first contact hole 120 and a second contact hole 121 that penetrate the source region 118 and expose the body region 117, the first contact hole 120 and the second contact hole 121 being distributed on both sides of the trench 112; and a source electrode 124, located on the interlayer dielectric layer 119 and filling the first contact hole 120 and the second contact hole 121.

[0097] Specifically, the first contact hole 120 and the second contact hole 121 are both located in the central region of two adjacent grooves 112, and the first contact hole 120 and the second contact hole 121 are arranged alternately in the horizontal direction.

[0098] Specifically, both the second contact hole 121 and the first contact hole 120 are elongated continuous shapes. The lateral width of the second contact hole 121 is equal to the lateral width of the first contact hole 120, and the lateral width of the first contact hole 120 is 0.2~0.3μm, while the lateral width of the second contact hole 121 is 0.4~0.6μm. For example, the lateral width of the first contact hole 120 is 0.2μm, 0.25μm, or 0.3μm, and the lateral width of the second contact hole 121 is 0.4μm, 0.5μm, or 0.6μm. Through this configuration, the channel region of the cell containing the second contact hole 121 has a higher ion concentration, resulting in a higher threshold voltage; the channel region of the cell containing the first contact hole 120 has a lower ion concentration, resulting in a lower threshold voltage. Based on the different threshold voltages between different cells of the shielded gate trench MOSFET device, the shielded gate trench MOSFET device can have the function of sequential activation, and the later-activated channel can also serve as a heat dissipation channel when the earlier-activated channel is operating.

[0099] Specifically, the shielded gate trench MOSFET device also includes a passivation layer 125 and a drain 126, with the drain 126 electrically connected to the bottom surface of the semiconductor substrate 110.

[0100] In summary, a shielded gate trench MOSFET device and its fabrication method involve fabricating elongated, continuous first and second contact holes with different lateral widths, alternating horizontally, in the interlayer dielectric layer of the cell region. The second contact hole has a wider lateral width than the first contact hole, resulting in a higher ion concentration in the channel region of the cell containing the second contact hole, thus leading to a higher threshold voltage. Conversely, the first contact hole has a lower ion concentration in its channel, resulting in a lower threshold voltage. This time-sharing mechanism allows the later-activated cells to act as heat dissipation channels, dispersing heat from the earlier-activated cells. This significantly improves the device's safe operating area (SOA) and heat dissipation capability. Furthermore, this fabrication method only requires adjusting the shape of the contact hole mask pattern, without adding any additional process steps, achieving improved reliability and application range of the MOSFET device at extremely low cost. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0101] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a shielded gate trench MOSFET device, characterized in that, Includes the following steps: A semiconductor substrate having an epitaxial layer is provided, wherein trenches are formed in the epitaxial layer at horizontal intervals, the trenches opening from the upper surface of the epitaxial layer and extending downward; A dielectric material layer and a conductive material layer are sequentially formed in the trench. The dielectric material layer is located on the inner wall and bottom surface of the trench and wraps around the side wall and bottom surface of the conductive material layer. The upper surface of the dielectric material layer is lower than the upper surface of the epitaxial layer. A gate dielectric layer and a gate conductive layer are sequentially formed on the surface of the dielectric material layer, wherein the gate dielectric layer covers the sidewalls of the trench and wraps the sidewalls and bottom surface of the gate conductive layer; Ion implantation is performed on the upper surface of the epitaxial layer on both sides of the trench to form a bulk region, and ion implantation is performed on the upper surface of the bulk region to form a source region; An interlayer dielectric layer is formed on the source region, and the interlayer dielectric layer, the source region and the body region are etched to form a first contact hole and a second contact hole that penetrate the interlayer dielectric layer and the source region and expose the body region. The first contact hole and the second contact hole are distributed on both sides of the trench. Metal is deposited on the interlayer dielectric layer to form a source electrode that fills the first contact hole and the second contact hole.

2. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: The first contact hole and the second contact hole are both located in the central region of two adjacent grooves, and the first contact hole and the second contact hole are arranged alternately in the horizontal direction.

3. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: The lateral width of the second contact hole is greater than the lateral width of the first contact hole.

4. The method for fabricating a shielded gate trench MOSFET device according to claim 3, characterized in that: The first contact hole has a lateral width of 0.2~0.3μm, and the second contact hole has a lateral width of 0.4~0.6μm.

5. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: The upper surfaces of the gate dielectric layer, the gate conductive layer, and the source region are flush.

6. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: After forming the source electrode, the process further includes forming a passivation layer, etching the passivation layer to form metal leads, and forming a drain electrode, wherein the passivation layer is located on the surface of the source electrode, and the drain electrode is electrically connected to the back side of the semiconductor substrate.

7. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: The width of the trench is 0.8~1.2μm, and the ratio of the lateral width of the conductive material layer to the lateral width of the dielectric material layer is 0.5~3.

8. A shielded gate trench MOSFET device, characterized in that, include: A semiconductor substrate and an epitaxial layer disposed on the semiconductor substrate; At least one cell unit is located in the epitaxial layer, the cell unit including trenches spaced apart in the horizontal direction; A shielding grid, comprising a dielectric material layer and a conductive material layer, wherein the dielectric material layer is located on the inner wall and bottom surface of the trench, the dielectric material layer wraps around the sidewall and bottom surface of the conductive material layer, and the upper surface of the dielectric material layer is lower than the upper surface of the epitaxial layer; A trench gate structure, comprising a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer is located on the inner wall of the trench and the upper surface of the dielectric material layer and wraps the sidewalls and bottom surface of the gate conductive layer; A second conductivity type body region and a first conductivity type source region, wherein the body region is located on the upper surface of the epitaxial layer, and the source region is located on the upper surface of the body region and is flush with the upper surface of the trench gate structure; An interlayer dielectric layer is located on the upper surface of the source region. The interlayer dielectric layer has a first contact hole and a second contact hole that penetrate the source region and expose the body region. The first contact hole and the second contact hole are distributed on both sides of the trench. The source electrode is located on the interlayer dielectric layer and fills the first contact hole and the second contact hole.

9. The shielded gate trench MOSFET device according to claim 8, characterized in that: The first contact hole and the second contact hole are both located in the central region of two adjacent grooves, and the first contact hole and the second contact hole are arranged alternately in the horizontal direction.

10. The shielded gate trench MOSFET device according to claim 8, characterized in that: The lateral width of the second contact hole is greater than the lateral width of the first contact hole, and the lateral width of the first contact hole is 0.2~0.3μm, while the lateral width of the second contact hole is 0.4~0.6μm.

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