A high frequency 1.5 frequency division circuit

Abstract

The present invention discloses a high-frequency 1.5 frequency division circuit, which relates to the technical field of frequency division circuits, and includes an upper half path and a lower half path; the upper half path is a frequency division circuit, which is triggered by double edges composed of latches to sample a signal with the same frequency as the sampling signal, and then outputs it to the lower half path; the lower half path plays a role of pulse engulfment, and when the lower half path is turned on, within two cycles, a half-cycle of high-level signals will be engulfed, and only a half-cycle of high-level signals will continue to exist; then the aforementioned half-cycle of high-level signals is sent to the upper half path and ANDed with the output of the upper half; finally, a high-level signal with a period of 1.5 times the original one is obtained, and at this time, the circuit realizes 1.5 frequency division. The present invention optimizes the traditional 1 / 1.5 frequency division circuit and improves its operating frequency. And greatly simplifies the circuit.

Description

Technical Field

[0001] The invention relates to the technical field of frequency division circuits, and in particular to a high-frequency 1.5 frequency division circuit. Background Art

[0002] The 1 / 1.5 frequency division circuit is a commonly used frequency division technique, which can reduce the quantization noise caused by the DSM (Δ-∑ modulator) by half in the phase-locked loop and improve the performance of the phase-locked loop. In the frequency division circuit, it often directly receives the signal from the voltage-controlled oscillator (VCO), so a very high working frequency is required, but due to the limitation of its circuit characteristics, it is difficult to achieve a higher clock frequency. Summary of the invention

[0003] The purpose of the present invention is to provide a high-frequency 1.5-frequency division circuit, which optimizes the architecture of the traditional 1 / 1.5 frequency division circuit, simplifies and integrates some internal key logics, reduces internal delays, and improves the overall operating frequency of the 1 / 1.5 module, which can effectively solve the above-mentioned technical problems.

[0004] To achieve the above object, the present invention provides the following technical solution: a high-frequency 1.5-frequency dividing circuit, the high-frequency 1.5-frequency dividing circuit comprises an upper half path and a lower half path, and both the upper half path and the lower half path have a MUX;

[0005] The upper path is a frequency-dividing circuit, which is triggered by double edges composed of latches to sample a signal with the same frequency as the sampling signal, and then output it to the lower path;

[0006] The lower half of the path plays the role of pulse engulfment. When the lower half of the path is turned on, within two cycles, a half-cycle of the high-level signal will be engulfed, and only a half-cycle of the high-level signal will continue to exist; then the aforementioned half-cycle of the high-level signal is sent to the upper half of the path and ANDed with the output of the upper half; finally, a high-level signal with a period of 1.5 times the original one is obtained, and at this time the circuit realizes 1.5 frequency division;

[0007] Among them, in this high-frequency 1.5-frequency division circuit, the NAND gate and the latch are integrated together to form a dual-input memory, and the balanced structure of the NAND gate can ensure the consistency of the delay of the two paths.

[0008] Preferably, in the high-frequency 1.5-frequency dividing circuit, the MUX in the upper and lower paths adopts a three-state gate method to reduce the delay caused by MUX selection, and uses two inputs of CLK and CLKB at the same time.

[0009] Preferably, in the high-frequency 1.5-frequency dividing circuit, there is only one latch and one MUX delay on both the upper and lower paths, and a frequency input of more than 6 GHz can be achieved under a 28 nm process.

[0010] Preferably, in the high-frequency 1.5-frequency dividing circuit, the EN signal input to the NAND gate in the lower half of the path is a signal obtained by first performing NAND on the external input signal MOD and the Control_code.

[0011] Preferably, in the high frequency 1.5 frequency division circuit, it should be ensured that the load of each input clock is consistent.

[0012] Compared with the prior art, the present invention has the following beneficial effects:

[0013] The high-frequency 1.5 frequency-dividing circuit of the present invention optimizes the traditional 1 / 1.5 frequency-dividing circuit and improves its operating frequency; mainly all NAND gates, inverters, MUX (multiplexer) and latches are simplified to reduce delay; at the same time, the NAND gates and latches are integrated to form a dual-input memory; MUX is realized by a three-state gate method, thereby reducing delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a circuit diagram of a traditional 1 / 1.5 divider.

[0015] Figure 2 This is a circuit structure diagram of the NAND gate and latch combination of the present invention.

[0016] Figure 3 This is a circuit structure diagram of the MUX (multiplexer) of the present invention using a three-state gate.

[0017] Figure 4 It is a schematic diagram of the high frequency 1.5 frequency division circuit structure of the present invention. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] The traditional 1 / 1.5 is mainly composed of a double-edge trigger composed of a latch and a MUX (multiplexer). The traditional 1 / 1.5 circuit consists of two parts, the upper part is mainly a frequency-dividing circuit, which samples a signal with the same frequency as the sampling signal through a double-edge trigger composed of a latch. Then it is output to the lower half of the channel. The lower half is mainly the pulse swallowing function. When the lower half is turned on, within two cycles, half of the high level of the cycle will be swallowed by the swallow, and only half of the high level of the cycle will continue to exist. Then this signal is sent to the upper half of the channel and ANDed with the output of the upper half. In this way, a signal with a period of 1.5 times the original can be obtained, realizing the so-called 1.5 frequency division.

[0020] From the above description, we can see that the main reason for limiting the speed is the setup time and hold time of the latch; and whether the pulse generated by the lower half and the output of the upper half produce the correct signal, that is, the delay between the upper and lower parts.

[0021] The present application mainly simplifies all NAND gates, inverters, MUX (multiplexer), and latches to reduce delay; merges NAND gates with latches to form a dual-input memory; and implements MUX with a tri-state gate to reduce delay.

[0022] Specifically, the present embodiment provides a high-frequency 1.5-frequency dividing circuit, which includes an upper half path and a lower half path, and both the upper half path and the lower half path have a MUX;

[0023] The upper path is a frequency-dividing circuit, which is triggered by double edges composed of latches to sample a signal with the same frequency as the sampling signal, and then output it to the lower path;

[0024] The lower half of the path plays the role of pulse engulfment. When the lower half of the path is turned on, within two cycles, a half-cycle of the high-level signal will be engulfed, and only a half-cycle of the high-level signal will continue to exist; then the aforementioned half-cycle of the high-level signal is sent to the upper half of the path and ANDed with the output of the upper half; finally, a high-level signal with a period of 1.5 times the original one is obtained, and at this time the circuit realizes 1.5 frequency division;

[0025] Among them, in this high-frequency 1.5-frequency division circuit, the NAND gate and the latch are integrated together to form a dual-input memory, and the balanced structure of the NAND gate can ensure the consistency of the delay of the two paths.

[0026] Figure 1It is a traditional 1 / 1.5 frequency divider. You can see that in the upper half of the path, an inverter and an AND gate have a large delay, and the lower half also has two AND gates and an inverter. MOD is the control signal when cascading with other modules, and Control_code is the control signal for selection. These two signals act on the 1.5 frequency divider at the same time.

[0027] Figure 2 As shown, the present invention combines the NAND gate and the latch together, and the balanced structure of the NAND gate can ensure that the delay of the two paths is consistent. Compared with the traditional latch composed of a three-state gate and an inverter, this structure only has one more PMOS or NMOS tube delay, but saves the delay of the entire NAND gate. In addition, Qb can be used for output, saving the delay of the inverter.

[0028] At the same time, the signals of the two external control words, MOD (mode) and Control_code (control word), can be ANDed first and then input into the circuit below, which can save the delay caused by a NAND gate.

[0029] For MUX (multiplexer), the traditional MUX is composed of three NAND gates, but the delay caused by this is too large. Figure 3 As shown, a three-state gate is used to reduce the delay caused by MUX, and two inputs, CLK and CLKB, are used here.

[0030] So in summary we can get Figure 4 The improved circuit has only one latch and one multiplexer delay on each upper and lower path, which can achieve a frequency input of more than 6GHz under the 28nm process.

[0031] Among them, MUX1b is the inverse signal of the output signal after being selected by Q1b and Q2b. The purpose of adding a set of MUX is to save an inverter in the delay. EN is the signal of the external input signal MOD and Control_code first and then the negative. MUX2b is the inverse signal of the pulse generated by the lower half circuit, which also saves an inverter compared to MUX2.

[0032] However, in this circuit, the duty cycle, offset, rising and falling edges of the input clock must be taken into consideration. The load of each input clock should be consistent.

[0033] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0034] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A high frequency 1.5 frequency division circuit, characterized in that: The high frequency 1.5 frequency division circuit comprises an upper half path and a lower half path, and both the upper half path and the lower half path have a Mux; The upper path is a frequency-dividing circuit, which is triggered by double edges composed of latches to sample a signal with the same frequency as the sampling signal, and then output it to the lower path; The lower half of the path plays the role of pulse engulfment. When the lower half of the path is turned on, within two cycles, a half-cycle of the high-level signal will be engulfed, and only a half-cycle of the high-level signal will continue to exist; then the aforementioned half-cycle of the high-level signal is sent to the upper half of the path and ANDed with the output of the upper half; finally, a high-level signal with a period of 1.5 times the original one is obtained, and at this time the circuit realizes 1.5 frequency division; The upper path includes Dlatch1, Dlatch2, Mux_1 and Mux_2; the lower path includes Dlatch3, Dlatch4, Mux_3 and NAND. Dlatch1, Dlatch2, Dlatch3 and Dlatch4 are internal input clocks. The upper input clock is CLKB input, and the lower input clock is CLK input. The Q terminal of Dlatch1 is connected to the input 1 terminal of Mux_2, the Qb terminal is connected to the input 1 terminal of Mux_1, the D terminal of Dlatch1 is connected to the output terminal of Mux_1, the EN terminal of Dlatch1 is connected to the output terminal of Mux_3, the first use terminal of Dlatch1 is connected to the external signal Fvcob, and the second use terminal is connected to the external signal Fvco; The Q end of Dlatch2 is connected to the input 0 end of MUX_2, the Qb end of Dlatch2 is connected to the input 0 end of Mux_1, the input end D of Dlatch2 is connected to the output end of Mux_3, the input end EN of Dlatch2 is connected to the output end of Mux_1, the first use end of Dlatch2 is connected to the external signal Fvco, and the second use end is connected to the external signal Fvcob; The output of Mux_2 is connected to the D terminal of Dlatch3 and the D terminal of Dlatch4, and is also used as the output PIN, which is CLK_OUT; The output Q terminal of Dlatch3 is floating, the Qb terminal is connected to the input 1 terminal of Mux_3, the first use terminal of Dlatch3 is connected to the external signal Fvcob, and the second use terminal is connected to the external signal Fvco; The output Q terminal of Dlatch4 is floating, the Qb terminal is connected to the input 0 terminal of Mux_3, the EN terminal of Dlatch4 is connected to the output of NAND, the first use terminal of Dlatch4 is connected to the external signal Fvco, and the second use terminal of Dlatch4 is connected to the external signal Fvcob; The selection terminals of Mux_1, Mux_2 and Mux_3 are connected to signals Fvco and Fvcob respectively; The input of NAND is external signal MOD and Control_code. After being ANDed, external signal MOD and Control_code form control signal EN and are input to EN terminals of Dlatch3 and Dlatch4. Among them, Dlatch1, 2, 3 and 4 have the same circuit structure, including 3 PMOS tubes, 5 NMOS tubes and two inverters; the PMOS tube has a source on the top, a drain on the bottom, a gate on the left and a substrate on the right; while the NMOS tube has a drain on the top, a source on the bottom, a gate on the left and a substrate on the right; CLKB is connected to the gate of the top PMOS_0, and CLK is connected to the gate of the bottom NMOS_3; The source of PMOS_0 is connected to VDD, and the drain is connected to the sources of PMOS_1 and PMOS_2. The drain of PMOS_1 is connected to the drain of NMOS_0, and the drain of PMOS_2 is connected to the drain of NMOS_1. The source of NMOS_0 is connected to the drain of NMOS_2, the source of NMOS_1 is connected to the drain of NMOS_3, and the sources of NMOS_2 and NMOS_3 are connected to the drain of NMOS_4. The source of NMOS_4 is connected to VSS. The EN terminal is connected to the gates of PMOS_1 and NMOS_0, and then to the gate of NMOS_3; the D terminal is connected to the gates of NMOS_2, NMOS_1, and PMOS_2; The Qb terminal is connected to the drains of PMOS_2 and NMOS_1, and is also connected to the drains of PMOS_1 and NMOS_0; The Qb terminal is connected to the input of INV0 and the output of INV1, the output of INV0 is connected to the input of INV1 and connected to Q; The substrates of all PMOS tubes are connected to VDD, and the substrates of all NMOS tubes are connected to VSS.

2. A high frequency 1.5 frequency division circuit according to claim 1, characterized in that: In this high frequency 1.5 division circuit, it should be ensured that the load of each input clock is consistent.

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