Data Processing Method, Apparatus, Medium and Electronic Device

Abstract

The present application provides a data processing method, apparatus, medium and electronic device. The data processing method includes: obtaining the time difference between the PTP time and the true standard time of the ingress packet timestamp sampling points of the device under test in a preset reference plane (timestamp measurement plane), and the ingress and egress path time sum; processing the time difference between the PTP time and the true standard time, the ingress and egress path time sum and a preset average link delay to obtain the egress delay and the ingress delay in the standard reference plane; verifying the test average link delay associated with the egress delay and the ingress delay based on the preset average link delay to obtain a verification result. The data processing method can quickly and effectively determine the standard reference plane without relying on internal calculations of chip design. And by further verifying the test average link delay and the preset average link delay, the correctness of the determined standard reference plane can be further verified.

Description

Technical Field

[0001] This application belongs to the field of chips and relates to a data processing method, in particular to a data processing method, device, medium and electronic device. Background Art

[0002] Generally, the reference plane of gPTP (generalized Precision Time Protocol) is taken at the connection of the cable and the device. The measurement sampling points of the incoming and outgoing timestamps are usually inside the gPTP device (often the digital part). The values of the ingress delay and egress delay are usually inconsistent. The ingress delay and egress delay include the delay of the analog part and the delay of the digital part. The delay of the digital part of the chip is relatively easy to calculate according to the chip design, but the delay of the analog part is not easy to obtain. The standard reference plane needs to be determined based on the ingress delay and egress delay. Currently, there is a problem that the standard reference plane cannot be correctly and feasibly determined. Summary of the Invention

[0003] The purpose of this application is to provide a data processing method, device, medium and electronic device, which is used to solve the problem that the standard reference plane cannot be correctly and feasibly determined currently.

[0004] In a first aspect, this application provides a data processing method, including: obtaining the time difference between the PTP time and the true standard time at the sampling point of the incoming message timestamp under the gPTP preset reference plane of the device to be tested and the sum of the incoming and outgoing path times, where the preset reference plane is the reference plane where the egress delay and ingress delay of the device to be tested are both 0; processing the time difference between the PTP time and the true standard time, the sum of the incoming and outgoing path times and the preset average link delay to obtain the egress delay and ingress delay under the standard reference plane; verifying the test average link delay associated with the egress delay and the ingress delay based on the preset average link delay to obtain a verification result.

[0005] In the data processing method, by processing the time difference between the PTP time and the true standard time, the sum of the incoming and outgoing path times and the preset average link delay to obtain the egress delay and ingress delay under the standard reference plane, it is possible to quickly and effectively determine the standard reference plane without relying on the internal calculation of the chip design. And by further verifying the test average link delay and the preset average link delay, the correctness of the determined standard reference plane can be further verified.

[0006] In an embodiment of this application, the time difference between the PTP time and the true standard time is expressed as:

[0007]

[0008] Among them, tod_offset represents the time difference between the PTP time and the true standard time, ingressLatency(i) represents the ingress latency under the standard reference plane i, egressLatency(i) represents the egress latency under the standard reference plane i, and the ingressLatency(i)-egressLatency(i) values of all standard reference planes are equal; rr represents the frequency ratio between the Grandmaster and the local clock;

[0009] For all reference planes, the sum of the ingress and egress path times is expressed as:

[0010] sum_time = ingressLatency + egressLatency + 2meanLinkDelay / nrr

[0011] Among them, sum_time represents the sum of the ingress and egress path times under a reference plane, meanLinkDelay represents the preset average link delay under this reference plane, nrr represents the frequency ratio between adjacent nodes, ingressLstency represents the ingress latency under this reference plane, and egressLatency represents the egress latency under this reference plane.

[0012] In an embodiment of the present application, the implementation method for obtaining the sum of the ingress and egress path times includes: obtaining the first moment when the device under test sends a request to the standard gPTP device at the first sending point; obtaining the second moment when the standard gPTP device receives the request at the first receiving point; obtaining the third moment when the standard gPTP device sends a response at the second sending point; obtaining the fourth moment when the device under test receives the response at the second receiving point; and obtaining the sum of the ingress and egress path times based on the first moment, the second moment, the third moment, the fourth moment, and the frequency ratio between adjacent nodes.

[0013] In an embodiment of the present application, the sum of the ingress and egress path times is expressed as:

[0014] sum_time = (t4 - t1) - (t3 - t2) / nrr

[0015] Among them, sum_time represents the sum of the ingress and egress path times, t4 represents the fourth moment, t1 represents the first moment, t3 represents the third moment, t2 represents the second moment, and nrr represents the frequency ratio between adjacent nodes.

[0016] At the same time, from a process perspective, the ingress and egress path time is the sum of the ingress latency, the egress latency, and twice the link latency:

[0017] It can be obtained that meanLinkDelay / nrr = (sum_time - ingressLatency - egressLatency) / 2. In an embodiment of the present application, the PTP time schedule is expressed as:

[0018] rx_point_tod′ = t0 + rr×(meanLinkDelay′ / nuu + ingressLatency′)

[0019] = t0 + rr×(sumtime + ingressLatency′ - egressLatency′) / 2

[0020] Wherein, rx_point_tod′ represents the PTP time, t0 represents the time when the standard gPTP device sends a synchronization message, sumtime represents the sum of the ingress and egress path times, ingressLatency′ represents the ingress delay under the preset reference plane, and egressLatency′ represents the egress delay under the preset reference plane;

[0021] The true standard time is expressed as:

[0022] rx_point_tod = t0 + rr×(sum_time + delta_latency) / 2

[0023] Wherein, rx_point_tod represents the true standard time, and delta_latency represents the fixed delay difference between the ingress delay and the egress delay of all standard reference planes;

[0024] The standard reference plane delay difference is expressed as:

[0025] delta_latency = ingressLatency(i) - egressLatency(i)

[0026] In an embodiment of the present application, the implementation method for obtaining the time difference between the PTP time of the ingress message timestamp sampling point of the device under test under the preset reference plane and the true standard time includes: obtaining the time difference between the rising edge of 1PPS of the device under test and the standard gPTP device, and the time difference between the rising edge of 1PPS of the device under test and the standard gPTP device is obtained by the oscilloscope measuring the device under test and the standard gPTP device; based on the time difference between the rising edge of 1PPS of the device under test and the standard gPTP device, obtaining the time difference between the PTP time and the true standard time.

[0027] In an embodiment of the present application, a method for verifying the test average link delay associated with the egress delay and the ingress delay based on the preset average link delay to obtain a verification result includes: obtaining the test average link delay, which is obtained by running the gPTP protocol stack to test the time difference between the rising edge of 1PPS of the device under test and the standard gPTP device according to the egress delay and the ingress delay; if the difference between the test average link delay and the preset average link delay is within a preset error range, the verification result is verification passed, otherwise the verification result is verification failed.

[0028] In a second aspect, the present application provides a data processing device, including: a time difference acquisition module, configured to acquire the time difference between the PTP time of the ingress packet timestamp sampling point of the device under test under a preset reference plane and the true standard time, and the sum of the ingress and egress path times, where the preset reference plane is a reference plane where both the egress delay and the ingress delay of the device under test are 0; a delay acquisition module, configured to process the time difference between the PTP time and the true standard time, the sum of the ingress and egress path times, and the preset average link delay to obtain the egress delay and the ingress delay under the standard reference plane; a delay verification module, configured to verify the test average link delay associated with the egress delay and the ingress delay based on the preset average link delay to obtain a verification result.

[0029] In a third aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the data processing method according to any one of the first aspects of the present application.

[0030] In a fourth aspect, the present application provides an electronic device, where the electronic device includes: a memory storing a computer program; a processor communicatively connected to the memory, and when the computer program is called, it executes the data processing method according to any one of the first aspects of the present application.

[0031] As described above, the data processing method, device, medium, and electronic device of the present application have the following beneficial effects:

[0032] In the data processing method, by processing the time difference between the PTP time and the true standard time, the sum of the ingress and egress path times, and the preset average link delay to obtain the egress delay and the ingress delay under the standard reference plane, it is possible to quickly and effectively determine the standard reference plane without relying on internal calculations of chip design. And by further verifying the test average link delay and the preset average link delay, it is possible to further verify the correctness of the determined standard reference plane. Description of the Drawings

[0033] Figure 1It shows a schematic diagram of the hardware structure of the data processing method according to the embodiments of the present application.

[0034] Figure 2 It shows a flowchart of the data processing method according to the embodiments of the present application.

[0035] Figure 3 It shows a schematic diagram of time synchronization between the standard gPTP device and the device under test according to the embodiments of the present application.

[0036] Figure 4 It shows a flowchart of the implementation method for obtaining the sum of the in-out path times according to the embodiments of the present application.

[0037] Figure 5 It shows a flowchart of the implementation method for obtaining the time difference between the PTP time and the true standard time of the ingress packet timestamp sampling point of the device under test under the first reference plane according to the embodiments of the present application.

[0038] Figure 6 It shows a schematic diagram of the time difference between the rising edges of 1PPS of the device under test and the standard gPTP device measured by an oscilloscope according to the embodiments of the present application.

[0039] Figure 7 It shows a flowchart of the data processing method according to the embodiments of the present application.

[0040] Figure 8 It shows a schematic diagram of the rising edges of 1PPS of the standard gPTP device and the device under test measured by an oscilloscope under the standard reference plane according to the embodiments of the present application.

[0041] Figure 9 It shows a schematic diagram of inconsistent link transceiver time delays according to the embodiments of the present application.

[0042] Figure 10 It shows a schematic diagram of the structure of the data processing device according to the embodiments of the present application.

[0043] Description of Component Labels

[0044] 10 Computing device

[0045] 110 Memory

[0046] 120 Processor

[0047] 130 Bus

[0048] 140 Access device

[0049] 150 Database

[0050] 1000 Data processing device

[0051] 1010 Time difference acquisition module

[0052] 1020 Delayed acquisition module

[0053] 1030 Delayed verification module

[0054] Steps S11 - S13

[0055] Steps S21 - S25

[0056] Steps S31 - S32

[0057] Steps S41 - S42 Detailed implementation manners

[0058] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0059] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. Therefore, only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0060] The following combines the accompanying drawings in the embodiments of the present application to describe the technical solutions in the embodiments of the present application in detail.

[0061] The data processing method provided by the embodiments of the present application can run on a computer device. Taking Figure 1 as an example, Figure 1 is a hardware structure block diagram of a computing device for running the data processing method. The computing device 10 includes but is not limited to a memory 110 and a processor 120. The processor 120 is connected to the memory 110 through a bus 130, and the database 150 is used to store data.

[0062] The computing device 10 further includes an access device 140, which enables the computing device 10 to communicate via one or more networks 160. Examples of such networks include the public switched telephone network, local area network, wide area network, personal area network, or a combination of communication networks such as the Internet. The access device 140 may include any type of wired or wireless network interface, for example, one or more of network interface cards, such as IEEE802.11 wireless local area network wireless interfaces, worldwide interoperability for microwave access interfaces, Ethernet interfaces, universal serial bus interfaces, cellular network interfaces, Bluetooth interfaces, near field communication interfaces, and so on.

[0063] In an embodiment of the present application, the above components of the computing device 10 and Figure 1 other components not shown may also be connected to each other, for example, via a bus. It should be understood that Figure 1 the block diagram of the computing device shown is only for illustrative purposes and is not a limitation on the scope of the present application. Those skilled in the art can add or replace other components as needed.

[0064] The computing device 10 can be any type of stationary or mobile computing device, including mobile computers or mobile computing devices (e.g., laptop computers, notebook computers, netbooks, etc.) or other types of mobile devices, or stationary computing devices such as desktop computers or PCs. The computing device 10 can also be a mobile or stationary server.

[0065] As Figure 2 shown, this embodiment provides a data processing method, including:

[0066] S11, obtaining the time difference between the PTP time of the ingress message timestamp sampling point of the device under test and the true standard time and the sum of the ingress and egress path times under a preset reference plane, where the preset reference plane is a reference plane with both the egress delay and the ingress delay of the device under test being 0.

[0067] Optionally, please refer to Figure 3 , Figure 3It shows a schematic diagram of time synchronization between a standard gPTP device and a device under test. In the device under test, there may be a message sending point A and a message receiving point D. The egress delay of the device under test may refer to the delay from the message sending point in the device under test to the reference plane, and the ingress delay of the device under test may refer to the delay from the reference plane to the message receiving point in the device under test. The egress delay and the ingress delay are associated with the reference plane. The sum of the ingress and egress path times may refer to the sum of the path time of the message from the standard gPTP device into the device under test and the path time of the message from the device under test to the standard gPTP device. For any reference plane, the sum of the ingress and egress path times is fixed. The ingress message timestamp sampling point may refer to the timestamp sampling point when the message enters the preset reference plane. The timestamp sampling point may refer to the time value that marks the data at a specific moment.

[0068] Optionally, when the synchronization process is correct, the PTP (Precision Timing Protocol) time is either the true standard time (Grandmaster uses the true standard time to synchronize the gPTP domain) or the standard time within the gPTP domain (Grandmaster uses his own time or a certain time source to synchronize the gPTP domain). All nodes within the same gPTP domain use the same standard time, and the PTP time is used to represent the PTP time calculated according to the gPTP protocol. The preset reference plane is also the timestamp measurement plane. The true standard time is the actual standard time, which can be the time of Grandmaster itself or a certain time source within the gPTP domain.

[0069] S12. Process the time difference between the PTP time and the true standard time, the sum of the ingress and egress path times, and the preset average link delay to obtain the egress delay and the ingress delay under the standard reference plane.

[0070] Optionally, the preset average link delay may refer to the preset average link delay under the standard reference plane, and the preset average link delay can be flexibly set according to the actual situation. This embodiment does not specifically limit it. For example, the preset average link delay can be 31 ns.

[0071] Optionally, there may be multiple standard reference planes. By setting different preset average link delays, the egress delay and the ingress delay of different standard reference planes can be obtained. The specific preset average link delay value is associated with the standard reference plane, and this embodiment will not elaborate further. The standard reference plane may refer to the plane where the PTP protocol can work correctly. Please refer to Figure 3, the standard reference plane 0 refers to the plane that demarcates the PTP port and the network link. The standard reference plane i can be a reference plane obtained by translating the standard reference plane 0 in parallel. The reference plane’ can be directly using the measurement plane as the reference plane, that is, the preset reference plane, which is usually a non-standard reference plane, unless the ingress delay is equal to the egress delay.

[0072] Preferably, the preset average link delay can be greater than the sum of the time stamps of the device under test and the standard gPTP device. The time stamp can be expressed as tick. For example, the tick value of the device under test is 5ns, the tick value of the gPTP device is 8ns, and the preset average link delay can be greater than 13ns.

[0073] Optionally, the time difference between the PTP time and the true standard time is expressed as:

[0074]

[0075] where tod_offset represents the time difference between the PTP time and the true standard time, ingressLatency(i) represents the ingress delay under the standard reference plane i, egressLatency(i) represents the egress delay under the standard reference plane i, and the ingressLatency(i) - egressLatency(i) values of all the standard reference planes are equal. rr, that is, rateRatio, represents the frequency ratio between the Grandmaster clock and the local clock. Among them, the value of rr is generally close to 1, and in this embodiment, the value of rr is regarded as 1.

[0076] For all the reference planes, that is, including the standard reference plane and the non-standard reference plane, the sum of the ingress and egress path times is expressed as:

[0077] sum_time = ingressLatency + egressLatency + 2meanLinkDelay / nrr

[0078] From a process perspective, the ingress and egress path time is the sum of the ingress delay, the egress delay, and twice the delay on the link.

[0079] Among them, the average link delay can be calculated as follows:

[0080] meanLinkDelay = [sum_time - egressLatency - ingressLatency] × nrr / 2

[0081] where sum_time represents the sum of the ingress and egress path times, and meanLinkDelay is the reference plane, that isFigure 3 The preset average link delay calculated under the Reference plane(k) (whether standard or non-standard reference plane), where nrr, i.e., neighborRateRatio, represents the frequency ratio between adjacent nodes.

[0082] Optionally, the PTP time under the refernce plane’ is expressed as:

[0083] rx_point_tod′ = t0 + rr × (sum_time + ingressLatency′ - egressLatency′) / 2

[0084] Where rx_point_tod′ represents the PTP time, t0 represents the time when the standard gPTP device sends a synchronization message, i.e., sync, sumtime represents the sum of the ingress and egress path times, ingressLatency′ represents the ingress latency under the preset reference plane, and egressLatency′ represents the egress latency under the preset reference plane. Since both the ingress latency under the preset reference plane and the egress latency under the preset reference plane are 0, the PTP time can be further expressed as:

[0085] rx_point_tod′ = t0 + rr × sum_time / 2

[0086] The true standard time is expressed as:

[0087] rx_point_tod = t0 + rr × (sum_time + delta_latency) / 2

[0088] Where rx_point_tod represents the true standard time, and delta_latency represents the fixed latency difference between the ingress latency and the egress latency of all standard reference planes.

[0089] The fixed latency difference can be expressed as:

[0090] delta_latency = ingressLatency(0) - egressLatency(0)

[0091] The PTP time can be expressed as:

[0092] rx_point_tod′ = rx_point_tod - rr × delta_latency / 2

[0093] When the device under test adopts the preset reference plane, there will be a deviation of rr×delta_latency / 2 between the PTP time and the true standard time. Since the choice of the reference plane does not affect the calculation of nrr and rr, this deviation is the time difference tod_offset between the PTP time and the true standard time, and tod_offset can be further expressed as:

[0094] tod_offset = rr×delta_latency / 2

[0095] Optionally, under the preset reference plane (measurement plane, with both configured ingressLatency′ and egressLatency’ being 0), the value of meanLinkDelay’ calculated through the gPTP protocol stack (using the peer-to-peer delay mechanism) is 361ns. Since both egressLatency′ and egressLatency’ are 0 and nrr is close to 1, the round-trip path time is approximately 762ns. The time difference (tod_offset) between the PTP time and the true standard time measured by the oscilloscope is 80ns. Taking a standard reference plane i with a certain link delay of 31ns (meanLinkDelay(i)), a system of linear equations can be solved according to the following formula, and the ingress latency of the standard reference plane i can be configured to be 420ns, and the egress latency can be 260ns.

[0096] ingressLatency(i) + egressLatency(i) = sum_time - 2×meanLinkDelay(i) / nrringressLatency(i) - egressLatency(i) = 2×tod_offset / rr

[0097] Optionally, if the standard reference plane 0 needs to be configured, the following method can be used to obtain the sum of the ingress latency and the egress latency:

[0098] 1. Estimate the cable length and the delay on the cable (cable length m * 5ns). Subtract twice the cable delay from the measured round-trip path time to obtain the sum of the ingress latency and the egress latency of the standard reference plane 0.

[0099] 2. Short-circuit the external port of the device under test and loop it back, then send and receive packets by itself. The received packet timestamp minus the sent packet timestamp is the sum of the ingress latency and the egress latency of the standard reference plane 0.

[0100] Optionally, if the standard gPTP device is the top-level master clock, i.e., the Grandmaster, and the distributed time is its local time, then rr is the same as nrr.

[0101] Optionally, if the device under test sends the time t0 in the sync message as the master clock node, i.e., the master, and the standard gPTP device is the slave clock node, i.e., the slave, then the PTP time of the sync received by the standard gPTP device is calculated as:

[0102] t0 + [meanLinkDelay(i) / nrr + egressLatency(i)] × rr = t0 + rr × [sum_time - ingressLatency(i) + egressLatency(i)] / 2. Similarly, when ensuring that delta_latency = ingressLatency(i) - egressLatency(i), the standard gPTP device can also obtain the correct PTP standard time.

[0103] S13. Based on the preset average link delay, verify the test average link delay associated with the egress delay and the ingress delay to obtain a verification result.

[0104] Optionally, the selection of the reference plane does not affect the calculation of nrr and rr of the device under test.

[0105] Optionally, the test average link delay may refer to the average link delay measured by running the gPTP protocol stack after calculating and configuring the egress delay and the ingress delay based on the 1PPS rising edge time difference tested under the preset reference plane. For example, under the preset reference plane, the value of meanLinkDelay’ measured by the gptp protocol stack is 361 ns, and the time difference between the 1PPS rising edge of the device under test and the standard device tested by the oscilloscope is 80 ns. Then, taking the preset average link delay as 31 ns, calculating the configured import delay of 420 ns and the egress delay of 260 ns, and running the gPTP protocol stack, the measured average link delay jitters between 31 ns and 32 ns, which is very close to 31 ns, indicating that the test average link delay is basically consistent with the preset average link delay.

[0106] Optionally, the verification result is either verification passed or verification failed. The implementation method for verifying the test average link delay associated with the egress delay and the ingress delay to obtain the verification result includes: when the difference between the test average link delay and the preset average link delay is within a preset error range, the verification result is verification passed; otherwise, the verification result is verification failed. The preset error range can be flexibly set according to the actual situation, for example, within a range of plus or minus 5 ns.

[0107] According to the above description, the data processing method described in this embodiment includes: obtaining the time difference between the PTP time of the ingress packet timestamp sampling point of the device under test in the gPTP preset reference plane and the true standard time, and the sum of the ingress and egress path times, where the preset reference plane is the reference plane with both the egress delay and the ingress delay of the device under test being 0; processing the time difference between the PTP time and the true standard time, the sum of the ingress and egress path times, and the preset average link delay to obtain the egress delay and the ingress delay in the standard reference plane; and verifying the test average link delay associated with the egress delay and the ingress delay based on the preset average link delay to obtain the verification result.

[0108] In the data processing method, by processing the time difference between the PTP time and the true standard time, the sum of the ingress and egress path times, and the preset average link delay to obtain the egress delay and the ingress delay in the standard reference plane, it is possible to quickly and effectively determine the standard reference plane without relying on the internal calculation of the chip design. And by further verifying the test average link delay and the preset average link delay, it is possible to further verify the correctness of the determined standard reference plane.

[0109] As Figure 4 shown, this embodiment provides an implementation method for obtaining the sum of the ingress and egress path times, including:

[0110] S21, obtaining the first moment when the device under test sends a request to the standard gPTP device at the first sending point.

[0111] Optionally, the request may refer to a path delay request, i.e., PDelay_Req.

[0112] S22, obtaining the second moment when the standard gPTP device receives the request at the first receiving point.

[0113] S23, obtaining the third moment when the standard gPTP device sends a response to the standard gPTP device at the second sending point.

[0114] Optionally, the response may refer to a path delay response, i.e., PDelay_Resp. The path delay response includes the second moment.

[0115] Optionally, the implementation method for obtaining the third moment when the standard gPTP device sends a response at the second sending point includes: obtaining the path delay response follow-up, i.e., PDelay_Resp_Follow_up, sent by the gPTP device to the standard gPTP device, and the path delay response follow-up includes the third moment.

[0116] S24. Obtain the fourth moment when the device under test receives the response at the second receiving point.

[0117] S25. Based on the first moment, the second moment, the third moment, the fourth moment, and the frequency ratio between adjacent nodes, obtain the sum of the in-and-out path times.

[0118] Optionally, refer to Figure 3 , the egress delay from the first sending point to the first standard reference plane, i.e., Reference plane(0), in the device under test is different from the ingress delay from the second receiving point to the first standard reference plane. The first standard reference plane may be the standard reference plane at the connection of the cable and the PTP device. The first sending point is Figure 3 Point A in Figure 3 Point B in Figure 3 Point C in Figure 3 Point D in Figure 3 t1 in Figure 3 t2 in Figure 3 t3 in Figure 3 t4 in Figure 3 Golden gPTPDevice in

[0119] Optionally, on the standard reference plane Reference plane(0), the delays on the transceiver lines are equal, both being meanLinkDelay(0). ingressLatency(0) - egressLatency(0) can be denoted as delta_latency. When ensuring that for any standard reference plane i, i.e., Reference plane(i), ingressLatency(i) - egressLatency(i) = delta_Latency, that is, ingressLatency(0) - egressLatency(0), then the PTP time at the ingress packet timestamp sampling point is the true standard time, which is expressed as: t0 + rr × (sum_time + delta_latency) / 2. t0 can be the PTP global time, i.e., PTP global time.

[0120] Optionally, since the selection of the reference plane does not affect the calculation of nrr and rr of the device under test, after the device under test obtains the true standard time and sets this time as the PTP time, the PTP time will be synchronized with the true standard time. That is to say, the reference plane Reference plane(n) obtained by translating Reference plane(0) downward (within the range) is correct and feasible. Translating Reference plane(0) downward is equivalent to putting a part of the equal device memory delays in both the outgoing and incoming directions onto the link delay. It is even possible to translate it downward beyond the range. In this case, ingressLatency(i) and egressLatency(i) will become negative.

[0121] Optionally, Figure 3 Reference plane(0) in Figure 3 is a standard reference plane. Due to the maximum error of the timestamp sampling point approaching one tick, if the timestamp sampling is rounded down to obtain the tick value, then

[0122] Optionally, the sum of the ingress and egress path times is expressed as:

[0123] sum_time = (t4 - t1) - (t3 - t2) / nrr

[0124] Wherein, sum_time represents the sum of the in - out path times, t4 represents the fourth moment, t1 represents the first moment, t3 represents the third moment, t2 represents the second moment, and nrr represents the frequency ratio between adjacent nodes.

[0125] Optionally, the average link delay under the preset reference plane can be expressed as:

[0126] meanLinkDelay′ = (nrr × (t4 - t1) - (t3 - t2)) / 2

[0127] Optionally, the value of nrr is close to 1. In this embodiment, the value of nrr can take an approximate value of 1 to calculate the in - out port delay.

[0128] As Figure 5 shown, this embodiment provides a method for obtaining the time difference between the PTP time and the true standard time of the ingress packet timestamp sampling point of the device under test under the preset reference plane, including:

[0129] S31, obtaining the time difference between the rising edge of 1PPS of the device under test and the standard gPTP device, and the time difference between the rising edge of 1PPS of the device under test and the standard gPTP device is obtained by the oscilloscope measuring the device under test and the standard gPTP device.

[0130] Optionally, if the device under test and the standard gPTP device do not support 1PPS, then 1PPS can be simulated. According to the deviation between the PTP time and the local time of the device itself, calculate the local tick value corresponding to the next whole second of the future PTP time, and then set the device to output a pulse at the corresponding local tick value.

[0131] Optionally, during actual measurement, the rising edge of 1PPS of the standard gPTP device can be used as a reference, and the center line of the jitter range of the rising edge of 1PPS of the device under test can be taken to calculate the time difference between the rising edge of 1PPS of the device under test and the standard gPTP device. Please refer to Figure 6 , Figure 6 shown as the time difference between the rising edge of 1PPS of the device under test and the standard gPTP device obtained by the oscilloscope measuring the device under test and the standard gPTP device. The rising edge of 1PPS of the device under test is after the standard gPTP device, that is, the PTP time of the device under test is smaller than the standard time. Figure 6 The time difference in

[0132] S32. Obtain the time difference between the PTP time and the true standard time based on the time difference between the rising edges of 1PPS of the device under test and the standard gPTP device.

[0133] Optionally, the time difference between the rising edges of 1PPS of the device under test and the standard gPTP device can be the time difference between the PTP time and the true standard time.

[0134] As Figure 7 shown, this embodiment provides an implementation method for verifying the test average link delay associated with the egress delay and the ingress delay based on the preset average link delay to obtain a verification result, including:

[0135] S41. Obtain the test average link delay, which is obtained by running the gPTP protocol stack to test the time difference between the rising edges of 1PPS of the device under test and the standard gPTP device according to the egress delay and the ingress delay.

[0136] Optionally, please refer to Figure 8 , Figure 8 which shows a schematic diagram of the rising edges of 1PPS of the standard gPTP device and the device under test measured by an oscilloscope under a standard reference plane. According to Figure 8 it can be known that the rising edges of 1PPS of the device under test and the standard gPTP device are almost the same.

[0137] S42. If the difference between the test average link delay and the preset average link delay is within the preset error range, the verification result is verification passed; otherwise, the verification result is verification failed.

[0138] Optionally, the comparison result can include comparison passed or comparison failed. When the difference between the test average link delay and the preset average link delay is within the preset range, the comparison result is comparison passed; when the difference between the test average link delay and the preset average link delay is not within the preset range, the comparison result is comparison failed. The preset range can be flexibly set according to the actual situation, and this embodiment will not elaborate on it.

[0139] In an embodiment of the present application, please refer to Figure 9 , Figure 9It is a schematic diagram showing inconsistent link transceiver time delays. In the case of inconsistent link transceiver time delays, that is, when delayAsymmetry is not 0, since the asymmetry on the link in the data processing method has been added to the ingress delay and egress delay, under the data processing method, delayAsymmetry does not need to be considered and can be regarded as 0. In addition, if the ingress delay and the egress delay are to be common to all cables, when performing standard tests, cables with consistent link transceiver times need to be used to measure and calculate a pair of common ingress delay and egress delay values.

[0140] The protection scope of the data processing method described in the embodiments of this application is not limited to the execution order of the steps listed in this embodiment. Any solution achieved by adding or reducing steps of the prior art and replacing steps according to the principles of this application is included in the protection scope of this application.

[0141] As Figure 10 shown, this embodiment provides a data processing apparatus 1000, and the data processing apparatus 1000 includes:

[0142] A time difference acquisition module 1010, configured to acquire the time difference between the PTP time of the ingress packet timestamp sampling point of the device under test and the true standard time and the ingress and egress path time sum under a preset reference plane, where the preset reference plane is a reference plane where the egress delay and the ingress delay of the device under test are both 0.

[0143] A delay acquisition module 1020, configured to process the time difference between the PTP time and the true standard time, the ingress and egress path time sum, and a preset average link delay to obtain the egress delay and the ingress delay under the standard reference plane.

[0144] A delay verification module 1030, configured to verify the test average link delay associated with the egress delay and the ingress delay based on the preset average link delay to obtain a verification result.

[0145] In the data processing apparatus 1000 provided in this embodiment, the time difference acquisition module 1010 corresponds one-to-one with Figure 2 step S11 of the data processing method shown in Figure 2 step S12 of the data processing method shown in Figure 2 step S13 of the data processing method shown in

[0146] In several embodiments provided in this application, it should be understood that the disclosed device or method can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules / units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of devices or modules or units can be in electrical, mechanical or other forms.

[0147] The modules / units described as separate components may or may not be physically separated. The components shown as modules / units may or may not be physical modules, that is, they can be located in one place or distributed to multiple network units. Some or all of the modules / units can be selected according to actual needs to achieve the objectives of the embodiments of this application. For example, in each embodiment of this application, the various functional modules / units can be integrated in a processing module, or each module / unit can exist physically alone, or two or more modules / units can be integrated in one module / unit.

[0148] Those of ordinary skill in the art should also further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0149] This embodiment provides an electronic device, the electronic device includes a memory storing a computer program; a processor communicatively connected to the memory and executing when calling the computer program Figure 2 the data processing method shown.

[0150] The embodiments of the present application also provide a computer-readable storage medium. Those of ordinary skill in the art can understand that all or part of the steps in the methods of the above embodiments can be completed by instructing a processor through a program. The program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as random access memory, read-only memory, flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disc, and any combination thereof. The above storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center integrating one or more available media. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, or a magnetic tape), an optical medium (such as a digital video disc (DVD)), or a semiconductor medium (such as a solid-state disk (SSD)).

[0151] The embodiments of the present application can also provide a computer program product, which includes one or more computer instructions. When the computer instructions are loaded and executed on a computing device, all or part of the processes or functions described in the embodiments of the present application are generated. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from a website, a computer, or a data center to another website, a computer, or a data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or a wireless manner (such as infrared, wireless, microwave, etc.).

[0152] When the computer program product is executed by a computer, the computer executes the method described in the foregoing method embodiments. The computer program product can be a software installation package. In the case where the foregoing method is required, the computer program product can be downloaded and executed on the computer.

[0153] The descriptions of the processes or structures corresponding to the above respective drawings each have their own emphases. For parts not detailed in a certain process or structure, reference can be made to the relevant descriptions of other processes or structures.

[0154] The above embodiments are only illustrative of the principles and effects of the present application and are not used to limit the present application. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those of ordinary skill in the art in the technical field without departing from the spirit and technical ideas disclosed by the present application should still be covered by the claims of the present application.

Claims

1. A data processing method, characterized in that: include: Obtain the time difference between the PTP time of the incoming message timestamp sampling point of the device under test under a preset reference plane and the real standard time, as well as the ingress and egress path time, wherein the preset reference plane is a reference plane in which the egress delay and the ingress delay of the device under test are both 0; Processing the time difference between the PTP time and the real standard time, the ingress and egress path time, and the preset average link delay to obtain the egress delay and the ingress delay under the standard reference plane; Based on the preset average link delay, verifying the test average link delay associated with the egress delay and the ingress delay to obtain a verification result; The implementation method of obtaining the entry and exit path time includes: obtaining the first moment when the device under test sends a request to the standard gPTP device at the first sending point; obtaining the second moment when the standard gPTP device receives the request at the first receiving point; obtaining the third moment when the standard gPTP device sends a response at the second sending point; obtaining the fourth moment when the device under test receives the response at the second receiving point; based on the first moment, the second moment, the third moment, and the fourth moment, obtaining the entry and exit path time; The entry and exit path time and expression are: sum_time=(t4-t1)-(t3-t2) Wherein, sum_time represents the entry and exit path time, t4 represents the fourth moment, t1 represents the first moment, t3 represents the third moment, and t2 represents the second moment; The method for obtaining the time difference between the PTP time of the entry message timestamp sampling point of the device under test under a preset reference plane and the real standard time includes: obtaining the time difference between the rising edges of 1PPS of the device under test and the standard gPTP device, the time difference between the rising edges of 1PPS of the device under test and the standard gPTP device being obtained by measuring the device under test and the standard gPTP device with an oscilloscope; based on the time difference between the rising edges of 1PPS of the device under test and the standard gPTP device, obtaining the time difference between the PTP time and the real standard time; The time difference between the PTP time and the real standard time is expressed as: Among them, tod _ offset represents the time difference between the PTP time and the real standard time, ingressLatency(i) represents the ingress delay under the standard reference plane i, and egressLatency(i) represents the egress delay under the standard reference plane i. The values ​​of ingressLatency(i)-egressLatency(i) of all standard reference planes are equal. The ingress delay and egress delay under the standard reference plane i are obtained according to the following binary linear equation: ingressLatency(i)+egressLatency(i)=sum_time-2×meanLinkDelay(i) ingressLatency(i)-egressLatency(i)=2×tod_offset Wherein, meanLinkDelay(i) is the preset average link delay under the standard reference plane i.

2. The data processing method according to claim 1, characterized in that: The PTP time is expressed as: rx_point_tod′=t0+(sumtime+ingressLatency′-egressLatency′) / 2 Among them, rx_point_tod′ represents the PTP time, t0 represents the time when the standard gPTP device sends the synchronization message, sumtime represents the ingress and egress path time, ingressLatency′ represents the ingress delay under the preset reference plane, and egressLatency′ represents the egress delay under the preset reference plane; The real standard time is expressed as: rx_point_tod=t0+(sum_time+delta_latency) / 2 Wherein, rx_point_tod represents the real standard time, delta_latency represents the fixed delay difference between the ingress delay and the egress delay of all standard reference planes; The delay difference is expressed as: delta_latency=ingressLatency(i)-egressLatency(i) The PTP time represents the time calculated according to the gPTP protocol. When the synchronization process is correct, the PTP time is the real standard time. The real standard time is the top master clock Grandmaster, the standard gPTP device is the Grandmaster, and the distributed time is its local time.

3. The data processing method according to claim 2, characterized in that: The implementation method of verifying the test average link delay associated with the egress delay and the ingress delay based on the preset average link delay to obtain a verification result includes: Obtain the test average link delay, where the test average link delay is obtained by running the gPTP protocol stack to test the time difference between the rising edges of 1PPS of the device under test and the standard gPTP device according to the exit delay and the entry delay; If the difference between the tested average link delay and the preset average link delay is within a preset error range, the verification result is verification passed; otherwise, the verification result is verification failed.

4. A data processing device, characterized in that: include: A time difference acquisition module is used to obtain the time difference between the PTP time of the incoming message timestamp sampling point of the device under test and the real standard time under a preset reference plane, and the in-and-out path time, wherein the preset reference plane is a reference plane in which the egress delay and the ingress delay of the device under test are both 0; A delay acquisition module, used to process the time difference between the PTP time and the real standard time, the ingress and egress path time and the preset average link delay to obtain the egress delay and the ingress delay under the standard reference plane; A delay verification module, configured to verify the test average link delay associated with the egress delay and the ingress delay based on the preset average link delay to obtain a verification result; The implementation method of obtaining the entry and exit path time includes: obtaining the first moment when the device under test sends a request to the standard gPTP device at the first sending point; obtaining the second moment when the standard gPTP device receives the request at the first receiving point; obtaining the third moment when the standard gPTP device sends a response at the second sending point; obtaining the fourth moment when the device under test receives the response at the second receiving point; based on the first moment, the second moment, the third moment, and the fourth moment, obtaining the entry and exit path time; The entry and exit path time and expression are: sum_time=(t4-t1)-(t3-t2) Wherein, sum_time represents the entry and exit path time, t4 represents the fourth moment, t1 represents the first moment, t3 represents the third moment, and t2 represents the second moment; The method for obtaining the time difference between the PTP time of the entry message timestamp sampling point of the device under test under a preset reference plane and the real standard time includes: obtaining the time difference between the rising edges of 1PPS of the device under test and the standard gPTP device, the time difference between the rising edges of 1PPS of the device under test and the standard gPTP device being obtained by measuring the device under test and the standard gPTP device with an oscilloscope; based on the time difference between the rising edges of 1PPS of the device under test and the standard gPTP device, obtaining the time difference between the PTP time and the real standard time; The time difference between the PTP time and the real standard time is expressed as: Among them, tod _ offset represents the time difference between the PTP time and the real standard time, ingressLatency(i) represents the ingress delay under the standard reference plane i, and egressLatency(i) represents the egress delay under the standard reference plane i. The values ​​of ingressLatency(i)-egressLatency(i) of all standard reference planes are equal. The ingress delay and egress delay under the standard reference plane i are obtained according to the following binary linear equation: ingressLatency(i)+egressLatency(i)=sum_time-2×meanLinkDelay(i) ingressLatency(i)-egressLatency(i)=2×tod_offset Wherein, meanLinkDelay(i) is the preset average link delay under the standard reference plane i.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data processing method according to any one of claims 1 to 3 is implemented.

6. An electronic device, characterized in that: The electronic device comprises: A memory storing a computer program; A processor is communicatively connected to the memory and executes the data processing method according to any one of claims 1 to 3 when calling the computer program.

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