A method, device, storage medium and electronic device for implementing synchronous multithreading

Abstract

The present invention proposes a synchronous multithreading implementation method, device, storage medium and electronic device, which obtains the renaming information of the target instruction, wherein the target instruction is the instruction transmitted by the target thread under the current clock, and the renaming information includes the mapping relationship between the architecture register and the physical register in the target instruction; updates the target speculative renaming mapping table according to the obtained renaming information; writes the renaming information into the target exclusive renaming record queue or the thread shared renaming record queue, wherein the target exclusive renaming record queue is the exclusive renaming record queue of the target thread. According to the characteristics of synchronous multithreading, the sharable resources are shared with different threads to realize resource sharing, and the thread blocking caused by resource preemption is solved by reserving a smaller exclusive resource for each thread. The synchronous multithreading technology can improve the processor performance and energy efficiency.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a method, device, storage medium and electronic device for implementing simultaneous multi-threading. Background Art

[0002] In recent years, whether in the field of high-end consumer electronics or servers, processor cores with more powerful performance have become the core competitiveness of major chip companies, such as the M1 chip based on the ARM architecture. High-performance processor cores have two main characteristics: out-of-order execution and superscalar. High-performance processor cores are mainly composed of the following parts: (1) branch prediction module, (2) instruction fetch module, (3) decoding module, (4) renaming module, (5) distribution module, (6) emission module, (7) execution module, (8) memory access module and (9) reordering module. Some high-performance processor cores also have floating-point and vector execution modules. Generally, the operating frequency of high-performance processors is above 2gHz and the superscalar width is greater than 4.

[0003] Currently, there is a lack of simultaneous multi-threading technology applications based on the ARM architecture. Summary of the invention

[0004] The object of the present invention is to provide a method, device, storage medium and electronic device for implementing simultaneous multithreading, so as to at least partially improve the above-mentioned problems.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0006] In a first aspect, an embodiment of the present invention provides a synchronous multi-threading implementation method, which is applied to a renaming module, wherein the renaming module is deployed with a thread-shared renaming record queue shared by multiple threads, a dedicated renaming record queue for each thread, and a speculative renaming mapping table for each thread, wherein the target speculative renaming mapping table includes a speculative mapping relationship between an architecture register and a physical register under a target thread, and the synchronous multi-threading implementation method includes:

[0007] Acquire renaming information of a target instruction, wherein the target instruction is an instruction transmitted by a target thread under a current clock, and the renaming information includes a mapping relationship between an architecture register and a physical register in the target instruction;

[0008] Update the target speculative rename mapping table according to the obtained rename information;

[0009] The renaming information is written into a target exclusive renaming record queue or the thread-shared renaming record queue, wherein the target exclusive renaming record queue is an exclusive renaming record queue of the target thread.

[0010] In a second aspect, an embodiment of the present invention provides a synchronous multi-threading implementation device, which is applied to a renaming module, wherein the renaming module is deployed with a thread-shared renaming record queue shared by multiple threads, a dedicated renaming record queue for each thread, and a speculative renaming mapping table for each thread, wherein the target speculative renaming mapping table includes a speculative mapping relationship between an architecture register and a physical register under a target thread, and the synchronous multi-threading implementation device includes:

[0011] A first processing unit, configured to obtain renaming information of a target instruction, wherein the target instruction is an instruction transmitted by a target thread under a current clock, and the renaming information includes a mapping relationship between an architecture register and a physical register in the target instruction;

[0012] A second processing unit, configured to update the target speculative rename mapping table according to the acquired rename information;

[0013] The second processing unit is further configured to write the renaming information into a target exclusive renaming record queue or the thread-shared renaming record queue, wherein the target exclusive renaming record queue is an exclusive renaming record queue of the target thread.

[0014] In a third aspect, an embodiment of the present invention provides a storage medium having a computer program stored thereon, and the computer program implements the above method when executed by a processor.

[0015] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising: a processor and a memory, wherein the memory is used to store one or more programs; when the one or more programs are executed by the processor, the above method is implemented.

[0016] Compared with the prior art, a synchronous multi-threading implementation method, device, storage medium and electronic device provided in an embodiment of the present invention are applied to a renaming module, in which a thread-shared renaming record queue shared by multiple threads, an exclusive renaming record queue for each thread and a speculative renaming mapping table for each thread are deployed. The target speculative renaming mapping table includes the speculative mapping relationship between the architecture register and the physical register under the target thread. The synchronous multi-threading implementation method includes: obtaining renaming information of the target instruction, wherein the target instruction is the instruction transmitted by the target thread under the current clock, and the renaming information includes the mapping relationship between the architecture register and the physical register in the target instruction; updating the target speculative renaming mapping table according to the obtained renaming information; and writing the renaming information into the target exclusive renaming record queue or the thread-shared renaming record queue, wherein the target exclusive renaming record queue is the exclusive renaming record queue of the target thread. According to the characteristics of simultaneous multi-threading, sharable resources are shared with different threads to achieve resource sharing. By reserving a smaller exclusive resource for each thread, thread blocking caused by resource preemption is solved. The use of simultaneous multi-threading technology can improve the performance and energy efficiency of ARM architecture processors.

[0017] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 This is one of the layout diagrams of the renaming module provided in the embodiment of the present invention.

[0020] Figure 2 The second schematic diagram of the layout of the renaming module provided in the embodiment of the present invention.

[0021] Figure 3 One of the flow charts of the synchronous multi-threading implementation method provided in the embodiment of the present invention.

[0022] Figure 4 The second flowchart of the synchronous multi-threading implementation method provided by the embodiment of the present invention.

[0023] Figure 5 The third flowchart of the synchronous multi-threading implementation method provided by the embodiment of the present invention.

[0024] Figure 6 The fourth flowchart of the synchronous multi-threading implementation method provided in the embodiment of the present invention.

[0025] Figure 7 A schematic diagram of a synchronous multi-threading implementation device provided in an embodiment of the present invention.

[0026] In the figure: 10 - thread shared rename record queue; 11 - thread rename record queue mapping table; 12 - exclusive rename record queue; 13 - speculative rename mapping table; 14 - architecture rename mapping table; 501 - first processing unit; 502 - second processing unit. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0028] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0030] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0031] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0032] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0033] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0034] The embodiment of the present invention provides a synchronous multi-threading implementation method, which is applied to the renaming module, which is an important component of the out-of-order CPU core and is used to resolve the pseudo-dependency between instructions to improve the parallelism of instructions. Figure 1 and Figure 2 , Figure 1 One of the layout diagrams of the renaming module provided in an embodiment of the present invention, Figure 2 The second schematic diagram of the layout of the renaming module provided in the embodiment of the present invention. Figure 1 and Figure 2As shown, the renaming module is deployed with a thread-shared renaming record queue 10 shared by multiple threads, a thread renaming record queue mapping table 11 for each thread, an exclusive renaming record queue 12 for each thread, a speculative renaming mapping table 13 for each thread, and an architecture renaming mapping table 14 for each thread.

[0035] Figure 1 and Figure 2 Four threads (thread T0, thread T1, thread T2, and thread T3) are used as an example, but this is not a limitation. The renaming module can also be connected to more or fewer threads.

[0036] exist Figure 1 and Figure 2 In the example, the thread-shared rename record queue 10 is provided with 15 rows (row numbers 0 to 14), each row having 8 entries, which are used to store rename information, wherein the rename information includes the mapping relationship between the architecture register and the physical register in the target instruction. The thread-shared rename record queue 10 is shared by multiple threads, and the rename information corresponding to each thread can be stored in the thread-shared rename record queue 10. It should be noted that Figure 1 and Figure 2 The number of rows and entries in the thread-shared rename record queue 10 shown can be adjusted by configuration parameters, which may be, but are not limited to Figure 1 and Figure 2 shown.

[0037] like Figure 1 and Figure 2 As shown, each thread has a corresponding thread renaming record queue mapping table 11, for example, thread T0, thread T1, thread T2 and thread T3 all have corresponding thread renaming record queue mapping table 11. When thread Ti is the target thread, the thread renaming record queue mapping table 11 corresponding to thread Ti is the target thread renaming record queue mapping table.

[0038] The target thread rename record queue mapping table is used to manage the writing and reading of the rename information corresponding to the target thread. The target thread rename record queue mapping table is provided with a plurality of entries, wherein the number of entries is at least greater than the number of rows in the thread-shared rename record queue 10; for example, the number of rows in the thread-shared rename record queue 10 is 15, and the target thread rename record queue mapping table is provided with at least 16 entries (entry numbers are 0 to 15 respectively). A write pointer and a read pointer are provided in the target thread rename record queue mapping table. The entry pointed to by the write pointer in the target thread rename record queue mapping table stores the identification information (such as a label) of the current write row corresponding to the target thread, that is, the write pointer in the target thread rename record queue mapping table is used to indicate the current write row corresponding to the target thread.

[0039] When the renaming information corresponding to the target thread is obtained, the current write row corresponding to the target thread can be determined according to the write pointer in the target thread renaming record queue mapping table, thereby completing the writing of the renaming information. It should be noted that the current write row can be any row in the thread-shared renaming record queue 10 or can be the target-exclusive renaming record queue described below. When the current write row is full, the write pointer in the target thread renaming record queue mapping table can be moved backward in sequence, and the identification information of the new current write row can be added to the entry corresponding to the write pointer after the move.

[0040] The read pointer and the restore pointer in the target thread rename record queue mapping table, wherein the read pointer is used to indicate the current read row corresponding to the target thread, and the restore pointer is used to indicate the current confirmation row corresponding to the target thread. The current read row refers to the read data row in the slave thread shared rename record queue 10 corresponding to the target thread. It should be noted that the rename module can determine whether the instruction corresponding to the rename information is submitted based on the interactive information of other modules. The row where the rename information of the current confirmation behavior is confirming whether the instruction is submitted is located. After the last rename information in the current read row is moved to the target exclusive rename record queue, the read pointer in the target thread rename record queue mapping table can be moved backward in sequence to indicate the new current read row. After the instruction corresponding to the last rename information in the current confirmation row has been submitted, the restore pointer in the target thread rename record queue mapping table can be moved backward in sequence to indicate the new current confirmation row. Of course, the corresponding first entry pointer and second entry pointer can also be set, the first entry pointer is used to indicate the last entry read out in the current read row, and the second entry pointer is used to indicate the last entry submitted in the current confirmation row.

[0041] like Figure 1 and Figure 2 As shown, each thread has a corresponding exclusive rename record queue 12, for example, thread T0, thread T1, thread T2 and thread T3 each have a corresponding target exclusive rename record queue. The number of entries in the target exclusive rename record queue is equal to the number of entries in a row of the thread shared rename record queue 10. The target exclusive rename record queue can also store the rename information corresponding to the target thread.

[0042] like Figure 1 and Figure 2As shown, each thread has a corresponding speculative renaming mapping table 13, for example, thread T0, thread T1, thread T2 and thread T3 all have corresponding target speculative renaming mapping tables. The speculative renaming mapping table 13 is used to record the relationship between the latest architecture registers and physical registers in the current cycle during the out-of-order CPU speculative execution process, and the relationship is used to indicate the dependency of subsequent instructions. The target speculative renaming mapping table includes the speculative mapping relationship between the architecture registers and the physical registers under the target thread. In an optional embodiment, there are 32 architecture registers, namely X0 to X31, and the number of physical registers is not limited here.

[0043] like Figure 1 and Figure 2 As shown, each thread has a corresponding architecture rename mapping table 14, for example, thread T0, thread T1, thread T2 and thread T3 all have corresponding target architecture rename mapping tables. The target architecture rename mapping table includes the mapping relationship between architecture registers and physical registers under the instructions submitted by the target thread.

[0044] It should be understood that Figure 1 and Figure 2 The structure shown is only a schematic diagram of the structure of the renaming module. The renaming module may also include Figure 1 and Figure 2 More or fewer components as shown, or with Figure 1 and Figure 2 Different configurations shown. Figure 1 and Figure 2 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0045] A synchronous multithreading implementation method provided by an embodiment of the present invention can be applied to, but not limited to, Figure 1 and Figure 2 For the detailed process of renaming modules, please refer to Figure 3 , the synchronous multi-threading implementation method includes: S101, S102 and S103, which are specifically described as follows.

[0046] S101, obtaining renaming information of a target instruction.

[0047] The target instruction is an instruction transmitted by the target thread under the current clock, and the renaming information includes a mapping relationship between an architecture register and a physical register in the target instruction.

[0048] It should be noted that the target thread is any thread connected to the renaming module. The target instruction involves multiple architectural registers, including the destination architectural register. When the renaming module obtains the target instruction, it can generate corresponding renaming information based on the architectural registers involved in the target instruction. The renaming information includes the mapping relationship between the architectural registers and the physical registers in the target instruction, and the physical registers include the destination physical registers corresponding to the destination architectural registers.

[0049] S102: Update the target speculative renaming mapping table according to the acquired renaming information.

[0050] S103, writing the renaming information into the target exclusive renaming record queue or the thread shared renaming record queue.

[0051] The target exclusive rename record queue is an exclusive rename record queue of the target thread.

[0052] In the synchronous multi-threading implementation method provided by the present invention, according to the characteristics of synchronous multi-threading, sharable resources are shared with different threads to achieve resource sharing, and a smaller exclusive resource is reserved for each thread to solve the thread blocking caused by resource preemption. The use of synchronous multi-threading technology can improve the performance and energy efficiency of ARM architecture processors.

[0053] exist Figure 3 Based on the content in S103, the embodiment of the present invention further provides an optional implementation, please refer to the following. S103, the step of writing the renaming information into the target exclusive renaming record queue or the thread shared renaming record queue includes: S103-1 to S103-8.

[0054] S103-1, based on the target thread rename record queue mapping table, determine whether the target thread occupies the thread shared rename record queue in the current clock. If the target thread does not occupy the thread shared rename record queue in the current clock, execute S103-2; if the target thread has occupied the thread shared rename record queue in the current clock, execute S103-6.

[0055] The target thread renaming record queue mapping table includes storage resource information occupied by the target thread at the current clock.

[0056] It can be understood that the identification information recorded in the entry between the write pointer and the read pointer in the target thread renaming record queue mapping table is the storage resource information occupied by the target thread in the current clock.

[0057] S103-2, determine whether there is an idle entry in the target exclusive rename record queue. If there is an idle entry in the target exclusive rename record queue, execute S103-3; if the target exclusive rename record queue is full, execute S103-4.

[0058] When the target thread does not occupy the thread-shared rename record queue at the current clock, and there are free entries in the target exclusive rename record queue (for example, when the chip is just powered on), the resources in the target exclusive rename record queue are used first, that is, S103-3. When the target thread does not occupy the thread-shared rename record queue at the current clock, but the target exclusive rename record queue is full (that is, there are no free entries), it is necessary to use the thread-shared rename record queue and S103-4 can be executed.

[0059] S103-3, write the renaming information into the first free entry in the target exclusive renaming record queue.

[0060] The first free entry in the target exclusive rename record queue is the first entry in the target exclusive rename record queue that is sorted after the most recently written entry. Optionally, a write pointer is provided in the target exclusive rename record queue, and the entry pointed to by the write pointer is the first free entry in the target exclusive rename record queue.

[0061] For example, the target exclusive rename record queue includes 8 entries, that is, each thread can have 8 (record) entries exclusively, which ensures that even under the maximum load, each thread still has independent resources and will not be blocked because all resources are occupied by other threads. In this example, the maximum rename record queue that each thread can use is 128 entries (120 shared + 8 exclusive). In most cases, the input of the module target exclusive rename record queue comes from the output of the thread shared rename record queue, but if a thread has not used the thread shared rename record queue before, then the latest instruction information of the thread will be directly bypassed to the target exclusive rename record queue corresponding to the thread.

[0062] S103-4, determine whether there is an idle row in the thread-shared rename record queue. If there is an idle row in the thread-shared rename record queue, execute S103-5; if there is no idle row in the thread-shared rename record queue, repeat S103-2.

[0063] S103-5, determining one of the free rows in the thread-shared rename record queue as a first-class target row, and writing the renaming information into the first free entry in the first-class target row.

[0064] Among them, the first type of target behavior is the current write row corresponding to the target thread in the current clock thread shared rename record queue.

[0065] It should be noted that if there are no free rows in the thread-shared rename record queue, it means that all rows in the thread-shared rename record queue are occupied by other threads. In this case, it means that there are no remaining resources in the thread-shared rename record queue and the target exclusive rename record queue, and it is necessary to wait for the two to release resources before continuing to write, so it is necessary to repeat S103-2 to determine whether there are released resources. When waiting for free entries in the target exclusive rename record queue, write the rename information to the first free entry in sequence, or, when waiting for free rows in the thread-shared rename record queue, determine one of the free rows in the thread-shared rename record queue as the first-class target row, and write the rename information to the first free entry in sequence in the first-class target row.

[0066] S103-6, determine whether there is a free entry in the first type target row. If there is a free entry in the first type target row, execute S103-7; if the first type target row is full, execute S103-8.

[0067] Among them, the first type of target behavior is the current write row corresponding to the target thread in the current clock thread shared rename record queue.

[0068] S103-7, write the renaming information into the first free entry in the first type of target row.

[0069] The first free entry in the first-category target row is the first entry in the first-category target row that is sorted after the most recently written entry.

[0070] S103-8, determining one of the free rows in the thread-shared rename record queue as a new first-category target row, and writing the renaming information into the first free entry in the first-category target row.

[0071] exist Figure 3 On the basis of how to further manage the writing of rename information, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 4 , after S103, the synchronous multi-threading implementation method further includes: S104, which is specifically described as follows.

[0072] S104, when writing the renaming information into the target exclusive renaming record queue or the thread shared renaming record queue, if the write row corresponding to the target thread changes (a new row resource is allocated), the target thread renaming record queue mapping table is updated.

[0073] The write pointer in the target thread rename record queue mapping table is used to indicate the current write row corresponding to the target thread.

[0074] Please refer to Figure 5 In an optional implementation, the synchronous multi-threading implementation method further includes: S201, S202 and S203, which are specifically described as follows.

[0075] S201, when the target thread has occupied the thread shared rename record queue in the current clock, if there is an idle entry in the target exclusive rename record queue, the target entry is moved from the thread shared rename record queue to the target exclusive rename record queue according to the writing order.

[0076] The target entry is the entry in the thread-shared rename record queue that corresponds to the target thread and has not yet been moved to the target exclusive rename record queue and has the earliest write time.

[0077] Specifically, the rename information in the target entry is moved to the first idle entry in the target exclusive rename record queue.

[0078] S202, when the first type of instruction is submitted, the target architecture renaming mapping table is updated according to the first type of renaming information, and after the update is completed, the first type of renaming information is deleted from the target exclusive renaming record queue.

[0079] Among them, the first category of instructions are instructions corresponding to the first category of renaming information, the first category of renaming information is the renaming information with the earliest writing time in the target exclusive renaming record queue, and the target architecture renaming mapping table includes the mapping relationship between the architecture registers and the physical registers under the instructions submitted by the target thread.

[0080] S203, after the instruction corresponding to the renaming information in the last entry in the second type target row in the thread shared renaming record queue is submitted, the read pointer in the target thread renaming record queue mapping table is moved backward from the entry recording the identifier of the second type target row.

[0081] It should be noted that when the read pointer in the target thread rename record queue mapping table is moved backward from the entry recording the identification of the second type of target row, although the identification information of the second type of target row is still stored in the target thread rename record queue mapping table, the corresponding instructions in the renaming information in the second type of target row have been submitted. By moving the read pointer in the target thread rename record queue mapping table backward, the resources of the second type of target row can be released again and put into an idle state for writing new renaming information.

[0082] Please refer to Figure 6In an optional implementation, the synchronous multi-threading implementation method further includes: S301, S302, S303 and S304, which are specifically described as follows.

[0083] S301, when it is determined that a branch prediction failure occurs in the target thread, entering a recovery state and suspending receiving instructions of the target thread.

[0084] S302, copying the target architecture rename mapping table to the target speculative rename mapping table.

[0085] It can be understood that the information in the target architecture rename mapping table is absolutely correct. When it is determined that a branch prediction failure occurs in the target thread, the target architecture rename mapping table can be used as the starting point for recovering the target speculative rename mapping table.

[0086] S303, according to the target thread renaming record queue mapping table, move the target entry from the thread shared renaming record queue to the target exclusive renaming record queue in the writing order until it is moved to the second type of renaming record information.

[0087] The second type of renaming information is the renaming information corresponding to the instruction for which branch prediction fails.

[0088] Optionally, the row occupied by the target thread can be determined based on the read pointer and the write pointer in the target thread rename record queue mapping table, and then the target entry is re-determined, and the rename information in the target entry is moved to the first free entry in the target exclusive rename record queue.

[0089] S304, updating the target speculative rename mapping table according to the first type of rename information, and after the update is completed, deleting the first type of rename information from the target exclusive rename record queue;

[0090] It should be noted that at this time, it is not necessary to determine whether the first type of instructions corresponding to the first type of renaming information have been submitted. The target speculative renaming mapping table can be directly updated. After the update is completed, the first type of renaming information is deleted from the target exclusive renaming record queue until the second type of renaming information is restored.

[0091] It should be noted that after the second type of renaming information is moved to the target exclusive renaming record queue, all the renaming information corresponding to the target thread in the thread-shared renaming record queue can still be moved to the target exclusive renaming record queue for other uses, which is not limited here.

[0092] In an optional implementation, the target thread will apply for resources from the renaming module in each clock cycle, and the amount of resources requested needs to be calculated in combination with the current demand of the target thread and the current remaining amount of the target thread. For example, if there are 5 entries left in the current write row corresponding to the target thread, and the current demand of the target thread in this clock cycle is 4 (that is, the target thread has 4 rename information to record), then the target thread does not need to apply for a new row. If the current demand of the target thread in this clock cycle is 6, then the target thread needs to apply for a new row and use 1 entry in the new row, and the remaining 7 entries are for the next clock cycle.

[0093] See also Figure 7 , Figure 7 A synchronous multi-threading implementation device is provided in an embodiment of the present invention. Optionally, the synchronous multi-threading implementation device is applied to the electronic device described above.

[0094] The synchronous multithreading implementation device includes: a first processing unit 501 and a second processing unit 502.

[0095] The first processing unit 501 is used to obtain renaming information of a target instruction, wherein the target instruction is an instruction transmitted by a target thread under a current clock, and the renaming information includes a mapping relationship between an architecture register and a physical register in the target instruction;

[0096] The second processing unit 502 is used to update the target speculative rename mapping table according to the acquired rename information;

[0097] The second processing unit 502 is further configured to write the renaming information into a target exclusive renaming record queue or a thread-shared renaming record queue, wherein the target exclusive renaming record queue is an exclusive renaming record queue of a target thread.

[0098] Optionally, the first processing unit 501 may execute the above-mentioned S101, and the second processing unit 502 may execute the above-mentioned other steps.

[0099] It should be noted that the synchronous multithreading implementation device provided in this embodiment can execute the method flow shown in the above method flow embodiment to achieve the corresponding technical effect. For the sake of brief description, for parts not mentioned in this embodiment, please refer to the corresponding content in the above embodiment.

[0100] The embodiment of the present invention also provides a storage medium, which stores computer instructions and programs, and when the computer instructions and programs are read and run, the synchronous multi-threading implementation method of the above embodiment is executed. The storage medium may include a memory, a flash memory, a register, or a combination thereof.

[0101] An electronic device is provided below, which may be a mobile phone device, a computer device, a server device, etc. The electronic device can implement the above-mentioned synchronous multi-threading implementation method; specifically, the electronic device includes: a processor, a memory, and a bus. The processor may be a CPU. The memory is used to store one or more programs, and when the one or more programs are executed by the processor, the synchronous multi-threading implementation method of the above-mentioned embodiment is executed.

[0102] In summary, an embodiment of the present invention provides a synchronous multi-threading implementation method, device, storage medium and electronic device, which are applied to a renaming module. A thread-shared renaming record queue shared by multiple threads, an exclusive renaming record queue for each thread and a speculative renaming mapping table for each thread are deployed in the renaming module. The target speculative renaming mapping table includes the speculative mapping relationship between the architecture register and the physical register under the target thread. The synchronous multi-threading implementation method includes: obtaining renaming information of the target instruction, wherein the target instruction is the instruction transmitted by the target thread under the current clock, and the renaming information includes the mapping relationship between the architecture register and the physical register in the target instruction; updating the target speculative renaming mapping table according to the acquired renaming information; and writing the renaming information into the target exclusive renaming record queue or the thread-shared renaming record queue, wherein the target exclusive renaming record queue is the exclusive renaming record queue of the target thread. According to the characteristics of simultaneous multi-threading, sharable resources are shared with different threads to achieve resource sharing. By reserving a smaller exclusive resource for each thread, thread blocking caused by resource preemption is solved. The use of simultaneous multi-threading technology can improve the performance and energy efficiency of ARM architecture processors.

[0103] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0104] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A synchronous multithreading implementation method, characterized in that: Applied to a renaming module, the renaming module is deployed with a thread-shared renaming record queue shared by multiple threads, a thread renaming record queue mapping table for each thread, an exclusive renaming record queue for each thread, a speculative renaming mapping table for each thread, and an architecture renaming mapping table for each thread, the target speculative renaming mapping table includes a speculative mapping relationship between an architecture register and a physical register under a target thread, the target architecture renaming mapping table includes a mapping relationship between an architecture register and a physical register under an instruction submitted by a target thread, the target thread renaming record queue mapping table includes storage resource information occupied by the target thread at the current clock, and the synchronous multithreading implementation method includes: Acquire renaming information of a target instruction, wherein the target instruction is an instruction transmitted by a target thread under a current clock, and the renaming information includes a mapping relationship between an architecture register and a physical register in the target instruction; Update the target speculative rename mapping table according to the obtained rename information; Writing the renaming information into a target exclusive renaming record queue or the thread-shared renaming record queue, wherein the target exclusive renaming record queue is an exclusive renaming record queue of the target thread; The synchronous multithreading implementation method also includes: When it is determined that the target thread has a branch prediction failure, entering a recovery state and suspending receiving instructions from the target thread; Copying the target architecture rename mapping table to the target speculative rename mapping table; According to the target thread renaming record queue mapping table, the target entry is moved from the thread shared renaming record queue to the target exclusive renaming record queue in a write order until it is moved to the second type of renaming information, wherein the second type of renaming information is the renaming information corresponding to the instruction with failed branch prediction, and the target entry is the entry corresponding to the target thread in the thread shared renaming record queue that has not been moved to the target exclusive renaming record queue and has the earliest write time; The target speculative rename mapping table is updated according to the first type of rename information. After the update is completed, the first type of rename information is deleted from the target exclusive rename record queue, wherein the first type of rename information is the rename information with the earliest writing time in the target exclusive rename record queue.

2. The method for implementing simultaneous multithreading as claimed in claim 1, characterized in that: The step of writing the renaming information into the target exclusive renaming record queue or the thread shared renaming record queue comprises: Determine whether the target thread occupies the thread shared rename record queue at the current clock based on the target thread rename record queue mapping table; If the target thread does not occupy the thread-shared rename record queue at the current clock, determining whether there is an idle entry in the target exclusive rename record queue; If there is an idle entry in the target exclusive rename record queue, the rename information is written into the first idle entry in the target exclusive rename record queue.

3. The method for implementing simultaneous multithreading as claimed in claim 2, characterized in that: The step of writing the renaming information into the target exclusive renaming record queue or the thread shared renaming record queue also includes: If the target exclusive rename record queue is full, determining whether there is an idle row in the thread-shared rename record queue; If there are free rows in the thread-shared rename record queue, determine one of the free rows in the thread-shared rename record queue as a first-type target row, and write the rename information into the first free entry in the first-type target row; Wherein, the first type of target behavior is the current write row corresponding to the target thread in the thread shared rename record queue at the current clock; If there is no free row in the thread-shared rename record queue, the renaming information is written into the first free entry in sequence while waiting for a free entry to exist in the target exclusive rename record queue. Alternatively, when waiting for a free row in the thread-shared rename record queue, one of the free rows in the thread-shared rename record queue is determined as a first-class target row, and the renaming information is written into the first free entry in sequence in the first-class target row.

4. The method for implementing simultaneous multithreading as claimed in claim 3, characterized in that: The step of writing the renaming information into the target exclusive renaming record queue or the thread shared renaming record queue also includes: When the target thread has occupied the thread-shared rename record queue at the current clock, determining whether there is an idle entry for the first type of target row; If there is a free entry in the first-category target row, writing the renaming information into the first free entry in the first-category target row; If the first-category target row is full, a new first-category target row is determined from the free rows of the thread-shared rename record queue, and the renaming information is written into the first free entry in the first-category target row.

5. The method for implementing simultaneous multithreading as claimed in claim 4, characterized in that: The synchronous multithreading implementation method also includes: When writing the renaming information into the target exclusive renaming record queue or the thread shared renaming record queue, if the write row corresponding to the target thread changes, the target thread renaming record queue mapping table is updated, wherein the write pointer in the target thread renaming record queue mapping table is used to indicate the current write row corresponding to the target thread.

6. The method for implementing simultaneous multithreading as claimed in claim 5, characterized in that: The synchronous multithreading implementation method also includes: When the target thread has occupied the thread-shared rename record queue at the current clock, if there is an idle entry in the target exclusive rename record queue, the target entry is moved from the thread-shared rename record queue to the target exclusive rename record queue in the order of writing; When the first type of instruction is submitted, the target architecture renaming mapping table is updated according to the first type of renaming information, and after the update is completed, the first type of renaming information is deleted from the target exclusive renaming record queue; Wherein, the first type of instructions are instructions corresponding to the first type of renaming information; After the instruction corresponding to the renaming information in the last entry in the second type target row in the thread shared renaming record queue is submitted, the read pointer in the target thread renaming record queue mapping table is moved backward from the entry recording the identifier of the second type target row.

7. A synchronous multithreading implementation device, characterized in that: Applied to a renaming module, the renaming module is deployed with a thread-shared renaming record queue shared by multiple threads, a thread renaming record queue mapping table for each thread, an exclusive renaming record queue for each thread, a speculative renaming mapping table for each thread, and an architecture renaming mapping table for each thread, the target speculative renaming mapping table includes a speculative mapping relationship between an architecture register and a physical register under a target thread, the target architecture renaming mapping table includes a mapping relationship between an architecture register and a physical register under an instruction submitted by a target thread, the target thread renaming record queue mapping table includes storage resource information occupied by the target thread at the current clock, and the synchronous multithreading implementation device includes: A first processing unit, configured to obtain renaming information of a target instruction, wherein the target instruction is an instruction transmitted by a target thread under a current clock, and the renaming information includes a mapping relationship between an architecture register and a physical register in the target instruction; A second processing unit, configured to update the target speculative rename mapping table according to the acquired rename information; The second processing unit is further configured to write the renaming information into a target exclusive renaming record queue or the thread shared renaming record queue, wherein the target exclusive renaming record queue is an exclusive renaming record queue of the target thread. The second processing unit is also used to enter a recovery state and suspend receiving instructions from the target thread when it is determined that a branch prediction failure occurs in the target thread; copy the target architecture rename mapping table to the target speculative rename mapping table; according to the target thread rename record queue mapping table, move the target entry from the thread shared rename record queue to the target exclusive rename record queue in a write order until it is moved to the second type of rename information, wherein the second type of rename information is the rename information corresponding to the instruction with a branch prediction failure, and the target entry is the entry corresponding to the target thread in the thread shared rename record queue that has not been moved to the target exclusive rename record queue and has the earliest write time; update the target speculative rename mapping table according to the first type of rename information, and after the update is completed, delete the first type of rename information from the target exclusive rename record queue, wherein the first type of rename information is the rename information with the earliest write time in the target exclusive rename record queue.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

9. An electronic device, characterized in that: include: A processor and a memory, the memory being used to store one or more programs; When the one or more programs are executed by the processor, the method according to any one of claims 1 to 6 is implemented.

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