A netlist simulation system and method based on SV language

Abstract

The present invention provides a netlist simulation system and method based on SV language, and relates to the field of chip verification technology. The netlist simulation system based on SV language includes a verification case module, a verification platform, an SV physical layer module designed based on SystemVerilog language, a PIPE interface excitation module and a netlist to be tested. Among them, the verification platform has a built-in verification environment, the verification environment is connected to the SV physical layer module, and the SV physical layer module is connected to the netlist to be tested through the PIPE interface excitation module. The present invention can save a lot of simulation time by replacing the physical layer model with the SV physical layer module and the PIPE interface excitation module. Through the SV physical layer module and the PIPE interface excitation module, multiple received data are injected with errors and randomized, that is, random skew differences are introduced between multiple data, and abnormal verification is performed, thereby improving the randomness and coverage of post-chip simulation.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to a netlist simulation system and method based on SV language. Background Art

[0002] In the process of circuit design, simulation and verification is an important link, which can check whether the designed circuit meets the requirements. Simulation can be divided into pre-simulation and post-simulation. Among them, post-simulation is to simulate the netlist and delay file obtained after logic synthesis, so as to check whether the netlist function is correct and whether the delay meets the timing requirements. The simulation results are close to the actual application situation.

[0003] Chip post-simulation is the most important link in the chip R&D process. The method of post-simulating a chip is to simulate the netlist to be tested with the physical layer model. At present, most physical layer models are implemented through simulation, that is, a real physical layer circuit is first implemented through simulation, and then the real physical layer circuit is converted into a physical layer model. The development cycle of the entire physical layer model is long and the R&D difficulty is high. In addition, the physical layer model can only test the netlist to be tested according to normal data, and cannot perform abnormal tests on the netlist to be tested, resulting in poor simulation randomness, few covered scenarios, and limited verification capabilities.

[0004] As the speed of high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIE) increases, the size of physical layer models required in simulation increases, so some physical layer models are designed using Verilog language. Since Verilog is a relatively basic hardware description language, it lacks some advanced abstractions and functions. Therefore, it is cumbersome to write and maintain code in Verilog language in large-scale physical layer design. Once a small error occurs, it may cause large-scale functional abnormalities. It is very time-consuming to locate the source of the problem, which increases the time and difficulty of physical layer development. At the same time, it also makes the simulation system need more computing resources and time to parse and simulate circuit behavior during verification, resulting in a long time period and low simulation efficiency for the entire chip post-simulation.

[0005] In summary, how to improve the efficiency and coverage of post-chip simulation is a technical problem that needs to be urgently solved by those skilled in the art. Summary of the invention

[0006] The purpose of the present invention is to provide a netlist simulation system and method based on SV language to improve the simulation speed and simulation randomness of the chip.

[0007] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0008] In a first aspect, the present invention provides a netlist simulation system based on SV language, comprising: a verification case module, a verification platform, an SV physical layer module designed based on SystemVerilog language, a PIPE interface stimulus module and a netlist to be tested; the verification platform has a built-in verification environment, the verification environment is connected to the SV physical layer module, and the SV physical layer module is connected to the netlist to be tested through the PIPE interface stimulus module; wherein the netlist to be tested is used to provide real physical circuit information with timing in the chip to be tested;

[0009] The verification case module is used to configure a variety of excitation signals that comply with the PCIE protocol;

[0010] The verification environment is used to send a variety of stimulus signals to the SV physical layer module;

[0011] The SV physical layer module and the PIPE interface excitation module are used to perform error injection and randomization operations on a variety of excitation signals to generate random excitation signals;

[0012] The netlist to be tested is also used to generate a processing signal according to the random stimulus signal, and send the processing signal to the PIPE interface stimulus module;

[0013] The PIPE interface excitation module and the SV physical layer module are also used to perform error injection and randomization operations on the processed signal to generate a random processed signal;

[0014] The verification environment is also used to parse the received random processing signal to determine whether the netlist to be tested meets expectations.

[0015] Optionally, the SV language-based netlist simulation system further includes a verification environment configuration module, and the verification environment configuration module is used to configure parameters of the verification platform, the SV physical layer module and the PIPE interface stimulus module.

[0016] Optionally, the verification environment configuration module uses a configuration file to implement parameter configuration, and the configuration file is written in a script to achieve randomization of configuration parameters.

[0017] Optionally, the verification platform further includes a VIP physical layer component provided by VIP, and the verification environment is connected to the SV physical layer module via the VIP physical layer component.

[0018] Optionally, when the chip to be tested is a Retimer chip, the verification environment includes an RC verification environment and an EP verification environment, the SV physical layer module includes a first SV physical layer module and a second SV physical layer module, and the PIPE interface stimulus module includes a first PIPE interface stimulus module and a second PIPE interface stimulus module; one end of the netlist to be tested is connected to one end of the first SV physical layer module through the first PIPE interface stimulus module, and the other end of the first SV physical layer module is connected to the RC verification environment; the other end of the netlist to be tested is connected to one end of the second SV physical layer module through the second PIPE interface stimulus module, and the other end of the second SV physical layer module is connected to the EP verification environment;

[0019] The verification case module is used to configure a plurality of first excitation signals that comply with the PCIE protocol;

[0020] The RC verification environment is used to send a plurality of first stimulus signals to the first SV physical layer module;

[0021] The first SV physical layer module and the first PIPE interface excitation module are used to perform error injection and randomization operations on a plurality of first excitation signals to generate a first random excitation signal;

[0022] The netlist to be tested is used to generate a first processing signal according to the first random stimulus signal, and send the first processing signal to the second PIPE interface stimulus module;

[0023] The second PIPE interface excitation module and the second SV physical layer module are used to perform error injection and randomization operations on the first processed signal to generate a first random processed signal;

[0024] The EP verification environment is used to parse the received first random processing signal to determine whether the netlist to be tested meets expectations.

[0025] Optionally, when the chip to be tested is a Retimer chip, the verification environment includes an RC verification environment and an EP verification environment, the SV physical layer module includes a first SV physical layer module and a second SV physical layer module, and the PIPE interface stimulus module includes a first PIPE interface stimulus module and a second PIPE interface stimulus module; one end of the netlist to be tested is connected to one end of the first SV physical layer module through the first PIPE interface stimulus module, and the other end of the first SV physical layer module is connected to the RC verification environment; the other end of the netlist to be tested is connected to one end of the second SV physical layer module through the second PIPE interface stimulus module, and the other end of the second SV physical layer module is connected to the EP verification environment;

[0026] The verification case module is used to configure a plurality of second excitation signals that comply with the PCIE protocol;

[0027] The EP verification environment is used to send a plurality of second stimulus signals to the second SV physical layer module;

[0028] The second SV physical layer module and the second PIPE interface excitation module are used to perform error injection and randomization operations on a plurality of second excitation signals to generate a second random excitation signal;

[0029] The netlist to be tested is used to generate a second processing signal according to the second random stimulus signal, and send the second processing signal to the first PIPE interface stimulus module;

[0030] The first PIPE interface excitation module and the first SV physical layer module are used to perform error injection and randomization operations on the second processed signal to generate a second random processed signal;

[0031] The RC verification environment is used to parse the received second random processing signal to determine whether the netlist to be tested meets expectations.

[0032] Optionally, the verification platform also includes a first VIP physical layer component and a second VIP physical layer component provided by VIP, the RC verification environment is connected to the first SV physical layer module through the first VIP physical layer component, and the EP verification environment is connected to the second SV physical layer module through the second VIP physical layer component.

[0033] In a second aspect, the present invention further provides a netlist simulation method based on SV language, which is applied to the netlist simulation system based on SV language described in any one of the first aspects above, and the netlist simulation method based on SV language includes:

[0034] The verification case module is configured with multiple excitation signals that comply with the PCIE protocol;

[0035] The verification environment sends a plurality of stimulus signals to the SV physical layer module;

[0036] The SV physical layer module and the PIPE interface excitation module perform error injection and randomization operations on a plurality of excitation signals to generate random excitation signals;

[0037] The netlist to be tested generates a processing signal according to the random stimulus signal, and sends the processing signal to the PIPE interface stimulus module;

[0038] The PIPE interface excitation module and the SV physical layer module perform error injection and randomization operations on the processed signal to generate a random processed signal;

[0039] The verification environment analyzes the received random processing signal to determine whether the netlist to be tested meets expectations.

[0040] Optionally, the SV language-based netlist simulation method further includes:

[0041] The verification case module configures a plurality of first excitation signals that comply with the PCIE protocol;

[0042] The RC verification environment sends a plurality of first stimulus signals to the first SV physical layer module;

[0043] The first SV physical layer module and the first PIPE interface excitation module perform error injection and randomization operations on a plurality of first excitation signals to generate a first random excitation signal;

[0044] The netlist to be tested generates a first processing signal according to the first random stimulus signal, and sends the first processing signal to the second PIPE interface stimulus module;

[0045] The second PIPE interface excitation module and the second SV physical layer module perform error injection and randomization operations on the first processed signal to generate a first random processed signal;

[0046] The EP verification environment analyzes the received first random processing signal to determine whether the netlist to be tested meets expectations.

[0047] Optionally, the SV language-based netlist simulation method further includes:

[0048] The verification case module configures a plurality of second excitation signals that comply with the PCIE protocol;

[0049] The EP verification environment sends a plurality of second stimulus signals to the second SV physical layer module;

[0050] The second SV physical layer module and the second PIPE interface excitation module perform error injection and randomization operations on a plurality of second excitation signals to generate a second random excitation signal;

[0051] The netlist to be tested generates a second processing signal according to the second random stimulus signal, and sends the second processing signal to the first PIPE interface stimulus module;

[0052] The first PIPE interface excitation module and the first SV physical layer module perform error injection and randomization operations on the second processed signal to generate a second random processed signal;

[0053] The RC verification environment analyzes the received second random processing signal to determine whether the netlist to be tested meets expectations.

[0054] Compared with the prior art, the present invention has the following beneficial effects:

[0055] The present invention provides a netlist simulation system and method based on SV language, which can effectively solve the drawbacks of the prior art by replacing the physical layer model with the SV physical layer module and the PIPE interface stimulus module to post-simulate the netlist to be tested. The reasons are as follows:

[0056] The SV physical layer module in the present invention is a physical layer model designed using the SystemVerilog language. Since the SystemVerilog language provides high-level data types, it can more flexibly represent data structures. At the same time, the SystemVerilog language also provides object-oriented programming, which can more conveniently support code inheritance, encapsulation and polymorphism, and help create modular and reusable codes. Therefore, it is easier to implement the physical layer model using the SystemVerilog language than using the Verilog language, which reduces the difficulty of physical layer development, shortens the time of physical layer development, and can provide more debugging time during post-simulation.

[0057] In addition, SystemVerilog has built-in powerful verification features, such as constraint randomization, assertions, and coverage analysis. The SV physical layer module can not only improve simulation efficiency, but also perform error injection and randomization operations on multiple received data, that is, introduce random skew differences between multiple data to perform abnormal verification. Moreover, the PIPE interface stimulus module can also add different delays and randomization operations to multiple received data to generate random signals, thereby improving the randomness and coverage of the simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the present invention will be briefly introduced below. It should be understood that the following drawings only show certain technical solutions of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0059] Figure 1 One of the structural schematic diagrams of a netlist simulation system based on SV language provided by the present invention;

[0060] Figure 2 The second structural diagram of a netlist simulation system based on SV language provided by the present invention;

[0061] Figure 3 The third structural diagram of a netlist simulation system based on SV language provided by the present invention;

[0062] Figure 4 One of the flow charts of a netlist simulation method based on SV language provided by the present invention;

[0063] Figure 5 The second flowchart of a netlist simulation method based on SV language provided by the present invention;

[0064] Figure 6 The third flowchart of a netlist simulation method based on SV language provided by the present invention.

[0065] Figure markings: 10-SV language-based netlist simulation system; 110-verification use case module; 120-verification platform; 121-verification environment; 1211-RC verification environment; 1212-EP verification environment; 122-VIP physical layer component; 1221-first VIP physical layer component; 1222-second VIP physical layer component; 130-SV physical layer module; 131-first SV physical layer module; 132-second SV physical layer module; 140-PIPE interface stimulus module; 141-first PIPE interface stimulus module; 142-second PIPE interface stimulus module; 150-netlist to be tested; 160-verification environment configuration module. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the drawings in the present invention. Obviously, the described technical solutions are part of the technical solutions of the present invention, but not all of the technical solutions. Generally, the components of the technical solutions of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0067] Therefore, the following detailed description of the technical solutions of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents the selected technical solutions of the present invention. Based on the technical solutions in the present invention, all other technical solutions obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0068] In the description of the present invention, terms such as "first", "second" and the like are only used to distinguish the description and cannot be understood as indicating or implying relative importance. It should be noted that the features of the present invention can be combined with each other without conflict.

[0069] As described in the background technology, the existing chip post-simulation methods are to simulate the netlist to be tested with the real physical layer model. Since the real physical layer model is designed based on the Verilog language, the use of the real physical layer model for post-simulation has problems such as long simulation time, complex simulation model, poor simulation randomness, and fewer covered scenarios.

[0070] To solve the above technical problems, please refer to Figure 1 The present invention provides a netlist simulation system 10 based on SV language. The system includes: a verification case module 110, a verification platform 120, an SV physical layer module 130 designed based on SystemVerilog language, a PIPE (Physical Interface for PCI Express, a physical layer interface of a high-speed serial computer expansion bus) interface stimulus module 140 and a netlist to be tested 150.

[0071] As an optional implementation, the verification platform 120 has a built-in verification environment 121, which is connected to the SV physical layer module 130, and the SV physical layer module 130 is connected to the netlist to be tested 150 through the PIPE interface stimulus module 140. The netlist to be tested 150 may be a PR (Placement and Routing) netlist, which is used to provide real physical circuit information with timing in the chip to be tested.

[0072] The workflow of the entire SV language-based netlist simulation system 10 is as follows:

[0073] The verification case module 110 is used to configure a variety of stimulus signals that comply with the PCIE protocol.

[0074] The verification environment 121 is used to send various stimulus signals to the SV physical layer module 130 .

[0075] The SV physical layer module 130 and the PIPE interface excitation module 140 are used to perform error injection and randomization operations on a variety of excitation signals to generate random excitation signals.

[0076] The netlist to be tested 150 is further used to generate a processing signal according to the random stimulus signal, and send the processing signal to the PIPE interface stimulus module 140 .

[0077] The PIPE interface stimulus module 140 and the SV physical layer module 130 are further used to perform error injection and randomization operations on the processed signal to generate a random processed signal.

[0078] The verification environment 121 is also used to analyze the received random processing signal to determine whether the netlist to be tested 150 meets expectations.

[0079] Therefore, by replacing the physical layer model with the SV physical layer module 130 and the PIPE interface stimulus module 140 to perform post-simulation on the netlist 150 to be tested, the drawbacks of the prior art can be effectively solved for the following reasons:

[0080] The SV physical layer module in this embodiment is a physical layer model designed using the SystemVerilog language. Since the SystemVerilog language provides advanced data types, it can more flexibly represent data structures. At the same time, the SystemVerilog language also provides object-oriented programming, which can more conveniently support code inheritance, encapsulation and polymorphism, and help create modular and reusable code. Therefore, it is easier to implement the physical layer model using the SystemVerilog language than using the Verilog language, which reduces the difficulty of physical layer development, shortens the time of physical layer development, and can provide more debugging time during post-simulation.

[0081] In addition, SystemVerilog also has built-in powerful verification features, such as constraint randomization, assertion, coverage analysis, etc. The SV physical layer module can not only improve the simulation efficiency, but also perform error injection and randomization operations on multiple received lanes, that is, introduce random skew differences between multiple lanes for abnormal verification. Moreover, the PIPE interface stimulus module can also add different delays and randomization operations to the multiple received lanes to generate random signals, thereby improving the randomness and coverage of the simulation.

[0082] As an alternative implementation, see Figure 2 The verification platform 120 further includes a VIP physical layer component 122 provided by a verification intellectual property core (VIP). The verification environment 121 is connected to the SV physical layer module 130 through the VIP physical layer component 122 .

[0083] Optionally, the verification environment 121 and the VIP physical layer component 122 perform bidirectional communication via a PIPE interface, and the VIP physical layer component 122 and the SV physical layer module 130 perform bidirectional communication via a serializer / deserializer (serdes) interface.

[0084] When the verification environment 121 sends a stimulus signal to the SV physical layer module 130 , the VIP physical layer component 122 is used to convert the parallel data in the PIPE interface into serial data.

[0085] When the SV physical layer module 130 sends a random processing signal to the verification environment 121 , the VIP physical layer component 122 is used to convert the serial data in the serdes interface into parallel data so that the verification environment 121 can parse the received data.

[0086] In addition, in order to further improve the post-simulation efficiency and randomness, the SV language-based netlist simulation system 10 further includes a verification environment configuration module 160 . The verification environment configuration module 160 is used to configure the parameters of the verification platform 120 , the SV physical layer module 130 and the PIPE interface stimulus module 140 .

[0087] Specifically, the verification environment configuration module 160 uses a configuration file to implement parameter configuration, and the configuration file is written in a script to achieve randomization of configuration parameters.

[0088] In the embodiment of the present invention, the verification environment 121, the VIP physical layer component 122, the SV physical layer module 130 and the PIPE interface stimulus module 140 can all independently call the verification environment configuration module 160 to dynamically configure parameters. During the simulation process, the stimulus changes can be achieved by modifying the parameters in the verification environment configuration module 160, which not only saves compilation time, but also saves simulation time for subsequent regression use cases, greatly improving the efficiency of post-chip simulation.

[0089] The above-mentioned SV language-based netlist simulation system can be used to post-simulate most chips, improving the efficiency and coverage of post-simulation. As the PCIE data transmission rate continues to double, it brings significant signal attenuation and reference clock timing reordering problems. In order to compensate for the loss of high-speed signals and improve signal quality, it is usually necessary to introduce ultra-high-speed timing integration chips, namely retimer chips, into the link.

[0090] Because the post-simulation of the Retimer chip needs to be performed between the root complex (RC) verification environment and the end point (EP) verification environment. Figure 2 Based on this, the embodiment of the present invention also provides a Figure 3 The SV language-based netlist simulation system 10 is shown and is suitable for post-Retimer chip simulation.

[0091] See also Figure 3 When the chip to be tested is a Retimer chip, the verification environment includes an RC verification environment 1211 and an EP verification environment 1212. The RC verification environment 1211 and the EP verification environment 1212 are constructed and simulated by the PCIE function model provided by VIP.

[0092] Since the netlist under test 150 containing the timing information of the Retimer chip needs to be set between the RC verification environment 1211 and the EP verification environment 1212 for post-simulation, it is necessary to set the SV physical layer module and the PIPE interface stimulus module on both sides of the netlist under test 150 respectively.

[0093] As a feasible implementation manner, the SV physical layer module includes a first SV physical layer module 131 and a second SV physical layer module 132 , and the PIPE interface excitation module includes a first PIPE interface excitation module 141 and a second PIPE interface excitation module 142 .

[0094] Among them, one end of the netlist to be tested 150 is connected to one end of the first SV physical layer module 131 through the first PIPE interface stimulus module 141, and the other end of the first SV physical layer module 131 is connected to the RC verification environment 1211. The other end of the netlist to be tested 150 is connected to one end of the second SV physical layer module 132 through the second PIPE interface stimulus module 142, and the other end of the second SV physical layer module 132 is connected to the EP verification environment 1212.

[0095] Optionally, the verification platform 120 further includes a first VIP physical layer component 1221 and a second VIP physical layer component 1222 provided by VIP. The RC verification environment 1211 is connected to the first SV physical layer module 131 through the first VIP physical layer component 1221, and the EP verification environment 1212 is connected to the second SV physical layer module 132 through the second VIP physical layer component 1222.

[0096] Based on the above design, when the chip to be tested is a retimer chip, the workflow of the entire SV language-based netlist simulation system 10 is divided into two parts. One part of the workflow is that the RC verification environment 1211 exchanges data with the EP verification environment 1212, and the other part of the workflow is that the EP verification environment 1212 exchanges data with the RC verification environment 1211.

[0097] Combine the following Figure 3 , firstly, the specific process of data interaction between the RC verification environment 1211 and the EP verification environment 1212 is described.

[0098] First, the verification case module 110 configures a plurality of first excitation signals that comply with the PCIE protocol, and sends the plurality of first excitation signals to the RC verification environment 1211. The RC verification environment 1211 sends the first excitation signal to the first SV physical layer module 131 through the first VIP physical layer component 1221. The first VIP physical layer component 1221 is used to encode and scramble the plurality of first excitation signals, and convert parallel data into serial data.

[0099] Next, the first SV physical layer module 131 and the first PIPE interface excitation module 141 perform error injection and randomization operations on the received multiple first excitation signals to generate a first random excitation signal.

[0100] The netlist under test 150 receives the first random excitation signal and descrambles it. At the same time, the control end in the netlist under test 150 parses and processes the descrambled first random excitation signal to generate a first processed signal, and scrambles the first processed signal and sends it to the second PIPE interface excitation module 142. The second PIPE interface excitation module 142 and the second SV physical layer module 132 perform error injection and randomization operations on the first processed signal to generate a first random processed signal.

[0101] Finally, the second VIP physical layer component 1222 performs serial-to-parallel conversion on the received first random processing signal and sends it to the EP verification environment 1212. The EP verification environment 1212 analyzes the received first random processing signal to determine whether the netlist 150 to be tested meets expectations.

[0102] Similarly, the specific process of the EP verification environment 1212 performing data interaction with the RC verification environment 1211 is as follows:

[0103] First, the verification case module 110 configures a plurality of second excitation signals that comply with the PCIE protocol, and sends the plurality of second excitation signals to the EP verification environment 1212. The EP verification environment 1212 sends the second excitation signal to the second SV physical layer module 132 through the second VIP physical layer component 1222. The second VIP physical layer component 1222 is used to encode and scramble the plurality of second excitation signals and convert parallel data into serial data.

[0104] Next, the second SV physical layer module 132 and the second PIPE interface excitation module 142 perform error injection and randomization operations on the received multiple second excitation signals to generate a second random excitation signal.

[0105] The netlist under test 150 receives the second random excitation signal and descrambles it. At the same time, the control end in the netlist under test 150 parses and processes the descrambled second random excitation signal to generate a second processed signal, and scrambles the second processed signal and sends it to the first PIPE interface excitation module 141. The first PIPE interface excitation module 141 and the first SV physical layer module 131 perform error injection and randomization operations on the second processed signal to generate a second random processed signal.

[0106] Finally, the first VIP physical layer component 1221 performs serial-to-parallel conversion on the received second random processing signal and sends it to the RC verification environment 1211. The RC verification environment 1211 analyzes the received second random processing signal to determine whether the netlist 150 to be tested meets expectations.

[0107] In the embodiment of the present invention, by sequentially setting the first PIPE interface stimulus module 141, the first SV physical layer module 131 and the RC verification environment 1211 on one side of the netlist to be tested 150, and sequentially setting the second PIPE interface stimulus module 142, the second SV physical layer module 132 and the EP verification environment 1212 on the other side of the netlist to be tested 150, not only can the post-simulation of the Retimer chip be realized, but also the efficiency and coverage of the post-simulation of the Retimer chip can be improved. In addition, the parameters in the verification platform 120, the first SV physical layer module 131, the first PIPE interface stimulus module 141, the second PIPE interface stimulus module 142 and the second SV physical layer module 132 can be adjusted more conveniently through the verification environment configuration module 160, which saves compilation time and further improves the efficiency of chip post-simulation.

[0108] As an alternative implementation, see Figure 4 The embodiment of the present invention also provides a netlist simulation method based on SV language, which is applied to Figure 1 or Figure 2 The SV language-based netlist simulation system shown in the figure comprises the following steps:

[0109] Step 210: Verify that the use case module configuration complies with multiple stimulus signals of the PCIE protocol.

[0110] Step 220: The verification environment sends a variety of stimulus signals to the SV physical layer module.

[0111] Step 230: The SV physical layer module and the PIPE interface excitation module perform error injection and randomization operations on the various excitation signals to generate random excitation signals.

[0112] Step 240: The netlist to be tested generates a processing signal according to the random stimulus signal, and sends the processing signal to the PIPE interface stimulus module.

[0113] Step 250: The PIPE interface stimulus module and the SV physical layer module perform error injection and randomization operations on the processed signal to generate a random processed signal.

[0114] Step 260: The verification environment analyzes the received random processing signal to determine whether the netlist to be tested meets expectations.

[0115] Through the SV physical layer module and the PIPE interface stimulus module, not only can the received data (i.e. stimulus signal or processing signal) be modified to perform abnormal tests on the data path, but also different delays can be randomly added to each piece of data to simulate more different stimuli, so that the simulation can cover many extreme scenarios and improve the efficiency and coverage of post-simulation. In addition, through the verification environment configuration module, the parameters of the verification platform, SV physical layer module, and PIPE interface stimulus module can be randomly changed to save compilation time and further improve the efficiency of chip post-simulation.

[0116] Since the Retimer chip is mainly used in the PCIE protocol, and the Retimer chip needs to be verified between the RC verification environment and the EP verification environment during post-simulation. Therefore, based on the above method, the embodiment of the present invention also provides a netlist simulation method based on the SV language specifically suitable for the post-simulation of the Retimer chip. The method is applied to Figure 3 The SV language-based netlist simulation system is shown.

[0117] Combine the following Figure 5 First, the specific steps for data exchange between the RC verification environment and the EP verification environment are described:

[0118] Step 310: Verify that the use case module is configured with multiple first stimulus signals that comply with the PCIE protocol.

[0119] Step 320: The RC verification environment sends a plurality of first stimulus signals to the first SV physical layer module.

[0120] Step 330: The first SV physical layer module and the first PIPE interface excitation module perform error injection and randomization operations on the plurality of first excitation signals to generate a first random excitation signal.

[0121] Step 340: The netlist to be tested generates a first processing signal according to the first random stimulus signal, and sends the first processing signal to the second PIPE interface stimulus module.

[0122] Step 350: The second PIPE interface excitation module and the second SV physical layer module perform error injection and randomization operations on the first processed signal to generate a first random processed signal.

[0123] Step 360: The EP verification environment analyzes the received first random processing signal to determine whether the netlist to be tested meets expectations.

[0124] Similarly, see Figure 6 The specific steps for the EP verification environment to exchange data with the RC verification environment are as follows:

[0125] Step 410: Verify that the use case module configuration complies with multiple second excitation signals of the PCIE protocol.

[0126] Step 420: The EP verification environment sends a plurality of second stimulus signals to the second SV physical layer module.

[0127] Step 430: The second SV physical layer module and the second PIPE interface excitation module perform error injection and randomization operations on the plurality of second excitation signals to generate a second random excitation signal.

[0128] Step 440: The netlist to be tested generates a second processed signal according to the second random stimulus signal, and sends the second processed signal to the first PIPE interface stimulus module.

[0129] Step 450: The first PIPE interface excitation module and the first SV physical layer module perform error injection and randomization operations on the second processed signal to generate a second random processed signal.

[0130] Step 460: The RC verification environment analyzes the received second random processing signal to determine whether the netlist to be tested meets expectations.

[0131] Through the first SV physical layer module and the first PIPE interface excitation module, the received first excitation signal and the second processed signal can be injected with errors and randomized, thereby outputting the first random excitation signal and the second random processed signal. Through the second PIPE interface excitation module and the second SV physical layer module, the received first processed signal and the second excitation signal can be injected with errors and randomized, thereby outputting the first random processed signal and the second random excitation signal. This ensures that the RC verification environment can provide randomness in simulation when interacting with the EP verification environment, or when the EP verification environment interacts with the RC verification environment, covering more scenarios.

[0132] In addition, the verification environment configuration module can randomly change the parameters of the verification platform, the first SV physical layer module, the first PIPE interface stimulus module, the second SV physical layer module and the second PIPE interface stimulus module, saving compilation time and further improving the efficiency and randomness of the Retimer chip post-simulation.

[0133] In summary, the embodiment of the present invention provides a netlist simulation system and method based on the SV language. By replacing the physical layer model with the SV physical layer module and the PIPE interface excitation module to post-simulate the netlist to be tested, the drawbacks existing in the prior art can be effectively solved. Since the SV physical layer module in the embodiment of the present invention is a physical layer model designed using the SystemVerilog language, the SystemVerilog language provides high-level data types and can more flexibly represent data structures. At the same time, the SystemVerilog language also provides object-oriented programming, which can more conveniently support code inheritance, encapsulation and polymorphism, and help create modular and reusable code. Therefore, it is easier to implement the physical layer model using the SystemVerilog language than using the Verilog language, which reduces the difficulty of physical layer development, shortens the time of physical layer development, and can provide more debugging time during post-simulation.

[0134] In addition, SystemVerilog also has built-in powerful verification features, such as constraint randomization, assertions, coverage analysis, etc. The SV physical layer module and PIPE interface stimulus module can not only improve the simulation efficiency, but also perform error annotation and randomization operations on multiple received data, and perform exception verification, thereby improving the randomness and coverage of post-chip simulation.

[0135] In addition, the verification environment configuration module can randomly change the parameters of the verification platform, SV physical layer module, and PIPE interface stimulus module. During the simulation process, the stimulus can be changed by modifying the parameters in the verification environment configuration module, saving compilation time and further improving the efficiency of post-chip simulation.

[0136] When the chip to be tested is a Retimer chip, by sequentially setting a first PIPE interface stimulus module, a first SV physical layer module and an RC verification environment on one side of the netlist to be tested, and sequentially setting a second PIPE interface stimulus module, a second SV physical layer module and an EP verification environment on the other side of the netlist to be tested, not only can post-simulation of the Retimer chip be achieved, but also the efficiency and coverage of post-simulation of the Retimer chip can be improved.

[0137] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0138] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A netlist simulation system based on SV language, characterized in that: include: Verification use case module, verification platform, SV physical layer module designed based on SystemVerilog language, PIPE interface stimulus module of physical layer interface of high-speed serial computer expansion bus and netlist to be tested; the verification platform has a built-in verification environment, the verification environment is connected to the SV physical layer module, and the SV physical layer module is connected to the netlist to be tested through the PIPE interface stimulus module; wherein the netlist to be tested is used to provide real physical circuit information with timing in the chip to be tested; The verification case module is used to configure a variety of excitation signals that comply with the PCIE protocol; The verification environment is used to send a variety of stimulus signals to the SV physical layer module; The SV physical layer module and the PIPE interface excitation module are used to perform error injection and randomization operations on a variety of excitation signals to generate random excitation signals; The netlist to be tested is also used to generate a processing signal according to the random stimulus signal, and send the processing signal to the PIPE interface stimulus module; The PIPE interface excitation module and the SV physical layer module are also used to perform error injection and randomization operations on the processed signal to generate a random processed signal; The verification environment is also used to parse the received random processing signal to determine whether the netlist to be tested meets expectations.

2. The SV language-based netlist simulation system according to claim 1, characterized in that: The SV language-based netlist simulation system also includes a verification environment configuration module, which is used to configure parameters of the verification platform, SV physical layer module and PIPE interface stimulus module.

3. The SV language-based netlist simulation system according to claim 2, characterized in that: The verification environment configuration module uses a configuration file to implement parameter configuration, and the configuration file is written in a script to achieve randomization of configuration parameters.

4. The SV language-based netlist simulation system according to claim 1, characterized in that: The verification platform also includes a VIP physical layer component provided by a verification intellectual property core VIP, and the verification environment is connected to the SV physical layer module through the VIP physical layer component.

5. The SV language-based netlist simulation system according to claim 1, characterized in that: When the chip to be tested is a retimer chip, the verification environment includes a root complex RC verification environment and an end device EP verification environment, the SV physical layer module includes a first SV physical layer module and a second SV physical layer module, and the PIPE interface stimulus module includes a first PIPE interface stimulus module and a second PIPE interface stimulus module; one end of the netlist to be tested is connected to one end of the first SV physical layer module through the first PIPE interface stimulus module, and the other end of the first SV physical layer module is connected to the RC verification environment; the other end of the netlist to be tested is connected to one end of the second SV physical layer module through the second PIPE interface stimulus module, and the other end of the second SV physical layer module is connected to the EP verification environment; The verification case module is used to configure a plurality of first excitation signals that comply with the PCIE protocol; The RC verification environment is used to send a plurality of first stimulus signals to the first SV physical layer module; The first SV physical layer module and the first PIPE interface excitation module are used to perform error injection and randomization operations on a plurality of first excitation signals to generate a first random excitation signal; The netlist to be tested is used to generate a first processing signal according to the first random stimulus signal, and send the first processing signal to the second PIPE interface stimulus module; The second PIPE interface excitation module and the second SV physical layer module are used to perform error injection and randomization operations on the first processed signal to generate a first random processed signal; The EP verification environment is used to parse the received first random processing signal to determine whether the netlist to be tested meets expectations.

6. The SV language-based netlist simulation system according to claim 1, characterized in that: When the chip to be tested is a retimer chip, the verification environment includes a root complex RC verification environment and an end device EP verification environment, the SV physical layer module includes a first SV physical layer module and a second SV physical layer module, and the PIPE interface stimulus module includes a first PIPE interface stimulus module and a second PIPE interface stimulus module; one end of the netlist to be tested is connected to one end of the first SV physical layer module through the first PIPE interface stimulus module, and the other end of the first SV physical layer module is connected to the RC verification environment; the other end of the netlist to be tested is connected to one end of the second SV physical layer module through the second PIPE interface stimulus module, and the other end of the second SV physical layer module is connected to the EP verification environment; The verification case module is used to configure a plurality of second excitation signals that comply with the PCIE protocol; The EP verification environment is used to send a plurality of second stimulus signals to the second SV physical layer module; The second SV physical layer module and the second PIPE interface excitation module are used to perform error injection and randomization operations on a plurality of second excitation signals to generate a second random excitation signal; The netlist to be tested is used to generate a second processing signal according to the second random stimulus signal, and send the second processing signal to the first PIPE interface stimulus module; The first PIPE interface excitation module and the first SV physical layer module are used to perform error injection and randomization operations on the second processed signal to generate a second random processed signal; The RC verification environment is used to parse the received second random processing signal to determine whether the netlist to be tested meets expectations.

7. The SV language-based netlist simulation system according to claim 5 or 6, characterized in that: The verification platform also includes a first VIP physical layer component and a second VIP physical layer component provided by a verification intellectual property core VIP. The RC verification environment is connected to the first SV physical layer module through the first VIP physical layer component, and the EP verification environment is connected to the second SV physical layer module through the second VIP physical layer component.

8. A netlist simulation method based on SV language, characterized in that: Applied to the SV language-based netlist simulation system according to any one of claims 1 to 7, the SV language-based netlist simulation method comprises: The verification case module is configured with multiple excitation signals that comply with the PCIE protocol; The verification environment sends a variety of stimulus signals to the SV physical layer module; The SV physical layer module and the PIPE interface excitation module perform error injection and randomization operations on a plurality of excitation signals to generate random excitation signals; The netlist to be tested generates a processing signal according to the random stimulus signal, and sends the processing signal to the PIPE interface stimulus module; The PIPE interface excitation module and the SV physical layer module perform error injection and randomization operations on the processed signal to generate a random processed signal; The verification environment analyzes the received random processing signal to determine whether the netlist to be tested meets expectations.

9. The SV language-based netlist simulation method according to claim 8, characterized in that: When the chip to be tested is a retimer chip, the verification environment includes a root complex RC verification environment and an end device EP verification environment, the SV physical layer module includes a first SV physical layer module and a second SV physical layer module, and the PIPE interface stimulus module includes a first PIPE interface stimulus module and a second PIPE interface stimulus module; one end of the netlist to be tested is connected to one end of the first SV physical layer module through the first PIPE interface stimulus module, and the other end of the first SV physical layer module is connected to the RC verification environment; the other end of the netlist to be tested is connected to one end of the second SV physical layer module through the second PIPE interface stimulus module, and the other end of the second SV physical layer module is connected to the EP verification environment; the netlist simulation method based on the SV language also includes: The verification case module configures a plurality of first excitation signals that comply with the PCIE protocol; The RC verification environment sends a plurality of first stimulus signals to the first SV physical layer module; The first SV physical layer module and the first PIPE interface excitation module perform error injection and randomization operations on a plurality of first excitation signals to generate a first random excitation signal; The netlist to be tested generates a first processing signal according to the first random stimulus signal, and sends the first processing signal to the second PIPE interface stimulus module; The second PIPE interface excitation module and the second SV physical layer module perform error injection and randomization operations on the first processed signal to generate a first random processed signal; The EP verification environment analyzes the received first random processing signal to determine whether the netlist to be tested meets expectations.

10. The SV language-based netlist simulation method according to claim 8, characterized in that: When the chip to be tested is a retimer chip, the verification environment includes a root complex RC verification environment and an end device EP verification environment, the SV physical layer module includes a first SV physical layer module and a second SV physical layer module, and the PIPE interface stimulus module includes a first PIPE interface stimulus module and a second PIPE interface stimulus module; one end of the netlist to be tested is connected to one end of the first SV physical layer module through the first PIPE interface stimulus module, and the other end of the first SV physical layer module is connected to the RC verification environment; the other end of the netlist to be tested is connected to one end of the second SV physical layer module through the second PIPE interface stimulus module, and the other end of the second SV physical layer module is connected to the EP verification environment; the netlist simulation method based on the SV language also includes: The verification case module configures a plurality of second excitation signals that comply with the PCIE protocol; The EP verification environment sends a plurality of second stimulus signals to the second SV physical layer module; The second SV physical layer module and the second PIPE interface excitation module perform error injection and randomization operations on a plurality of second excitation signals to generate a second random excitation signal; The netlist to be tested generates a second processing signal according to the second random stimulus signal, and sends the second processing signal to the first PIPE interface stimulus module; The first PIPE interface excitation module and the first SV physical layer module perform error injection and randomization operations on the second processed signal to generate a second random processed signal; The RC verification environment analyzes the received second random processing signal to determine whether the netlist to be tested meets expectations.

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