A charging current limiting device, method and main control circuit

Abstract

The present application discloses a charging current limiting device, method and main control circuit, which detects the line voltage phase value and trigger angle by using a zero-crossing detection circuit, detects the bus voltage value by using a DC bus voltage detection circuit, and controls the conduction angle of the first thyristor according to the line voltage phase value and the bus voltage value to control the bus capacitor charging current, thereby controlling the current in each stage of the bus capacitor charging step, without increasing the hardware cost, and only by modifying the bus capacitor charging control method, the effect of smooth charging of the bus capacitor can be achieved. The device has the advantages of cost saving and simple control method, and has better reliability than the existing current limiting resistor charging method, and reduces the failure rate in the bus capacitor charging step.

Description

Technical Field

[0001] The present application relates to the field of charging devices, and in particular to a charging current limiting device, method and main control circuit. Background Art

[0002] When the DC bus is charged, the current limiting resistor is used to reduce the current when the bus capacitor is charged. Since the bus capacitor is large, the voltage across the capacitor is zero when the power is connected. Therefore, the charging current of the bus capacitor is very large at the moment of power-on. Excessive current will damage the rectifier bridge diode. To protect the rectifier bridge, a high-power charging resistor is connected in series to the DC bus to limit the charging current at the moment of power-on. When the capacitor voltage reaches a certain level, the charging resistor is short-circuited by a relay or a diode. However, the current limiting resistor generates severe heat during charging, which will reduce the efficiency of the electrical equipment. If the grid voltage fluctuates too much, the ambient temperature is too high, or the charging time is too long, the charging resistor will burn out. Summary of the invention

[0003] The main purpose of this application is to provide a charging current limiting device, method and main control circuit, aiming to solve the technical problem that when charging the bus capacitor, excessive grid voltage fluctuations, high ambient temperature and long charging time will cause the charging resistor to burn out.

[0004] To achieve the above-mentioned purpose, the present application provides a charging current limiting device, a DC bus voltage detection circuit, a zero-crossing detection circuit, a thyristor drive circuit, a DC bus capacitor charging circuit, a bus capacitor, a first thyristor, a main control circuit and a rectifier circuit; the three input ends of the rectifier circuit are respectively connected to the first bus to the third bus, the first output end of the rectifier circuit and the second output end of the rectifier circuit are respectively connected to the first end of the bus capacitor and the second end of the bus capacitor; the first input end of the DC bus voltage detection circuit is connected to the first end of the bus capacitor, the second input end of the DC bus voltage detection circuit is connected to the second end of the bus capacitor, and the DC bus voltage detection circuit is connected to the second end of the bus capacitor. The output end of the bus voltage detection circuit is connected to the first input end of the main control circuit; the input end of the thyristor drive circuit is connected to the output end of the main control circuit, and the two output ends of the thyristor drive circuit are respectively connected to the common end and the first end of the first thyristor, the common end and the first end of the first thyristor are both connected to the first end of the bus capacitor, and the second end of the first thyristor is connected to the first bus; the first input end of the zero-crossing detection circuit is connected to the first bus, the second input end of the zero-crossing detection circuit is connected to the third bus, and the output end of the zero-crossing detection circuit is connected to the second input end of the main control circuit.

[0005] Optionally, the DC bus voltage detection circuit includes a voltage follower circuit, a first voltage limiting circuit, a second voltage limiting circuit, a first current limiting module, a second current limiting module and a first RC filter branch; wherein the first RC filter branch voltage follower circuit includes an amplifier and a second RC filter branch, the first end of the second RC filter branch is connected to the in-phase input end of the amplifier, the second end of the second RC filter branch is connected to the output end of the amplifier, and the output end of the amplifier is connected to the first input end of the main control circuit; the first end of the first voltage limiting circuit is connected to the power supply, and the second end is connected to the in-phase input end of the amplifier; the The first end of the second voltage limiting circuit is connected to the power supply, and the second end is connected to the inverting input of the amplifier; the first current limiting module includes a plurality of first resistors connected in series, the first end of the first current limiting module is connected to the first end of the bus capacitor, and the second end is connected to the non-inverting input of the voltage follower circuit; the second current limiting module includes a plurality of second resistors connected in series, the first end of the second current limiting module is connected to the second input of the bus capacitor, and the second end of the second current limiting module is connected to the inverting input of the amplifier; the first end of the first RC filter branch is connected to the inverting input of the amplifier, and the second end of the first RC filter branch is grounded.

[0006] Optionally, the zero-crossing detection circuit includes: an integration circuit, wherein the in-phase input terminal and the inverting input terminal are respectively connected to the first bus and the third bus, and the output terminal of the integration circuit is connected to the second input terminal of the main control circuit; a third voltage limiting circuit, wherein the first input terminal is connected to the power supply, and the second terminal of the third voltage limiting circuit is connected to the in-phase input terminal of the integration circuit; a fourth voltage limiting circuit, wherein the first input terminal is connected to the power supply, and the second terminal of the fourth voltage limiting circuit is connected to the inverting input terminal of the integration circuit; and a third RC filter branch, wherein the input terminal is connected to the output terminal of the integration circuit, and the output terminal of the third RC filter branch is grounded.

[0007] Optionally, the thyristor drive circuit includes a second thyristor, a gate protection resistor, a bidirectional rectifier, a primary reset circuit, a transformer, a first rectifier diode, a second rectifier diode, a current limiting resistor, a third rectifier diode and a load voltage divider resistor; wherein the first end of the gate protection resistor is connected to the gate of the second thyristor, and the second end is grounded; the first end of the bidirectional rectifier is connected to the gate of the second thyristor, and the second end of the bidirectional rectifier is connected to the first electrode and the ground end of the second thyristor; the two input ends of the primary reset circuit are respectively connected to the power supply and the second electrode of the second thyristor, and the two output ends of the primary reset circuit are respectively connected to the two input ends of the primary side of the transformer; the anode of the first rectifier diode is connected to the The first output end of the transformer, the cathode of the first rectifier diode is connected to the first end of the load voltage-dividing resistor, and the second end of the load voltage-dividing resistor is the first load end of the transformer; the first end of the second rectifier diode is connected between the anode of the first rectifier diode and the load voltage-dividing resistor, the cathode of the second rectifier diode is connected to the second load end of the transformer, the second load end of the transformer is connected to the first end of the first thyristor, and the first load end of the transformer is connected to the common end of the first thyristor; the first end of the current-limiting resistor is connected to the first output end of the main control circuit, and the second end of the current-limiting resistor is connected to the first pole of the second thyristor, the first end of the bidirectional rectifier and the second end of the gate protection resistor.

[0008] Optionally, the primary reset circuit includes a third rectifier diode, a fourth rectifier diode, and a fourth RC filter branch; the cathode of the third rectifier diode is connected to the first input terminal of the primary side of the transformer, the second end of the third rectifier diode is connected to the anode of the fourth rectifier diode, and the cathode of the fourth rectifier diode is connected to the second input terminal of the primary side of the transformer and the second pole of the second thyristor; the fourth RC filter branch is connected to the power supply, and the second end of the fourth RC filter branch is connected to the first input terminal of the primary side of the transformer and the cathode of the first diode.

[0009] Optionally, the DC bus capacitor charging circuit includes a rectifier circuit, a first relay, a second relay and a bus capacitor; the first input end to the third output end of the rectifier circuit are respectively connected to the first bus to the third bus, the first output end of the rectifier circuit is connected to the first end of the bus capacitor, and the second output end of the rectifier circuit is connected to the second input end of the bus capacitor; the second normally open contact of the first relay is connected to the first end of the bus capacitor, the common end of the first thyristor and the first end of the first thyristor, the first end of the coil of the first relay is grounded, and the second end of the coil of the first relay is connected to the first input and output ends of the main control circuit; the first normally closed contact of the second relay is connected to the third bus, the second normally closed contact of the second relay is connected to the second end of the bus capacitor, the first end of the coil of the second relay is grounded, and the second end of the coil of the second relay is connected to the second input and output ends of the main control circuit.

[0010] In order to achieve the above-mentioned purpose, the present invention also provides a charging current limiting method, which is executed by a main control circuit, and the charging current limiting method includes: obtaining the line voltage zero-crossing moment output by the zero-crossing detection circuit; obtaining the bus capacitor voltage value output by the DC bus voltage detection circuit; and controlling the charging current of the bus capacitor according to the line voltage zero-crossing moment and the bus capacitor voltage value.

[0011] Optionally, the charging current of the bus capacitor is controlled according to the time when the line voltage crosses zero and the bus capacitor voltage value, including: judging that the bus capacitor is in the initial charging stage according to the bus capacitor voltage value, and controlling the first relay to open and the second relay to close; controlling the first thyristor to be turned on according to the time when the line voltage crosses zero, and obtaining the initial conduction angle of the first thyristor, the initial value of the bus capacitor charging current, and the initial value of the bus voltage; each time the first thyristor is turned on, controlling the conduction angle of the first thyristor to increase linearly, and controlling the initial value of the bus capacitor charging current and the initial value of the bus voltage to increase linearly until they reach a first preset value of the bus capacitor charging current and a first preset value of the bus voltage respectively; controlling the conduction angle of the first thyristor to decrease, and controlling the first preset value of the bus voltage to continue to increase to a second preset value of the bus voltage, and controlling the bus capacitor charging current to drop from the first preset value to zero.

[0012] Optionally, after controlling the bus capacitor charging current to drop from a first preset value to zero, the charging current limiting method further includes: turning off the first thyristor and the first relay, and turning on the second relay; and charging the bus capacitor using the line voltage until the maximum value of the bus capacitor is reached.

[0013] In order to achieve the above objectives, the present invention also provides a main control circuit, which includes: at least one processor, a memory and an input and output unit; wherein the memory is used to store a computer program, and the processor is used to call the computer program stored in the memory to execute the charging current limiting method.

[0014] The embodiments of the present application propose a charging current limiting device, method and main control circuit, which detect the line voltage phase value and trigger angle through a zero-crossing detection circuit, detect the bus voltage value through a DC bus voltage detection circuit, and control the conduction angle of the first thyristor according to the line voltage phase value and the bus voltage value to control the bus capacitor charging current, thereby controlling the current in each stage of the bus capacitor charging step. The bus capacitor can be smoothly charged without increasing the hardware cost, and the effect of the bus capacitor being smoothly charged can be achieved by only modifying the bus capacitor charging control method. The device has the advantages of low cost and simple control method, and has better reliability than the existing current limiting resistor charging method, thereby reducing the failure rate in the bus capacitor charging step. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A structural diagram of a charging current limiting device provided in one embodiment of the present application;

[0016] Figure 2 A circuit diagram of a DC bus voltage detection circuit provided in an embodiment of the present application;

[0017] Figure 3 A circuit diagram of a zero-crossing detection circuit provided in one embodiment of the present application;

[0018] Figure 4 A circuit diagram of a thyristor driving circuit provided in an embodiment of the present application;

[0019] Figure 5 A circuit diagram of a DC bus capacitor charging circuit provided in an embodiment of the present application;

[0020] Figure 6 A flow chart of a charging current limiting method provided in an embodiment of the present invention.

[0021] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0022] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] Figure 1 This is a structural diagram of a charging current limiting device provided in an embodiment of the present application, refer to Figure 1The charging current limiting device may include: a DC bus voltage detection circuit 100, a zero-crossing detection circuit 200, a thyristor drive circuit 300, a DC bus capacitor charging circuit 400, a bus capacitor C1, a first thyristor Q1, a main control circuit 500 and a rectifier circuit 600, wherein the three input ends of the rectifier circuit 600 are respectively connected to the first bus L1 to the third bus L3, the first output end of the rectifier circuit 600 and the second output end of the rectifier circuit 600 are respectively connected to the first end of the bus capacitor C1 and the second end of the bus capacitor C1; the first input end of the DC bus voltage detection circuit 100 is connected to the first end of the bus capacitor C1, and the second input end of the DC bus voltage detection circuit 100 is connected to the second end of the bus capacitor C1. The output end of the DC bus voltage detection circuit 100 is connected to the first input end of the main control circuit 500; the input end of the thyristor drive circuit 300 is connected to the output end of the main control circuit 500, and the two output ends of the thyristor drive circuit 300 are respectively connected to the common end and the first end of the first thyristor Q1, the first end of the first thyristor Q1 is connected to the first end of the bus capacitor C1, and the second end of the first thyristor Q1 is connected to the first bus L1; the first input end of the zero-crossing detection circuit 200 is connected to the first bus L1, the second input end of the zero-crossing detection circuit 200 is connected to the third bus L3, and the output end of the zero-crossing detection circuit 200 is connected to the second input end of the main control circuit 500.

[0024] In the embodiment of the present application, the bus capacitor voltage value on both sides of the bus capacitor C1 is detected by the DC bus voltage detection circuit 100, and the zero-crossing detection circuit 200 is used to detect the zero-crossing point of the bus line voltage. After detecting the moment when the line voltage crosses zero, the main control circuit 500 controls the first thyristor Q1 to turn on. During the conduction time of the first thyristor Q1 controlled by the main control circuit 500, the first thyristor Q1 controls the increase of the bus capacitor voltage and the charging current, and finally the bus capacitor voltage at both ends of the bus capacitor C1 reaches saturation, thereby completing the charging of the bus capacitor C1.

[0025] The embodiment of the present invention improves the existing inverter bus capacitor C1 charging control circuit, so that the bus capacitor C1 can adapt to different input voltages on the inverter grid side, and can limit the charging current of the bus capacitor C1, thereby preventing the initial charging current from being too large and breaking down the bus capacitor C1.

[0026] Exemplarily, the main control circuit 500 is used to read the voltage value of the bus capacitor C1. The main control circuit 500 fuses the voltage value of the bus capacitor and the data at the time when the line voltage passes through zero, realizes the shift control of the first thyristor, and further realizes the control of the charging current of the bus capacitor C1.

[0027] Figure 2 A circuit diagram of a DC bus voltage detection circuit provided in an embodiment of the present application, referring to Figure 2 In an embodiment of the present invention, a DC bus voltage detection circuit 100 may include a voltage follower circuit U1C, a first voltage limiting circuit D1, a second voltage limiting circuit D2, a first current limiting module R1, a second current limiting module R2 and a first RC filter branch RC1, wherein the voltage follower circuit U1C includes an amplifier and a second RC filter branch RC2, a first end of the second RC filter branch RC2 is connected to the in-phase input end of the amplifier, a second end of the second RC filter branch RC2 is connected to the output end of the amplifier, and the output end of the amplifier is connected to the first input end of the main control circuit 500; a first end of the first voltage limiting circuit is connected to a power supply, and a second end is connected to the in-phase input end of the amplifier; a first end of the second voltage limiting circuit is connected to a power supply, and a second end is connected to the in-phase input end of the amplifier. The first current limiting module R1 includes a plurality of first resistors connected in series, wherein the first end of the first current limiting module R1 is connected to the first end of the bus capacitor C1, and the second end is connected to the non-inverting input end of the amplifier; the second current limiting module R2 includes a plurality of second resistors connected in series, wherein the first end of the second current limiting module R2 is connected to the second end of the bus capacitor C1, and the second end of the second current limiting module R2 is connected to the inverting input end of the amplifier; the first end of the first RC filter branch RC1 is connected to the inverting input end of the amplifier, and the second end of the first RC filter branch RC1 is grounded.

[0028] Specifically, the first voltage limiting circuit D1 is used to keep the voltage at the in-phase input terminal of the amplifier fluctuating within a small range. The first voltage limiting circuit D1 includes a first diode and a second diode, the cathode of the first diode is connected to the +5V power supply, the anode is connected to the in-phase input terminal of the amplifier, the anode of the second diode is connected to the ground, and the cathode is connected to the in-phase input terminal of the amplifier. The second voltage limiting circuit D2 is used to keep the voltage at the inverting input terminal of the amplifier fluctuating within a small range. The second voltage limiting circuit D2 includes a third diode and a fourth diode, wherein the anode of the third diode is connected to the power supply, the cathode is connected to the inverting input terminal of the amplifier, the first end of the first RC filter branch RC1 is connected to the inverting input terminal of the amplifier, and the second end is grounded. The first current limiting module R1 and the second current limiting module R2 respectively include the same number of first resistors and second resistors. The first current limiting module R1 and the second current limiting module R2 limit the input current of the amplifier. The input voltage and output voltage of the voltage follower circuit U1C remain unchanged.

[0029] Figure 3 A circuit diagram of a zero-crossing detection circuit provided in an embodiment of the present application, referring to Figure 3In an embodiment of the present application, the zero-crossing detection circuit 200 may include an integration circuit U1B, a third voltage limiting circuit D3, a fourth voltage limiting circuit D4 and a third RC filter branch RC3, wherein the in-phase input terminal and the inverting input terminal of the integration circuit U1B are respectively connected to the first bus L1 and the third bus L3, and the output terminal of the integration circuit U1B is connected to the second input terminal of the main control circuit 500; the first input terminal of the third voltage limiting circuit D3 is connected to the power supply, and the second terminal of the third voltage limiting circuit D3 is connected to the in-phase input terminal of the integration circuit U1B; the first input terminal of the fourth voltage limiting circuit D4 is connected to the power supply, and the second terminal of the fourth voltage limiting circuit D4 is connected to the inverting input terminal of the integration circuit U1B; the input terminal of the third RC filter branch RC3 is connected to the output terminal of the integration circuit U1B, and the output terminal of the third RC filter branch RC3 is grounded.

[0030] Specifically, the third voltage limiting circuit D3 is used to keep the voltage at the in-phase input terminal of the integration circuit U1B fluctuating within a small range. The third voltage limiting circuit D3 may include a fifth diode, a sixth diode and a first filter capacitor C2, wherein the cathode of the fifth diode is connected to a +5V power supply, the anode is connected to the in-phase input terminal of the integration circuit U1B, the anode of the sixth diode is grounded, the cathode is connected to the inverting input terminal of the integration circuit U1B, the first end of the first filter capacitor C2 is grounded, and the second end is connected to the in-phase input terminal of the integration circuit U1B. The fourth voltage limiting circuit D4 is used to keep the voltage at the inverting input terminal of the integration circuit U1B fluctuating within a small range. The fourth voltage limiting circuit D4 includes a seventh diode, an eighth diode and a second filter capacitor C3, wherein the cathode of the seventh diode is connected to a +5V power supply, the anode is connected to the inverting input terminal of the integration circuit U1B, the anode of the sixth diode is grounded, the cathode is connected to the reverse end of the integration circuit U1B, the first end of the second filter capacitor C3 is grounded, and the second end is connected to the in-phase input terminal of the integration circuit U1B. The zero-crossing detection circuit 200 further includes a first current limiting resistor R6 and a second current limiting resistor R7, which are connected to the non-inverting input terminal of the integration circuit U1B and the inverting input terminal of the integration circuit U1B, respectively.

[0031] Figure 4 A circuit diagram of a thyristor driving circuit provided in an embodiment of the present application is shown in FIG. Figure 4In an embodiment of the present invention, the thyristor driving circuit 300 includes a second thyristor Q2, a gate protection resistor R5, a bidirectional rectifier G, a primary reset circuit X, a transformer T1, a current limiting resistor R4, a first rectifier diode D5, a second rectifier diode D6 and a load voltage divider resistor R3, wherein a first end of the gate protection resistor R5 is connected to the gate of the second thyristor Q2, and a second end is grounded; a first end of the bidirectional rectifier G is connected to the gate of the second thyristor Q2, and a second end of the bidirectional rectifier G is connected to the first electrode and the ground of the second thyristor Q2; two input ends of the primary reset circuit X are respectively connected to a power supply and a second electrode of the second thyristor Q2, and two output ends of the primary reset circuit X are respectively connected to two input ends of the primary side of the transformer T1; an anode of the first rectifier diode D5 is connected to a The first output terminal of the transformer T1 is connected to the cathode of the first rectifier diode D5, and the second end of the load voltage-dividing resistor is the first load terminal of the transformer T1; the anode of the second rectifier diode D6 is connected between the anode of the first rectifier diode D5 and the load voltage-dividing resistor R3, and the cathode of the second rectifier diode D6 is connected to the second load terminal of the transformer T1, and the second load terminal of the transformer T1 is connected to the first end of the first thyristor Q1, and the first load terminal of the transformer T1 is connected to the common terminal of the first thyristor Q1; the first end of the current-limiting resistor R4 is connected to the first output terminal of the main control circuit 500, and the second end of the current-limiting resistor R4 is connected to the first electrode of the second thyristor Q2, the first end of the bidirectional rectifier G and the second end of the gate protection resistor R5.

[0032] Specifically, the first thyristor Q1 is used to control the path from the first bus L1 to the bus capacitor C1, and to control the charging current and charging voltage of the bus capacitor C1. The gate protection resistor R5 is used to limit the voltage of the second thyristor Q2. The bidirectional rectifier G is used to rectify the current. The primary reset circuit X is used to reset the transformer T1 to the initial state, and also has the function of eliminating the spike of the primary side of the transformer T1. The second rectifier diode D6 is used to reset the secondary side of the transformer T1 to the initial state.

[0033] In an embodiment of the present application, the primary reset circuit X includes a third rectifier diode D7, a fourth rectifier diode D8, and a fourth RC filter branch RC4, wherein the cathode of the third rectifier diode D7 is connected to the first input terminal of the primary side of the transformer, the second end of the third rectifier diode D7 is connected to the anode of the fourth rectifier diode D8, and the cathode of the fourth rectifier diode D8 is connected to the second input terminal of the primary side of the transformer T1 and the second pole of the second thyristor Q2; the first end of the fourth RC filter branch RC4 is connected to the power supply, and the second end of the fourth RC filter branch RC4 is connected to the first input terminal of the primary side of the transformer T1 and the cathode of the third rectifier diode D7.

[0034] Figure 5 A circuit diagram of a DC bus capacitor charging circuit provided in an embodiment of the present application, referring to Figure 5 In an embodiment of the present application, a DC bus capacitor charging circuit 400 includes a rectifier circuit 600, a first relay A1, a second relay A2, and a bus capacitor C1, wherein the first input end to the third output end of the rectifier circuit 600 are respectively connected to the first bus L1 to the third bus L3, the first output end of the rectifier circuit 600 is connected to the first end of the bus capacitor C1, and the second output end of the rectifier circuit 600 is connected to the second end of the bus capacitor C1; the first normally open contact of the first relay A1 is connected to the first output end of the rectifier circuit 600, and the second normally open contact of the first relay A2 is connected to the first output end of the rectifier circuit 600. The first end of the bus capacitor C1, the common end of the first thyristor Q1 and the first end of the first thyristor Q1 are connected, the first end of the coil of the first relay A1 is grounded, and the second end of the coil of the first relay A1 is connected to the first input-output end of the main control circuit 500; the first normally closed contact of the second relay A2 is connected to the third bus L3, the second normally closed contact of the second relay A2 is connected to the second end of the bus capacitor C1, the first end of the coil of the second relay A2 is grounded, and the second end of the coil of the second relay A2 is connected to the second input-output end of the main control circuit 500.

[0035] Based on the above embodiment, the embodiment of the present invention further provides a charging current limiting method, which is executed by the main control circuit 500. Figure 6 A flow chart of a charging current limiting method provided by an embodiment of the present invention, referring to Figure 6 , the charging current limiting method comprises:

[0036] S10, obtaining the zero-crossing moment of the line voltage output by the zero-crossing detection circuit 200;

[0037] S20, obtaining the bus capacitor voltage value output by the DC bus voltage detection circuit 100;

[0038] S30. Control the charging current of the bus capacitor according to the line voltage zero-crossing point moment and the bus capacitor voltage value.

[0039] Specifically, controlling the charging current of the bus capacitor according to the line voltage zero-crossing point moment and the bus capacitor voltage value includes:

[0040] S31, judging that the bus capacitor is in the initial charging stage according to the bus capacitor voltage value, and controlling the first relay to be turned on and the second relay to be turned off;

[0041] S32, controlling the first thyristor to conduct according to the zero-crossing moment of the line voltage, and obtaining an initial conduction angle of the first thyristor, an initial value of the bus capacitor charging current, and an initial value of the bus voltage;

[0042] S33, each time the first thyristor is turned on, controlling the conduction angle of the first thyristor to increase linearly, and controlling the initial value of the bus capacitor charging current and the initial value of the bus voltage to increase linearly, until they reach a first preset value of the bus capacitor charging current and a first preset value of the bus voltage respectively;

[0043] S34, controlling the conduction angle of the first thyristor to decrease, controlling the bus voltage to continue to increase from the first preset value to the second preset value of the bus voltage, and controlling the bus capacitor charging current to continue to decrease from the first preset value to zero.

[0044] Specifically, after controlling the bus capacitor charging current to continuously decrease from the first preset value to zero, the charging current limiting method further includes:

[0045] S35, turning off the first thyristor and the first relay, and turning on the second relay;

[0046] S36. Using the line voltage to charge the bus capacitor until the bus capacitor reaches a maximum value.

[0047] Specifically, through the above connection, the main control circuit 500 controls the conduction of the first thyristor Q1 through the thyristor driving circuit 300, so as to start charging the bus capacitor. When charging starts, the first relay A1 is turned on and the second relay A2 is turned off. At this time, the first thyristor Q1 is turned on, and the first bus L1 outputs a small DC to charge the bus capacitor C1. The main control circuit 500 controls the conduction angle of the first thyristor Q1, so as to control the bus voltage and bus charging current at both ends of the bus capacitor C1 to increase linearly until the bus voltage reaches the first preset value and the bus capacitor charging current reaches the first preset value. The bus capacitor charging current is the maximum current value that the bus capacitor can withstand. Thereafter, the main control circuit 500 controls the conduction angle of the first thyristor Q1 to decrease, so that the charging voltage continues to increase, while the charging current decreases, until the charging current decreases to 0, and the charging at this stage is stopped. In this way, the excessive charging current of the bus capacitor C1 can be avoided to break down the bus capacitor C1. Then, the main control circuit 500 controls the conduction angle of the first thyristor Q1 to close, the first relay A1 to close, and the second relay A2 to open. The main control circuit 500 controls the bus capacitor C1 to enter the next stage of charging. At this time, the first bus L1, the second bus output terminal L2 and the third bus L3 supply power to the bus capacitor C1 through the rectifier circuit 600, and the voltage across the bus capacitor C1 further increases until it reaches the maximum voltage across the bus capacitor.

[0048] Based on the above embodiments, an embodiment of the present invention further provides a main control circuit, which includes: at least one processor, a memory and an input and output unit; wherein the memory is used to store a computer program, and the processor is used to call the computer program stored in the memory to execute the charging current limiting method.

[0049] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A charging current limiting device, characterized in that: include: DC bus voltage detection circuit, zero-crossing detection circuit, thyristor drive circuit, first thyristor and main control circuit, bus capacitor and rectification circuit; The three input ends of the rectifier circuit are respectively connected to the first bus to the third bus, and the first output end of the rectifier circuit and the second output end of the rectifier circuit are respectively connected to the first end of the bus capacitor and the second end of the bus capacitor; The first input end of the DC bus voltage detection circuit is connected to the first end of the bus capacitor, the second input end of the DC bus voltage detection circuit is connected to the second end of the bus capacitor, and the output end of the DC bus voltage detection circuit is connected to the first input end of the main control circuit; The input end of the thyristor drive circuit is connected to the output end of the main control circuit, the two output ends of the thyristor drive circuit are respectively connected to the common end and the first end of the first thyristor, the first end of the first thyristor is connected to the first end of the bus capacitor, and the second end of the first thyristor is connected to the first bus; The first input end of the zero-crossing detection circuit is connected to the first bus, the second input end of the zero-crossing detection circuit is connected to the third bus, and the output end of the zero-crossing detection circuit is connected to the second input end of the main control circuit; Among them, the DC bus voltage detection circuit is used to detect and obtain the bus voltage value, the zero-crossing detection circuit is used to detect and obtain the line voltage phase value, and the bus voltage value and the line voltage phase value are used to control the conduction angle of the first thyristor to control the bus capacitor charging current.

2. The charging current limiting device according to claim 1, characterized in that: The DC bus voltage detection circuit includes a voltage follower circuit, a first voltage limiting circuit, a second voltage limiting circuit, a first current limiting module, a second current limiting module and a first RC filter branch; The voltage follower circuit includes an amplifier and a second RC filter branch, wherein a first end of the second RC filter branch is connected to a non-inverting input end of the amplifier, a second end of the second RC filter branch is connected to an output end of the amplifier, and the output end of the amplifier is connected to a first input end of the main control circuit; A first end of the first voltage limiting circuit is connected to a power supply, and a second end is connected to a non-inverting input end of the amplifier; A first end of the second voltage limiting circuit is connected to a power supply, and a second end is connected to an inverting input end of the amplifier; The first end of the first current limiting module is connected to the first end of the bus capacitor, and the second end is connected to the non-inverting input end of the voltage follower circuit; the first end of the second current limiting module is connected to the second input end of the bus capacitor, and the second end of the second current limiting module is connected to the inverting input end of the amplifier; A first end of the first RC filter branch is connected to the inverting input end of the amplifier, and a second end of the first RC filter branch is grounded.

3. The charging current limiting device according to claim 1, characterized in that: The zero-crossing detection circuit comprises: An integration circuit, wherein the in-phase input terminal and the inverting input terminal are respectively connected to the first bus and the third bus, and the output terminal is connected to the second input terminal of the main control circuit; A third voltage limiting circuit, having a first input terminal connected to a power supply, and a second terminal connected to a non-inverting input terminal of the integration circuit; a fourth voltage limiting circuit, wherein a first input terminal is connected to a power supply, and a second terminal is connected to an inverting input terminal of the integration circuit; The third RC filter branch has an input end connected to the output end of the integration circuit and an output end connected to the ground.

4. The charging current limiting device according to claim 1, characterized in that: The thyristor drive circuit includes a second thyristor, a gate protection resistor, a bidirectional rectifier, a primary reset circuit, a transformer, a first rectifier diode, a second rectifier diode, a current limiting resistor, a third rectifier diode and a load voltage divider resistor; Wherein, a first end of the gate protection resistor is connected to the gate of the second thyristor, and a second end is grounded; The first end of the bidirectional rectifier is connected to the gate of the second thyristor, and the second end of the bidirectional rectifier is connected to the first electrode of the second thyristor and the ground terminal; The two input ends of the primary reset circuit are respectively connected to the power supply and the second electrode of the second thyristor, and the two output ends of the primary reset circuit are respectively connected to the two input ends of the primary side of the transformer; The anode of the first rectifier diode is connected to the first output terminal of the transformer, the cathode of the first rectifier diode is connected to the first end of the load voltage-dividing resistor, and the second end of the load voltage-dividing resistor serves as the first load end of the transformer; The first end of the second rectifier diode is connected between the anode of the first rectifier diode and the load voltage divider resistor, the cathode of the second rectifier diode is connected to the second load end of the transformer, the second load end of the transformer is connected to the first end of the first thyristor, and the first load end of the transformer is connected to the common end of the first thyristor; The first end of the current limiting resistor is connected to the first output end of the main control circuit, and the second end of the current limiting resistor is connected to the first electrode of the second thyristor, the first end of the bidirectional rectifier and the second end of the gate protection resistor.

5. The charging current limiting device according to claim 4, characterized in that: The primary reset circuit includes a third rectifier diode, a fourth rectifier diode, and a fourth RC filter branch; The cathode of the third rectifier diode is connected to the first input terminal of the primary side of the transformer, the second end of the third rectifier diode is connected to the anode of the fourth rectifier diode, and the cathode of the fourth rectifier diode is connected to the second input terminal of the primary side of the transformer and the second electrode of the second thyristor; The fourth RC filter branch is connected to the power supply, and the second end of the fourth RC filter branch is connected to the first input end of the primary side of the transformer and the cathode of the third rectifier diode.

6. The charging current limiting device according to claim 1, characterized in that: The charging current limiting device also includes a first relay and a second relay; The first input end to the third output end of the rectifier circuit are respectively connected to the first bus to the third bus, the first output end of the rectifier circuit is connected to the first end of the bus capacitor, and the second output end of the rectifier circuit is connected to the second input end of the bus capacitor; The second normally open contact of the first relay is connected to the first end of the bus capacitor, the common end of the first thyristor and the first end of the first thyristor, the first end of the coil of the first relay is grounded, and the second end of the coil of the first relay is connected to the first input and output end of the main control circuit; The first normally closed contact of the second relay is connected to the third bus, the second normally closed contact of the second relay is connected to the second end of the bus capacitor, the first end of the coil of the second relay is grounded, and the second end of the coil of the second relay is connected to the second input and output end of the main control circuit.

7. A charging current limiting method, applied to the charging current limiting device according to any one of claims 1 to 6, characterized in that: The charging current limiting method is executed by a main control circuit, and the charging current limiting method includes: Obtaining the zero-crossing moment of the line voltage output by the zero-crossing detection circuit; Obtaining a bus capacitor voltage value output by the DC bus voltage detection circuit; The charging current of the bus capacitor is controlled according to the zero-crossing point of the line voltage and the voltage value of the bus capacitor.

8. The charging current limiting method according to claim 7, characterized in that: The DC bus capacitor charging circuit also includes a first relay and a second relay, wherein the second normally open contact of the first relay is connected to the first end of the bus capacitor, the common end of the first thyristor and the first end of the first thyristor, the first end of the coil of the first relay is grounded, and the second end of the coil of the first relay is connected to the first input-output end of the main control circuit; the first normally closed contact of the second relay is connected to the third bus, the second normally closed contact of the second relay is connected to the second end of the bus capacitor, the first end of the coil of the second relay is grounded, and the second end of the coil of the second relay is connected to the second input-output end of the main control circuit, and the charging current of the bus capacitor is controlled according to the zero-crossing moment of the line voltage and the voltage value of the bus capacitor, including: According to the bus capacitor voltage value, determine that the bus capacitor is in the initial charging stage, and control the first relay to open and the second relay to close; Controlling the first thyristor to conduct according to the zero-crossing moment of the line voltage, and obtaining an initial conduction angle of the first thyristor, an initial value of the bus capacitor charging current, and an initial value of the bus voltage; Each time the first thyristor is turned on, the conduction angle of the first thyristor is controlled to increase linearly, and the initial value of the bus capacitor charging current and the initial value of the bus voltage are controlled to increase linearly, until they reach a first preset value of the bus capacitor charging current and a first preset value of the bus voltage respectively; The conduction angle of the first thyristor is controlled to decrease, the first preset value of the bus voltage is controlled to continue to increase to the second preset value of the bus voltage, and the charging current of the bus capacitor is controlled to decrease from the first preset value to zero.

9. The charging current limiting method according to claim 8, characterized in that: After controlling the bus capacitor charging current to drop from the first preset value to zero, the charging current limiting method further includes: Turn off the first thyristor and the first relay, and turn on the second relay; The bus capacitor is charged by utilizing the line voltage until the bus capacitor reaches a maximum value.

10. A main control circuit, characterized in that: The main control circuit comprises: at least one processor, a memory and an input-output unit; wherein the memory is used to store a computer program, and the processor is used to call the computer program stored in the memory to execute the charging current limiting method according to any one of claims 7 to 9.

Images