Display panel, display device and manufacturing method

Abstract

The application discloses a display panel, a display device and a manufacturing method. The display panel of one embodiment comprises a hole region and a display region, the display region comprises a pixel light-emitting region located on at least one side of the hole region, the display module comprises a substrate, a plurality of mutually insulated wiring layers, a pixel definition layer, an encapsulation layer and a shielding layer which are sequentially stacked, wherein the pixel definition layer is provided with a first through hole in the hole region, the first through hole is a first hole projection in the orthographic projection of the substrate; the combination projection of the orthographic projection of the plurality of wiring layers located in the display region surrounds the first hole projection, the plurality of wiring layers comprise a first wiring layer and a second wiring layer, the first wiring layer is closer to the substrate than the second wiring layer, in the first direction, the first wiring layer is disconnected close to the center position of the first through hole, the two ends of the second wiring layer are respectively electrically connected to the disconnected first wiring layer, and the first distance between the first wiring layer and the first hole projection is smaller than the second distance between the second wiring layer and the first hole projection.

Description

Technical Field

[0001] This invention relates to the field of display technology. More specifically, it relates to a display panel, a display device, and a method of manufacturing it. Background Technology

[0002] With the development of COE (color film on encapsulation) technology, for display panels with sensing capabilities, customers have requirements for sensor apertures that go beyond transmittance; the field of view (FOV) at the sensor aperture location has also become a strong demand. However, with increasingly complex display driving circuits, the design space left for sensor apertures is limited. Therefore, under the influence of increasingly narrow circuit traces, effectively improving the FOV while ensuring the transmittance of the sensor apertures has become a pressing issue that needs to be addressed. Summary of the Invention

[0003] The purpose of this invention is to provide a display panel, a display device, and a manufacturing method to solve at least one of the problems existing in the prior art.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] A first aspect of the present invention provides a display panel, the display panel including an aperture region and a display area at least surrounding a portion of the aperture region, the display area including a pixel light-emitting region located on at least one side of the aperture region, characterized in that the display panel includes a substrate, a plurality of mutually insulated wiring layers, a pixel defining layer, an encapsulation layer, and a shielding layer sequentially stacked.

[0006] Wherein, the pixel defining layer forms a first through hole in the hole area, and the shielding layer forms a second through hole in the hole area at a position corresponding to the first through hole, and the orthographic projection of the first through hole onto the substrate is the first hole projection;

[0007] The combined projection of the orthographic projection of the multiple wiring layers located in the display area onto the substrate surrounds the projection of the first aperture.

[0008] The plurality of wiring layers includes a first wiring layer and a second wiring layer, both extending along a first direction, wherein the first wiring layer is closer to the substrate than the second wiring layer.

[0009] In a first direction, the first trace layer is disconnected near the center of the first via, and the two ends of the second trace layer are electrically connected to the disconnected first trace layer.

[0010] The minimum distance between the projection boundary of the first wiring layer on the substrate and the projection boundary of the first hole in the second direction is the first distance, and the minimum distance between the projection boundary of the second wiring layer on the substrate and the projection boundary of the first hole in the second direction is the second distance, wherein the first distance is less than the second distance.

[0011] In an optional embodiment, the first trace layer and the second trace layer are two non-adjacent conductive layers in the stacking direction.

[0012] The display panel further includes: at least one third wiring layer and a plurality of insulating layers located between the first wiring layer and the second wiring layer, wherein the plurality of insulating layers are used to insulate the first wiring layer, the at least one third wiring layer, and the second wiring layer, respectively.

[0013] The first wiring layer and the second wiring layer are electrically connected through a first connection hole that penetrates the plurality of insulating layers.

[0014] In an optional embodiment, the disconnected first trace layer and second trace layer are provided on both sides of the two opposite first boundaries of the first hole projection.

[0015] With the central axis extending along the first direction as the first axis of symmetry, the orthographic projections of the disconnected first and second trace layers on the substrate located on each side of the first boundary are symmetrical about the first axis of symmetry.

[0016] In an optional embodiment, the first aperture projection includes a first boundary extending along a first direction and a second boundary extending along a second direction, wherein the first boundary includes at least a straight boundary extending along the first direction.

[0017] The distance between the projection boundary of the first wiring layer on the substrate and the straight boundary of the first boundary is the first distance, and the distance between the projection boundary of the second wiring layer on the substrate and the straight boundary of the first boundary is the first distance.

[0018] In an optional embodiment, the second trace layer includes: a first end and a second end of the first trace layer that are electrically disconnected, and a first connection portion located between the first end and the second end.

[0019] Wherein, the orthographic projection of the first end on the substrate overlaps with the orthographic projection of a break edge of the first wiring layer on the substrate, and the orthographic projection of the second end on the substrate overlaps with the orthographic projection of another break edge of the first wiring layer on the substrate.

[0020] The extension length of the first connection portion along the first direction in the orthographic projection of the substrate is greater than or equal to the extension length of the straight boundary of the first boundary.

[0021] In an optional embodiment, the plurality of wiring layers further includes a fourth wiring layer and a fifth wiring layer insulated from the fourth insulating layer, wherein the fourth wiring layer is closer to the substrate than the fifth wiring layer.

[0022] The fifth routing layer includes:

[0023] A third end electrically connected to the fourth wiring layer via a second connection hole, wherein the orthographic projection of the third end onto the substrate overlaps the orthographic projection of the fourth wiring layer onto the substrate; and

[0024] The second connecting portion extending along the second direction,

[0025] The minimum distance between the third end and the second boundary extending along the second direction of the projection of the first hole is the third distance, and the minimum distance between the second connecting part and the second boundary extending along the second direction of the projection of the first hole is the fourth distance. The third distance is less than the fourth distance.

[0026] In an optional embodiment, the fourth and fifth wiring layers are two adjacent conductive layers in the stacking direction.

[0027] The display panel further includes an insulating layer located between the fourth wiring layer and the fifth wiring layer, wherein the fourth wiring layer and the fifth wiring layer are electrically connected through a second connection hole penetrating the insulating layer.

[0028] In an optional embodiment, the fourth routing layer and the fifth routing layer are provided on both sides of the two opposite second boundaries of the projection of the first hole.

[0029] With the central axis extending along the second direction from the projection of the first hole as the second axis of symmetry, the orthographic projections of the fourth and fifth wiring layers located on each side of the second boundary onto the substrate are symmetrical projections with the second axis of symmetry as the second axis of symmetry.

[0030] In an optional embodiment, the second boundary includes at least a straight boundary extending along the first direction.

[0031] The combined projection of the third end and the second connection portion onto the substrate extends along the second direction at a length greater than the extension length of the straight boundary of the second boundary.

[0032] In an optional embodiment, in the stacking direction, the distance between the first wiring layer, the fourth wiring layer and the second wiring layer and the substrate gradually increases, the fourth wiring layer and the third wiring layer are disposed in the same layer, and the second wiring layer and the fifth wiring layer are disposed in the same layer.

[0033] In an optional embodiment, in the stacking direction, the distance between the first wiring layer, the fourth wiring layer, the at least one third wiring layer, and the second wiring layer and the substrate gradually increases, one of the at least one third wiring layers closer to the substrate is disposed in the same layer as the fourth wiring layer, and one of the at least one third wiring layers is disposed in the same layer as the fifth wiring layer.

[0034] In an optional embodiment, the plurality of wiring layers further includes at least one sixth wiring layer, which is the wiring layer among the plurality of wiring layers that has the largest distance from the substrate in the stacking direction.

[0035] The first routing layer, the second routing layer, the fourth routing layer, the fifth routing layer, and the sixth routing layer constitute a display driving circuit;

[0036] or

[0037] The first routing layer, the second routing layer, the third routing layer, the fourth routing layer, the fifth routing layer, and the sixth routing layer constitute a display driving circuit.

[0038] In an optional embodiment, taking the central axis extending along the second direction from the projection of the first aperture as a cross section, the minimum boundary distance L between the sidewall of each routing layer near the projection of the first aperture and the first boundary of the projection of the first aperture satisfies the following formula:

[0039]

[0040] Wherein, H1 is the interlayer thickness between the surface of each wiring layer near the substrate and the surface of the shielding layer near the substrate;

[0041] a is the diameter of the cross-section of the second through hole at the cross-section;

[0042] d is the distance between one side wall of the first through hole and one side wall of the second through hole;

[0043] c is the interlayer thickness between the surface of the pixel defining layer away from the substrate and the surface of the shielding layer close to the substrate;

[0044] e is the thickness of the pixel-defining layer.

[0045] In an optional embodiment, the display area includes a first display area and a second display area surrounding the first display area.

[0046] The first display area includes a pixel light-emitting area and a non-pixel light-emitting area located around the pixel light-emitting area.

[0047] The pixel light-emitting area is provided with sub-pixels defined by a pixel delimiting layer.

[0048] The non-pixel light-emitting area is provided with at least one of the aperture areas, which are disposed in the gaps between each sub-pixel.

[0049] A second aspect of the present invention provides a display device, including the display panel described in the first aspect of the present invention.

[0050] In an optional embodiment, the display device further includes a sensing element disposed at a location corresponding to the hole area, located on the side of the substrate of the display panel away from the plurality of wiring layers.

[0051] A third aspect of the present invention provides a method for manufacturing a display panel according to the first aspect of the present invention, the method comprising:

[0052] Multiple mutually insulating wiring layers are sequentially formed on the substrate corresponding to the display area;

[0053] A pixel delimiting layer is formed on the wiring layer of the display area and on the insulating layer covering the wiring layer of the hole area;

[0054] The pixel defining layer located in the hole region is etched to form a first via, and the orthographic projection of the first via on the substrate is the first hole projection;

[0055] An encapsulation layer and a masking layer are sequentially formed on the pixel definition layer;

[0056] The shielding layer is etched at the location corresponding to the first through-hole to form a second through-hole;

[0057] The method further includes forming multiple mutually insulating wiring layers sequentially on the substrate corresponding to the display area, and further comprising:

[0058] A first trace layer extending in a first direction is formed on a substrate corresponding to the display area, wherein the first trace layer is interrupted near the center of the first via in the first direction;

[0059] A second trace layer is formed on the first trace layer and extends along a first direction, which is insulated from the first trace layer. The two ends of the second trace layer are electrically disconnected from the first trace layer. The minimum distance between the projection boundary of the first trace layer on the substrate and the projection boundary of the first hole in the second direction is a first distance. The minimum distance between the projection boundary of the second trace layer on the substrate and the projection boundary of the first hole in the second direction is a second distance. The first distance is less than the second distance.

[0060] The beneficial effects of this invention are as follows:

[0061] In this embodiment of the invention, the traces extending along the first direction on both the upper and lower sides of the first through hole are designed to cross over each other, and the distance between the traces extending along the first direction and the first through hole is calculated. Near the center of the first through hole, the second distance between the second trace layer located above the first through hole in the layer structure and the first through hole is set to be greater than the first distance between the first trace layer and the first through hole, so as to achieve the effect of increasing the field of view. Attached Figure Description

[0062] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0063] Figure 1 The diagram illustrates the wiring design around the hole area in a display panel of a related technology.

[0064] Figure 2 Show Figure 1 A schematic diagram of the layer structure when all routing layers are on the same layer under the routing structure shown;

[0065] Figure 3 The wiring design of the display panel on both sides of the first through hole is shown in the first embodiment of the present invention;

[0066] Figure 4 Show Figure 3 A schematic diagram of the layered structure at the mid-section location;

[0067] Figure 5 Show Figure 3 and Figure 4 The diagram shows the field of view under the wiring design.

[0068] Figure 6 The wiring design of the display panel on both sides of the first through hole is shown in a second optional embodiment of the present invention;

[0069] Figure 7 Show Figure 6 A schematic diagram of the layered structure at the mid-section location;

[0070] Figure 8 Show Figure 6 and Figure 7 The diagram shows the field of view under the wiring design.

[0071] Figure 9 This illustrates the wiring design around the hole area in a display panel of another related technology;

[0072] Figure 10 The wiring design of the display panel on both sides of the first through hole is shown in a third optional embodiment of the present invention;

[0073] Figure 11 Show Figure 10 A schematic diagram of the layered structure at the mid-section location;

[0074] Figure 12 A fourth optional embodiment of the present invention is shown. Figure 3 and Figure 10 The wiring design of the combined embodiment shown;

[0075] Figure 13 Show Figure 11 A schematic diagram of the layered structure at the mid-section location;

[0076] Figure 14 A fifth alternative embodiment of the present invention is shown. Figure 6 and Figure 10 The wiring design of the combined embodiment shown;

[0077] Figure 15 Show Figure 14 A schematic diagram of the layered structure at the mid-section location;

[0078] Figure 16 A schematic diagram showing the boundary distance between each routing layer and the sidewall of the first via;

[0079] Figure 17 This diagram illustrates the location of the hole region in one embodiment of the present invention.

[0080] Figure 18 Show Figure 17 A schematic diagram showing the positions of each sub-pixel in the aperture area and pixel light-emitting area of ​​this embodiment of the invention. Detailed Implementation

[0081] To more clearly illustrate the present invention, the following description, in conjunction with embodiments and accompanying drawings, further explains the invention. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of the present invention.

[0082] Figure 1 This illustrates the wiring design of the display area near the hole area of ​​a display panel in the related art. Figure 2 It shows that Figure 1 The vertical axis shown is a schematic diagram of the layered structure under the cross-section, as shown below. Figure 1 As shown, each wiring layer 20 is routed around the hole area NA. The metal wiring space of each wiring layer 20 around the hole area is further compressed. At this time, the field of view (FOV) of the sensor hole is mainly affected by the opening of the uppermost shielding layer 50 of the display panel and the spacing of the lowermost wiring layer 20 of the display panel. In view of this, the present invention provides a display panel, a display panel and a manufacturing method to solve the above problems.

[0083] The first embodiment of the present invention proposes a display panel, such as Figures 3 to 16 As shown, the display panel includes an aperture region NA and a display region AA that at least partially surrounds the aperture region NA. The display region AA includes a pixel light-emitting region Pix located on at least one side of the aperture region NA. The display panel includes a substrate 10, a plurality of mutually insulated wiring layers 20, a pixel defining layer 30, an encapsulation layer 40, and a shielding layer 50, which are stacked sequentially.

[0084] The pixel defining layer 30 forms a first through hole 31 in the hole region NA, and the shielding layer 50 forms a second through hole 51 in the hole region NA at the position corresponding to the first through hole 31. The orthographic projection of the first through hole 31 onto the substrate 10 is the first hole projection.

[0085] The combined projection of the orthographic projection of the plurality of wiring layers 20 located in the display area AA onto the substrate 10 surrounds the projection of the first aperture.

[0086] The plurality of wiring layers 20 include a first wiring layer 21 and a second wiring layer 22, both extending along a first direction, wherein the first wiring layer 21 is closer to the substrate 10 than the second wiring layer 22.

[0087] In the first direction, the first trace layer 21 is disconnected near the center of the first via 31, and the two ends of the second trace layer 22 are electrically connected to the disconnected first trace layer 21.

[0088] The minimum distance between the projection boundary of the first wiring layer 21 on the substrate 10 and the projection boundary of the first hole in the second direction is the first distance D1. The minimum distance between the projection boundary of the second wiring layer 22 on the substrate 10 and the projection boundary of the first hole in the second direction is the second distance D2. The first distance D1 is less than the second distance D2.

[0089] In this embodiment of the invention, the traces extending along the first direction on the upper and lower sides of the first through hole 31 are designed to cross-connect, and the distance between the traces extending along the first direction and the first through hole 31 is calculated. Near the center position of the first through hole 31, the second distance D2 between the second trace layer 22 located above the first through hole 31 in the layer structure is set to be larger than the first distance D1 between the first trace layer 21 and the first through hole 31, so as to achieve the effect of increasing the field of view.

[0090] like Figure 1 As shown, the first hole projection in this embodiment is a square projection with rounded corners. In another example, the first hole projection may also be a square projection without rounded corners. For example, the first hole projection may also be a circular projection. That is, the shape of the first hole projection in this embodiment is designed according to the actual application.

[0091] In an optional embodiment, the first aperture projection includes a first boundary extending along a first direction and a second boundary extending along a second direction. The first boundary includes at least a straight line boundary extending along the first direction, and the second boundary includes at least a straight line boundary extending along the second direction. That is, the first aperture projection in this embodiment is... Figure 1 The square projection shown has rounded corners. This design increases the aperture ratio of the first hole projection, thereby improving the display effect of the display panel.

[0092] In this embodiment, Figure 1 The first hole projection shown is an illustrative example. The minimum distance between the projection boundary of the first wiring layer on the substrate and the straight line boundary of the first boundary is the first distance, and the minimum distance between the projection boundary of the second wiring layer on the substrate and the straight line boundary of the first boundary is the second distance.

[0093] When the first hole projection is a circular projection, the first distance is the minimum distance between the projection boundary of the first wiring layer in the orthographic projection on the substrate and a certain arc-shaped position in the circular projection, and the second distance is the minimum distance between the projection boundaries of the second wiring layer in the orthographic projection on the substrate at that arc-shaped position. The wiring layout of the display panel according to the embodiments of the present invention will now be described using different examples.

[0094] In an optional embodiment, such as Figures 3-5 As shown, in the stacking direction, the first trace layer 21 and the second trace layer 22 are two non-adjacent conductive layers.

[0095] The display panel further includes at least one third wiring layer 23 and a plurality of insulating layers located between the first wiring layer 21 and the second wiring layer 22, wherein the plurality of insulating layers are used to insulate the first wiring layer 21, the at least one third wiring layer 23 and the second wiring layer 22 respectively.

[0096] The first wiring layer 21 and the second wiring layer 22 are electrically connected through a first connection hole 201 that penetrates the plurality of insulating layers.

[0097] In other words, in this embodiment of the invention, the routing layers serving as the first routing layer 21 and the second routing layer 22 can have different positional relationships. This setting improves the application range under different driving circuits. The first routing layer 21 and the second routing layer 22 are electrically connected through the first connection hole 201, which can ensure the signal transmission effect under the original circuit structure.

[0098] In an optional embodiment, such as Figures 3-5 As shown, Figure 4 for Figure 3 A schematic diagram of the layer structure at section BB. Figure 5 The cross-sectional view in the middle is Figure 3 A schematic diagram of the combined cross-section of all layers at the mid-section BB and the cross-section CC, viewed from the same perspective. In other words, it is impossible to obtain the desired result using only one cross-section line. Figure 5 The layer structure diagram shown is, for example Figure 5 The dashed lines indicate the second layer, sixth routing layer 262, and the first layer, sixth routing layer 261. Figure 3 (not shown in the image) and the third wiring layer 23 in Figure 3 This can be seen at the CC position of the midsection, while Figure 5 In the first routing layer 21 and the second routing layer 22 Figure 3 This can be seen at the midsection BB position, therefore... Figure 5 This is merely an illustrative example used to illustrate the position of multiple routing layers in the stacking direction.

[0099] like Figures 3-5 As shown, the number of third wiring layers 23 is one. Therefore, the third wiring layers 23 in the stacking direction are sequentially the first wiring layer 21, the third wiring layer 23, and the second wiring layer 22. In an optional embodiment, the plurality of wiring layers 20 further includes at least one sixth wiring layer 26, which is the wiring layer among the plurality of wiring layers 20 with the largest distance from the substrate 10 in the stacking direction. For example, as shown... Figure 3 and Figure 4 The sixth routing layer 26 shown has two layers.

[0100] In one embodiment, the first wiring layer 21 is disposed on the same layer as the first gate layer of the display panel, the third wiring layer 23 is disposed on the same layer as the second gate layer located on the side of the first gate layer away from the substrate 10, and the second wiring layer 22 is disposed on the same layer as the first source / drain electrode layer located on the side of the second gate layer away from the substrate 10. That is, when forming the layer structure of the thin-film driving transistor of the driving circuit, each wiring layer 20 is formed around the hole region NA using the same process, thereby improving the process manufacturing efficiency.

[0101] In a specific example, such as Figure 4 As shown, a first gate insulating layer 61 with a thickness of p is disposed on the substrate 10. A first wiring layer 21 with a thickness of o is disposed on the first gate insulating layer 61. A second gate insulating layer 62 with a thickness of n is disposed on the first wiring layer 21. A third wiring layer 23 with a thickness of m is disposed on the second gate insulating layer 62. An interlayer dielectric layer 63 with a thickness of l is disposed on the third wiring layer 23. A second wiring layer 22 with a thickness of k is disposed on the interlayer dielectric layer 63. A first planarization layer 64 with a thickness of j is disposed on the second wiring layer 22.

[0102] In an optional embodiment, the field of view (FOV) at the central axis (section BB) extending along the second direction from the projection of the first aperture is taken as the section, and the field of view (FOV) at the section satisfies the following formula:

[0103]

[0104] Wherein, H1 is the interlayer thickness between the surface of the second wiring layer 22 near the substrate 10 and the surface of the shielding layer 50 near the substrate 10; a is the cross-sectional diameter of the second via 51 in the cross-section; and d is the sidewall distance between one side wall of the first via 31 and one side wall of the second via 51.

[0105] In a specific example, such as Figure 3 and Figure 4 In the structure shown, between the surface of the second wiring layer 22 near the substrate 10 and the surface of the shielding layer 50 near the substrate 10, a first planarization layer 64 of thickness j, a first sixth wiring layer 261 of thickness i, a second planarization layer 65 of thickness h covering the first sixth wiring layer 261, a second sixth wiring layer 262 of thickness g, a third planarization layer 66 of thickness f covering the second sixth wiring layer 262, a pixel delimiting layer of thickness e located on the third planarization layer 66, and an encapsulation layer of thickness c covering the pixel delimiting layer.

[0106] Based on the above membrane structure, with the central axis extending along the second direction from the projection of the first hole as the cross section (the center position of the cross section BB), the field of view angle under the cross section is:

[0107]

[0108] For example, in Figure 1 and Figure 2 Under the structure shown, the improved perspective of Embodiment 1 of the present invention can be obtained from the cross-sectional view:

[0109]

[0110] In another example, in Figure 1 and Figure 2 Under the membrane structure shown, the viewing angle under the cross-section can be obtained from the cross-sectional view:

[0111]

[0112] In other words, the present invention Figure 3 and Figure 4 The field of view of the embodiment shown is relatively large. Figure 1 and Figure 2 The related technology improves the field of view by 1.36° on one side and 2.72° on both sides, thus achieving the goal of increasing the field of view.

[0113] Considering that the display driving circuit has multiple routing layers, in another optional embodiment, the number of the third routing layer 23 is two, such as... Figures 6-8 As shown,

[0114] Figure 7 for Figure 6 A schematic diagram of the layer structure at section DD. Figure 8 The cross-sectional view in the middle is Figure 6 A schematic diagram of the combined cross-section of all layers at the mid-section DD and the cross-section EE, viewed from the same perspective. In other words, it is impossible to obtain the desired result using only one cross-section line. Figure 8 The layer structure diagram shown is, for example Figure 8 The dashed lines represent the sixth routing layer 26 and the first and third routing layers 231. Figure 6 This can be seen at the location of section EE, and Figure 8 In the first routing layer 21 and the second routing layer 22 Figure 6 This can be seen at the DD section, therefore... Figure 8 This is merely an illustrative example used to illustrate the position of multiple routing layers in the stacking direction.

[0115] like Figures 6-8As shown, the third routing layer 23 includes a first third routing layer 231 and a second third routing layer 232. Therefore, the routing layer 20 structure in the stacking direction is sequentially a first routing layer 21, a first third routing layer 231, a second third routing layer 232, and a second routing layer 22. The first third routing layer 231 and the second third routing layer 232 (…) Figure 6 (Not shown in the image) is used to transmit data signals.

[0116] In one embodiment, such as Figures 6-8 In the structure shown, the first wiring layer 21 is disposed on the same layer as the first gate layer of the display panel, the first third wiring layer 231 is disposed on the same layer as the second gate layer located on the side of the first gate layer away from the substrate 10, the second third wiring layer 232 is disposed on the same layer as the first source-drain electrode layer located on the side of the second gate layer away from the substrate 10, and the second wiring layer 22 is disposed on the same layer as the second source-drain electrode layer located on the side of the first source-drain electrode layer away from the substrate 10. That is, when forming the layer structure of the thin-film driving transistor of the driving circuit, each wiring layer 20 is formed around the hole region NA using the same process, thereby improving the process manufacturing efficiency.

[0117] In a specific example, such as Figures 6-8 In the structure shown, between the surface of the second wiring layer 22 near the substrate 10 and the surface of the shielding layer 50 near the substrate 10, a second planarization layer 65 of thickness h covering the first sixth wiring layer 26, a sixth wiring layer 26 of thickness g, a third planarization layer 66 of thickness f covering the sixth wiring layer 26, a pixel defining layer 30 of thickness e located on the third planarization layer 66, and an encapsulation layer 40 of thickness c covering the pixel defining layer 30 are sequentially disposed on the third planarization layer 22 of thickness i.

[0118] Based on the above membrane structure, with the central axis (center of section DD) extending along the second direction from the projection of the first hole as the cross section, the field of view angle under the cross section is:

[0119]

[0120]

[0121] In other words, the present invention Figures 6-8 The field of view of the embodiment shown is relatively large. Figure 1 and Figure 2 The related technology improves the field of view by 4.85° on one side and 9.7° on both sides. Figures 2-5 Based on the embodiment shown, the field of view is further improved.

[0122] In an optional embodiment, such as Figure 3 and Figure 6 As shown, on both sides of the two opposing first boundaries 311 of the first aperture projection, the disconnected first routing layer 21 and second routing layer 22 are provided. That is, the cross-line design of the first routing layer 21 and second routing layer 22 in this embodiment of the invention can be applied not only to one side of the first aperture projection, such as the upper or lower side, but also to both sides of the first aperture projection. For example, the first routing layer 21 and second routing layer 22 with the cross-line design are provided above and below the first aperture projection, thereby improving the field of view on both sides. Figure 3 The shown bilateral field of view will increase the field of view by 2.72°. Figure 6 The bilateral field of view shown will increase the field of view by 9.7°.

[0123] In an optional embodiment, such as Figure 3 and Figure 6 As shown, with the central axis extending along the first direction of the first hole projection as the first axis of symmetry, the orthographic projections of the disconnected first wiring layer 21 and second wiring layer 22 on the substrate 10 located on one side of each first boundary 311 are symmetrical about the first axis of symmetry.

[0124] That is, the first wiring layer 21 and the second wiring layer 22 of the crossover design located on the upper side of the first boundary 311 in this embodiment of the invention and the first wiring layer 21 and the second wiring layer 22 of the crossover design located on the lower side of the first boundary 311 are symmetrically designed. The first through hole 31 is located in the middle of the horizontal crossover design on both sides, ensuring the consistency of the bilateral viewing angle on both sides, thereby reducing the complexity of the process.

[0125] In an optional embodiment, the first boundary 311 includes at least a straight boundary extending along the first direction, such as... Figure 3 and Figure 6 As shown, the shape of the first hole projection is approximately rectangular, with arc-shaped structures at each right-angle position of the rectangle and straight-line structures at the non-arc-shaped positions.

[0126] Based on the shape and structure of the first hole projection, the embodiment of the present invention further designs the structure of the second wiring layer 22 closer to the center position.

[0127] In an optional embodiment, such as Figure 3 and Figure 6 As shown, the second routing layer 22 includes: a first end 221 and a second end 222 of the first routing layer 21, which are electrically disconnected, and a first connection portion 223 located between the first end 221 and the second end 222.

[0128] Wherein, the orthographic projection of the first end 221 on the substrate 10 overlaps with the orthographic projection of a broken edge of the first wiring layer 21 on the substrate 10, and the orthographic projection of the second end 222 on the substrate 10 overlaps with the orthographic projection of another broken edge of the first wiring layer 21 on the substrate 10.

[0129] That is, in this embodiment, the first end 221 and the second end 222 are electrically connected to the first routing layer 21, and the first connection hole 201 falls within the overlapping projection of the orthographic projection of the first end 221 and the first routing layer 21, and falls within the overlapping projection of the orthographic projection of the second end 222 and the first routing layer 21, to ensure the electrical conductivity of the first routing layer 21 and the second routing layer 22 when they are connected across layers through vias.

[0130] In this embodiment, the extension length of the first connecting portion 223 along the first direction of the orthographic projection of the substrate 10 is greater than or equal to the extension length of the straight boundary of the first boundary 311. That is, the length of the second wiring layer 22 in the first direction is greater than or equal to the extension length of the straight boundary of the first boundary 311. With this setting, the distance between the second wiring layer 22 and the first boundary 311 is guaranteed to be equal. For example, the first end 221 and the second end 222 are respectively set at the position corresponding to the arc-shaped structure of the first hole projection, and the first connecting portion 223 is set at the position of the straight boundary of the first hole projection, thereby ensuring the consistency of the field of view within the extension range of the second wiring layer 22.

[0131] In an optional embodiment, in the second direction, the width of the first connecting portion 223 in the second direction is smaller than the width of the first end portion 221 in the second direction. In other words, the width of the first connecting portion 223 in the second direction is smaller than the width of the first wiring layer 21 in the second direction. This embodiment achieves the design that the second distance D2 between the first connecting portion 223 and the first wiring layer 21 is greater than the first distance D1 between the first wiring layer 21 and the first hole projection, thereby improving the field of view.

[0132] The above embodiment describes the design of the wiring bridging and wiring structure on the upper and lower sides of the first aperture projection, thereby improving the field of view on both the upper and lower sides. Figure 9 The structural design of the display driving circuit on both sides of the first through-hole 31 is shown, such as... Figure 9As shown, trace layers are also provided on the left and right sides of the first through-hole 31 to form a display driving circuit. Therefore, when the trace space is limited, the distance between the trace layers on the left and right sides of the first through-hole 31 and the first through-hole 31 is also small, that is, the field of view on the left and right sides of the first through-hole 31 is also limited. In another aspect, the present invention proposes a design that optimizes the trace span and trace structure on both sides of the projection of the first hole, thereby improving the field of view on the left and right sides.

[0133] In an optional embodiment, such as Figure 10 and Figure 11 As shown, the plurality of wiring layers 20 further includes a fourth wiring layer 24 and a fifth wiring layer 25 that is insulated from the fourth wiring layer 24. The fourth wiring layer 24 is closer to the substrate 10 than the fifth wiring layer 25.

[0134] The fifth wiring layer 25 includes:

[0135] The third end 251, electrically connected to the fourth wiring layer 24 via the second connection hole 202, has its orthographic projection on the substrate 10 covering the orthographic projection of the fourth wiring layer 24 on the substrate 10; and

[0136] The second connecting portion 252 extending along the second direction has a third distance D3 between its third end 251 and the second boundary 312 extending along the second direction from the projection of the first hole, and a fourth distance D4 between the second connecting portion 252 and the second boundary 312 extending along the second direction from the projection of the first hole. The third distance D3 is less than the fourth distance D4.

[0137] In this embodiment of the invention, the traces extending along the second direction on the left and right sides of the first through hole 31 are designed to cross over each other, and the distance between the traces extending along the second direction and the first through hole 31 is calculated. In the layer structure, the fourth distance D4 between the second connecting part 252 and the second boundary 312 extending along the second direction of the projection of the first hole is set to be larger than the third distance D3 between the third end 251 and the second boundary 312 extending along the second direction of the projection of the first hole, so as to achieve the effect of increasing the field of view.

[0138] In an optional embodiment, such as Figure 11 As shown, Figure 11 It shows Figure 10 A schematic diagram of the layer structure at the FF section, as shown below. Figure 11 As shown, in the stacking direction, the fourth wiring layer 24 and the fifth wiring layer 25 are two adjacent conductive layers.

[0139] The display panel further includes an insulating layer located between the fourth wiring layer 24 and the fifth wiring layer 25, wherein the fourth wiring layer 24 and the fifth wiring layer 25 are electrically connected through a second connection hole 202 penetrating the insulating layer.

[0140] Since the routing circuit in the second direction is relatively complex, this embodiment of the invention sets the fourth routing layer 24 and the fifth routing layer 25 as two adjacent routing layers, thereby avoiding significant modifications to the display driving circuit and reducing the difficulty of manufacturing.

[0141] In an optional embodiment, the fourth routing layer 24 and the fifth routing layer 25 are provided on both sides of the two opposite second boundaries 312 of the first hole projection.

[0142] With the central axis extending along the second direction of the first hole projection as the second axis of symmetry, the orthographic projections of the fourth wiring layer 24 and the fifth wiring layer 25 located on one side of each second boundary 312 onto the substrate 10 are symmetrical projections with the second axis of symmetry as the second axis of symmetry.

[0143] In an optional embodiment, such as Figure 3 and Figure 6 As shown, on both sides of the two opposite second boundaries 312 of the first aperture projection, a fourth wiring layer 24 and a fifth wiring layer 25 electrically connected to the fourth wiring layer 24 are provided. That is to say, the cross-line design of the fourth wiring layer 24 and the fifth wiring layer 25 in this embodiment of the invention can not only be applied to one side of the first aperture projection, such as the left or right side of the first aperture projection, but also to both sides of the first aperture projection, such as the left and right sides of the first aperture projection, where the fourth wiring layer 24 and the fifth wiring layer 25 with the cross-line design are provided, thereby improving the field of view on both sides.

[0144] That is, the fourth wiring layer 24 and the fifth wiring layer 25 of the cross-line design on the left side of the second boundary 312 on the left side of the embodiment of the present invention and the fourth wiring layer 24 and the fifth wiring layer 25 of the cross-line design on the right side of the second boundary 312 on the right side are symmetrically designed. The first through hole 31 is located at the center of the vertical cross-line design on both sides, ensuring the consistency of the bilateral viewing angle on both sides, thereby reducing the complexity of the process.

[0145] In an optional embodiment, the second boundary 312 includes at least a straight boundary extending along the second direction, such as... Figure 3 and Figure 6 As shown, the shape of the first hole projection is approximately rectangular, with arc-shaped structures at each right-angle position of the rectangle and straight-line structures at the non-arc-shaped positions.

[0146] Based on the shape and structure of the first hole projection, this embodiment of the invention further designs the structure of the fifth wiring layer 25. In an optional embodiment, the combined projection of the third end 251 and the second connection portion 252 onto the substrate 10 extends along the second direction at a length greater than the extension length of the straight boundary of the second boundary 312, thereby ensuring the consistency of the field of view within the extension range of the second wiring layer 22.

[0147] It is worth noting that the embodiments of the present invention Figure 10 and Figure 11 The field-of-view structure design shown for the left and right sides of the display panel can also be applied to... Figure 3 and Figure 6 The design of the field of view structure on the top and bottom sides of the display panel is described. Considering that the wiring is more complex under the two combined schemes, this embodiment of the invention describes the layer design of multiple wiring layers 20 under the two embodiments.

[0148] When the display panel simultaneously uses Figure 3 and Figure 10 The routing design shown creates a pattern as follows: Figure 12 and Figure 13 The layer structure diagram shown, in an optional embodiment, is as follows: Figure 12 and Figure 13 As shown, in the stacking direction, the distance between the first wiring layer 21, the fourth wiring layer 24 and the second wiring layer 22 and the substrate 10 gradually increases. The fourth wiring layer 24 and the third wiring layer 23 are disposed in the same layer, and the second wiring layer 22 and the fifth wiring layer 25 are disposed in the same layer.

[0149] In one embodiment, the first wiring layer 21 is disposed on the same layer as the first gate layer of the display panel, the third wiring layer 23 is disposed on the same layer as the second gate layer located on the side of the first gate layer away from the substrate 10, the fourth wiring layer 24 is disposed on the same layer as the third wiring layer 23, that is, the fourth wiring layer 24 is also disposed on the same layer as the second gate layer located on the side of the first gate layer away from the substrate 10, the second wiring layer 22 is disposed on the same layer as the first source / drain electrode layer located on the side of the second gate layer away from the substrate 10, and the fifth wiring layer 25 is disposed on the same layer as the first source / drain electrode layer located on the side of the second gate layer away from the substrate 10. That is, when forming the layer structure of the thin-film driving transistor of the driving circuit, each wiring layer 20 is formed around the hole region NA using the same process, thereby improving the process manufacturing efficiency.

[0150] In an optional embodiment, such as Figure 12 and Figure 13As shown, the plurality of wiring layers 20 further includes at least one sixth wiring layer 26, which is the wiring layer among the plurality of wiring layers 20 that has the largest distance from the substrate 10 in the stacking direction.

[0151] In a specific example, such as Figure 12 and Figure 13 As shown, there are two sixth routing layers 26, including a first sixth routing layer 261 located on the second routing layer 22 (or the fifth routing layer 25 on the same layer as the second routing layer 22), and a second sixth routing layer 262 located above the first sixth routing layer 261.

[0152] In this embodiment, the first sixth wiring layer 261 extends along the second direction in the orthographic projection of the substrate 10. The end of the first sixth wiring layer 261 in the second direction is closer to the first boundary located below than the third end 251. In the extension direction of the second direction, the orthographic projection of the first sixth wiring layer 261 extends to the orthographic projection of the first wiring layer 21 located below.

[0153] In this embodiment, the second sixth wiring layer 262 extends along the second direction in the orthogonal projection of the substrate 10, and overlaps with the projections of the first wiring layer 21 located above the first via 51 and the first wiring layer 21 located below the first via 51.

[0154] The wiring layer also includes a data wiring layer 28 disposed on the same layer as the second wiring layer 22, which is used to transmit data signals. The orthogonal projection of the data wiring layer 28 on the substrate overlaps with the orthogonal projection of the first wiring layer 20.

[0155] In this embodiment, the first routing layer 21, the second routing layer 22, the data routing layer 28, a third routing layer 23, a fourth routing layer 24, a fifth routing layer 25, and a plurality of sixth routing layers 26 constitute a display driving circuit. For example, the display driving circuit is an 8T1C display driving circuit.

[0156] For example, the 8T1C display driving circuit is a circuit composed of 8 thin-film driving transistors and 1 capacitor unit, wherein the data routing layer 28 is used to transmit data signals, and the first routing layer 21 and the second routing layer 22, which are horizontally routed and connected, transmit a first initial signal.

[0157] The fourth routing layer 24 and the fifth routing layer 25, which are vertically routed and connected, transmit the second initial signal.

[0158] The first layer, sixth layer 261 of the vertical routing transmits the power supply voltage (VDD) signal; the second layer, sixth layer 262 of the vertical routing transmits the common voltage (VSS) signal. Thus, while ensuring the maximum viewing angle, it is applied to the 8T1C display driver circuit, so that the display panel has better display effect and lower power consumption.

[0159] In an optional embodiment, when the display panel simultaneously employs Figure 6 and Figure 10 The routing design shown creates a pattern as follows: Figure 14 and Figure 15 The schematic diagram shows that, in the stacking direction, the distance between the first wiring layer 21, the fourth wiring layer 24, the at least one third wiring layer 23, and the second wiring layer 22 and the substrate 10 gradually increases. Among the at least one third wiring layer 23, the third wiring layer 231 closest to the first layer and the fourth wiring layer 24 are disposed in the same layer, and the second third wiring layer 232 and the fifth wiring layer 25 furthest from the substrate 10 among the at least one third wiring layer 23 are disposed in the same layer.

[0160] In a specific example, the first wiring layer 21 is disposed on the same layer as the first gate layer of the display panel, the first third wiring layer 231 is disposed on the same layer as the second gate layer located on the side of the first gate layer away from the substrate 10, the fourth wiring layer 24 is disposed on the same layer as the first third wiring layer 231, that is, the fourth wiring layer 24 is disposed on the same layer as the second gate layer, the second third wiring layer 232 is disposed on the same layer as the first source / drain electrode layer located on the side of the second gate layer away from the substrate 10, one of the at least one third wiring layers 23 away from the substrate 10 is disposed on the same layer as the fifth wiring layer 25, that is, the fifth wiring layer 25 is disposed on the same layer as the first source / drain electrode layer, and the second wiring layer 22 is disposed on the same layer as the second source / drain electrode layer located on the side of the first source / drain electrode layer away from the substrate 10. In other words, when forming the layer structure of the thin-film driving transistor of the driving circuit, each wiring layer 20 is formed around the via region NA using the same process, thereby improving the process manufacturing efficiency.

[0161] In an optional embodiment, the plurality of wiring layers 20 further includes a sixth wiring layer 26, which is the wiring layer among the plurality of wiring layers 20 that has the largest distance from the substrate 10 in the stacking direction. In this embodiment, the orthographic projection of the sixth wiring layer 26 onto the substrate 10 extends along a second direction and overlaps with the projections of both the first wiring layer 21 located above the first via 51 and the first wiring layer 21 located below the first via 51.

[0162] like Figure 15In the structure shown, the plurality of wiring layers 20 also includes a seventh wiring layer 27 disposed on the same layer as the second wiring layer 22. The orthographic projection of the seventh wiring layer 27 on the substrate 10 extends along the second direction. In this embodiment, the end of the seventh wiring layer 27 in the second direction is closer to the lower first boundary than the third end 251. In the extension direction of the second direction, the orthographic projection of the seventh wiring layer 27 extends to the orthographic projection of the lower first wiring layer 21.

[0163] In an optional embodiment, the wiring layer further includes a data transmission wiring layer 28 disposed on the same layer as the second third wiring layer 232 (fifth wiring layer 25), and the data transmission wiring layer 28 partially overlaps with the orthographic projection of the first wiring layer 21 onto the substrate.

[0164] In this embodiment, the first routing layer 21, the second routing layer 22, multiple third routing layers 23, the fourth routing layer 24, the fifth routing layer 25, the sixth routing layer 26, the seventh routing layer 27, and the data transmission routing layer 28 constitute a display driving circuit. For example, the display driving circuit is an 8T1C display driving circuit.

[0165] For example, the 8T1C display driving circuit is a circuit consisting of 8 thin-film driving transistors and 1 capacitor unit.

[0166] Data transmission trace layer 28 is used to transmit data signals.

[0167] The first routing layer 21 and the second routing layer 22, which are horizontally routed and connected, transmit the first initial signal.

[0168] The fourth routing layer 24 and the fifth routing layer 25, which are vertically routed and connected, transmit the second initial signal.

[0169] The seventh routing layer of the vertical routing transmits the power supply voltage (VDD) signal.

[0170] The sixth routing layer 26 of the vertical routing transmits the common voltage (VSS) signal, which is applied to the 8T1C display driver circuit while ensuring the maximum viewing angle, so that the display panel has better display effect and lower power consumption.

[0171] based on Figure 12 and Figure 13 Implementation examples and based on Figure 14 and Figure 15In the embodiments of the present invention, the wiring structure can be applied to display panels of various embodiments. While ensuring that the size of the second through-hole 51 remains unchanged, it can be applied to circuit designs with complex structures, achieving an improved viewing angle within a limited wiring space. It has broad application prospects and will not be elaborated further here. To ensure manufacturing precision, in an optional embodiment, the minimum boundary distance L between each wiring layer 20 and the sidewall of the first through-hole 31 facing each wiring layer 20 satisfies the following formula:

[0172]

[0173] Wherein, H1 is the interlayer thickness between the surface of each wiring layer 20 near the substrate 10 and the surface of the shielding layer 50 near the substrate 10;

[0174] a is the diameter of the second through hole 51, and a is usually less than 10 μm; b is the diameter of the first through hole 31, and b is usually less than 12 μm.

[0175] d is the distance between one side wall of the first through hole 31 and one side wall of the second through hole 51, and d is usually 1 μm;

[0176] c is the interlayer thickness between the surface of the pixel defining layer 30 away from the substrate 10 and the surface of the shielding layer 50 close to the substrate 10;

[0177] e is the thickness of the pixel defining layer 30.

[0178] In a specific example, with Figure 12 and Figure 13 The wiring layout of the display panel shown is an example. Figure 16 A schematic diagram showing all the wiring layers 20 in the same layer structure is shown. Figure 16 The layered structure in the diagram uses the axes of the horizontal and vertical symmetry axes of the first through-hole 21 as cross-sections, and embodies the membrane layers in the two cross-sections in the same layered structure. Figure 16 This is to illustrate the distance design relationship between each routing layer 20 and the first via 31, that is, Figure 16 The layer structure shown is for illustrative purposes only. This layer structure is an integral layer structure that integrates the vertical axis section and the horizontal axis section. In other words, the minimum boundary distance L in this embodiment refers to the minimum boundary distance between each wiring layer 20 and the sidewall corresponding to the first boundary 311 or the second boundary 312 of the first through hole 31.

[0179] It is worth noting that, in the embodiments of the present invention, the thickness of the insulating film layer refers to the distance between the surface of the insulating film layer away from the substrate and the surface of the wiring layer covered by the insulating film layer that is in contact with the substrate. In a specific example, the thicknesses of each film layer are as follows:

[0180] The thickness of the first gate insulating layer 61 disposed on the substrate 10 is p, typically 0.13 μm.

[0181] The thickness of the first wiring layer 21 disposed on the first gate insulating layer 61 is 0, typically 0.3 μm.

[0182] The thickness of the second gate insulating layer 62 disposed on the first wiring layer 21 is n, that is, the thickness between the surface of the second gate insulating layer 62 away from the substrate and the surface of the first wiring layer 21 away from the substrate is n, which is typically 0.13 μm.

[0183] A third wiring layer 23 with a thickness of m, typically 0.3 μm, is disposed on the second gate insulating layer 62.

[0184] The thickness of the interlayer dielectric layer 63 disposed on the third wiring layer 23 is l, that is, the thickness between the surface of the third wiring layer 23 away from the substrate and the surface of the third wiring layer 23 away from the substrate is l, which is typically 0.13 μm.

[0185] The thickness of the second wiring layer 22 disposed on the interlayer dielectric layer 63 is k, typically 0.6 μm.

[0186] The thickness of the first planarization layer 64 disposed on the second wiring layer 22 is j, that is, the thickness between the surface of the first planarization layer 64 away from the substrate and the surface of the second wiring layer 22 away from the substrate is j, which is usually 1.5um.

[0187] The thickness of the first sixth wiring layer 261, which is set on the first planarization layer 64, is i, typically 0.6 μm.

[0188] The thickness of the second planarization layer 65 disposed on the first sixth wiring layer 261 is h, that is, the thickness between the surface of the second planarization layer 65 away from the substrate and the surface of the first sixth wiring layer 261 away from the substrate is h, which is usually 1.5um.

[0189] The thickness of the second sixth wiring layer 262 set on the second flattening layer 65 is g, typically 0.6um;

[0190] The thickness of the third planarization layer 66 disposed on the sixth wiring layer 262 of the second layer is f, that is, the thickness between the surface of the third planarization layer 66 away from the substrate and the surface of the sixth wiring layer 262 away from the substrate is f, which is usually 1.5um;

[0191] e is the thickness of the pixel boundary layer 30, which is usually 1.5um;

[0192] c is the thickness of the encapsulation layer 40, that is, the thickness between the surface of the encapsulation layer 40 away from the substrate and the surface of the pixel defining layer 30 away from the substrate. Typically, c is 10 μm.

[0193] By the Pythagorean theorem, we have: Tanα = (a + d) / (c + e)

[0194] =r / (f+g)

[0195] =s / (f+g+h+i)

[0196] =t / (f+g+h+i+j+k)

[0197] =u / (f+g+h+i+j+k+l+m)

[0198] =v / (f+g+h+i+j+k+l+m+n+o);

[0199] The vertical plane containing the bottom edge of the first sidewall of the first through hole 31 of the pixel defining layer 30 near the substrate 10 is the first included angle side. The line connecting the first bottom edge of the first sidewall of the first through hole 31 of the pixel defining layer 30 near the substrate 10 and the top edge of the second sidewall of the second through hole 51 away from the first bottom edge is the second included angle side. The included angle formed by the first included angle side and the second included angle side is α.

[0200] When it is required that the various routing layers 20 below the first via 31 do not affect the viewing angle of the first via 31, different routing layers 20 have different interlayer thicknesses H1, according to... Based on the above definition of Tanα, the minimum boundary distances of the sidewalls of the first via 31 facing each routing layer 20 are as follows:

[0201] The minimum boundary distance Lr between the second and sixth routing layers 262, which is the topmost layer on the multiple routing layers 20, and the second boundary 312 of the first via 31 is:

[0202]

[0203] The minimum boundary distance L between the first and sixth routing layers 261 located on multiple routing layers 20 s1 for:

[0204]

[0205] For example, when the fifth routing layer 25 and the first sixth routing layer 261 are disposed on the same layer, the minimum boundary distance L between the fifth routing layer 25 and the second boundary 312 of the first via 31 is... s1 for:

[0206]

[0207] The minimum boundary distance Lt between the second routing layer 22, located in the plurality of routing layers 20, and the first boundary 311 of the first via 31 is:

[0208]

[0209] The minimum boundary distance L between the third routing layer 23 (one of the multiple routing layers 20) and the first via 31, and the second boundary 312. u1 for:

[0210]

[0211] For example, when the fourth routing layer 24 and the third routing layer 23 are disposed on the same layer, the minimum boundary distance L between the fourth routing layer 24 and the second boundary 312 of the first via 31 is... u2 for:

[0212]

[0213] The minimum boundary distance Lv of the first routing layer 21, which is connected to the second routing layer 22 among multiple routing layers 20, is:

[0214]

[0215] Based on the minimum boundary distance design between each wiring layer 20 and the first via 31, it can be seen that from the direction of the substrate 10 from the encapsulation layer 40, the minimum boundary distance between each wiring layer 20 and the sidewall corresponding to the first boundary 311 or the second boundary 312 of the first via 31 gradually decreases, thereby ensuring that the field of view is not affected by each wiring layer 20 and ensuring the optimal display effect.

[0216] In an optional embodiment, such as Figure 17 and Figure 18 As shown, the display area AA includes a first display area AA01 and a second display area AA02 surrounding the first display area AA01.

[0217] The second display area AA02 includes a pixel light-emitting area Pix.

[0218] The first display area AA01 includes the pixel light-emitting area Pix and the non-pixel light-emitting area NPix located around the pixel light-emitting area Pix.

[0219] The pixel light-emitting area Pix is ​​provided with each sub-pixel (R / G / B) defined by a pixel boundary layer, and the non-pixel light-emitting area NPix is ​​provided with at least one aperture area NA, which is disposed in the gap between each sub-pixel.

[0220] This embodiment describes the location of the hole area, such as... Figure 17 As shown, the hole area described in this embodiment of the invention can not only be set at the top of the display panel, but also in the first display area AA01 located in the center of the display panel surrounded by the second display area AA02, thereby expanding the application scenarios of the display panel that uses the hole area NA for light sensing detection, such as camera acquisition, fingerprint recognition, brightness adjustment and other functions.

[0221] In this embodiment of the invention, the difference between the first display area AA01 and the second display area AA02 lies in whether or not a hole area NA is provided. That is, the second display area AA02 is provided with a non-pixel light-emitting area NPix for setting the hole area NA, such as... Figure 18 As shown, the aperture region NA is set in the gap between each sub-pixel. At the location of the aperture region NA, the pixel defining layer is not only used to define each sub-pixel (R / G / B), but also to open a first through hole in multiple gaps between each sub-pixel (R / G / B). The shielding layer at each location of the first through hole opens a second through hole to improve light transmittance. The structure of each trace layer is described with reference to the above embodiment. The boundary distance of each trace layer at the location of the first through hole is designed based on each first through hole, which will not be repeated here.

[0222] Another embodiment of the present invention provides a display device, which includes the display panel of the above embodiments of the present invention. The display device of the present invention can be any product or component requiring a liquid crystal display panel, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or vehicle display device; the embodiments of the present invention do not limit this.

[0223] In an optional embodiment, such as Figure 16 As shown, the display device further includes a sensor 70 disposed at a location corresponding to the hole area, located on the side of the substrate 10 of the display panel away from the plurality of wiring layers 20. The sensor is used to emit and receive sensing signals to perform sensing. In this embodiment, the sensing signal is emitted from the first through hole 31, and the received sensing signal includes the collected sensing information, such as image information obtained by taking a picture of a face. The sensing signal is then processed in the processor to realize the sensing function of the display panel.

[0224] Another embodiment of the present invention provides a method for manufacturing the above-mentioned display panel, the method comprising:

[0225] Multiple mutually insulating wiring layers 20 are sequentially formed on the substrate 10 corresponding to the display area AA;

[0226] A pixel defining layer 30 is formed on the wiring layer 20 of the display area AA and on the insulating layer covering the wiring layer 20 of the hole area NA;

[0227] The pixel defining layer 30 located in the aperture region NA is etched to form a first via 31, and the orthogonal projection of the first via 31 onto the substrate 10 is the first aperture projection.

[0228] An encapsulation layer 40 and a masking layer 50 are sequentially formed on the pixel defining layer 30;

[0229] The shielding layer 50 is etched at the position corresponding to the first through hole 31 to form a second through hole 51;

[0230] Among them, a plurality of mutually insulating wiring layers 20 are sequentially formed on the substrate 10 corresponding to the display area AA, further including:

[0231] A first trace layer 21 extending in a first direction is formed on the substrate 10 corresponding to the display area AA. In the first direction, the first trace layer 21 is broken near the center of the first via 31.

[0232] A second wiring layer 22 is formed on the first wiring layer 21 and extends along a first direction while being insulated from the first wiring layer 21. The two ends of the second wiring layer 22 are electrically connected to the disconnected first wiring layer 21. The distance between the projection boundary of the first wiring layer on the substrate and the projection boundary at any position of the first hole projection is a first distance. The minimum distance between the projection boundary of the first wiring layer on the substrate and the projection boundary of the first hole projection in a second direction is a first distance. The minimum distance between the projection boundary of the second wiring layer on the substrate and the projection boundary of the first hole projection in a second direction is a second distance. The first distance is less than the second distance.

[0233] The manufacturing method of this invention does not add complicated process steps. The manufacturing process of multiple wiring layers 20 can refer to the manufacturing process of related technologies. In the process of manufacturing wiring layers 20, the distance between the first wiring layer 21 and the second wiring layer 22 and the first through hole 31 is designed. On the basis of ensuring the optimal size design of the first through hole 31 and the second through hole 51, the purpose of increasing the field of view is achieved.

[0234] It is worth noting that specific embodiments of the manufacturing method of the display panel in this invention can be found in the display panel of the foregoing embodiments, and will not be repeated here.

[0235] In the description of this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0236] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims

1. A display panel, the display panel comprising an aperture region and a display area at least surrounding a portion of the aperture region, the display area comprising a pixel light-emitting region located on at least one side of the aperture region, characterized in that, The display panel includes a substrate, multiple mutually insulated wiring layers, a pixel defining layer, an encapsulation layer, and a shielding layer stacked sequentially. Wherein, the pixel defining layer forms a first through hole in the hole area, and the shielding layer forms a second through hole in the hole area at a position corresponding to the first through hole, and the orthographic projection of the first through hole onto the substrate is the first hole projection; The combined projection of the orthographic projection of the multiple wiring layers located in the display area onto the substrate surrounds the projection of the first aperture. The plurality of wiring layers include a first wiring layer and a second wiring layer, both extending along a first direction, wherein the first wiring layer is closer to the substrate than the second wiring layer. In a first direction, the first trace layer is disconnected near the center of the first via, and the two ends of the second trace layer are electrically connected to the disconnected first trace layer. The minimum distance between the projection boundary of the first wiring layer on the substrate and the projection boundary of the first hole in the second direction is the first distance, and the minimum distance between the projection boundary of the second wiring layer on the substrate and the projection boundary of the first hole in the second direction is the second distance, wherein the first distance is less than the second distance.

2. The display panel according to claim 1, characterized in that, In the stacking direction, the first trace layer and the second trace layer are two non-adjacent conductive layers. The display panel further includes: at least one third wiring layer and a plurality of insulating layers located between the first wiring layer and the second wiring layer, wherein the plurality of insulating layers are used to insulate the first wiring layer, the at least one third wiring layer, and the second wiring layer, respectively. The first wiring layer and the second wiring layer are electrically connected through a first connection hole that penetrates the plurality of insulating layers.

3. The display panel according to claim 1, characterized in that, On both sides of the two opposite first boundaries of the first hole projection, the disconnected first trace layer and second trace layer are provided. With the central axis extending along the first direction as the first axis of symmetry, the orthographic projections of the disconnected first and second trace layers on the substrate located on each side of the first boundary are symmetrical about the first axis of symmetry.

4. The display panel according to claim 1, characterized in that, The first aperture projection includes a first boundary extending along a first direction and a second boundary extending along a second direction, wherein the first boundary includes at least a straight boundary extending along the first direction. The minimum distance between the projection boundary of the first wiring layer on the substrate and the straight boundary of the first boundary is the first distance, and the minimum distance between the projection boundary of the second wiring layer on the substrate and the straight boundary of the first boundary is the first distance.

5. The display panel according to claim 4, characterized in that, The second routing layer includes: a first end and a second end of the first routing layer that are electrically disconnected, and a first connection portion located between the first end and the second end. Wherein, the orthographic projection of the first end on the substrate overlaps with the orthographic projection of a break edge of the first wiring layer on the substrate, and the orthographic projection of the second end on the substrate overlaps with the orthographic projection of another break edge of the first wiring layer on the substrate. The extension length of the first connection portion along the first direction in the orthographic projection of the substrate is greater than or equal to the extension length of the straight boundary of the first boundary.

6. The display panel according to claim 2, characterized in that, The plurality of wiring layers further includes a fourth wiring layer and a fifth wiring layer that is insulated from the fourth wiring layer, wherein the fourth wiring layer is closer to the substrate than the fifth wiring layer. The fifth routing layer includes: A third end electrically connected to the fourth wiring layer via a second connection hole, wherein the orthographic projection of the third end onto the substrate overlaps the orthographic projection of the fourth wiring layer onto the substrate; and The second connecting portion extending along the second direction, The minimum distance between the third end and the second boundary extending along the second direction of the projection of the first hole is the third distance, and the minimum distance between the second connecting part and the second boundary extending along the second direction of the projection of the first hole is the fourth distance. The third distance is less than the fourth distance.

7. The display panel according to claim 6, characterized in that, In the stacking direction, the fourth wiring layer and the fifth wiring layer are two adjacent conductive layers. The display panel further includes an insulating layer located between the fourth wiring layer and the fifth wiring layer, wherein the fourth wiring layer and the fifth wiring layer are electrically connected through a second connection hole penetrating the insulating layer.

8. The display panel according to claim 6, characterized in that, On both sides of the two opposite second boundaries of the first hole projection, the fourth routing layer and the fifth routing layer are respectively provided. With the central axis extending along the second direction from the projection of the first hole as the second axis of symmetry, the orthographic projections of the fourth and fifth wiring layers located on each side of the second boundary onto the substrate are symmetrical projections with the second axis of symmetry as the second axis of symmetry.

9. The display panel according to claim 6, characterized in that, The second boundary includes at least a straight boundary extending along the first direction. The combined projection of the third end and the second connection portion onto the substrate extends along the second direction at a length greater than the extension length of the straight boundary of the second boundary.

10. The display panel according to claim 6, characterized in that, In the stacking direction, the distance between the first wiring layer, the fourth wiring layer and the second wiring layer and the substrate gradually increases. The fourth wiring layer and the third wiring layer are disposed in the same layer, and the second wiring layer and the fifth wiring layer are disposed in the same layer.

11. The display panel according to claim 6, characterized in that, In the stacking direction, the distance between the first wiring layer, the fourth wiring layer, the at least one third wiring layer, and the second wiring layer and the substrate gradually increases. Among the at least one third wiring layer, the third wiring layer closest to the substrate is disposed in the same layer as the fourth wiring layer, and one of the at least one third wiring layers is disposed in the same layer as the fifth wiring layer.

12. The display panel according to claim 6, characterized in that, The plurality of wiring layers further includes at least one sixth wiring layer, which is the wiring layer among the plurality of wiring layers that has the largest distance from the substrate in the stacking direction. The first routing layer, the second routing layer, the fourth routing layer, the fifth routing layer, and the sixth routing layer constitute a display driving circuit; or The first routing layer, the second routing layer, the third routing layer, the fourth routing layer, the fifth routing layer, and the sixth routing layer constitute a display driving circuit.

13. The display panel according to claim 6, characterized in that, Taking the central axis extending along the second direction from the projection of the first hole as a cross section, the minimum boundary distance L between the sidewall of each routing layer near the projection of the first hole and the first boundary of the projection of the first hole satisfies the following formula: ； in, The interlayer thickness between the surface of each wiring layer near the substrate and the surface of the shielding layer near the substrate; a is the diameter of the cross-section of the second through hole under the cross-section; d is the distance between one side wall of the first through hole and one side wall of the second through hole; c is the interlayer thickness between the surface of the pixel defining layer away from the substrate and the surface of the shielding layer close to the substrate; e is the thickness of the pixel-defining layer.

14. The display panel according to claim 1, characterized in that, The display area includes a first display area and a second display area surrounding the first display area. The first display area includes a pixel light-emitting area and a non-pixel light-emitting area located around the pixel light-emitting area. The pixel light-emitting area is provided with sub-pixels defined by a pixel delimiting layer. The non-pixel light-emitting area is provided with at least one of the aperture areas, which are disposed in the gaps between each sub-pixel.

15. A display device, characterized in that, The display device includes the display panel according to any one of claims 1 to 14.

16. The display device according to claim 15, characterized in that, The display device further includes a sensing element disposed at a location corresponding to the hole area, located on the side of the substrate of the display panel away from the plurality of wiring layers.

17. A method for manufacturing a display panel according to any one of claims 1 to 14, characterized in that, The method includes: Multiple mutually insulating wiring layers are sequentially formed on the substrate corresponding to the display area; A pixel delimiting layer is formed on the wiring layer of the display area and on the insulating layer covering the wiring layer of the hole area; The pixel defining layer located in the hole region is etched to form a first via, and the orthographic projection of the first via on the substrate is the first hole projection; An encapsulation layer and a masking layer are sequentially formed on the pixel definition layer; The shielding layer is etched at the location corresponding to the first through-hole to form a second through-hole; The method further includes forming multiple mutually insulating wiring layers sequentially on the substrate corresponding to the display area, and further comprising: A first trace layer extending in a first direction is formed on a substrate corresponding to the display area, wherein the first trace layer is interrupted near the center of the first via in the first direction; A second trace layer is formed on the first trace layer and extends along a first direction, which is insulated from the first trace layer. The two ends of the second trace layer are electrically disconnected from the first trace layer. The minimum distance between the projection boundary of the first trace layer on the substrate and the projection boundary of the first hole in the second direction is a first distance. The minimum distance between the projection boundary of the second trace layer on the substrate and the projection boundary of the first hole in the second direction is a second distance. The first distance is less than the second distance.

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