A pixel driving data signal writing method and a driving circuit thereof

Abstract

The application discloses a pixel driving data signal writing method, comprising: generating a target potential based on the gray scale required by a next frame of a sub-pixel; using the principle of charge conservation to calculate the data signal voltage required when the potential of a pixel electrode changes to the target potential in the charge transfer process; and writing the data signal voltage into a pre-storage electrode. The application quantitatively calculates the actual data signal voltage required in the charge transfer process based on the residual charge of the pixel electrode of the current frame, corrects the data signal, solves the color deviation and brightness difference problem caused by the residual charge without increasing TFT and wiring, and improves the pixel aperture ratio. Meanwhile, by further improving the circuit structure, the pre-storage electrode and / or the pixel electrode are coupled by using a jumping global signal line, the required data signal voltage range is reduced, and the driving difficulty and the power consumption of a source IC are reduced.

Description

Technical Field

[0001] This invention relates to the field of pixel driving technology, and more specifically to a pixel driving data signal writing method and its driving circuit. Background Technology

[0002] In field sequential or color sequential display technologies, the backlight can only be turned on after all screen data has been written and the liquid crystal has deflected to a stable state. Otherwise, screen chaos will occur. Therefore, the data writing and liquid crystal deflection time greatly compress the backlight turn-on time, making it difficult to improve the brightness of the display, as well as the refresh rate and resolution, increase power consumption, and increase the cost of backlight materials.

[0003] Traditional pixel driving circuits, refer to Figure 1 (A pixel driving circuit proposed by Canon in its US Patent No. 6,181,311) differs from the conventional 1T2C pixel design in that, in addition to the pixel signal write switch TFT T1, it includes a data storage capacitor Cs1, a signal transfer TFT T2, and a reset TFT T3. The signal storage capacitor Cs1 is used to pre-store the pixel data voltage required for the next frame. The signal transfer TFT T2 transfers the pixel data voltage pre-stored in the signal storage capacitor Cs1 to the corresponding pixel voltage storage capacitor Cs2 and the liquid crystal capacitor Clc. The reset TFT T3 eliminates residual charge on the pixel capacitors to prevent color shift and brightness differences caused by residual charge. This circuit design allows the signal storage capacitor Cs1 to pre-store the pixel data voltage of the next frame during backlight illumination, and all pixels synchronously read the pixel data voltage in the corresponding Cs1 when switching frames. This pixel data voltage register design saves pixel write time and correspondingly increases backlight illumination time.

[0004] However, this pixel circuit design faces the problem of voltage reduction due to charge sharing, which requires increasing the range of data voltage supply to meet the operating voltage range of the liquid crystal. This places higher demands on the output voltage range of the source IC. At the same time, compared with the traditional 1T2C circuit, the added TFTs and wiring will increase the complexity of the circuit structure and lead to a decrease in aperture ratio.

[0005] In summary, traditional pixel driving circuits suffer from low aperture ratio. Summary of the Invention

[0006] In view of this, the present invention provides a pixel-driven data signal writing method and its driving circuit, which solves the problem of low aperture ratio in traditional pixel driving circuits by improving the data writing method and circuit structure.

[0007] To address the above problems, the technical solution of this invention is to employ a pixel-driven data signal writing method, comprising: generating a target potential based on the grayscale required for the next frame of the sub-pixel; calculating the data signal voltage required when the pixel electrode potential changes to the target potential during charge transfer using the principle of charge conservation; and writing the data signal voltage to a pre-stored electrode.

[0008] Optionally, the method for calculating the data signal voltage includes: generating a transferred charge based on the voltage difference between the pixel electrode potential of the current frame of the sub-pixel and the target potential, the pixel capacitance, and the holding capacitance; and calculating the potential of the pre-stored electrode required before the charge transfer stage based on the transferred charge, the target potential, and the pre-stored capacitance, wherein the potential is the data signal voltage.

[0009] Optionally, when the pixel capacitor of the pixel driving circuit is coupled to the global signal, if the transition timing of the global signal is after the charge transfer stage of the (N-1)th frame and before the data writing stage of the Nth frame, then the method for calculating the data signal voltage includes: calculating the intermediate voltage required by the pixel electrode before the global signal transition in the current frame based on the target potential of the sub-pixel in the next frame; generating a transferred charge based on the voltage difference between the pixel electrode potential of the sub-pixel in the current frame and the intermediate voltage, the pixel capacitance, and the holding capacitance; and calculating the potential of the pre-stored electrode required before the charge transfer based on the transferred charge, the intermediate voltage, and the pre-stored capacitance, which is the data signal voltage.

[0010] Optionally, the global signal is configured such that: when the (N-1)th frame is a positive frame, the global signal remains at a high potential during the data writing phase and then jumps to a low potential after the charge transfer phase; when the Nth frame is a negative frame, the global signal remains at a low potential during the data writing phase and then jumps to a high potential after the charge transfer phase.

[0011] Accordingly, the present invention provides a pixel driving circuit that applies the above-described data signal writing method. The pixel driving circuit includes a first sub-pixel and a second sub-pixel. Both the first sub-pixel and the second sub-pixel include a first transistor, a pre-storage capacitor, a second transistor, a holding capacitor, and a pixel capacitor. The first source-drain of the first transistor is coupled to a data signal line, and its gate is coupled to a control signal line. The second source-drain is coupled to the first source-drain of the second transistor and one end of the pre-storage capacitor. The gate of the second transistor is coupled to a transfer signal line, and its second source-drain is coupled to one end of the holding capacitor and one end of the pixel capacitor. The end of the holding capacitor away from the second transistor is coupled to a reference signal line. The end of the pre-storage capacitor of the first sub-pixel away from the first transistor is coupled to a first global signal line, and the end of the pixel capacitor of the first sub-pixel away from the second transistor is coupled to the first global signal line. The end of the pre-storage capacitor of the second sub-pixel away from the first transistor is coupled to a second global signal line, and the end of the pixel capacitor of the second sub-pixel away from the second transistor is coupled to the second global signal line.

[0012] Optionally, during the data writing stage, the control signal jumps to a high potential, the first transistor turns on, and after the data signal is written to the pre-storage electrode, the control signal jumps back to a low potential and enters the charge transfer stage. The transfer signal jumps to a high potential, the second transistor turns on, and after the data signal is transferred to the pixel electrode, the transfer signal jumps back to a low potential.

[0013] Optionally, in the (N-1)th frame, if the first sub-pixel is a positive frame and the second sub-pixel is a negative frame, then after the charge transfer phase, the first global signal line jumps to a low potential and the second global signal line jumps to a high potential. In the Nth frame, if the first sub-pixel is a negative frame and the second sub-pixel is a positive frame, then after the charge transfer phase, the first global signal line jumps to a high potential and the second global signal line jumps to a low potential.

[0014] Accordingly, the present invention provides a pixel driving circuit that applies the above-described data signal writing method. The pixel driving circuit includes a first sub-pixel and a second sub-pixel. Both the first sub-pixel and the second sub-pixel include a first transistor, a pre-storage capacitor, a second transistor, a holding capacitor, and a pixel capacitor. The first source-drain of the first transistor is coupled to a data signal line, and its gate is coupled to a control signal line. The second source-drain is coupled to the first source-drain of the second transistor and one end of the pre-storage capacitor. The gate of the second transistor is coupled to a transfer signal line, and its second source-drain is coupled to one end of the holding capacitor and one end of the pixel capacitor. The ends of the holding capacitor and the pixel capacitor away from the second transistor are coupled to a global signal line. The end of the pre-storage capacitor of the first sub-pixel away from the first transistor is coupled to a first coupling signal line. The end of the pre-storage capacitor of the second sub-pixel away from the first transistor is coupled to a second coupling signal line.

[0015] Optionally, during the data writing stage, the control signal jumps to a high potential, the first transistor turns on, and after the data signal is written to the pre-storage electrode, the control signal jumps back to a low potential and enters the charge transfer stage. The transfer signal jumps to a high potential, the second transistor turns on, and after the data signal is transferred to the pixel electrode, the transfer signal jumps back to a low potential.

[0016] Optionally, in the (N-1)th frame, if the first sub-pixel is a positive frame and the second sub-pixel is a negative frame, then after the data writing phase, the first coupling signal line jumps to a high potential and the second coupling signal line jumps to a low potential; in the Nth frame, if the first sub-pixel is a negative frame and the second sub-pixel is a positive frame, then after the data writing phase, the first coupling signal line jumps to a low potential and the second coupling signal line jumps to a high potential. The primary improvement of this invention lies in the pixel-driven data signal writing method, which overcomes the technical biases of conventional techniques in the field (i.e., the TFT T3 must be reset to eliminate the charge remaining on the pixel capacitor to prevent color shift and brightness differences caused by residual charge). Utilizing the principle of charge conservation, the actual data signal voltage required during charge transfer is quantitatively calculated based on the residual charge on the pixel electrode of the current frame, thus correcting the data signal. Without adding additional TFTs or wiring, this solves the problem of color shift and brightness differences caused by residual charge while improving the pixel aperture ratio. Furthermore, by further improving the circuit structure and using a transitional global signal line to couple the pre-store electrode and / or pixel electrode, the required data signal voltage range is reduced, lowering the driving difficulty and source IC power consumption. Attached Figure Description

[0017] Figure 1This is a simplified circuit diagram of a pixel driving circuit proposed by Canon in US Patent No. 6,181,311; Figure 2 This is a simplified flowchart of the pixel-driven data signal writing method of the present invention; Figure 3 This is a simplified circuit diagram of a pixel driving circuit according to a preferred embodiment of the present invention; Figure 4 This is a driving timing diagram of a pixel driving circuit according to a preferred embodiment of the present invention; Figure 5 This is a simplified circuit diagram of a pixel driving circuit according to another preferred embodiment of the present invention; Figure 6 This is a timing diagram of the pixel driving circuit according to another preferred embodiment of the present invention. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0023] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0024] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0025] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0026] Specifically, such as Figure 2 As shown, a pixel-driven data signal writing method includes: S1: Generate target potential based on the grayscale required for the next frame of the sub-pixel.

[0027] Furthermore, the target potential V is calculated using the formula p=f(V), where p is the gray level and f(V) is the gray level voltage function. This function is affected by the physical properties of the liquid crystal and can be obtained by EDA software simulation, as it is not specifically limited in this application.

[0028] S2: Using the principle of charge conservation, calculate the data signal voltage required for the pixel electrode potential to change to the target potential during the charge transfer process.

[0029] Furthermore, the method for calculating the data signal voltage includes: generating a transferred charge amount based on the voltage difference between the pixel electrode potential of the current frame of the sub-pixel and the target potential, the pixel capacitance, and the holding capacitance; and calculating the potential of the pre-stored electrode required before the charge transfer stage based on the transferred charge amount, the target potential, and the pre-stored capacitance, which is the data signal voltage.

[0030] Furthermore, when the pixel capacitor of the pixel driving circuit is coupled to the global signal, if the transition timing of the global signal is after the charge transfer stage of the (N-1)th frame and before the data writing stage of the Nth frame, then the method for calculating the data signal voltage includes: calculating the intermediate voltage required by the pixel electrode before the global signal transition in the current frame based on the target potential of the sub-pixel in the next frame; generating a transferred charge based on the voltage difference between the pixel electrode potential of the sub-pixel in the current frame and the intermediate voltage, the pixel capacitance, and the holding capacitance; and calculating the potential of the pre-stored electrode required before the charge transfer based on the transferred charge, the intermediate voltage, and the pre-stored capacitance, which is the data signal voltage.

[0031] The global signal is configured such that: when the (N-1)th frame is a positive frame, the global signal remains at a high potential during the data writing phase and then jumps to a low potential after the charge transfer phase; when the Nth frame is a negative frame, the global signal remains at a low potential during the data writing phase and then jumps to a high potential after the charge transfer phase.

[0032] S3: Write the data signal voltage to the pre-stored electrode.

[0033] Furthermore, the calculation process in steps S1-S2 can be performed by T-con (not limited to T-con, but also by other processors such as SOC) after the above logical calculations are performed, and the generated data signal voltage is transmitted to Driver IC and written to sub-pixels through data lines.

[0034] This invention overcomes the technical biases of conventional techniques in the field (i.e., the TFT T3 must be reset to eliminate the residual charge on the pixel capacitor to prevent color shift and brightness differences caused by residual charge). Utilizing the principle of charge conservation, it quantitatively calculates the actual data signal voltage required during charge transfer based on the residual charge on the pixel electrode of the current frame, thereby correcting the data signal. Without adding additional TFTs or wiring, it solves the problem of color shift and brightness differences caused by residual charge while improving the pixel aperture ratio. Furthermore, by further improving the circuit structure and using a transitional global signal line to couple the pre-store electrode and / or pixel electrode, it reduces the required data signal voltage range, lowers the driving difficulty, and reduces the power consumption of the source IC.

[0035] In one embodiment, such as Figure 3As shown, the pixel driving circuit includes: a first sub-pixel and a second sub-pixel. Both the first and second sub-pixels include a first transistor T1, a pre-storage capacitor Cs1, a second transistor T2, a holding capacitor Cs2, and a pixel capacitor Clc. The first source-drain of the first transistor T1 is coupled to the data signal line Data, and its gate is coupled to the control signal line Scan. The second source-drain is coupled to the first source-drain of the second transistor T2 and one end of the pre-storage capacitor Cs1. The gate of the second transistor T2 is coupled to the transfer signal line Tran, and its second source-drain is coupled to one end of the holding capacitor Cs2 and one end of the pixel capacitor Clc. The holding capacitor... The end of capacitor Cs2 furthest from the second transistor T2 is coupled to the reference signal line Vref; the end of the pre-storage capacitor Cs1 of the first sub-pixel furthest from the first transistor T1 is coupled to the first global signal line Vcom-Even, and the end of the pixel capacitor Clc of the first sub-pixel furthest from the second transistor T2 is coupled to the first global signal line Vcom-Even; the end of the pre-storage capacitor Cs1 of the second sub-pixel furthest from the first transistor T1 is coupled to the second global signal line Vcom-Odd, and the end of the pixel capacitor Clc of the second sub-pixel furthest from the second transistor T2 is coupled to the second global signal line Vcom-Odd. The terminal of the pixel capacitor Clc furthest from the global signal line is defined as the pixel electrode, and the terminal of the pre-storage capacitor Cs1 furthest from the global signal line is defined as the pre-storage electrode; the pre-storage capacitor Cs1 is used to pre-store the data signal voltage of the next frame during the data writing phase (the backlight illumination time of the current frame).

[0036] Furthermore, during the data writing stage, the control signal jumps to a high potential, the first transistor T1 turns on, and after the data signal is written to the pre-storage electrode, the control signal jumps back to a low potential and enters the charge transfer stage (during the backlight off time of the current frame). The transfer signal jumps to a high potential, the second transistor T2 turns on, and after the data signal is transferred to the pixel electrode, the transfer signal jumps back to a low potential.

[0037] Furthermore, such as Figure 4 As shown, in frame N-1, the first sub-pixel is a positive frame and the second sub-pixel is a negative frame. After the charge transfer phase, the first global signal line Vcom-Even jumps to a low potential and the second global signal line Vcom-Odd jumps to a high potential. In frame N, the first sub-pixel is a negative frame and the second sub-pixel is a positive frame. After the charge transfer phase, the first global signal line Vcom-Even jumps to a high potential and the second global signal line Vcom-Odd jumps to a low potential.

[0038] It should be noted that, such as Figure 3 and Figure 4The circuit and driving timing shown are applicable to achieving pixel polarity reversal in a column-inverting manner. That is, in a given frame, odd-numbered column pixel electrodes have a positive voltage, and even-numbered column pixel electrodes have a negative voltage (based on the Vcom voltage). The pixel voltage polarity of each pixel is reversed periodically, one frame at a time (this is necessary for the polarity reversal of the liquid crystal drive; if the liquid crystal is driven by DC voltage, it will lead to liquid crystal polarization, resulting in DC image retention and liquid crystal damage). Those skilled in the art, after understanding the technical solution claimed in this application, can adaptively modify the circuit and driving timing to achieve polarity reversal methods such as row inversion or dot inversion. Furthermore, the circuit in this application uses an N-type TFT as the TFT device. In the timing diagram, a high level corresponds to the gate control signal, indicating on, and a normal potential indicates off. This can also be extended to a P-type TFT, where a low level indicates on and a high level indicates off.

[0039] Based on the driving circuit in this embodiment, the above-mentioned data signal voltage calculation method will now be further explained: Let Cs2 = m * Cs1, Clc = p * Cs1, where p is a function of grayscale voltage, i.e., p = f(V). Then Vdn can be characterized as D(Vn) = Vn + Vop_max * [f(Vn) / (m + f(Vn)], where Vdn is the intermediate voltage and Vn is the target voltage.

[0040] For the first frame (positive frame) of a certain sub-pixel (Vpixel is the reference voltage 0V when writing the first frame): In the positive frame, the pre-written voltage of capacitor Cs1 is Vcs11. If Vpixel needs to be equal to V1... We have [(Vcs11)-(Vd1)]*Cs1=((Vd1)-(0))*(Cs2+Clc)=((Vd1)-(0))*(m+p)Cs1, That is, Vcs11 = Vd1*(m+p)+1)-Vop_max, charge sharing is completed, and after ACcom jumps, Vpixel = V1, Vcs11 = D(V1)*[m+f(V1)+1]; Vd1 = D(V1), p = f(V1); The second frame (negative frame): If Vpixel needs to be V2, then [(Vcs12-0)-(Vd2)]*Cs1=((Vd2) - (V1))*(Cs2+Clc)=((V2) - (V1))*(m+p)Cs1, That is, Vcs12 = Vd2*(m+p+1) - V1*(m+p). Similarly, after charge sharing is completed, ACcom jumps and satisfies Vpixel = V2, Vcs12 = D(V2)*[m+f(V2)+1] - V1*(m+f(V2); Vd2 = D(V2), p = f(V2); The third frame (positive frame): If Vpixel needs to be V3, then [(Vcs13)-(Vd3)]*Cs1=((Vd3) - (V2))*(Cs2+Clc), That is, Vcs13 = Vd3*(m+p+1)-V2*(m+p). Similarly, after charge sharing is completed, ACcom jumps and satisfies Vpixel=V3, Vcs13=D(V3)*[m+f(V3)+1]-V2*(m+f(V3))-Vop_max; Vd3=D(V3), p=f(V3); Fourth frame (negative frame): If Vpixel needs to be V4, then [(Vcs14+0)-(Vd4)]*Cs1=((Vd4) - (V3))*(Cs2+Clc), That is, Vcs14 = Vd4*(m+p+1) - V3*(m+p). Similarly, after charge sharing is completed, ACcom jumps and satisfies Vpixel = V4, Vcs14 = D(V4)*[m+f(V4)+1] - V3*(m+f(V4)); Vd4 = D(V4), p = f(V4); … Frame n-1 (positive frame): If Vpixel is required to be Vn-1, then... We have [(Vcs1n-1-Vop)-(Vdn-1-Vop)]*Cs1=((Vdn-1-Vn-2)*Cs2+(Vdn-1-Vn-2)*Clc [Vcs1n-1-Vdn-1+Vop]*Cs1=((Vdn-1-Vn-2)*(Cs2+Clc) That is, Vcs1n-1 = Vdn-1*(m+p+1)-Vn-2*(m+p). After charge sharing is completed, ACcom jumps and satisfies Vpixel=Vn-1, Vcs1n-1=D(Vn-1)*[m+f(Vn-1)+1]-Vn-2*(m+f(Vn-1)); Vdn-1=D(Vn-1), p=f(Vn-1); Frame n (negative frame): If Vpixel needs to be Vn. There is [(Vcs1n -0)-(Vdn-0)]*Cs1=((Vdn-Vn-1)*Cs2+(Vdn-Vn-1)*Clc [Vcs1n-Vop-Vdn]*Cs1=((Vdn-Vn-1)*(Cs2+Clc) That is, Vcs1n = Vdn*(m+p+1)-Vn-1*(m+p), charge sharing is completed, and after ACcom jumps, Vpixel=Vn, Vcs1n=D(Vn)*[m+f(Vn)+1]-Vn-1*(m+f(Vn))+Vop; Vdn=D(Vn), p=f(Vn); where Vdn=D(Vn) =Vn+ Vop_max *[f(Vn) / (m+f(Vn)).

[0041] Similarly, the calculation principle of the data signal of the sub-pixels in the first frame being a negative frame will not be elaborated here.

[0042] From the above derivation, it can be concluded that, compared with the write voltage of conventional products, this invention compensates for the pre-storage electrode and reduces the required Data signal voltage range by switching the signal coupled to the end of the pre-storage capacitor Cs1 furthest from the pre-storage electrode. Simultaneously, it creatively proposes a method for calculating the data signal voltage, solving the problems of color shift and brightness differences caused by residual charge while improving the pixel aperture ratio without adding additional TFTs or wiring.

[0043] In one embodiment, such as Figure 5 As shown, the pixel driving circuit includes a first sub-pixel and a second sub-pixel. Both the first and second sub-pixels include a first transistor T1, a pre-storage capacitor Cs1, a second transistor T2, a holding capacitor Cs2, and a pixel capacitor Clc. The first source-drain of the first transistor T1 is coupled to a data signal line Data, and its gate is coupled to a control signal line Scan. Its second source-drain is coupled to the first source-drain of the second transistor T2 and one end of the pre-storage capacitor Cs1. The gate of the second transistor T2 is coupled to a transfer signal line Tran, and its second source-drain is coupled to one end of the holding capacitor Cs2 and one end of the pixel capacitor Clc. The ends of the holding capacitor Cs2 and the pixel capacitor Clc furthest from the second transistor T2 are coupled to a global signal line Vcom. The end of the pre-storage capacitor Cs1 of the first sub-pixel furthest from the first transistor T1 is coupled to a first coupling signal line Couple-Odd. The end of the pre-storage capacitor Cs1 of the second sub-pixel furthest from the first transistor T1 is coupled to a second coupling signal line Couple-Even.

[0044] Furthermore, during the data writing stage, the control signal jumps to a high potential, the first transistor T1 turns on, and after the data signal is written to the pre-storage electrode, the control signal jumps back to a low potential and enters the charge transfer stage. The transfer signal jumps to a high potential, the second transistor T2 turns on, and after the data signal is transferred to the pixel electrode, the transfer signal jumps back to a low potential.

[0045] Furthermore, such as Figure 6 As shown, in the (N-1)th frame, the first sub-pixel is a positive frame and the second sub-pixel is a negative frame. Then, after the data writing phase, the first coupling signal line Couple-Odd jumps to a high potential and the second coupling signal line Couple-Odd jumps to a low potential. In the Nth frame, the first sub-pixel is a negative frame and the second sub-pixel is a positive frame. Then, after the data writing phase, the first coupling signal line Couple-Even jumps to a low potential and the second coupling signal line Couple-Even jumps to a high potential.

[0046] The method for calculating the data signal voltage used in the driving circuit of this embodiment will now be explained: Frame n-1 (positive frame): If Vpixel is required to be Vn-1, then... There is [Vcs1 n-1-(Vn-1+2Vop_max)]*Cs1=((Vn-1-Vn-2)*(Cs2+Clc); Frame n (negative frame): If Vpixel needs to be Vn. There is [(Vcs1 n-(Vn-2Vop_max)]*Cs1=(Vn-Vn-1)*(Cs2+Clc). The above describes the pixel-driven data signal writing method and its driving circuit provided by the embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principle of the invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0047] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can implement the described functions using different methods for each specific application, but such implementation should not be considered beyond the scope of the invention. The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be implemented directly in hardware, software modules executed by a processor, or a combination of both. Software modules can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

Claims

1. A pixel-driven data signal writing method, characterized in that, include: Generate target potential based on the grayscale required for the next frame of the sub-pixel; Utilizing the principle of charge conservation, the method calculates the data signal voltage required for a pixel electrode potential to change to a target potential during charge transfer. This includes: generating a transferred charge based on the voltage difference between the pixel electrode potential of the sub-pixel in the current frame and the target potential, the pixel capacitance, and the holding capacitance; and calculating the potential of the pre-stored electrode required before the charge transfer stage based on the transferred charge, the target potential, and the pre-stored capacitance, which is the data signal voltage. Specifically, when the pixel capacitor of the pixel driving circuit is coupled to a global signal, if the transition timing of the global signal is after the charge transfer stage of frame N-1 and before the data writing stage of frame N, the method for calculating the data signal voltage includes: calculating the intermediate voltage required by the pixel electrode before the global signal transition in the current frame based on the target potential of the sub-pixel in the next frame; generating a transferred charge based on the voltage difference between the pixel electrode potential of the sub-pixel in the current frame and the intermediate voltage, the pixel capacitance, and the holding capacitance; and calculating the potential of the pre-stored electrode required before the charge transfer based on the transferred charge, the intermediate voltage, and the pre-stored capacitance, which is the data signal voltage. The data signal voltage is written to the pre-stored electrode.

2. The data signal writing method according to claim 1, characterized in that, The global signal is configured as follows: When the (N-1)th frame is a positive frame, the global signal remains at a high potential during the data writing phase and then jumps to a low potential after the charge transfer phase. When the Nth frame is a negative frame, the global signal remains at a low potential during the data writing phase and then jumps to a high potential after the charge transfer phase.

3. A pixel driving circuit, characterized in that, According to the data signal writing method of any one of claims 1 to 2, the pixel driving circuit includes: a first sub-pixel and a second sub-pixel, each of the first sub-pixel and the second sub-pixel including a first transistor (T1), a pre-storage capacitor (Cs1), a second transistor (T2), a holding capacitor (Cs2), and a pixel capacitor (Clc). The first source-drain of the first transistor (T1) is coupled to a data signal line (Data), and its gate is coupled to a control signal line (Scan). The second source-drain is coupled to the first source-drain of the second transistor (T2) and one end of the pre-storage capacitor (Cs1). The gate of the second transistor (T2) is coupled to a transfer signal line (Tran), and its second source-drain is coupled to one end of the holding capacitor (Cs2) and one end of the pixel capacitor (Clc). The end of the holding capacitor (Cs2) furthest from the second transistor (T2) is coupled to a reference signal line (Vref). The pre-storage capacitor (Cs1) of the first sub-pixel is coupled to the first global signal line (Vcom-Even) at the end away from the first transistor (T1), and the pixel capacitor (Clc) of the first sub-pixel is coupled to the first global signal line (Vcom-Even) at the end away from the second transistor (T2). The pre-storage capacitor (Cs1) of the second sub-pixel is coupled to the second global signal line (Vcom-Odd) at the end away from the first transistor (T1), and the pixel capacitor (Clc) of the second sub-pixel is coupled to the second global signal line (Vcom-Odd) at the end away from the second transistor (T2).

4. The driving circuit according to claim 3, characterized in that, During the data writing phase, the control signal jumps to a high potential, the first transistor (T1) turns on, and after the data signal is written to the pre-storage electrode, the control signal jumps back to a low potential and enters the charge transfer phase. The transfer signal jumps to a high potential, the second transistor (T2) turns on, and after the data signal is transferred to the pixel electrode, the transfer signal jumps back to a low potential.

5. The driving circuit according to claim 4, characterized in that, In the (N-1)th frame, if the first sub-pixel is a positive frame and the second sub-pixel is a negative frame, then after the charge transfer phase, the first global signal line (Vcom-Even) jumps to a low potential and the second global signal line (Vcom-Odd) jumps to a high potential. In frame N, if the first sub-pixel is a negative frame and the second sub-pixel is a positive frame, then after the charge transfer phase, the first global signal line (Vcom-Even) jumps to a high potential and the second global signal line (Vcom-Odd) jumps to a low potential.

6. A pixel driving circuit, characterized in that, According to the data signal writing method of any one of claims 1 to 2, the pixel driving circuit includes: a first sub-pixel and a second sub-pixel, each of the first sub-pixel and the second sub-pixel including a first transistor (T1), a pre-storage capacitor (Cs1), a second transistor (T2), a holding capacitor (Cs2), and a pixel capacitor (Clc). The first source-drain of the first transistor (T1) is coupled to a data signal line (Data), and its gate is coupled to a control signal line (Scan). The second source-drain is coupled to the first source-drain of the second transistor (T2) and one end of the pre-storage capacitor (Cs1). The gate of the second transistor (T2) is coupled to a transfer signal line (Tran), and its second source-drain is coupled to one end of the holding capacitor (Cs2) and one end of the pixel capacitor (Clc). The ends of the holding capacitor (Cs2) and the pixel capacitor (Clc) furthest from the second transistor (T2) are coupled to a global signal line (Vcom). The pre-storage capacitor (Cs1) of the first sub-pixel is coupled to the first coupling signal line (Couple-Odd) at the end away from the first transistor (T1). The pre-storage capacitor (Cs1) of the second sub-pixel is coupled to the second coupling signal line (Couple-Even) at the end away from the first transistor (T1).

7. The driving circuit according to claim 6, characterized in that, During the data writing phase, the control signal jumps to a high potential, the first transistor (T1) turns on, and after the data signal is written to the pre-storage electrode, the control signal jumps back to a low potential and enters the charge transfer phase. The transfer signal jumps to a high potential, the second transistor (T2) turns on, and after the data signal is transferred to the pixel electrode, the transfer signal jumps back to a low potential.

8. The driving circuit according to claim 6, characterized in that, In the (N-1)th frame, if the first sub-pixel is a positive frame and the second sub-pixel is a negative frame, then after the data writing phase, the first coupling signal line (Couple-Odd) jumps to a high potential and the second coupling signal line (Couple-Even) jumps to a low potential. In the Nth frame, if the first sub-pixel is a negative frame and the second sub-pixel is a positive frame, then after the data writing phase, the first coupling signal line (Couple-Odd) jumps to a low potential and the second coupling signal line (Couple-Even) jumps to a high potential.

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