Signal receiving circuit, signal receiving device, and clock recovery method for receiving signal

Abstract

A signal receiving circuit includes: first to third pulse generators; and a clock signal recovery unit (100) for generating a recovered clock signal (RCLK) and a recovered clock delay signal (RCLKD) using at least one of pulses including a first pulse, a second pulse, a third pulse, and first to third inverted pulses, the recovered clock delay signal being a signal obtained by delaying the recovered clock signal by a first delay time. The clock signal recovery unit includes: a loop interrupt circuit (110) including an input node (111) and an output node (112) and being turned on or off by at least one of the pulses; and a delay circuit having an input end connected to the output node (112) and an output end connected to the input node (111), wherein a signal value of the input node and a signal value of the output node are in an anti-correlation relationship. The present application can ensure at least one of accuracy, miniaturization, and low power consumption of clock signal recovery in a high-speed communication environment.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a signal receiving circuit, a signal receiving apparatus, and a clock recovery method for receiving a signal. BACKGROUND

[0002] C-PHY is a high-speed communication standard proposed by MIPI Alliance. It uses three lines and three-phase signals to represent six states, and encodes using state transitions between consecutive states as symbols. The protocol forces a state transition to always exist between consecutive symbols, and this feature allows clock information required for recovery of embedded symbols (data) to be embedded.

[0003] A C-PHY receiver is equipped with a circuit that recovers a clock signal based on information embedded in a received signal. The clock recovery circuit should generate a clock signal corresponding to each symbol, and as the communication rate increases, the symbol interval decreases, and thus, a clock recovery circuit that can operate at high speed is required.

[0004] Previously proposed clock recovery methods include a full-rate clock recovery method and a half-rate clock recovery method.

[0005] The full-rate clock recovery method generates a clock signal so that one rising edge corresponds to each received symbol (only the rising edge of the clock signal is used when a symbol is recovered). At this time, since a falling edge of the clock should exist between symbol clocks, although the falling edge does not directly participate in symbol recovery, an additional time delay is required to produce the falling edge, thereby limiting the maximum operating speed.

[0006] The half-rate clock recovery method generates a clock signal so that one rising edge or one falling edge corresponds to each symbol. Since both the rising edge and the falling edge of the clock signal are used when a symbol is recovered, the additional time delay is reduced, and this is advantageous for high-speed operation compared to the full-rate clock recovery method.

[0007] Patent Document 1 proposes a MIPI C-PHY receiving circuit that applies a full-rate clock recovery method. The full-rate clock recovery method has limitations in high-speed operation, and to solve this problem, the half-rate clock recovery method described in Patent Documents 2 and 3 is proposed.

[0008] However, according to the related art, there are limitations in reducing the delay time that inevitably involves when recovering a clock signal using an input signal, and thus, there is a problem that the accuracy and efficiency of clock signal recovery decrease as the communication rate increases.

[0009] In addition, according to the related art, there are limitations in reducing the area or power consumption of a circuit that performs a clock signal recovery function.

[0010] Therefore, there is a need to develop a technology capable of ensuring accuracy of clock signal recovery, miniaturization, low power consumption, and the like in a high-speed communication environment.

[0011] The above background art is technical information that the inventors have grasped in order to derive the present application, or that has been obtained in the process of deriving the present application, and cannot necessarily be regarded as known art that has been publicly disclosed to the public before the filing of the present application.

[0012] (Patent Document 1) US2021-0336760 A1 (2021.10.28)

[0013] (Patent Document 2) US11038666 B1 (2021.06.15)

[0014] (Patent Document 3) WO2018 / 034495 A1 (2018.02.22) SUMMARY

[0015] One aspect of the present application provides a signal receiving circuit capable of ensuring at least one of accuracy of clock signal recovery, miniaturization, and low power consumption in a high-speed communication environment.

[0016] To achieve the above object, according to one embodiment of the present application, there is provided a signal receiving circuit which receives a first input signal A, a second input signal B and a third input signal C having different signal levels in each unit interval (UI), the circuit comprising: a first pulse generator for receiving a first difference signal RX_AB obtained by subtracting the second input signal B from the first input signal A, and generating a first pulse pulAB which is high (H) at an edge of the first difference signal RX_AB; a second pulse generator for receiving a second difference signal RX_BC obtained by subtracting the third input signal C from the second input signal B, and generating a second pulse pulBC which is high (H) at an edge of the second difference signal RX_BC; a third pulse generator for receiving a third difference signal RX_CA obtained by subtracting the first input signal A from the third input signal C, and generating a third pulse pulCA which is high (H) at an edge of the third difference signal RX_CA; a clock signal recovery unit 100 for generating a recovered clock signal RCLK and a recovered clock delay signal RCLKD obtained by delaying the recovered clock signal by a first delay time, using at least one of the pulses including the first pulse, the second pulse, the third pulse, a first inverted pulse pulbAB which is an inverted signal of the first pulse, a second inverted pulse pulbBC which is an inverted signal of the second pulse, and a third inverted pulse pulbCA which is an inverted signal of the third pulse, wherein the clock signal recovery unit comprises: a loop interrupt circuit 110 including an input node 111 and an output node 112, and turned on and off by at least one of the pulses; and a delay circuit 120 having an input end connected to the output node 112, and an output end connected to the input node 111, wherein a signal value of the input node and a signal value of the output node have an anti-correlation.

[0017] At this time, the loop interrupt circuit can include a first PMOS transistor MP1 having one end connected to the input node and the other end connected to the output node, a first NMOS transistor MN1 having one end connected to the input node and the other end connected to the output node, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor each having one end connected to the other end of the first PMOS transistor and a gate to which the first inverted pulse, the second inverted pulse, or the third inverted pulse is applied, and a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor each having one end connected to the other end of the first NMOS transistor and a gate to which the first pulse, the second pulse, or the third pulse is applied.

[0018] In addition, the loop interrupt circuit can include a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor each having one end connected to the input node and the other end connected to the output node, and a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor each having one end connected to the input node and the other end connected to the output node, wherein the first pulse can be applied to a gate of the first NMOS transistor, the second pulse can be applied to a gate of the second NMOS transistor, the third pulse can be applied to a gate of the third NMOS transistor, the first inverted pulse can be applied to a gate of the first PMOS transistor, the second inverted pulse can be applied to a gate of the second PMOS transistor, and the third inverted pulse can be applied to a gate of the third PMOS transistor.

[0019] In addition, the clock signal recovery unit can further include a keeper 130 connected to the output node to prevent jitter of a signal output to the output node.

[0020] In addition, the loop interrupt circuit can further include a plurality of transistors, wherein, when the plurality of pulses are applied to the plurality of transistors, the plurality of transistors start to operate after an injection delay is passed, and the first delay time can be greater than a timing shift of the plurality of edges of the first to third differential signals and can be less than a value obtained by subtracting the injection delay from the unit interval.

[0021] According to one embodiment of the present application, a clock recovery method of a received signal includes the steps of receiving first, second, and third input signals each having a different signal level at each unit interval; generating first, second, and third difference signals, the first difference signal being a difference signal of the first and second input signals, the second difference signal being a difference signal of the second and third input signals, and the third difference signal being a difference signal of the third and first input signals; and a clock signal recovery step of recovering a clock signal using at least one of pulses including first through third pulses that are high (H) at edges of the first through third difference signals, and first through third inverted pulses that are inverted signals of the first through third pulses, wherein the clock signal recovery step is performed by a clock signal recovery unit including a loop constituted by a loop interrupt circuit and a delay circuit, and includes the steps of generating the recovered clock signal due to the loop interrupt circuit turning on when one of the first through third pulses becomes high (H), generating a recovered clock delay signal obtained by delaying the recovered clock signal by a first delay time by the delay circuit, and inputting the recovered clock delay signal to an input node of the loop interrupt circuit, wherein a signal value of the input node and a signal value of an output node have an anti-correlation.

[0022] At this time, the clock signal recovery step can include the steps of outputting a high level signal to an output node of the loop interrupt circuit when one of the first through third pulses becomes high (H), outputting a high level signal to the output node of the loop interrupt circuit when one of the first through third pulses becomes high (H) before the first delay time elapses, and outputting a low level signal to the output node of the loop interrupt circuit when one of the first through third pulses becomes high (H) after the first delay time elapses.

[0023] A signal receiving apparatus according to an embodiment of the present application includes first through Nth clock recovery modules 1200 operating with a half-rate clock recovery method, and a logic operation unit for performing a logic operation on recovered clock signals output from the first through Nth clock recovery modules and outputting the recovered clock signals, wherein the first through Nth clock recovery modules generate recovered clock delay signals obtained by delaying the recovered clock signals by a second delay time, the second delay time being greater than the unit interval, and the first through Nth clock recovery modules are sequentially enabled at each unit interval. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 FIG. 1 is a diagram schematically illustrating a signal receiving circuit according to an embodiment of the present application.

[0025] Figure 2 FIG. 2 is a diagram schematically illustrating a clock signal recovery unit according to an embodiment of the present application.

[0026] Figure 3 FIG. 3 is a diagram illustrating in detail the clock signal recovery unit according to an embodiment of the present application.

[0027] Figure 4 FIG. 4 is a diagram schematically illustrating a signal timing chart of the signal receiving circuit according to an embodiment of the present application.

[0028] Figure 5 FIG. 5 is a diagram illustrating in detail a keeper according to an embodiment of the present application.

[0029] Figure 6 FIG. 6 is a diagram illustrating in detail the clock signal recovery unit according to another embodiment of the present application.

[0030] Figure 7 FIG. 7 is a diagram illustrating in detail the clock signal recovery unit according to still another embodiment of the present application.

[0031] Figure 8 FIG. 8 is a diagram schematically illustrating a signal receiving apparatus according to an embodiment of the present application.

[0032] Figure 9 FIG. 9 is a diagram schematically illustrating a signal timing chart of the signal receiving apparatus according to an embodiment of the present application.

[0033] Figure 10 FIG. 10 is a diagram schematically illustrating a clock recovery method of a received signal according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] The advantages and features of the present application and a method of accomplishing the same will become apparent from the following embodiments described in detail in conjunction with the accompanying drawings. However, the present application is not limited to the embodiments disclosed herein and can be implemented in various different forms. These embodiments are provided so that the disclosure of the present application is complete and fully conveys the scope of the present application to those skilled in the art. The same reference numerals are used throughout the specification to refer to the same components.

[0035] The terms used in the present specification are used to describe the embodiments and are not intended to limit the present application. In the present specification, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise. The terms such as "include" and / or "comprise" used in the specification mean that the mentioned components, steps, operations and / or elements do not exclude one or more other components, steps, operations and / or elements.

[0036] Hereinafter, the configuration and effects of the present application will be described in more detail with reference to the accompanying drawings.

[0037] Figure 1 FIG. 1 is a diagram schematically illustrating a signal receiving circuit according to an embodiment of the present application, Figure 2 FIG. 2 is a diagram schematically illustrating a clock signal recovery unit according to an embodiment of the present application, Figure 3 FIG. 3 is a diagram illustrating in detail the clock signal recovery unit 100 according to an embodiment of the present application, Figure 4 FIG. 4 is a diagram schematically illustrating a signal timing chart of the signal receiving circuit 1000 according to an embodiment of the present application, Figure 5 FIG. 5 is a diagram illustrating in detail a keeper according to an embodiment of the present application, Figure 6 FIG. 6 is a diagram illustrating in detail the clock signal recovery unit 100 according to another embodiment of the present application, Figure 7 FIG. 7 is a diagram illustrating in detail the clock signal recovery unit 100 according to still another embodiment of the present application, Figure 8 FIG. 8 is a diagram schematically illustrating a signal receiving apparatus 2000 according to an embodiment of the present application, Figure 9 FIG. 9 is a diagram schematically illustrating a signal timing chart of the signal receiving apparatus 2000 according to an embodiment of the present application, Figure 10 FIG. 10 is a diagram schematically illustrating a clock recovery method of a received signal according to an embodiment of the present application.

[0038] The present application relates to a signal receiving circuit 1000.

[0039] The signal receiving circuit 1000 according to an embodiment of the present application can satisfy the C-PHY specification of Mobile Industry Processing Interface (MIPI), but is not limited thereto.

[0040] The signal receiving circuit 1000 according to an embodiment of the present application can include a clock signal recovery unit 100. In an embodiment, the clock signal recovery unit 100 can operate using a half-rate clock recovery method.

[0041] In an embodiment, the signal receiving circuit 1000 can receive first, second, and third input signals A, B, and C having different signal levels in each unit interval (UI), and recover a clock signal.

[0042] In one embodiment, the clock signal recovery unit 100 generates the recovered clock signal RCLK using at least one of the pulses. In one embodiment, the clock signal recovery unit 100 can generate a recovered clock delay signal RCLKD.

[0043] In one embodiment, the pulse generator can generate the pulses. At this time, the pulses can include a first pulse pulAB, a second pulse pulBC, a third pulse pulCA, a first inverted pulse pulbAB (an inverted signal of the first pulse pulAB), a second inverted pulse pulbBC (an inverted signal of the second pulse pulBC), and a third inverted pulse pulbCA (an inverted signal of the third pulse pulCA).

[0044] For example, the first pulse generator 21 can receive a first differential signal RX_AB obtained by subtracting the second input signal B from the first input signal A, and generate the first pulse pulAB which is high (H) at an edge of the first differential signal RX_AB.

[0045] Further, the second pulse generator 22 can receive a second differential signal RX_BC obtained by subtracting the third input signal C from the second input signal B, and generate the second pulse pulBC which is high (H) at an edge of the second differential signal RX_BC.

[0046] Further, the third pulse generator 23 can receive a third differential signal RX_CA obtained by subtracting the first input signal A from the third input signal C, and generate the third pulse pulCA which is high (H) at an edge of the third differential signal RX_CA.

[0047] Reference Figure 1 When the control signal of the pulse generator FOH is high (H), the first pulse pulAB, the second pulse pulBC, and the third pulse pulCA can all be high (H). In one embodiment, when the FOH is high (H), the recovered clock signal RCLK generated by the clock signal recovery unit is independent of the first input signal A, the second input signal B, and the third input signal C, and the frequency thereof is determined by the first delay time t D . Considering these features, in a state where the FOH is high (H), by observing the frequency of the recovered clock signal RCLK while changing the control signal of the delay circuit 120 implemented as a programmable delay line, the relationship between the control signal and the first delay time t D can be grasped. Since the value of the first delay time t D required when actually recovering the clock from the received signal is determined by the operating frequencies of the first input signal A, the second input signal B, and the third input signal C, and the timing offset tskew The size of the FOH is determined in relation to the size of the programmable delay line, so the above-described relationship can be used to determine the control signal to be applied to the programmable delay line. That is, the control signal of the programmable delay line can be adaptively controlled or calibrated using the FOH.

[0048] Referring to Figure 1 , the first differential signal RX_AB, the second differential signal RX_BC, and the third differential signal RX_CA can be input to the first AND gate 11, the second AND gate 12, and the third AND gate 13, ANDed with the enable signal EN, and provided to the first pulse generator 21, the second pulse generator 22, and the third pulse generator 23, respectively.

[0049] Meanwhile, the first inverted pulse pulbAB, the second inverted pulse pulbBC, and the third inverted pulse pulbCA do not necessarily need to be generated by the pulse generators. That is, the first inverted pulse pulbAB, the second inverted pulse pulbBC, and the third inverted pulse pulbCA can be generated by a method of providing an inverter or the like between the pulse generators and the clock signal recovery unit 100 or inside the clock signal recovery unit 100.

[0050] In one embodiment, the clock signal recovery unit 100 can include a loop interrupt circuit 110 and a delay circuit 120. The loop interrupt circuit 110 includes an input node 111 and an output node 112. In addition, the loop interrupt circuit 110 can connect or disconnect the input node 111 and the output node 112 by at least one of the above-described pulses.

[0051] In one embodiment, an input terminal of the delay circuit 120 is connected to the output node 112 of the loop interrupt circuit 110, and an output terminal of the delay circuit 120 is connected to the input node 111 of the loop interrupt circuit 110. Then, the delay circuit 120 outputs the input signal delayed by a predetermined first delay time t D .

[0052] The signal output through the output node 112 of the loop interrupt circuit 110 is delayed by the first delay time t D by the delay circuit 120 and applied to the input node 111 of the loop interrupt circuit 110.

[0053] The signal receiving circuit 1000 according to one embodiment of the present application makes the signal value of the input node 111 and the signal value of the output node 112 in an inverted relationship. In one embodiment, an inverter can be provided between the output node 112 and the delay circuit 120 (A1) or between the delay circuit 120 and the input node 111 (A2) to invert the signal values. In another embodiment, the signal values can be inverted by the delay circuit 120 itself (e.g., a flip-flop). Figure 6 and7 As shown, inverters are provided in the delay circuit 120 to perform signal delay and signal inversion. In another embodiment, the loop break circuit 110 itself can invert the signal value of the input node 111 and output the inverted signal value to the output node 112 (see Figure 3 the embodiment shown).

[0054] In one embodiment, when at least one of the first pulse pulAB, the second pulse pulBC, and the third pulse pulCA becomes high (H), the input node 111 and the output node 112 are connected, and the signal value of the input node 111 can be transmitted to the output node 112. Further, even when another one of the first pulse pulAB, the second pulse pulBC, and the third pulse pulCA becomes high (H) after a first delay time t D elapsed by the delay circuit 120, the signal value of the output node 112 is maintained. Then, when the other one of the first pulse pulAB, the second pulse pulBC, and the third pulse pulCA becomes high (H) after a second delay time t D elapsed, the signal value of the output node 112 is inverted. In this way, the recovery clock signal RCLK can be generated by the clock signal recovery unit 100. Here, a signal obtained by delaying the recovery clock signal RCLK by the first delay time t D elapsed can be referred to as a recovery clock delay signal RCLKD. The signal reception circuit 1000 according to one embodiment of the present application can recover data to be transmitted through the first signal A, the second signal B, and the third signal C by using at least one of the recovery clock signal RCLK and the recovery clock delay signal RCLKD generated by the clock signal recovery unit 100. To this end, a data recovery unit (not shown) can be included in the signal reception circuit 1000.

[0055] Although a method of recovering a clock signal using the first pulse pulAB, the second pulse pulBC, and the third pulse pulCA is described in the above-described embodiment, a first inverted pulse pulbAB, a second inverted pulse pulbBC, and a third inverted pulse pulbCA can be used, or both the first pulse pulAB, the second pulse pulBC, and the third pulse pulCA and the first inverted pulse pulbAB, the second inverted pulse pulbBC, and the third inverted pulse pulbCA can be used to recover a clock signal.

[0056] In one embodiment, the loop break circuit 110 can be implemented as a tri-state inverter. At this time, the tri-state inverter can take three states, i.e., a high level (H), a low level (L), and a high impedance (Hi-Z), and the high impedance (Hi-Z) state refers to a state within an interval in which the tri-state inverter is not activated. Here, when the first pulse pulAB, the second pulse pulBC, and the third pulse pulCA are low levels (L), the tri-state inverter is inactivated.

[0057] Referring to Figure 3 , the loop break circuit 110 can include first to fourth PMOS transistors and first to fourth NMOS transistors. A gate of the first PMOS transistor MP1 is connected to the input node 111, and one end is connected to the output node 112. A gate of the first NMOS transistor MN1 is connected to the input node 111, and one end is connected to the output node 112. One end of each of the second to fourth PMOS transistors MP2, MP3, MP4 is connected to the other end of the first PMOS transistor MP1, and first to third inverted pulses pulbAB, pulbBC, and pulbCA are applied to gates of the second to fourth PMOS transistors, respectively. One end of each of the second to fourth NMOS transistors MN2, MN3, MN4 is connected to the other end of the first NMOS transistor MN1, and first to third pulses pulbAB, pulbC, and pulCA are applied to gates of the second to fourth NMOS transistors, respectively.

[0058] Referring to Figure 3 and Figure 4 , in a state in which the input node 111 is a low level (L), when the first pulse pulAB becomes a high level (H) at a rising edge of the first differential signal RX_AB, and the high level (H) signal value of the first pulse pulAB is applied to the loop break circuit 110, as the first to fourth PMOS transistors and the first to fourth NMOS transistors start to operate, the low level (L) signal value of the input node 111 is inverted and output to the output node 112, and the signal value of the output node 112 changes from a low level (L) to a high level (H). At the same time, the signal output to the output node 112 can be referred to as a recovered clock signal RCLK.

[0059] In one embodiment, the delay circuit 120 outputs a recovered clock delay signal RCLKD obtained by delaying the recovered clock signal RCLK by a first delay time t D , and the recovered clock delay signal RCLKD is applied to the input node 111.

[0060] Next, the third pulse pulCA becomes high (H) at the rising edge of the third differential signal RX_CA, and when the high signal value of the third pulse pulCA is applied to the loop break circuit 110, the first to fourth PMOS transistors and the first to fourth NMOS transistors start to operate.

[0061] At this time, since it is in a state of applying the recovery clock delay signal RCLKD to the input node 111, the low (L) signal value of the recovery clock delay signal RCLKD is inverted and output to the output node 112, and the signal value of the output node 112 is maintained as high (H).

[0062] Next, when the first delay time t D passes, the recovery clock delay signal becomes high (H), and the signal value of the input node 111 becomes high (H).

[0063] Next, the second pulse pulBC becomes high (H) at the falling edge of the second differential signal (RX_BC), and when the high (H) signal value of the third pulse pulCA is applied to the loop break circuit 110, as the first to fourth PMOS transistors start to operate, the high (H) signal value of the input node 111 is inverted and output to the output node 112, and the signal value of the output node 112 changes from high (H) to low (L).

[0064] Referring to Figure 3 , the clock signal recovery unit 100 can further include a keeper 130. In one embodiment, the keeper 130 is connected to the output node 112, and can perform a function of preventing jitter of the signal output to the output node 112.

[0065] Referring to Figure 5 , in one embodiment, the keeper 130 can include a NAND gate 131 and an inverter 132. At this time, the output node 112 can be connected to the first input terminal of the NAND gate 131, and a control signal can be applied to the second input terminal of the NAND gate 131. In addition, the input terminal of the inverter 132 can be connected to the output terminal of the NAND gate 131, and the output terminal of the inverter 132 can be connected to the output node 112.

[0066] In Figure 4 , t injmay represent a delay time determined according to a time required for a transistor to react when the first pulse pulAB, the second pulse pulBC, and the third pulse pulCA, and the first inverted pulse pulbAB, the second inverted pulse pulbBC, and the third inverted pulse pulbCA are applied to the loop interrupt circuit 110, and can be referred to as an injection delay.

[0067] Further, t skew may represent a timing skew in which the timing of edges of the first differential signal RX_AB, the second differential signal RX_BC, and the third differential signal RX_CA does not match within a unit interval (UI) skew .

[0068] When the second pulse pulBC or the third pulse pulCA becomes high (H) within the timing skew tskew after the first pulse pulAB becomes high (H), the recovered clock signal RCLK can be made not to be affected, thereby solving the timing skew problem. To this end, the recovered clock signal RCLK, which becomes high (H) corresponding to the edge of the differential signal that is first generated within a unit interval (UI), is generated, and the recovered clock signal RCLK remains despite the edge of the differential signal again occurring within the first delay time tD. At this time, the first delay time tD can be set to be greater than the timing skew tskew of the edges of the first differential signal RX_AB, the second differential signal RX_BC, and the third differential signal RX_CA, and less than a value obtained by subtracting the injection delay tinj from the unit interval (UI). Here, the first delay time tD can be determined by the delay circuit 120, and in one embodiment, when the delay circuit 120 is implemented as a programmable delay line, the first delay time tD can also be adjusted.

[0069] Since the first delay time t D is set to be greater than the timing skew t skew and less than a value obtained by subtracting the injection delay t inj in the signal receiving circuit 1000 according to the embodiment of the present application can recover a clock signal in a half-rate clock recovery method.

[0070] In the related art, as the unit interval (UI) decreases, a large delay time inevitably occurs in the circuit design in addition to the deliberately adjusted delay time, and thus the setting of the delay time becomes difficult. However, in the signal receiving circuit 1000 according to the embodiment of the present application, since the delay time that inevitably occurs for clock recovery is only the above-described injection delay t inj , the setting of the first delay time t Dmargin can be ensured. That is, when a unit interval (UI) is reduced as a communication rate increases and thus a timing offset t skew As the difference between the timing offset t and the unit interval (UI) is reduced, the present application is advantageous in improving the precision of clock recovery compared to other conventional techniques.

[0071] In addition, although in many cases, conventional circuits occupy a considerable area on a circuit or consume considerable power to recover a clock signal, since the signal receiving circuit 1000 according to the embodiment of the present application can recover a clock signal using only the loop interrupt circuit 110 and the delay circuit 120 configured by transistors, the precision and efficiency of clock signal recovery can be improved, and it is advantageous in reducing the area and power consumption.

[0072] Referring to Figure 6 The loop interrupt circuit 110 can be implemented using the first to third NMOS transistors. At this time, one ends of the first to third NMOS transistors are connected to the input node 111, and the other ends are connected to the output node 112. In addition, the first pulse pulAB is applied to the gate of the first NMOS transistor MN1, the second pulse pulBC is applied to the gate of the second NMOS transistor MN2, and the third pulse pulCA is applied to the gate of the third NMOS transistor MN3.

[0073] Accordingly, when any one of the pulses becomes a high level (H), the signal value of the input node 111 is output to the output node 112. In addition, the output signal is delayed by the delay circuit 120 by a first delay time t D and then applied to the input node 111.

[0074] Referring to Figure 7 The loop interrupt circuit 110 can be implemented using the first to third NMOS transistors and the first to third PMOS transistors. At this time, one ends of the first to third NMOS transistors and the first to third PMOS transistors are connected to the input node 111, and the other ends are connected to the output node 112. In addition, the first pulse pulAB is applied to the gate of the first NMOS transistor MN1, the second pulse pulBC is applied to the gate of the second NMOS transistor MN2, the third pulse pulCA is applied to the gate of the third NMOS transistor MN3, the first inverted pulse pulbAB is applied to the gate of the first PMOS transistor MP1, the second inverted pulse pulbBC is applied to the gate of the second PMOS transistor MP2, and the third inverted pulse pulbCA is applied to the gate of the third PMOS transistor MP3.

[0075] Accordingly, when any one of the pulses becomes high (H), the signal value of the input node 111 is output to the output node 112. Further, the output signal is delayed by the delay circuit 120 by a first delay time t D is then applied to the input node 111. Here, the signal delay and the signal inversion can be performed by the delay circuit 120 itself. An inverter (not shown) can be provided between the output node 112 and the delay circuit 120 (A1) or between the delay circuit 120 and the input node 111 (A2).

[0076] Reference Figure 8 and Figure 9 The signal receiving apparatus 2000 according to an embodiment of the present application is a signal receiving apparatus 2000 that receives a first input signal A, a second input signal B, and a third input signal C having different signal levels in each unit interval (UI).

[0077] In one embodiment, the signal receiving apparatus 2000 can include first to Nth clock recovery modules 1200 and a logic operation unit 1300.

[0078] Each of the first to Nth clock recovery modules 1200 operates in a half-rate clock recovery method and generates a recovered clock signal and a recovered clock delayed signal (obtained by delaying the recovered clock signal by a second delay time t D2 ).

[0079] The logic operation unit 1300 performs a logic operation on the recovered clock signals output from the first to Nth clock recovery modules 1200 and outputs the same. At this time, the logic operation can include an XOR operation or the like, and can be implemented as an edge combiner 1300 or the like.

[0080] The second delay time t D2 is greater than a unit interval (UI), and the first to Nth clock recovery modules 1200 are sequentially enabled in each unit interval (UI).

[0081] In one embodiment, when an injection delay t inj is less than a multiple of the unit interval (UI), and the second delay time t D2 is greater than a multiple of the unit interval (UI) by adding the timing offset t D2 to the injection delay t skewWhen values obtained by adding N-1 unit intervals (UIs) are added, N 1 / 2N-rate clock signals are generated, and can be used as a reference clock for data recovery by performing a logical operation on the values. Thus, even when the communication rate increases and thus the unit interval (UI) becomes shorter than the delay time that can be designed, the 1 / 2N-rate clock recovery method can be used to recover the clock signal.

[0082] In one embodiment, the signal receiving apparatus 2000 can further include a control unit 1100. The control unit 1100 can receive the first differential signal RX_AB, the second differential signal RX_BC, and the third differential signal RX_CA, and provide the first to Nth enable signals (EN1, EN2, …, ENN) to the first to Nth clock recovery modules 1200.

[0083] For example, the case where N is 2 is described below.

[0084] The first clock recovery module can be activated and generate a first recovered clock signal RCLK1 and a first recovered clock delay signal RCLKD1.

[0085] Next, when one unit interval (UI) elapses from the point in time at which the first clock recovery module is activated, the second clock recovery module is activated, generating a second recovered clock signal RCLK2 and a second recovered clock delay signal RCLKD2.

[0086] Next, the logical operation unit 1300 can generate a recovered clock signal RCLK by performing an XOR operation on the first recovered clock signal RCLK1 and the second recovered clock signal RCLK2. H .

[0087] The clock signal recovery method according to an embodiment of the present application includes the steps of receiving a first input signal A, a second input signal B, and a third input signal C (S110), generating a first differential signal RX_AB, a second differential signal RX_BC, and a third differential signal RX_CA (S120), and recovering a clock signal.

[0088] The first to third input signals have different signal levels at each unit interval (UI).

[0089] A pulse can be generated using the first differential signal RX_AB, the second differential signal RX_BC, and the third differential signal RX_CA. At this time, the pulse can include a first pulse pulAB, a second pulse pulBC, and a third pulse pulCA, and a first inverted pulse pulbAB, a second inverted pulse pulbBC, and a third inverted pulse pulbCA.

[0090] In the clock signal recovery step, at least one pulse is used to recover the clock signal.

[0091] The clock signal recovery step can be performed by a clock signal recovery unit 100 including a loop constituted by a loop interrupt circuit 110 and a delay circuit 120.

[0092] First, when one of the first pulse pulAB, the second pulse pulBC, and the third pulse pulCA becomes a high level (H), the loop interrupt circuit 110 is turned on (S132), and a recovered clock signal RCLK is generated (S134).

[0093] Next, the delay circuit 120 generates a recovered clock delay signal RCLKD (S136) that is a signal obtained by delaying the recovered clock signal RCLK by a first delay time t D This recovered clock delay signal RCLKD is input to an input node 111 of the loop interrupt circuit 110. At this time, the signal value of the input node 111 and the signal value of an output node 112 are in an inverse correlation relationship.

[0094] In one embodiment, when one of the first pulse pulAB, the second pulse pulBC, and the third pulse pulCA becomes a high level (H), a high level signal is output to the output node 112 of the loop interrupt circuit 110.

[0095] At this time, when one of the first pulse pulAB, the second pulse pulBC, and the third pulse pulCA becomes a high level (H) before a first delay time t D passes, a high level signal is output to the output node 112 of the loop interrupt circuit 110.

[0096] Further, when one of the first pulse pulAB, the second pulse pulBC, and the third pulse pulCA becomes a high level (H) after a first delay time t D passes, a low level signal is output to the output node 112 of the loop interrupt circuit 110.

[0097] In one embodiment, when one of the first pulse pulAB, the second pulse pulBC, and the third pulse pulCA becomes a high level while a high level (H) signal is applied to the input node 111, the high level (H) signal applied to the input node 111 of the loop interrupt circuit 110 is inverted, and a low level (L) signal is output to the output node 112 of the loop interrupt circuit 110.

[0098] In the present specification, all the differential signals, pulses, inverted pulses, recovered clock signals, recovered clock delay signals, and the like can be represented as digital signals.

[0099] In the present specification, the type of the transistor to which a pulse is applied and a timing chart are described based on a case where a high pulse is generated at an edge of a differential signal. However, those skilled in the art will readily understand that it can be replaced accordingly based on a case where a low pulse is generated at an edge of a differential signal.

[0100] Although the present application has been described with reference to the embodiments illustrated in the drawings, this is merely illustrative and those skilled in the art will understand that various modifications and other equivalent embodiments can be made thereby. Therefore, the true scope of the present application should be determined only by the appended claims.

[0101] According to the embodiments of the present application, a useful effect of being able to ensure at least one of accuracy of clock signal recovery, miniaturization, and low power consumption in a high-speed communication environment is achieved.

[0102] In particular, since the clock signal can be recovered only by the loop interrupt circuit and the delay circuit configured by the transistor, it is possible to improve the accuracy and efficiency of the clock signal recovery, and it is advantageous to reduce the area and power consumption.

Claims

1. A signal receiving circuit that receives a first input signal A, a second input signal B, and a third input signal C, the first input signal A, the second input signal B, and the third input signal C having different signal levels per unit interval (UI), the circuit comprising: a first pulse generator that receives a first difference signal RX_AB obtained by subtracting the second input signal B from the first input signal A, and generates a first pulse pulAB that is high (H) at an edge of the first difference signal RX_AB; a second pulse generator that receives a second difference signal RX_BC obtained by subtracting the third input signal C from the second input signal B, and generates a second pulse pulBC that is high (H) at an edge of the second difference signal RX_BC; a third pulse generator that receives a third difference signal RX_CA obtained by subtracting the first input signal A from the third input signal C, and generates a third pulse pulCA that is high (H) at an edge of the third difference signal RX_CA; and a clock signal recovery unit (100) that generates a recovered clock signal RCLK and a recovered clock delay signal RCLKD using at least one of the pulses including the first pulse, the second pulse, the third pulse, a first inverted pulse pulbAB that is an inverted signal of the first pulse, a second inverted pulse pulbBC that is an inverted signal of the second pulse, and a third inverted pulse pulbCA that is an inverted signal of the third pulse, the recovered clock delay signal RCLKD being a signal obtained by delaying the recovered clock signal by a first delay time, wherein the clock signal recovery unit includes: a loop interrupt circuit (110) that includes an input node (111) and an output node (112), and turns on and off by at least one of the pulses; and a delay circuit (120) whose input end is connected to the output node (112), whose output end is connected to the input node (111), wherein a signal value of the input node and a signal value of the output node have an anti-correlation.

2. The circuit of claim 1, wherein, the loop interrupt circuit includes: a first PMOS transistor MP1 whose gate is connected to the input node and one end is connected to the output node; a first NMOS transistor MN1 whose gate is connected to the input node and one end is connected to the output node; a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, each transistor having one end connected to the other end of the first PMOS transistor, and a gate to which the first inverted pulse, the second inverted pulse, or the third inverted pulse is applied; and a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, each transistor having one end connected to the other end of the first NMOS transistor, and a gate to which the first pulse, the second pulse, or the third pulse is applied.

3. The circuit of claim 1, wherein, the loop interrupt circuit includes: a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, one end of each transistor being connected to the input node and the other end being connected to the output node; and a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor, one end of each transistor being connected to the input node and the other end being connected to the output node, wherein the first pulse is applied to the gate of the first NMOS transistor, the second pulse is applied to the gate of the second NMOS transistor, the third pulse is applied to the gate of the third NMOS transistor, the first inverted pulse is applied to the gate of the first PMOS transistor, the second inverted pulse is applied to the gate of the second PMOS transistor, and the third inverted pulse is applied to the gate of the third PMOS transistor.

4. The circuit of claim 1, wherein, The clock signal recovery unit further includes a keeper (130) connected to the output node to prevent jitter of a signal output to the output node.

5. The circuit of claim 1, wherein, The loop interrupt circuit further includes a plurality of transistors, wherein, when the plurality of pulses are applied to the plurality of transistors, the plurality of transistors start to operate after passing through an injection delay, and the first delay time is greater than a timing shift of the plurality of edges of the first to third differential signals and is less than a value obtained by subtracting the injection delay from the unit interval.

6. A clock recovery method of receiving a signal, the method comprising: a step of receiving a first input signal, a second input signal, and a third input signal, each input signal having a different signal level at each unit interval; a step of generating a first differential signal, a second differential signal, and a third differential signal, the first differential signal being a differential signal of the first input signal and the second input signal, the second differential signal being a differential signal of the second input signal and the third input signal, and the third differential signal being a differential signal of the third input signal and the first input signal; and a clock signal recovery step of generating a recovered clock signal using at least one of pulses including first to third pulses that are high (H) at edges of the first to third differential signals and first to third inverted pulses that are inverted signals of the first to third pulses, wherein the clock signal recovery step is performed by a clock signal recovery unit including a loop constituted by a loop interrupt circuit and a delay circuit, wherein the loop interrupt circuit includes an input node and an output node, and the clock signal recovery step includes the following steps: generating the recovered clock signal due to conduction of the loop interrupt circuit when one of the first to third pulses becomes high (H); generating, by the delay circuit, a recovered clock delay signal obtained by delaying the recovered clock signal by a first delay time; and inputting the recovered clock delay signal to the input node, wherein a signal value of the input node and a signal value of the output node have an anti-correlation.

7. The method of claim 6, wherein, The clock signal recovery step includes the steps of: outputting a high level signal to an output node of the loop interrupt circuit when one of the first to third pulses becomes a high level (H), outputting a high level signal to the output node of the loop interrupt circuit when one of the first to third pulses becomes a high level (H) before the first delay time elapses, and outputting a low level signal to the output node of the loop interrupt circuit when one of the first to third pulses becomes a high level (H) after the first delay time elapses.

8. A signal receiving apparatus comprising the signal receiving circuit according to any one of claims 1 to 4, the apparatus comprising: first to Nth clock recovery modules (1200) that operate with a half-rate clock recovery method; and a logic operation unit that logically operates the recovery clock signals output from the first to Nth clock recovery modules and outputs the recovery clock signals, wherein the first to Nth clock recovery modules generate recovery clock delay signals that delay the recovery clock signals by a second delay time, wherein the second delay time is longer than the unit interval, and the first to Nth clock recovery modules are sequentially enabled every unit interval.

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