Entity page management method and storage device

Abstract

A method and a storage device for managing physical pages, the method comprising: obtaining a first total number of bits of a target physical page by applying a first read voltage to the target physical page; in response to determining that the first total number of bits is not less than a first predetermined threshold, setting a second read voltage according to the first read voltage and a voltage level width; obtaining a second total number of bits of the target physical page by applying the second read voltage to the target physical page; calculating a target total number of bits according to the first total number of bits and the second total number of bits; and in response to determining that the target total number of bits is greater than a second predetermined threshold, determining that the target physical page is a blank page.

Description

Technical Field

[0001] This invention relates to a memory management technology, and more particularly to a physical page management method for non-volatile memory, and a storage device using the method. Background Technology

[0002] Non-volatile memory refers to computer memory that retains its data even when the current is cut off. It has advantages such as non-volatile data, low power consumption, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] Common non-volatile memory (NVMemory) is memory configured with flash memory (such as SSDs), which features high read and write speeds and does not require mechanical structures for data access. To distinguish whether a physical page in flash memory is blank (erase-free), the memory controller uses the number of bits at a fixed read voltage. However, when voltage shifts occur in the memory, it can lead to false positives for blank pages. Summary of the Invention

[0004] The purpose of this invention is to solve the above-mentioned problems and avoid the influence of voltage offset on physical page identification. To this end, we provide a physical page management method that can effectively identify the blank / erase status of physical pages.

[0005] Another embodiment of the present invention provides a physical page management method for a storage controller. The method includes: obtaining a first total number of bits corresponding to the target physical page by applying a first read voltage to the target physical page; setting a second read voltage based on the first read voltage and the voltage level width in response to determining that the first total number of bits is not less than a first predetermined threshold; obtaining a second total number of bits corresponding to the target physical page by applying the second read voltage to the target physical page; calculating a target total number of bits based on the first total number of bits and the second total number of bits; and determining that the target physical page is a blank page in response to determining that the target total number of bits is greater than a second predetermined threshold.

[0006] In one embodiment of the present invention, in response to determining that the total number of the first bits is less than a first predetermined threshold, the target entity page is determined to be a blank page.

[0007] In one embodiment of the present invention, in the operation of obtaining the voltage level width of a target entity page corresponding to the plurality of entity pages, a plurality of read voltages of different levels are applied to the target entity page to obtain the total number of bits of the target entity page corresponding to the plurality of read voltages respectively, wherein the maximum read voltage and the minimum read voltage among the plurality of read voltages are identified based on the total number of bits, and the level of the maximum read voltage is subtracted from the level of the minimum read voltage to obtain the difference as the voltage level width.

[0008] In one embodiment of the invention, during the operation of setting the first read voltage, a difference obtained by subtracting one-quarter of the voltage level width from the level of the maximum read voltage is calculated, and the calculated difference is set as the first level of the first read voltage.

[0009] In one embodiment of the present invention, during the operation of setting the second read voltage according to the first read voltage and the voltage level width, a difference obtained by subtracting half of the voltage level width from the first level of the first read voltage is calculated, and the calculated difference is set as the second level of the second read voltage.

[0010] In one embodiment of the present invention, in the operation of calculating the target total number of bits based on the first total number of bits and the second total number of bits, the difference obtained by subtracting the first total number of bits from the second total number of bits is calculated, and the calculated difference is set as the target total number of bits.

[0011] In one embodiment of the present invention, the total number of bits corresponding to multiple read voltages is identified, wherein the total number of bits corresponding to the maximum read voltage is 0, and the total number of bits corresponding to the second largest read voltage is greater than 0, wherein the total number of bits corresponding to the minimum read voltage is the largest among the multiple total number of bits, and the total number of bits corresponding to the second smallest read voltage is the second largest among the multiple total number of bits.

[0012] In one embodiment of the present invention, the step of calculating the target total number of bits based on the first total number of bits and the second total number of bits includes: calculating the difference obtained by subtracting the first total number of bits from the second total number of bits, and setting the calculated difference as the target total number of bits.

[0013] In one embodiment of the present invention, determining that the target entity page is a blank page in response to determining that the total number of target bits is greater than a second predetermined threshold includes:

[0014] Obtain the maximum total number of bits in the target entity page, and set half of the maximum total number of bits as the second predetermined threshold.

[0015] Another embodiment of the present invention provides a storage device, including: a connection interface circuit, a rewritable non-volatile memory module, and a storage controller. The connection interface circuit is electrically connected to a host system. The rewritable non-volatile memory module includes a plurality of memory chips, wherein each memory chip has a plurality of physical blocks, and each physical block has a plurality of physical pages. The storage controller is electrically connected to the connection interface circuit and the rewritable non-volatile memory module. The storage controller is configured to: obtain a voltage level width corresponding to a target entity page among the plurality of entity pages; set a first read voltage; obtain a first total number of bits corresponding to the target entity page by applying the first read voltage to the target entity page; in response to determining that the first total number of bits is not less than a first predetermined threshold, set a second read voltage based on the first read voltage and the voltage level width; obtain a second total number of bits corresponding to the target entity page by applying the second read voltage to the target entity page; calculate a target total number of bits based on the first total number of bits and the second total number of bits; and determine whether the target total number of bits is greater than a second predetermined threshold, wherein in response to determining that the target total number of bits is not greater than the second predetermined threshold, the target entity page is determined to be a blank page, wherein in response to determining that the target total number of bits is greater than the second predetermined threshold, the target entity page is determined to be a blank page.

[0016] Based on the above, the physical page management method used in the storage device provided by this embodiment of the invention can accurately identify the blank state of physical pages by setting different read voltage levels and different blank page thresholds. Even if there is a serious deviation in the critical voltage distribution of a physical page, it can adaptively determine whether the physical page is blank. The provided physical page management method can identify the current data storage state of multiple physical pages in the storage device, improve the accuracy of erasing page (blank page) determination, reduce the probability of false judgment, thereby improving page utilization and enhancing the management efficiency of the storage device. Attached Figure Description

[0017] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0018] Figure 1 This is a block diagram illustrating a host system and storage device according to an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram illustrating the use of read voltage to read a normally erased page;

[0020] Figure 3A schematic diagram illustrating the use of an adjusted read voltage to read an abnormally erased page;

[0021] Figure 4 A schematic diagram illustrating the use of an adjusted read voltage to read a normally erased page;

[0022] Figure 5 A flowchart illustrating an entity page management method according to an embodiment of the present invention;

[0023] Figure 6 This is a schematic diagram illustrating the acquisition of the maximum read voltage width according to an embodiment of the present invention;

[0024] Figure 7 This is a schematic diagram illustrating the use of a first read voltage and a second read voltage to obtain the target total number of bits according to an embodiment of the present invention;

[0025] Figure 8 This is a schematic diagram of the critical voltage distribution for writing a page according to an embodiment of the present invention;

[0026] Figure 9 This is a schematic diagram illustrating the use of a first read voltage and a second read voltage to obtain the target total number of bits according to an embodiment of the present invention.

[0027] Explanation of icon numbers

[0028] 10: Host System

[0029] 20: Storage device

[0030] 110, 211: Processor

[0031] 120: Host memory

[0032] 130: Data transmission interface circuit

[0033] 210: Storage Controller

[0034] 212: Data Management Circuit

[0035] 213: Memory Interface Control Circuit

[0036] 214: Buffer memory

[0037] 220: Rewritable Non-volatile Memory Module

[0038] 230: Connection interface circuit

[0039] S310, S320, S330, S340, S350, S360, S370, S380, S390, S400: Flow steps of entity page management method; 21, 22, 31, 41, 61: Critical voltage distribution of entity pages.

[0040] Vry, Vry', Vry1, Vry2: Read voltage

[0041] Vry max Maximum read voltage

[0042] Vry min Minimum read voltage

[0043] ΔVry: Maximum read voltage level width

[0044] A201, A202: Arrows

[0045] 41_1, 41_1, 41_1, 61(1), 61(2), 61(2)_1, 61(2)_2, 61(2)_3: Partial critical voltage distribution Detailed Implementation

[0046] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0047] Figure 1 This is a block diagram illustrating a host system and storage device according to an embodiment of the present invention. Please refer to... Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110, host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is electrically connected (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be mounted on the motherboard of the host system 10.

[0048] Storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211, a data management circuit 212, and a memory interface control circuit 213.

[0049] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0050] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0051] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0052] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0053] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it must be understood that the present invention is not limited thereto, and the host memory 120 may also be other suitable memories.

[0054] The storage controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to the instructions of the host system 10.

[0055] More specifically, the processor 211 in the storage controller 210 is hardware with computing capabilities, used to control the overall operation of the storage controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program codes, and these control instructions / program codes are executed during the operation of the storage device 20 to perform operations such as writing, reading, and erasing data. Furthermore, in this embodiment, the control instructions / program codes can also be executed to perform physical page management operations (also known as physical page identification operations) to implement the physical page management method provided by this invention. The control instructions / program codes corresponding to the physical page management method can also be implemented as hardware circuit units to implement the physical page management method provided by this invention.

[0056] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and the present invention is not limited thereto.

[0057] In this embodiment, as described above, the storage controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the storage controller 210 can also be considered as operations performed by the storage controller 210 itself.

[0058] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to perform data transfer. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., performing a write operation according to a write instruction from the host system 10). Another example is reading data from one or more physical units of the rewritable non-volatile memory module 220 (data can be read from one or more memory cells in one or more physical units) via the memory interface control circuit 213 and writing the read data to the host system 10 (e.g., host memory 120) via the connection interface circuit 230 (e.g., performing a read operation according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

[0059] The memory interface control circuit 213 is used to receive instructions from the processor 211 and, in conjunction with the data management circuit 212, perform write (also known as programming), read, or erase operations (also known as erasure) on the rewritable non-volatile memory module 220.

[0060] In one embodiment, the storage controller 210 further includes a buffer memory 214. The buffer memory 214 is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data used to manage the storage device 20 (e.g., instruction queues storing various instructions, suspended instructions, and resume instructions) so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 214.

[0061] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213) and is used to store data written by the host system 10. In this embodiment, the rewritable non-volatile memory module 220 has multiple word lines, each of which is coupled to multiple memory cells (each memory cell can store 1 or more bits of data, depending on the form of the memory die), also called columns (or physical columns). Multiple columns on the same word line form a physical programming unit (also called a physical page). In addition, multiple physical pages can form a physical block (also called a physical erase unit). Each memory die in the multiple memory dies of the rewritable non-volatile memory module has multiple physical blocks.

[0062] Figure 2 This is a schematic diagram illustrating the use of read voltage to read normally erased pages. Please refer to... Figure 2 The existing method for confirming whether a target physical page is an erased page involves applying a predetermined read voltage to the target physical cell to obtain the total number of bits with a value of 0 corresponding to the predetermined read voltage (also called the total number of bits). Then, it is determined whether the total number of bits is less than a predetermined threshold for a blank erased page to determine whether the target physical page is an erased page (or a blank page). Figure 2 In this case, all bits of the critical voltage distribution 21 of the target physical page are to the left of the read voltage level Vry, meaning all bits have a value of 1. Since there are no bits to the right of the read voltage level Vry, the total number of bits with a value of 0 (bit 0) is 0 (also referred to as a total bit count of 0). In this example, because the total bit count is less than a predetermined threshold, the storage controller 210 determines that this target physical page is an erase page (blank page).

[0063] Figure 3 This is a schematic diagram of using an adjusted read voltage to read an abnormal erased page. However, using a single read voltage has drawbacks. For example, when the voltage curve of the rewritable non-volatile memory module shifts overall (as indicated by arrow A201, shifting to the right), the critical voltage distribution 22 for the erased page that caused this abnormality will have a portion appearing to the right of the predetermined read voltage level Vry. This will cause an increase in the total number of bits with a value of 0 obtained, which in turn will cause the erased page to be misjudged as not being a blank page / erase page because the total number of bits exceeds a predetermined threshold.

[0064] In one embodiment, to address the aforementioned rightward offset issue, the read voltage level Vry can be adjusted to the right to obtain a read voltage level Vry' (as shown by arrow A202). Thus, when the adjusted read voltage level Vry' reaches this abnormally erased page, the memory controller 210 determines that the total number of bits with a value of 0 is 0, which is less than a predetermined threshold, and thus correctly identifies this abnormally erased page as a blank page.

[0065] However, there are some problems with using this adjusted voltage level Vry' to determine whether it is a blank page.

[0066] Figure 4 This diagram illustrates how to read a normally erased page using an adjusted read voltage. Please refer to... Figure 4 Suppose a physical page has been programmed and its critical voltage distribution is biased to the left. When the storage controller 210 uses the adjusted read voltage level Vry' to determine whether this physical page is blank, the critical voltage distribution 31 of this physical page is entirely to the left of the adjusted read voltage level Vry'. This causes the storage controller 210 to recognize that the total number of bits acquired is 0, thus misjudging the physical page as blank. In other words, simply adjusting the read voltage level to the right or left will encounter some unsuitable situations, leading to misjudgments of the data storage status of the physical page.

[0067] It should be noted that the term "total number of bits" mentioned in the following embodiments refers to the total number of bits (memory cells) with a bit value of 0 under the read voltage, but the present invention is not limited thereto. For example, in another embodiment, "total number of bits" refers to the total number of bits (memory cells) with a bit value of 1 to the left of the read voltage, but the relevant judgment criteria and conditions will be adjusted accordingly.

[0068] Figure 5 This is a flowchart illustrating an entity page management method according to an embodiment of the present invention.

[0069] Please refer to Figure 5In step S310, the storage controller 210 (or processor 211) obtains the voltage level width of the corresponding target physical page. Specifically, in the operation of obtaining the voltage level width of the target physical page among multiple physical pages through pre-testing, the storage controller 210 applies multiple read voltages of different levels to the test physical page to obtain the total number of bits of the test physical page corresponding to the multiple read voltages respectively. The storage controller 210 identifies the maximum and minimum read voltages among the multiple read voltages based on the total number of bits. The total number of bits corresponding to the maximum read voltage is 0, and the total number of bits corresponding to the second largest read voltage is greater than 0. The total number of bits corresponding to the minimum read voltage is the largest among the multiple bit totals, and the total number of bits corresponding to the second smallest read voltage is the second largest among the multiple bit totals. The storage controller 210 subtracts the level of the minimum read voltage from the level of the maximum read voltage, and uses the difference as the voltage level width.

[0070] Figure 6 This is a schematic diagram illustrating the acquisition of the maximum read voltage width according to an embodiment of the present invention. For example, such as Figure 6 As shown, at the corresponding maximum read voltage Vry max The total number of bits is 0, and it corresponds to the minimum read voltage Vry. min The total number of bits is the maximum value (maximum total number of bits BN). max At the maximum read voltage Vry max The total number of bits at the second-largest read voltage (unit level) on the left is not zero, and at the minimum read voltage Vry min The total number of bits at the second smallest read voltage of a unit level on the right is less than the maximum total number of bits BN. max To put it more simply, the maximum read voltage Vry max and minimum read voltage Vry min The voltage level width between them is the voltage level width ΔVry and covers all the critical voltage distributions of the target entity page 41.

[0071] Please return to Figure 5 In step S320, the memory controller 210 sets a first read voltage. Specifically, in one embodiment, during the operation of setting the first read voltage, the memory controller 210 calculates the difference obtained by subtracting one-quarter of the voltage level width from the maximum read voltage level, and sets the calculated difference as the first level of the first read voltage. Simply put, the level of the first read voltage is one-quarter of the voltage level width to the left of the maximum read voltage. In another embodiment, the first level of the first read voltage is three-quarters of the voltage level width to the right of the minimum read voltage.

[0072] In step S330, the memory controller 210 obtains the first total number of bits for the corresponding target physical page by applying a first read voltage to the target physical page. Then, in step S340, the memory controller 210 determines whether the first total number of bits is less than a first predetermined threshold.

[0073] In response to the determination that the total number of first bits is less than the first predetermined threshold (S340 → Yes), in step S350, the storage controller 210 determines that the target entity page is a blank page.

[0074] However, if the total number of the first bits is less than the first predetermined threshold, the entity page management method of the present invention will further confirm whether the target entity page is indeed a blank page by performing multiple steps (e.g., steps S360 to S400). That is, in response to determining that the total number of the first bits is not less than the first predetermined threshold (S340 → No), in step S360, the storage controller 210 sets the second read voltage according to the first read voltage and the voltage level width.

[0075] More specifically, in the operation of setting the second read voltage based on the first read voltage and the voltage level width, the memory controller 210 calculates the difference obtained by subtracting half of the voltage level width from the first level of the first read voltage, and sets the calculated difference as the second level of the second read voltage.

[0076] In simple terms, the second level of the second read voltage is the first read voltage minus half its voltage level width. In another embodiment, the second level of the second read voltage is three-quarters of the voltage level width to the left of the maximum read voltage. In yet another embodiment, the second level of the second read voltage is the minimum read voltage increased by one-quarter of its voltage level width.

[0077] In other words, the width between the first level of the first read voltage and the second level of the second read voltage is half the width of the voltage level.

[0078] For example, please refer to Figure 7 , continuing Figure 6 The critical voltage distribution of the physical pages in the memory controller 210 can determine the first level Vry1 (also called the first read voltage level Vry1) and the second level Vry2 (also called the second read voltage level Vry2) of the first read voltage based on the voltage level width. The width between the first read voltage level Vry1 and the second read voltage level Vry2 is half of the voltage level width (e.g., The first read voltage level Vry1 and the second read voltage level Vry2 can divide the critical voltage distribution 41 of the target entity page into three parts: the first part to the right of the first read voltage level Vry1, the second part 41_2 between the first read voltage level Vry1 and the second read voltage level Vry2, and the third part 41_3 to the left of the second read voltage level Vry2.

[0079] Please return Figure 5 In step S370, the memory controller 210 obtains the second total number of bits for the corresponding target physical page by applying a second read voltage to the target physical page. In step S380, the memory controller 210 calculates the target total number of bits based on the first total number of bits and the second total number of bits.

[0080] In one embodiment, during the operation of calculating the target total number of bits based on the first total number of bits and the second total number of bits, the storage controller 210 calculates the difference obtained by subtracting the first total number of bits from the second total number of bits, and sets the calculated difference as the target total number of bits.

[0081] For example, please refer to Figure 7 By applying a first read voltage level Vry1, the memory controller 210 can obtain the total number of bits corresponding to the first part 41_1 (also called the first total number of bits). By applying a second read voltage level Vry1, the memory controller 210 can obtain the total number of bits corresponding to both the first part 41_1 and the second part 41_2 (also called the second total number of bits). To obtain the total number of bits corresponding only to the second part 41_2, the memory controller 210 can subtract the first total number of bits from the second total number of bits to obtain a difference. This difference is the total number of bits corresponding to the second part 41_2 (also called the target total number of bits, as shown in gray).

[0082] It is worth noting that the first predetermined threshold can be preset based on the first total number of bits. For example, in one embodiment, the first predetermined threshold can be set to 1.5 times or twice the average of the multiple first total number of bits corresponding to multiple entity pages. In another embodiment, the first predetermined threshold can be set to the maximum total number of bits BN. max One-eighth or less of the value.

[0083] In step S390, the storage controller 210 determines whether the target total number of bits is greater than a second predetermined threshold. In this embodiment, the second predetermined threshold can be set to the maximum total number of bits BN. max Half of that. In other words, the total number of bits in the second part of the critical voltage distribution of the erase page (target total number of bits) should be greater than the maximum total number of bits BN, even if the voltage curve deviates slightly from the target. max One-half of.

[0084] If the total number of target bits is greater than the second predetermined threshold (S390 → Yes), proceed to step S350; if the total number of target bits is not greater than the second predetermined threshold (S390 → No), proceed to step S400.

[0085] In step S400, the storage controller 210 determines that the target entity page is not a blank page. That is, the storage controller 210 determines that the target entity page has been programmed.

[0086] The following uses Figure 8 , Figure 9 Here's an example illustrating a non-blank physical page.

[0087] Figure 8 This is a schematic diagram of the critical voltage distribution for writing a page, as shown in an embodiment of the present invention. Figure 9 This is a schematic diagram illustrating the use of a first read voltage and a second read voltage to obtain the target total number of bits according to an embodiment of the present invention. Please refer to... Figure 8 Assume the target entity page has been programmed (for writing pages). Furthermore, assume the critical voltage distribution 61 of the target entity page can be divided into two sub-distributions, such as the first sub-distribution 61(1) on the left and the second sub-distribution 61(2) on the right. Assume the total number of bits covered by each sub-distribution is half the maximum total number of bits BN. max .

[0088] Please refer to Figure 9 By applying a first read voltage level Vry1, the storage controller 210 can obtain the total number of bits (also called the first total number of bits) corresponding to the first part 61(2)_1 of the second sub-distribution 61(2). By applying a second read voltage level Vry1, the storage controller 210 can obtain the total number of bits (also called the second total number of bits) corresponding to both the first part 61(2)_1 and the second part 61(2)_2 of the second sub-distribution 61(2). In order to obtain the total number of bits corresponding only to the second part 61_2, the storage controller 210 can subtract the first total number of bits from the second total number of bits to obtain a difference. This difference is the total number of bits (also called the target total number of bits, as shown in gray) corresponding only to the second part 61(2)_2 of the second sub-distribution 61(2).

[0089] Theoretically, the target total number of bits in the second part of the second sub-distribution of the critical voltage distribution for writing pages, which is generally or slightly deviates from the voltage curve, should be less than the maximum total number of bits BN. max One-half of.

[0090] Based on the above, the storage device, storage controller, and physical page management method used by the storage controller provided in this embodiment of the invention can accurately identify the blank state of physical pages by setting different levels of read voltage and different blank page thresholds. Even if there is a serious deviation in the critical voltage distribution of a physical page, it can adaptively determine whether the physical page is blank. The provided physical page management method can identify the current data storage state of multiple physical pages in the storage device, improve the accuracy of erasing page (blank page) judgment, reduce the probability of false judgment, thereby improving page utilization and enhancing the management efficiency of the storage device.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An entity page management method for a storage device, the method comprising: include: A first read voltage is applied to the target physical page to obtain the first total number of bits corresponding to the target physical page; In response to determining that the total number of the first bits is not less than a first predetermined threshold, a second read voltage is set according to the first read voltage and the voltage level width; as well as The second read voltage is applied to the target entity page to obtain the second total number of bits corresponding to the target entity page; The target total number of bits is calculated based on the first total number of bits and the second total number of bits, wherein the target total number of bits is the difference obtained by subtracting the first total number of bits from the second total number of bits. as well as In response to determining that the total number of target bits is greater than a second predetermined threshold, the target entity page is determined to be a blank page, wherein the second predetermined threshold is based on a maximum total number of bits in the target entity page, wherein the maximum total number of bits corresponds to a minimum read voltage.

2. The physical page management method of claim 1, wherein, In response to determining that the total number of the first bits is less than a first predetermined threshold, the target entity page is determined to be a blank page.

3. The method of claim 1, wherein, The steps for obtaining the voltage level width through pre-testing include: Multiple read voltages of different levels are applied to the test entity page to obtain the total number of bits of the test entity page corresponding to the multiple read voltages respectively; Based on the total number of bits, identify the maximum and minimum read voltages among the multiple read voltages; and The voltage level width is obtained by subtracting the minimum read voltage level from the maximum read voltage level.

4. The physical page management method of claim 3, wherein, The step of setting the first read voltage based on the maximum read voltage and the voltage level width includes: calculating the difference obtained by subtracting one-quarter of the voltage level width from the level of the maximum read voltage, and setting the calculated difference as the first level of the first read voltage.

5. The physical page management method of claim 3, wherein, The step of setting the second reading voltage based on the first reading voltage and the voltage level width includes: calculating the difference obtained by subtracting half of the voltage level width from the first level of the first reading voltage, and setting the calculated difference as the second level of the second reading voltage.

6. The physical page management method of claim 3, wherein, The step of identifying the maximum and minimum read voltages among the plurality of read voltages based on the total number of bits includes: Identify the total number of bits corresponding to the multiple read voltages, wherein the total number of bits corresponding to the maximum read voltage is 0, and the total number of bits corresponding to the second largest read voltage is greater than 0, wherein the total number of bits corresponding to the minimum read voltage is the largest among the multiple total number of bits, and the total number of bits corresponding to the second smallest read voltage is the second largest among the multiple total number of bits.

7. The entity page management method according to claim 1, characterized in that, The second predetermined threshold is set to half of the maximum total number of bits.

8. A memory device, comprising: include: Connecting interface circuitry for electrical connection to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of memory dies, wherein each memory die has a plurality of physical blocks, and each physical block has a plurality of physical pages; and The storage controller is electrically connected to the connection interface circuit and the rewritable non-volatile memory module. The storage controller is used to: A first read voltage is applied to the target physical page to obtain the first total number of bits corresponding to the target physical page; In response to determining that the total number of the first bits is not less than a first predetermined threshold, a second read voltage is set according to the first read voltage and the voltage level width; as well as The second read voltage is applied to the target entity page to obtain the second total number of bits corresponding to the target entity page; The target total number of bits is calculated based on the first total number of bits and the second total number of bits, wherein the target total number of bits is the difference obtained by subtracting the first total number of bits from the second total number of bits. as well as In response to determining that the total number of target bits is greater than a second predetermined threshold, the target entity page is determined to be a blank page, wherein the second predetermined threshold is based on a maximum total number of bits in the target entity page, wherein the maximum total number of bits corresponds to a minimum read voltage.

9. The memory device of claim 8, wherein, In response to determining that the total number of the first bits is less than a first predetermined threshold, the storage controller determines that the target entity page is a blank page.

10. The memory device of claim 8, wherein, The voltage level width is obtained through pre-testing, and its operation includes: The storage controller applies multiple read voltages of different levels to the test entity page to obtain the total number of bits of the test entity page corresponding to the multiple read voltages respectively; The memory controller identifies the maximum and minimum read voltages among the plurality of read voltages based on the total number of bits; and The storage controller subtracts the minimum read voltage from the maximum read voltage level to obtain the difference as the voltage level width.

11. The storage device according to claim 10, characterized in that, The storage controller sets the first read voltage based on the maximum read voltage and the voltage level width, and its operation includes: The storage controller calculates the difference obtained by subtracting one-quarter of the voltage level width from the level of the maximum read voltage, and sets the calculated difference as the first level of the first read voltage.

12. The storage device according to claim 10, characterized in that, In the operation of setting the second read voltage based on the first read voltage and the voltage level width, The storage controller calculates the difference obtained by subtracting half of the voltage level width from the first level of the first read voltage, and sets the calculated difference as the second level of the second read voltage.

13. The storage device according to claim 10, characterized in that, The step of identifying the maximum and minimum read voltages among the plurality of read voltages based on the total number of bits includes: The storage controller identifies the total number of bits corresponding to the plurality of read voltages, wherein the total number of bits corresponding to the maximum read voltage is 0, and the total number of bits corresponding to the second largest read voltage is greater than 0, wherein the total number of bits corresponding to the minimum read voltage is the largest among the plurality of total bits, and the total number of bits corresponding to the second smallest read voltage is the second largest among the plurality of total bits.

14. The storage device according to claim 8, characterized in that, The method of determining that the target entity page is a blank page in response to determining that the total number of target bits is greater than a second predetermined threshold includes: The storage controller obtains the maximum total number of bits in the target entity page and sets half of the maximum total number of bits as the second predetermined threshold.

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