Dynamic physical testing method, system, apparatus, and medium for programmable logic devices

Abstract

The application provides a dynamic physical test method, system, device and medium of a programmable logic device, the method comprising: obtaining physical test requirements of programmable logic of a to-be-tested FPGA, an FPGA source program, a control module circuit diagram, an interface control file and an electronic component file; developing a plurality of physical test cases according to the physical test requirements, the FPGA source program, the control module circuit diagram, the interface control file and the electronic component file; injecting excitation into the to-be-tested FPGA according to each physical test case, collecting output information corresponding to each physical test case; and judging whether the to-be-tested FPGA passes the physical test according to all the output information. The application greatly improves the fault tolerance of the programmable logic device of the aviation acquisition device, stably improves the use quality of the product, and can improve testability, ease of operation and the coverage of requirements.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of avionics, and relates to a dynamic physical test method, system, device and medium for a programmable logic device. BACKGROUND

[0002] At present, programmable logic devices (FPGA) of high integration of an aviation acquisition device are increasingly widely applied to various types of aircraft, and it is unrealistic to eliminate design defects of the programmable logic device through exhaustive verification. For example, the DO-254 system stipulates the verification process and verification method required for FPGA verification. Generally, the signals inside the FPGA can be verified through functional simulation, timing simulation or code analysis, and the signals of the external pins of the FPGA are realized through physical testing. However, in most cases, it cannot be guaranteed whether the use cases and program development time left for the test personnel in the product life cycle of the aviation acquisition device, the time period of the test and the technical level of the test personnel can meet the design development script, and thus it is difficult to guarantee the testability, ease of operation and robustness of the programmable logic device.

[0003] At the same time, in order to meet the airworthiness requirements, that is, to show through airworthiness certification that the design has realized the expected function and no unexpected function occurs, and thus to avoid safety hazards. Therefore, it is necessary to design a dynamic physical test method for the programmable logic device. SUMMARY

[0004] In order to solve the technical problems in the prior art that whether the use cases and program development time left for the test personnel in the product life cycle of the aviation acquisition device, the time period of the test and the technical level of the test personnel can meet the design development script cannot be guaranteed, and it is difficult to guarantee the testability, ease of operation and robustness of the programmable logic device during testing, the application discloses a dynamic physical test method for a programmable logic device, which comprises the following steps:

[0005] S1, acquiring physical test requirements of programmable logic of a to-be-tested FPGA, an FPGA source program, a control module circuit diagram, an interface control file and an electronic component file;

[0006] S2, developing a plurality of physical test cases according to the physical test requirements, the FPGA source program, the control module circuit diagram, the interface control file and the electronic component file;

[0007] S3, injecting excitation into the to-be-tested FPGA according to each physical test case, and collecting output information corresponding to each physical test case;

[0008] S4, judging whether the to-be-tested FPGA passes the physical test according to all the output information.

[0009] Further, in the step S2, the multiple physical test cases are developed according to the physical test requirements, the FPGA source program, the control module circuit diagram, the interface control file and the electronic component file, including:

[0010] S21, judging the test attribute of each of the physical test requirements according to the control module circuit diagram and the electronic component file, the test attribute including direct test and indirect test;

[0011] S22, setting the external connection pin according to the control module circuit diagram, the electronic component file and the interface control file, and developing the first physical test case corresponding to each of the directly testable physical test requirements;

[0012] S23, developing the second physical test case corresponding to each of the indirectly testable physical test requirements according to the interface control file and the FPGA source program by physical test and manual analysis method.

[0013] Further, in the step S23, the second physical test case corresponding to each of the indirectly testable physical test requirements is developed according to the interface control file and the FPGA source program by physical test and manual analysis method, including:

[0014] S231, selecting the information of the register related to each of the indirectly testable physical test requirements in the interface control file to develop the initial physical test case;

[0015] S232, developing the second physical test case of each of the indirectly testable physical test requirements by manually analyzing the FPGA source program and developing the initial physical test case again.

[0016] Further, in the step S3, the excitation is injected into the to-be-tested FPGA according to each of the physical test cases, and the output information corresponding to each of the physical test cases is collected, including:

[0017] S31, setting a constraint condition, and injecting excitation into the bus and the non-bus of the to-be-tested FPGA according to each of the physical test cases based on the constraint condition;

[0018] S32, setting a breakpoint or CPU software plug-in for the CPU software of the to-be-tested FPGA using a debugger, reading and writing the register value by serial printing, collecting the register value output by the PC end or collecting the waveform output by the oscilloscope after transforming the register value.

[0019] Further, in the step S32, the output information includes a waveform displayed by an oscilloscope, a debugger output data displayed by a PC, and a value of a serial port print register displayed by the PC.

[0020] Further, in the step S31, the constraint condition is that a program of the FPGA source program is not changeable.

[0021] Further, in the step S4, the judging whether the to-be-tested FPGA passes the physical test according to all the output information includes:

[0022] S41, judging each of the output information, if each of the output information can completely cover the physical test requirement corresponding to the output information, judging that the to-be-tested FPGA passes the test, if any of the output information cannot completely cover the physical test requirement corresponding to the output information, judging that the to-be-tested FPGA does not pass the test.

[0023] Alternatively, S42, transforming the output information of each of the physical test requirements to obtain data strongly related to the physical test requirement, and judging whether the to-be-tested FPGA passes the test according to the data.

[0024] Embodiments of the present application also provide a dynamic physical test system of a programmable logic device, which includes an information extraction module, a use case development module, a test and output module, and a judging module.

[0025] The information extraction module is used to acquire a physical test requirement of programmable logic of a to-be-tested FPGA, an FPGA source program, a control module circuit diagram, an interface control file, and an electronic component file.

[0026] The use case development module is used to develop a plurality of physical test use cases according to the physical test requirement, the FPGA source program, the control module circuit diagram, the interface control file, and the electronic component file.

[0027] The test and output module is used to inject an excitation to the to-be-tested FPGA according to each of the physical test use cases, and collect output information corresponding to each of the physical test use cases.

[0028] The judging module is used to judge whether the to-be-tested FPGA passes a physical test according to all the output information.

[0029] The embodiment of the present application further provides a computer device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the dynamic physical test method of the programmable logic device, so as to ensure the testability, operability and robustness of the programmable logic device.

[0030] The embodiment of the present application further provides a computer readable storage medium, which stores a computer program for executing the dynamic physical test method of the programmable logic device, so as to ensure the testability, operability and robustness of the programmable logic device.

[0031] Compared with the prior art, the above at least one technical solution adopted by the embodiment of the present application can achieve the beneficial effects at least including that the dynamic physical test method of the programmable logic device can greatly improve the fault tolerance of the programmable logic device of the aviation acquisition device, stably improve the use quality of the product, and improve the testability, operability and coverage of the programmable logic device during testing. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1 The flowchart of the dynamic physical test method of the programmable logic device disclosed by the embodiment of the present application;

[0034] Figure 2 The architecture diagram of the dynamic physical test system of the programmable logic device disclosed by the embodiment of the present application;

[0035] Figure 3 The schematic diagram of the computer device disclosed by the embodiment of the present application

[0036] Among them, 201, information extraction module; 202, use case development module; 203, test and output module; 204, judgment module; 301 memory; 302, processor. DETAILED DESCRIPTION

[0037] The embodiments of the present application will be described in detail below with reference to the drawings.

[0038] Following make the application's implementation through specific concrete example, the person skilled in the art can easily understand the other advantages and efficacy of the application from the disclosure of this specification. Obviously, the described embodiments are only a part of the embodiments of the application, not all the embodiments. The application can also be implemented or applied by another different specific implementation, and the details in the specification can be based on different views and applications, various modifications or changes are made without departing from the spirit of the application. It should be noted that the following embodiments and the features of the embodiments can be combined with each other without conflict. Based on the embodiments in the application, all other embodiments obtained by the person skilled in the art without creative labor belong to the scope of protection of the application.

[0039] The embodiment of the application discloses a dynamic physical test method of programmable logic device, see Figure 1 The method comprises the following steps:

[0040] S1, obtaining the physical test requirements of programmable logic of the to-be-tested FPGA, FPGA source program, control module circuit diagram, interface control file and electronic component file;

[0041] S2, developing a plurality of physical test cases according to the physical test requirements, the FPGA source program, the control module circuit diagram, the interface control file and the electronic component file;

[0042] S3, injecting excitation into the to-be-tested FPGA according to each physical test case, and collecting output information corresponding to each physical test case;

[0043] S4, judging whether the to-be-tested FPGA passes the physical test according to all the output information.

[0044] Further, in the above step S2, the developing a plurality of physical test cases according to the physical test requirements, the FPGA source program, the control module circuit diagram, the interface control file and the electronic component file comprises the following steps:

[0045] S21, judging the test attribute of each physical test requirement through the control module circuit diagram and the electronic component file, wherein the test attribute comprises direct test and indirect test; wherein the direct test means that the output can be tested through external pins, and the indirect test means that the test cannot be realized by viewing external pins.

[0046] S22, setting external connection pins according to the control module circuit diagram, the electronic component file and the interface control file, and developing first physical test cases corresponding to each directly testable physical test requirement; in particular, according to the names and approximate positions of circuit pins needing to inject excitation or view output during physical testing, the detailed description of the accurate positions and attributes of the circuit pins in the electronic component file, and the addresses, contents and lengths of registers used when injecting excitation in the interface control file, the external connection pins are designed to develop the first physical test cases, and the output information of the external connection pins is viewed to make judgments during dynamic physical testing.

[0047] S23, developing second physical test cases corresponding to each indirectly testable physical test requirement according to the interface control file and the FPGA source program through physical testing and manual analysis methods. In particular, the second physical test cases are designed for each indirectly testable physical test requirement through physical testing combined with manual analysis. When developing the cases, since the indirectly testable requirements correspond to no external pins that can be tested in the circuit board, the physical test cases are only used to prove whether the functions of the indirectly testable requirements exist. All information of registers related to the current requirements in the interface control file is referred to for preliminary development, and since the coverage of the physical test cases developed at this time does not reach 100% for the requirements, secondary development is needed, that is, the output content described for the remaining requirements is manually analyzed from the FPGA source program, and finally the second physical test cases are obtained.

[0048] Further, in the step S23, the developing of the second physical test cases corresponding to each indirectly testable physical test requirement according to the interface control file and the FPGA source program through physical testing and manual analysis methods comprises:

[0049] S231, selecting information of registers related to each indirectly testable physical test requirement in the interface control file to develop initial physical test cases;

[0050] S232, developing the initial physical test cases through manual analysis of the FPGA source program to obtain the second physical test cases of each indirectly testable physical test requirement.

[0051] Further, in the step S3, the injecting of excitation into the to-be-tested FPGA according to each physical test case and the collecting of output information corresponding to each physical test case comprises:

[0052] S31, setting a constraint condition, and injecting excitation into the bus and non-bus of the to-be-tested FPGA according to each physical test case based on the constraint condition;

[0053] S32, setting a breakpoint or CPU software plug-in for the CPU software of the to-be-tested FPGA using a debugger, reading and writing to obtain register values by serial printing, collecting register values output by a PC terminal or waveforms output by an oscilloscope after the register values are transformed.

[0054] Further, in the step S32, the output information includes waveforms displayed by an oscilloscope, debugger output data displayed by a PC terminal, and values of serial printed registers displayed by a PC terminal.

[0055] Further, in the step S31, the constraint condition is that a program of the FPGA source program cannot be modified.

[0056] Further, in the step S4, one way of judging whether the to-be-tested FPGA passes the physical test according to all the output information is:

[0057] S41, judging each piece of the output information, if each piece of the output information can completely cover the physical test requirement corresponding thereto, judging that the to-be-tested FPGA passes the test, and if any piece of the output information cannot completely cover the physical test requirement corresponding thereto, judging that the to-be-tested FPGA does not pass the test. In the specific implementation, for each verification point of each physical test requirement, it is a segmented test of the requirement description. For example, when the current physical test requirement includes three segments of implementation of a pre-enable, function of a current register, and output data, according to the differences of the description contents of each segment, a verification personnel who designs the physical test case divides them into three verification points, which are tests of the pre-enable signal, the current register function, and the output signal, respectively.

[0058] Further, in the step S4, another way of judging whether the to-be-tested FPGA passes the physical test according to all the output information is:

[0059] S42, transforming the output information of each of the physical test requirements to obtain data strongly related to the physical test requirement, and judging whether the to-be-tested FPGA passes the test according to the data, specifically, the strongly related data obtained by transformation can be confirmed according to the excitation injected at each time of physical test, and the data of FPGA configuration and pin output, to judge whether the to-be-tested FPGA passes the test, when the strongly related data obtained is consistent with the excitation injected, and the data of FPGA configuration and pin output, it is indicated that the corresponding physical test requirement passes the test, if it is not consistent, the physical test requirement does not pass the test, and then the result of whether the to-be-tested FPGA passes the test can be obtained.

[0060] Based on the same inventive concept, the embodiment of the present application also provides a dynamic physical test system of programmable logic device, as described in the following embodiment. Since the principle of solving problems of the dynamic physical test system is similar to the dynamic physical test method of programmable logic device in the above embodiment, the implementation of the dynamic physical test system can be referred to the implementation of the above dynamic physical test method, and the repeated parts will not be described again. The term "unit" or "module" used below can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiment is preferably implemented in software, hardware, or a combination of software and hardware is also possible and is conceived.

[0061] Figure 2 is a structural block diagram of the dynamic physical test system of programmable logic device of the embodiment of the present application, as Figure 2 shown, the dynamic physical test system includes an information extraction module 201, a use case development module 202, a test and output module 203 and a judgment module 204, and the structure will be described below.

[0062] The information extraction module 201 is used to obtain the physical test requirements of programmable logic of to-be-tested FPGA, FPGA source program, control module circuit diagram, interface control file and electronic component file.

[0063] The use case development module 202 is used to develop a plurality of physical test cases according to the physical test requirements, the FPGA source program, the control module circuit diagram, the interface control file and the electronic component file.

[0064] The test and output module 203 is used to inject excitation into the to-be-tested FPGA according to each of the physical test cases, and collect output information corresponding to each of the physical test cases.

[0065] The judgment module 204 is used to judge whether the to-be-tested FPGA passes the physical test according to all the output information.

[0066] The embodiment of the present application realizes the following technical effects: the dynamic physical test method of the programmable logic device greatly improves the fault tolerance of the programmable logic device of the aviation acquisition equipment, stably improves the use quality of the product, and can improve the testability, easy operability and coverage of the programmable logic device during testing.

[0067] In the embodiment, a computer device is provided, which comprises a memory 301, a processor 302, and a computer program stored in the memory and executable on the processor, and the processor implements the dynamic physical test method of the programmable logic device according to any of the above embodiments when executing the computer program. Figure 3 As shown in the figure, the computer device comprises a memory 301, a processor 302, and a computer program stored in the memory and executable on the processor, and the processor implements the dynamic physical test method of the programmable logic device according to any of the above embodiments when executing the computer program.

[0068] Specifically, the computer device can be a computer terminal, a server or a similar computing device.

[0069] In the embodiment, a computer readable storage medium is provided, which stores a computer program for executing the dynamic physical test method of the programmable logic device according to any of the above embodiments.

[0070] Specifically, the computer readable storage medium includes permanent and non-permanent, removable and non-removable media, which can be realized by any method or technology to store information. The information can be computer readable instructions, data structures, program modules or other data. Examples of computer readable storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tape, magnetic tape disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. According to the definition in this paper, computer readable storage media does not include transitory media, such as modulated data signals and carriers.

[0071] Obviously, those skilled in the art should understand that each module or each step of the above-mentioned embodiments of the present application can be realized by a general computing device, which can be centralized on a single computing device or distributed on a network composed of multiple computing devices, and optionally, each module or each step can be realized by program codes executable by a computing device, so that each module or each step can be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described can be executed in different orders, or each module can be manufactured as an individual integrated circuit module, or multiple modules or steps can be manufactured as a single integrated circuit module. Therefore, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0072] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. The embodiments of the present application can be variously changed and modified by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of dynamic physical testing of a programmable logic device, comprising: The method comprises the following steps: S1, obtaining physical test requirements of programmable logic of a to-be-tested FPGA, an FPGA source program, a control module circuit diagram, an interface control file and an electronic component file; S2, developing a plurality of physical test cases according to the physical test requirements, the FPGA source program, the control module circuit diagram, the interface control file and the electronic component file, comprising: S21, judging a test attribute of each of the physical test requirements through the control module circuit diagram and the electronic component file, the test attribute comprising direct testability and non-direct testability; S22, setting external connection pins according to the control module circuit diagram, the electronic component file and the interface control file to develop a first physical test case corresponding to each of the physical test requirements with direct testability; S23, developing a second physical test case corresponding to each of the physical test requirements with non-direct testability according to the interface control file and the FPGA source program through physical testing and manual analysis methods; S3, injecting excitation into a bus and a non-bus of the to-be-tested FPGA according to each of the physical test cases based on a constraint condition that a program of the FPGA source program is not changeable, and collecting output information corresponding to each of the physical test cases; S4, judging whether the to-be-tested FPGA passes the physical test according to all of the output information.

2. The method of claim 1, wherein the programmable logic device is a field programmable gate array (FPGA). The developing of the second physical test case corresponding to each of the physical test requirements with non-direct testability according to the interface control file and the FPGA source program through physical testing and manual analysis methods comprises: S231, selecting information of a register related to each of the physical test requirements with non-direct testability in the interface control file to develop an initial physical test case; S232, developing the initial physical test case again through manual analysis of the FPGA source program to obtain the second physical test case of each of the physical test requirements with non-direct testability.

3. The method of claim 1, wherein the programmable logic device is a field programmable gate array (FPGA). The collecting of the output information corresponding to each of the physical test cases comprises: setting a breakpoint for CPU software of the to-be-tested FPGA or inserting CPU software by using a debugger, reading and writing register values by using serial printing, collecting register values output by a PC terminal or collecting waveforms output by an oscilloscope after the register values are transformed.

4. The method of claim 3, wherein the programmable logic device is a field programmable gate array (FPGA). The output information comprises waveforms displayed by the oscilloscope, debugger output data displayed by the PC terminal and values of the serial printed registers displayed by the PC terminal.

5. The method of claim 1, wherein the programmable logic device is a field programmable gate array (FPGA). The judging of whether the to-be-tested FPGA passes the physical test according to all of the output information comprises: S41, judging each of the output information, if each of the output information can completely cover the physical test requirement corresponding thereto, judging that the to-be-tested FPGA passes the test, and if any of the output information cannot completely cover the physical test requirement corresponding thereto, judging that the to-be-tested FPGA does not pass the test; Or, S42, the output information of each of the physical test requirements is converted to obtain data strongly related to the physical test requirements, and whether the FPGA to be tested passes the test is determined according to the data.

6. A dynamic physical test system for programmable logic devices, characterized by A dynamic physical test method for implementing any one of claims 1 to 5, comprising: an information extraction module configured to obtain physical test requirements of programmable logic of the FPGA to be tested, an FPGA source program, a control module circuit diagram, an interface control file, and an electronic component file; a use case development module configured to develop a plurality of physical test use cases according to the physical test requirements, the FPGA source program, the control module circuit diagram, the interface control file, and the electronic component file; a test and output module configured to inject excitation into the FPGA to be tested according to each of the physical test use cases, and collect output information corresponding to each of the physical test use cases; a judgment module configured to determine whether the FPGA to be tested passes the physical test according to all of the output information.

7. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor implements the dynamic physical test method of the programmable logic device according to any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program for implementing the dynamic physical test method of the programmable logic device according to any one of claims 1 to 5.

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