Multi-mode compatible zq calibration circuit in memory device

Abstract

In certain aspects, a circuit for multi-mode calibration can include a resistor input. The circuit can also include a first comparator connected to the resistor input and to a first plurality of voltage sources. The circuit can additionally include a first pull-up driver. The circuit can also include a logic pull-up code generator to calibrate the first pull-up driver. The circuit can additionally include a copy of the first pull-up driver. The circuit can also include a first pull-down driver and a second comparator connected to the copy, the first pull-down driver, and a second plurality of voltage sources. The second comparator can compare a voltage of a midpoint between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources. The circuit can also include a logic pull-down code generator.

Description

[0001] This application is a divisional of the patent application with the application date of March 24, 2021, the name of “Multi-mode compatible ZQ calibration circuit in a memory device”, and the application number of 202180000929.2. BACKGROUND

[0002] The present disclosure relates to a memory device and a calibration method thereof.

[0003] Flash memory is a low-cost, high-density, non-volatile, solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory or NAND flash memory named after NOR logic gates and NAND logic gates.

[0004] NAND flash memory can operate its data bus at double data rate (DDR), transferring data on both the rising and falling edges of a clock signal, which is also known as toggle mode. Various versions of DDR standards (e.g., DDR2, DDR3, DDR4, etc.) have been introduced to achieve higher bus speeds and lower power. SUMMARY

[0005] In one aspect, a circuit for multi-mode calibration can include a resistor input configured to be connected to an external resistor. The circuit can further include a first comparator connected to the resistor input and to a first plurality of voltage sources. The circuit can further include a first pull-up driver configured to compare with the external resistor using the first comparator. The first comparator can be configured to use one of the first plurality of voltage sources in the comparison. The circuit can further include a logic pull-up code generator configured to calibrate the first pull-up driver based on the first comparator. The circuit can additionally include a second pull-up driver. The second pull-up driver can be configured as a copy of the first pull-up driver and capable of being calibrated by the same calibration as the first pull-up driver. The circuit can further include a first pull-down driver and a second comparator connected to the second pull-up driver, the first pull-down driver, and a second plurality of voltage sources. The second comparator can be configured to compare a voltage of a midpoint between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources. The circuit can further include a logic pull-down code generator configured to calibrate the first pull-down driver based on the second comparator.

[0006] In another aspect, a circuit for multi-mode calibration can include a first comparator connected to a first plurality of voltage sources. The circuit can also include a first pull-up driver configured to compare with an external resistor using the first comparator. The first comparator can be configured to use one of the first plurality of voltage sources in the comparison. The circuit can also include a second pull-up driver. The second pull-up driver can be configured as a copy of the first pull-up driver and capable of being calibrated by the same calibration as the first pull-up driver. The circuit can additionally include a first pull-down driver. The circuit can also include a second comparator connected to the second pull-up driver, the first pull-down driver, and a second plurality of voltage sources. The second comparator can be configured to compare a voltage of a midpoint between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources.

[0007] In yet another aspect, a system can include a storage device configured to store data and a storage controller coupled to the storage device and configured to control the storage device. The storage device includes a NAND storage array and a peripheral circuit coupled to the NAND storage array and including a circuit for multi-mode calibration. The circuit for multi-mode calibration can include a first comparator connected to a first plurality of voltage sources. The circuit can also include a first pull-up driver configured to compare with an external resistor using the first comparator. The first comparator can be configured to use one of the first plurality of voltage sources in the comparison. The circuit can also include a second pull-up driver. The second pull-up driver can be configured as a copy of the first pull-up driver and capable of being calibrated by the same calibration as the first pull-up driver. The circuit can additionally include a first pull-down driver. The circuit can also include a second comparator connected to the second pull-up driver, the first pull-down driver, and a second plurality of voltage sources. The second comparator can be configured to compare a voltage of a midpoint between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources.

[0008] In yet another aspect, a calibration method can include calibrating a first pull-up driver and a copy of the first pull-up driver based on a comparison with an external resistor. The calibration of the first pull-up driver can be performed using a first comparator according to a first standard. The method can also include calibrating a first pull-down driver based on a comparison with the copy of the first pull-up driver. The calibration of the first pull-down driver can be performed using a second comparator according to the first standard. The method can also include calibrating a second pull-up driver and a copy of the second pull-up driver using the first comparator according to a second standard. The method can additionally include calibrating a second pull-down driver based on a comparison with the copy of the second pull-up driver using the second comparator according to the second standard.

[0009] In yet another aspect, a memory device includes a NAND memory array and a peripheral circuit coupled to the NAND memory array and including circuitry for multi-mode calibration. The circuitry for multi-mode ZQ calibration can include a resistor input configured to be connected to an external resistor. The circuitry for multi-mode ZQ calibration can also include a first comparator connected to the resistor input and to a first plurality of voltage sources. The circuitry for multi-mode calibration can also include a first pull-up driver configured to compare to the external resistor using the first comparator. The first comparator can be configured to use one of the first plurality of voltage sources in the comparison. The circuitry for multi-mode calibration can additionally include a logic pull-up code generator configured to calibrate the first pull-up driver based on the first comparator. The circuitry for multi-mode calibration can also include a second pull-up driver. The second pull-up driver can be configured as a copy of the first pull-up driver and capable of being calibrated by the same calibration as the first pull-up driver. The circuitry for multi-mode calibration can also include a first pull-down driver. The circuitry for multi-mode calibration can additionally include a second comparator connected to the second pull-up driver, the first pull-down driver, and a second plurality of voltage sources, the second comparator configured to compare a voltage of a midpoint between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources. The circuitry for multi-mode calibration can also include a logic pull-down code generator configured to calibrate the first pull-down driver based on the second comparator. BRIEF DESCRIPTION OF DRAWINGS

[0010] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the relevant art to make and use the present disclosure.

[0011] Figure 1 A third generation double data rate (DDR3) two-step calibration is shown.

[0012] Figure 2A A fourth generation low power double data rate (LPDDR4) two-step calibration is shown.

[0013] Figure 2B A second step of the LPDDR4 two-step calibration is shown.

[0014] Figure 3 A block diagram of an exemplary NAND flash memory device in accordance with some aspects of the present disclosure is shown.

[0015] Figure 4 Circuitry for multi-mode calibration in accordance with some aspects of the present disclosure is shown.

[0016] Figure 5A block diagram of an exemplary system with a memory device is shown in accordance with some aspects of the present disclosure.

[0017] Figure 6A A diagram of an exemplary memory card with a memory device is shown in accordance with some aspects of the present disclosure.

[0018] Figure 6B A diagram of an exemplary solid state drive (SSD) with a memory device is shown in accordance with some aspects of the present disclosure.

[0019] Figure 7 A flow diagram of an exemplary calibration method is shown in accordance with some aspects of the present disclosure.

[0020] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0021] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Moreover, the present disclosure can also be employed in a variety of other applications. The functional and structural features described in the present disclosure can be combined, adjusted, and modified, both separately and in various combinations, and can be combined, adjusted, and modified in ways not specifically described in the figures, so that the combinations, adjustments, and modifications are within the scope of the present disclosure.

[0022] In general, the terminology can be understood at least in part based on a usage in the context of the present disclosure. For example, the term“one or more” as used herein, depending at least in part upon a context, can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe combinations of features, structures, or characteristics in a plural sense. Similarly, terms, such as“a” or“the,” again, depending at least in part upon a context, can be understood either to refer to a singular feature or feature of combination, or alternatively, to

[0023] Data pins in a bidirectional bus can be labeled DQ, and a strobe pin can be labeled DQS. As input / output (IO) speeds increase, NAND flash memory is adopting a fourth generation low power double data rate (LPDDR4) IO standard to reduce power consumption in DQ / DQS output buffers. During a transition from a third generation double data rate (DDR3) to the LPDDR4 standard, NAND memory devices including their ZQ calibration circuitry can have to be backward compatible with older DDR3 controllers. ZQ calibration changes the value of an on-chip pull-up resistor and a pull-down resistor connected to a Vccq / 2 pin (also known as a ZQ pin).

[0024] For example, Figure 1 A third generation double data rate (DDR3) two-step calibration is shown. DDR3 type ZQ circuits in NAND flash memory typically take a two-step calibration. In the first step, pull-up driver 10 is calibrated with reference to external reference resistor 12 applied to resistor input 14. Pull-up driver 10 is shown calibrated to 300Ω. External reference resistor 12 is a 300Ω resistor. This calibration is performed by logic pull-up code generator 16 based on a comparison made with first comparator 18. In the second step, pull-down driver 20 is calibrated with reference to a copy 22 of pull-up driver 10 calibrated in the first step. Pull-down driver 20 and copy 22 are shown calibrated to 300Ω. This calibration is performed by logic pull-down code generator 26 based on a comparison made with second comparator 24. The reference voltage for each of first comparator 18 and second comparator 24 for this calibration is one-half of the supply voltage, i.e., Vccq / 2.

[0025] A ZQ calibration circuit for a new generation of NAND flash memory can also have to support LPDDR4 mode. As with DDR3, LPDDR4 type ZQ calibration also performs calibration in two steps. For example, Figure 2A A first step of LPDDR4 two-step calibration is shown, while Figure 2B A second step of LPDDR4 two-step calibration is shown.

[0026] As shown in Figure 2A In the first step, pull-down driver 28 is calibrated with reference to external reference resistor 30, which is shown as a 240Ω resistor connected between Vccq and pull-down driver 28. Pull-down driver 28 can be controlled according to a variable strength control having a strength N, where N can range from a maximum of 1 to a minimum of 0. The strength control can be performed by circuitry not shown. Calibration for the strength control of pull-down driver 28 can be based on a comparison with reference voltage Vccq / 2 using first comparator 32.

[0027] As shown in Figure 2B In the second step, pull-up driver 31 is calibrated with reference to a copy 33 of pull-down driver 28 (see Figure 2A ) calibrated in the first step. For example, a strength control can be applied until the midpoint of pull-up driver 31 and pull-down driver 33 reaches a voltage level close to Vohtarget used as the reference voltage in second comparator 34.

[0028] As an example, the replica 33 can be calibrated to 60 Ω or 120 Ω. For example, calibrated N-type metal-oxide-semiconductor (NMOS) power delivery (PD) control and on-die termination (ODT) information can be used to calibrate the replica 33. The replica 33 can be connected between the source voltage Vssq and the pull-up driver 31.

[0029] However, current ZQ calibration circuits support either the DDR3 standard or the LPDDR4 standard, but not both. During the transition from the DDR3 standard to the LPDDR4 standard, NAND memory devices including their ZQ calibration circuits can have to be backward compatible with older DDR3 controllers. To address the foregoing issues, certain aspects of the present disclosure introduce efficient ZQ calibration circuits in NAND flash memory that are compatible with both the DDR3 standard and the LPDDR4 standard.

[0030] Figure 3 An exemplary NAND flash memory 300 that is compatible with both the DDR3 standard and the LPDDR4 standard in accordance with some aspects of the present disclosure is shown. As Figure 3 As shown in FIG. 3, the NAND flash memory 300 (e.g., a three-dimensional (3D) NAND memory) can include a NAND storage array 301 that includes an array of NAND storage cells in the form of NAND storage strings. The NAND flash memory 300 can also include peripheral circuitry configured to facilitate the operation of the NAND storage cells, such as reading, programming, and erasing. The peripheral circuitry can include, for example, a page buffer 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, registers 314, an interface 316, and a data bus 318. It should be appreciated that other peripheral circuitry can also be included in some examples. As described in detail below, a ZQ calibration circuit that is compatible with both the DDR3 standard and the LPDDR4 standard can be implemented in any suitable component of the NAND flash memory 300, such as the interface 316 and / or the data bus 318.

[0031] The page buffer 304 can be configured to read data from and program data to the NAND memory array 301 under the control of the control logic unit 312. In one example, the page buffer 304 can store a page of program data (write data) to be programmed into one page of the NAND memory array 301. In another example, the page buffer 304 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells coupled to a selected word line. The row decoder / word line driver 308 can be configured to be controlled by the control logic unit 312 and select a block of the NAND memory array 301 and a word line of the selected block. The row decoder / word line driver 308 can also be configured to drive the selected word line using a word line voltage generated by the voltage generator 310. The voltage generator 310 can be configured to be controlled by the control logic unit 312 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, and verify voltages) to be provided to the NAND memory array 301. The column decoder / bit line driver 306 can be configured to be controlled by the control logic unit 312 and select one or more NAND memory strings by applying a bit line voltage generated by the voltage generator 310. For example, the column decoder / bit line driver 306 can apply a column signal for selecting a set of N-bit data from the page buffer 304 to be output in a read operation.

[0032] The control logic unit 312 can be coupled to each of the peripheral circuits and configured to control the operation of the peripheral circuits. The registers 314 can be coupled to the control logic unit 312 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each of the peripheral circuits.

[0033] The interface 316 can be coupled to the control logic unit 312 and act as a control buffer to buffer and forward control commands received from a host (not shown) to the control logic unit 312 and to buffer and forward status information received from the control logic unit 312 to the host. The interface 316 can also be coupled to the page buffer 304 via the column decoder / bit line driver 306 and act as an IO interface and data buffer to buffer and forward program data received from the host (not shown) to the page buffer 304 and to buffer and forward read data from the page buffer 304 to the host. As shown in FIG. 3, the bidirectional data bus 318 can connect the interface 316 and the column decoder / bit line driver 306 to transfer data to and from the NAND memory array 301. Figure 3 As shown in FIG. 3, the bidirectional data bus 318 can connect the interface 316 and the column decoder / bit line driver 306 to transfer data to and from the NAND memory array 301. Figure 4The calibration can be provided to pull-up drivers and pull-down drivers associated with the data bus 318 and / or the interface 316. The multi-mode calibration circuit can also be used to calibrate other drivers, which uses are provided by way of example and illustration only, and not by way of limitation.

[0034] Figure 4 An exemplary circuit for multi-mode calibration is shown in accordance with certain aspects of the disclosure. Figure 4 The circuit shown in FIG. 1 can be used in conjunction with Figure 3 Some components shown in FIG. 1 (e.g., the interface 316 and / or the data bus 318) can be used in conjunction with Figure 4 A combined ZQ calibration circuit is shown that is compatible with both the DDR3 standard and the LPDDR4 standard. In this case, the two comparators, the first comparator 112 and the second comparator 116, can be shared between the DDR3 mode and the LPDDR4 mode, which can save silicon area. In the DDR3 mode, an external 300Ω reference resistor 111a can be used for the circuit, thereby being compatible with the DDR3 standard ZQ calibration.

[0035] In the DDR3 mode, the pull-up drivers 114 can first be calibrated with reference to the external 300Ω reference resistor 111a connected to ground. The ZQ pad voltage can be fed to the first comparator 112. The output of the first comparator 112 can be sent to the logic circuit for closed loop calibration, i.e., the logic pull-up (PU) code generator 115. In the DDR3 mode, after the pull-up drivers 114 are calibrated, the resulting pull-up code can be sent to the pull-up drivers 118, which can be a copy of the DDR3 pull-up drivers 114, to calibrate the DDR3 pull-down drivers 120 with reference to the pull-up drivers 118. The voltage at the midpoint between the copy of the DDR3 pull-up drivers (i.e., the pull-up drivers 118) and the DDR3 pull-down drivers 120 under calibration can be fed to the second comparator 116. The output of the second comparator 116 can be sent to the logic circuit for closed loop calibration, i.e., the logic pull-down (PD) code generator 125.

[0036] In the LPDDR4 mode, an external 300Ω reference resistor 111b can be used for the circuit, thereby being compatible with the LPDDR4 standard ZQ calibration. In the LPDDR4 mode, the pull-down driver set (e.g., the pull-down drivers 134 and the pull-down drivers 136) can first be calibrated with reference to the external 300Ω reference resistor 111b. The ZQ pad voltage can be fed to the first comparator 112. The output of the first comparator 112 is sent to the logic circuit for closed loop calibration, i.e., the logic pull-up code generator 115.

[0037] After the pull-down driver group (e.g., pull-down driver 134 and pull-down driver 136) is calibrated, the generated PD code can be sent to a copy of the LPDDR4 pull-down driver circuit (two 300Ω pull-down drivers in parallel for the case of Voh target = Vccq / 3 (e.g., see pull-down drivers 138 and 140), and one 300Ω pull-down driver for the case of Voh target = Vccq / 2.5 (e.g., see pull-down driver 148)), and the LPDDR4 pull-up driver 142 can be calibrated with reference to the copy of the LPDDR4 pull-down driver circuit. The voltage at the midpoint between the copy of the LPDDR4 pull-down driver and the calibrated LPDDR4 pull-up driver 142 can be fed to a second comparator 116. The output of the second comparator 116 is sent to logic circuitry for closed-loop calibration (e.g., logic pull-up code generator 115).

[0038] In DDR4 mode, with VOH target = Vccq / 3, two 300Ω pull-down drivers connected in parallel (e.g., see pull-down drivers 134 and 136) can form a pull-down driver group, thereby achieving more accurate pull-down and pull-up driver Ron calibration when Voh target = Vccq / 3. In DDR4 mode, with Voh target = Vccq / 3, LPDDR4 pull-up driver 142 can be calibrated to 300Ω, thus achieving full compatibility with the LPDDR4 standard. In DDR4 mode, with Voh target = Vccq / 2.5, a 300Ω pull-down driver and a 600Ω pull-down driver connected in parallel (see pull-down driver 146 and pull-down driver 144, respectively) form a pull-down driver group to achieve more accurate pull-down driver Ron calibration. However, in pull-up driver calibration, only a single 300Ω pull-down driver copy can be used. In DDR4 mode, with Voh target = Vccq / 2.5, pull-up driver 142 can be calibrated to 450Ω, thus achieving full compatibility with the LPDDR4 standard.

[0039] Therefore, more specifically, such as Figure 4 As shown, the circuitry for multi-mode calibration may include resistor inputs 110a or 110b configured to be connected to external resistors 111a or 111b (either can be considered a resistor input and the other a second resistor input). Resistor input 110b is paired with external resistor 111b, and resistor input 111a is paired with external resistor input 110a. External resistor 111a can be used for DDR3 mode ZQ calibration or for LPDDR4 mode ZQ calibration. On the other hand, external resistor 111b can be connected to Vccq for LPDDR4 mode calibration.

[0040] The circuit can also include a first comparator 112 connected to the resistor input 110a or 110b (or both) and to a first plurality of voltage sources 113 (labeled Vccq / 2, Vccq / 3, and Vccq / 2.5, respectively). The first plurality of voltage sources 113 can be selected for comparison based on an intended Voh target.

[0041] The first pull-up driver 114 can be configured to compare with the external resistor 111a or the external resistor 111b using the first comparator 112. The first comparator 112 can be configured to use one of the first plurality of voltage sources 113 in the comparison, as explained above. The logic pull-up code generator 115 can be configured to calibrate the first pull-up driver 114 based on the comparison provided by the first comparator 112.

[0042] The circuit can also include a second pull-up driver 118. The second pull-up driver 118 can be configured as a duplicate of the first pull-up driver 114 and can be calibrated by the same calibration as the first pull-up driver 114. For example, the second pull-up driver 118 can be calibrated using the code generated for the first pull-up driver 114, as explained above.

[0043] The circuit can also include a first pull-down driver 120 and a second comparator 116 connected to the second pull-up driver 118, the first pull-down driver 120, and a second plurality of voltage sources 117. The second comparator 116 can be configured to compare the first pull-down driver 120 with the second pull-up driver 118. The second comparator 116 can also be configured to use one of the second plurality of voltage sources 117 for the comparison.

[0044] The circuit additionally includes a logic pull-down code generator 125 configured to calibrate the first pull-down driver 120 based on the second comparator 116. The circuit can also include a third pull-up driver 122 configured to compare with the external resistor 111a or the external resistor 111b using the first comparator 112 and calibrated by the logic pull-up code generator 115.

[0045] The circuit can also include a fourth pull-up driver 124 configured as a duplicate of the third pull-up driver 122 and configured to be calibrated by the same calibration as the third pull-up driver 122. The circuit can also include a second pull-down driver 126. The second pull-down driver 126 can be configured to compare with the fourth pull-up driver 124 using the second comparator 116.

[0046] Additionally, the circuit can include a fifth pull-up driver 128 configured to compare with the external resistor 111a or the external resistor 111b using the first comparator 112 and calibrated by the logic pull-up code generator 115.

[0047] The circuit can further include a sixth pull-up driver 130 configured as a duplicate of the fifth pull-up driver 128 and configured to be calibrated by the same calibration as the fifth pull-up driver 128. In addition, the circuit can include a third pull-down driver 132. The third pull-down driver 132 can be configured to compare with the sixth pull-up driver 130 using the second comparator 116.

[0048] The circuit can further include a fourth pull-down driver 134 and a fifth pull-down driver 136 connected in parallel and configured to compare with the external resistor 111a or the external resistor 111b by the first comparator 112 and configured to be calibrated by the logic pull-down code generator 125.

[0049] The circuit can further include a sixth pull-down driver 138 and a seventh pull-down driver 140 configured as duplicates of the fourth pull-down driver 134 and the fifth pull-down driver 136, respectively, and configured to be calibrated by the same calibration as the fourth pull-down driver 134 and the fifth pull-down driver 136. In addition, the circuit can include a seventh pull-up driver 142 configured to be calibrated by the logic pull-up code generator 115 based on a comparison made by the second comparator 116 with the sixth pull-down driver 138 and the seventh pull-down driver 140 in a first case (e.g., when the Voh target is Vccq / 3).

[0050] The circuit can further include an eighth pull-down driver 144 and a ninth pull-down driver 146 connected in parallel and configured to compare with the external resistor 111a and the external resistor 111b by the first comparator 112 and configured to be calibrated by the logic pull-down code generator 125.

[0051] The circuit can further include a tenth pull-down driver 148 configured as a duplicate of the seventh pull-down driver 140 and configured to be calibrated by the logic pull-down code generator 125.

[0052] In a second case (e.g., when the Voh target is Vccq / 2.5), the seventh pull-up driver 142 can be configured to be calibrated by the logic pull-up code generator 115 based on a comparison made by the second comparator 116 with the tenth pull-down driver 148.

[0053] Figure 4The circuitry can be configured to calibrate according to at least two modes. A first of the at least two modes can be a DDR3 mode, and a second of the at least two modes can be a LPDDR4 mode. The second mode can be calibrated for either a Voh target of Vccq / 3 (the first case mentioned above) or a Voh target of Vccq / 2.5 (the second case mentioned above).

[0054] Various calibrations can be made to the drivers. For example, pull-up drivers 114 and 118 can be calibrated to 300Ω, pull-up drivers 122 and 124 can be calibrated to 600Ω, pull-up drivers 128 and 130 can be calibrated to 450Ω, and pull-up driver 142 can be calibrated to 450Ω or 300Ω.

[0055] Similarly, pull-down drivers 134, 136, 146, 148, 138, 140, 126, 132, and 120 can be calibrated to 300Ω, and pull-down driver 144 can be calibrated to 600Ω.

[0056] Various modifications can be made to the embodiments shown in Figure 4 More generally, in certain embodiments, for LPDDR4 mode ZQ calibration, an external 300Ω resistor can be connected to ground or Vccq for user selection. For DDR3 mode, the external 300Ω resistor can be connected to ground to comply with DDR3 mode ZQ calibration standards. In addition, certain aspects of the disclosure can employ only two comparators, thereby saving silicon area.

[0057] The pull-up drivers can be designed to be calibrated to 300Ω or 450Ω to support more LPDDR4 Ron and ODT combinations. Semi-strength pull-up and pull-down drivers that can be calibrated to 600Ω can be added to support more LPDDR4 Ron and ODT combinations.

[0058] Figure 5 A block diagram of an exemplary system 500 having a memory device in accordance with some aspects of the disclosure is shown. The system 500 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other appropriate electronic device having a memory device therein. As Figure 5As shown in FIG. 5, the system 500 can include a host 508 and a storage system 502 having one or more NAND flash memories 300 and a storage controller 506. The host 508 can be a processor of an electronic device, such as a central processing unit (CPU) or a system on a chip (SoC), such as an application processor (AP). The host 508 can be configured to send or receive data to or from the NAND flash memory 300.

[0059] The NAND flash memory 300, as described above, can include a ZQ calibration circuit that is compatible with both the DDR3 standard and the LPDDR4 standard. The ZQ calibration circuit disclosed herein can be implemented as any suitable component of the peripheral circuit of the NAND flash memory 300, such as the interface 316 and / or the data bus 318.

[0060] According to some embodiments, the storage controller 506 is coupled to the NAND flash memory 300 and the host 508, and is configured to control the NAND flash memory 300. The storage controller 506 can manage data stored in the NAND flash memory 300 and communicate with the host 508. In some embodiments, the storage controller 506 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the storage controller 506 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which are used as data storage devices for mobile devices such as smartphones, tablets, laptops, etc. and enterprise storage arrays. The storage controller 506 can be configured to control operations of the NAND flash memory 300, such as read, erase, and program operations. The storage controller 506 can also be configured to manage various functions related to data stored in or to be stored in the NAND flash memory 300, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the storage controller 506 is also configured to process error correction codes (ECCs) related to data read from or written to the NAND flash memory 300. Any other appropriate functions can also be performed by the storage controller 506, such as formatting the NAND flash memory 300. The storage controller 506 can communicate with external devices (e.g., the host 508) according to a particular communication protocol. For example, the storage controller 506 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0061] The storage controller 506 and the one or more NAND flash memories 300 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the storage system 502 can be implemented and packaged into different types of final electronic products. In the case of a UFS package, the storage system 502 can be implemented and packaged into a mobile device, such as a smartphone, a tablet, a laptop, etc. In the case of an eMMC package, the storage system 502 can be implemented and packaged into a mobile device, such as a smartphone, a tablet, a laptop, etc. Figure 6AIn one example shown, the storage controller 506 and a single NAND flash memory 300 can be integrated into the memory card 602. The memory card 602 can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 602 may also include a connection between the memory card 602 and a host computer (e.g., Figure 5 The memory card connector 604 is coupled to the host 508. In such a... Figure 6B In another example shown, the storage controller 506 and multiple NAND flash memory units 300 can be integrated into the SSD 606. The SSD 606 may also include components for connecting the SSD 606 to a host computer (e.g., Figure 5 The SSD connector 608 is coupled to the host 508 in the memory card 602. In some embodiments, the storage capacity and / or operating speed of the SSD 606 is higher than that of the memory card 602.

[0062] Figure 7 A flowchart illustrating an exemplary calibration method according to some aspects of this disclosure is shown. Certain embodiments may allow the same comparator to be reused for multiple standards. As mentioned above, these multiple standards may depend on different measurements and combinations of pull-up and pull-down drivers. In the examples below, one pull-up driver and one pull-down driver are calibrated according to each standard, but many such drivers can be calibrated, wherein... Figure 4 Several options are shown.

[0063] like Figure 7 As shown, the method may include calibrating a first pull-up driver and a copy of the first pull-up driver at 710 based on a comparison with an external resistor. The calibration of the first pull-up driver at 710 may be performed using a first comparator according to a first standard. The method may also include calibrating a first pull-down driver at 720 based on a comparison with a copy of the first pull-up driver. The calibration of the first pull-down driver at 720 may be performed using a second comparator according to the first standard. The method may also include calibrating a second pull-up driver and a copy of the second pull-up driver at 730 using the first comparator according to a second standard. The method may additionally include calibrating a second pull-down driver at 740 using the second comparator according to a second standard based on a comparison with a copy of the second pull-up driver. The first standard may be DDR3, and the second standard may be LPDDR4. This method can be similarly extended to reference [reference / ... Figure 4 Each of the described standards, wherein the calibrations shown are provided as examples only. Modifications to the calibration methods and associated devices are permitted.

[0064] According to one aspect of the disclosure, a circuit for multi-mode calibration can include a resistor input configured to connect to an external resistor. The circuit can also include a first comparator connected to the resistor input and to a first plurality of voltage sources. The circuit can also include a first pull-up driver configured to compare to the external resistor using the first comparator. The first comparator can be configured to use one of the first plurality of voltage sources in the comparison. The circuit can also include a logic pull-up code generator configured to calibrate the first pull-up driver based on the first comparator. The circuit can additionally include a second pull-up driver. The second pull-up driver can be configured as a copy of the first pull-up driver and capable of being calibrated by the same calibration as the first pull-up driver. The circuit can also include a first pull-down driver and a second comparator connected to the second pull-up driver, the first pull-down driver, and a second plurality of voltage sources. The second comparator can be configured to compare a voltage of a midpoint between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources. The circuit can also include a logic pull-down code generator configured to calibrate the first pull-down driver based on the second comparator.

[0065] In some embodiments, the circuit can also include a third pull-up driver configured to compare to the external resistor using the first comparator and calibrated by the logic pull-up code generator.

[0066] In some embodiments, the circuit can also include a fourth pull-up driver configured as a copy of the third pull-up driver and configured to be calibrated by the same calibration as the third pull-up driver.

[0067] In some embodiments, the circuit can also include a second pull-down driver. The second pull-down driver can be configured to compare to the fourth pull-up driver using the second comparator.

[0068] In some embodiments, the circuit can also include a fifth pull-up driver configured to compare to the external resistor using the first comparator and calibrated by the logic pull-up code generator.

[0069] In some embodiments, the circuit can also include a sixth pull-up driver configured as a copy of the fifth pull-up driver and configured to be calibrated by the same calibration as the fifth pull-up driver.

[0070] In some embodiments, the circuit can also include a third pull-down driver. The third pull-down driver can be configured to compare to the sixth pull-up driver using the second comparator.

[0071] In some embodiments, the circuit can further include a fourth pull-down driver and a fifth pull-down driver connected in parallel, configured to compare to the external resistor by the first comparator, and configured to be calibrated by the logic pull-down code generator.

[0072] In some embodiments, the circuit can further include a sixth pull-down driver and a seventh pull-down driver configured as a copy of the fourth pull-down driver and the fifth pull-down driver, respectively, and configured to be calibrated by the same calibration as the fourth pull-down driver and the fifth pull-down driver.

[0073] In some embodiments, the circuit can further include a seventh pull-up driver configured to be calibrated by the logic pull-up code generator based on a comparison made by the second comparator to the sixth pull-down driver and the seventh pull-down driver in the first case.

[0074] In some embodiments, the circuit can further include an eighth pull-down driver and a ninth pull-down driver connected in parallel, configured to compare to the external resistor by the first comparator, and configured to be calibrated by the logic pull-down code generator.

[0075] In some embodiments, the circuit can further include a tenth pull-down driver configured as a copy of the seventh pull-down driver and configured to be calibrated by the logic pull-down code generator.

[0076] In some embodiments, the seventh pull-up driver can be configured to be calibrated by the logic pull-up code generator based on a comparison made by the second comparator to the tenth pull-down driver in the second case.

[0077] In some embodiments, the circuit can be configured to be calibrated according to at least two modes.

[0078] In some embodiments, a first mode of the at least two modes can be a DDR3 mode.

[0079] In some embodiments, a second mode of the at least two modes can be a LPDDR4 mode.

[0080] In some embodiments, the second mode can be calibrated for a Voh target of Vccq / 3.

[0081] In some embodiments, the second mode can be calibrated for a Voh target of Vccq / 2.5.

[0082] In some embodiments, the external resistor can be connected to ground.

[0083] In some embodiments, the external resistor can be connected to Vccq.

[0084] According to another aspect of the disclosure, a circuit for multi-mode calibration can include a first comparator connected to a first plurality of voltage sources. The circuit can also include a first pull-up driver configured to compare with an external resistor using the first comparator. The first comparator can be configured to use one of the first plurality of voltage sources in the comparison. The circuit can also include a second pull-up driver. The second pull-up driver can be configured as a copy of the first pull-up driver and capable of being calibrated by the same calibration as the first pull-up driver. The circuit can additionally include a first pull-down driver. The circuit can also include a second comparator connected to the second pull-up driver, the first pull-down driver, and a second plurality of voltage sources. The second comparator can be configured to compare a voltage of a midpoint between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources.

[0085] In some embodiments, the circuit can also include a logic pull-up code generator configured to calibrate the first pull-up driver and the second pull-up driver based on the comparison by the first comparator.

[0086] In some embodiments, the circuit can also include a logic pull-down code generator configured to calibrate the first pull-down driver based on the comparison by the second comparator.

[0087] According to yet another aspect of the disclosure, a system can include a memory device configured to store data and a storage controller coupled to the memory device and configured to control the memory device. The memory device includes a NAND memory array and a peripheral circuit coupled to the NAND memory array and including a circuit for multi-mode calibration. The circuit for multi-mode calibration can include a first comparator connected to a first plurality of voltage sources. The circuit can also include a first pull-up driver configured to compare with an external resistor using the first comparator. The first comparator can be configured to use one of the first plurality of voltage sources in the comparison. The circuit can also include a second pull-up driver. The second pull-up driver can be configured as a copy of the first pull-up driver and capable of being calibrated by the same calibration as the first pull-up driver. The circuit can additionally include a first pull-down driver. The circuit can also include a second comparator connected to the second pull-up driver, the first pull-down driver, and a second plurality of voltage sources. The second comparator can be configured to compare a voltage of a midpoint between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources.

[0088] In some embodiments, the system can also include a host coupled to the storage controller and configured to send or receive data.

[0089] In some embodiments, the memory device includes a 3D NAND memory.

[0090] According to yet another aspect of the disclosure, a calibration method can include calibrating a first pull-up driver and a copy of the first pull-up driver based on a comparison with an external resistor. The calibration of the first pull-up driver can be performed according to a first standard using a first comparator. The method can further include calibrating a first pull-down driver based on a comparison with the copy of the first pull-up driver. The calibration of the first pull-down driver can be performed according to the first standard using a second comparator. The method can further include calibrating a second pull-up driver and a copy of the second pull-up driver according to a second standard using the first comparator. The method can additionally include calibrating a second pull-down driver based on a comparison with the copy of the second pull-up driver according to the second standard using the second comparator.

[0091] In some implementations, the first standard can be DDR3 and the second standard can be LPDDR4.

[0092] According to yet another aspect of the disclosure, a memory device includes a NAND memory array and a peripheral circuit coupled to the NAND memory array and including circuitry for multi-mode calibration. The circuitry for multi-mode ZQ calibration can include a resistor input configured to be connected to an external resistor. The circuitry for multi-mode ZQ calibration can further include a first comparator connected to the resistor input and to a first plurality of voltage sources. The circuitry for multi-mode calibration can further include a first pull-up driver configured to compare with the external resistor using the first comparator. The first comparator can be configured to use one of the first plurality of voltage sources in the comparison. The circuitry for multi-mode calibration can additionally include a logic pull-up code generator configured to calibrate the first pull-up driver based on the first comparator. The circuitry for multi-mode calibration can further include a second pull-up driver. The second pull-up driver can be configured as a copy of the first pull-up driver and capable of being calibrated by the same calibration as the first pull-up driver. The circuitry for multi-mode calibration can further include a first pull-down driver. The circuitry for multi-mode calibration can additionally include a second comparator connected to the second pull-up driver, the first pull-down driver, and a second plurality of voltage sources, the second comparator configured to compare a voltage of a midpoint between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources. The circuitry for multi-mode calibration can further include a logic pull-down code generator configured to calibrate the first pull-down driver based on the second comparator.

[0093] In some implementations, the circuitry for multi-mode ZQ calibration can further include a third pull-up driver configured to compare with the external resistor using the first comparator and to be calibrated by the logic pull-up code generator.

[0094] In some implementations, the circuit for multi-mode ZQ calibration can further include a fourth pull-up driver configured as a copy of the third pull-up driver and configured to be calibrated by the same calibration as the third pull-up driver.

[0095] In some implementations, the circuit for multi-mode ZQ calibration can further include a second pull-down driver. The second pull-down driver can be configured to compare with the fourth pull-up driver using the second comparator.

[0096] In some implementations, the circuit for multi-mode ZQ calibration can further include a fifth pull-up driver configured to compare with an external resistor using the first comparator and calibrated by the logic pull-up code generator.

[0097] In some implementations, the circuit for multi-mode ZQ calibration can further include a sixth pull-up driver configured as a copy of the fifth pull-up driver and configured to be calibrated by the same calibration as the fifth pull-up driver.

[0098] In some implementations, the circuit for multi-mode ZQ calibration can further include a third pull-down driver. The third pull-down driver can be configured to compare with the sixth pull-up driver using the second comparator.

[0099] In some implementations, the circuit for multi-mode ZQ calibration can further include a fourth pull-down driver and a fifth pull-down driver connected in parallel, configured to compare with the external resistor through the first comparator, and configured to be calibrated by the logic pull-down code generator.

[0100] In some implementations, the circuit for multi-mode ZQ calibration can further include a sixth pull-down driver and a seventh pull-down driver configured as copies of the fourth pull-down driver and the fifth pull-down driver, respectively, and configured to be calibrated by the same calibration as the fourth pull-down driver and the fifth pull-down driver.

[0101] In some implementations, the circuit for multi-mode ZQ calibration can further include a seventh pull-up driver configured to be calibrated by the logic pull-up code generator based on a comparison made by the second comparator with the sixth pull-down driver and the seventh pull-down driver in a first case.

[0102] In some implementations, the circuit for multi-mode ZQ calibration can further include an eighth pull-down driver and a ninth pull-down driver connected in parallel, configured to compare with the external resistor through the first comparator, and configured to be calibrated by the logic pull-down code generator.

[0103] In some embodiments, the circuit for multi-mode ZQ calibration can further include a tenth pull-down driver configured as a copy of the seventh pull-down driver and configured to be calibrated by the logic pull-down code generator.

[0104] In some embodiments, in the second case, the seventh pull-up driver can be configured to be calibrated by the logic pull-up code generator based on a comparison with the tenth pull-down driver through the second comparator.

[0105] In some embodiments, the circuit for multi-mode ZQ calibration can be configured to be calibrated according to at least two modes.

[0106] In some embodiments, a first mode of the at least two modes can be a DDR3 mode.

[0107] In some embodiments, a second mode of the at least two modes can be a LPDDR4 mode.

[0108] In some embodiments, the second mode can be calibrated for a Voh target of Vccq / 3.

[0109] In some embodiments, the second mode can be calibrated for a Voh target of Vccq / 2.5.

[0110] In some embodiments, the external resistor can be connected to ground or Vccq.

[0111] The foregoing description of the specific embodiments will be readily appreciated by those skilled in the art through the teachings of the teachings and guidance provided herein. Accordingly, such adaptations and modifications are intended to fall within the meaning and range of equivalents of the disclosed embodiments, based on the teachings and guidance provided herein.

[0112] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined in accordance with the following claims and their equivalents.

Claims

1. A circuit for multi-mode ZQ calibration, comprising: a first resistor input coupled to a first set of pull-up drivers and a first external resistor; a first comparator coupled to the first resistor input and a plurality of selectable voltage sources; a second set of pull-up drivers each coupled to a first set of pull-down drivers at a plurality of first midpoints; a second comparator coupled to the plurality of first midpoints and the plurality of selectable voltage sources; a logic pull-up code generator coupled to the first comparator and the second comparator and configured to calibrate the first set of pull-up drivers and the second set of pull-up drivers; and a logic pull-down code generator coupled to the first comparator and the second comparator and configured to calibrate the first set of pull-down drivers. The circuit is configured to calibrate according to at least two modes.

2. The circuit of claim 1, wherein, A first mode of the at least two modes is a DDR3 mode.

3. The circuit of claim 2, wherein, A second mode of the at least two modes is a LPDDR4 mode.

4. The circuit of claim 2, wherein, The second mode is calibrated for a Voh target of Vccq / 3 or Vccq / 2.

5.

5. The circuit of claim 4, wherein, The first mode is calibrated for a Voh target of Vccq / 2.

6. The circuit of claim 3, wherein, In the second mode, the first comparator is configured to compare a voltage of the first resistor input to one of the plurality of selectable voltage sources; 7. The circuit of claim 4, wherein, and The logic pull-down code generator is configured to receive an output signal from the first comparator and generate a pull-down code to calibrate the first set of pull-down drivers. The first set of pull-up drivers includes a first pull-up driver, the second set of pull-up drivers includes a second pull-up driver, the second pull-up driver is configured as a copy of the first pull-up driver, and the second pull-up driver is calibrated by the same calibration as the first pull-up driver.

8. The circuit of claim 3, wherein, In the first mode, the first comparator is configured to compare a voltage of the first resistor input to a first selectable voltage of the plurality of selectable voltage sources; 9. The circuit of claim 8, wherein, and The logic pull-up code generator is configured to receive an output signal from the first comparator and generate a pull-up code to calibrate the first set of pull-up drivers and the second set of pull-up drivers. A first midpoint of the plurality of first midpoints couples the second pull-up driver and a first pull-down driver of the first set of pull-down drivers, wherein, in the first mode, the second comparator is configured to compare a voltage of the first midpoint to the first selectable voltage; and 10. The circuit of claim 9, wherein, The logic pull-down code generator is configured to receive an output signal from the second comparator and generate a pull-down code to calibrate the first pull-down driver. A third pull-up driver of the second set of pull-up drivers is configured as a copy of a fourth pull-up driver of the first set of pull-up drivers, and the third pull-up driver is calibrated by the same calibration as the fourth pull-up driver; 11. The circuit of claim 4, wherein, ​ wherein, in the second mode, the first comparator is configured to compare a voltage of the first resistor input to a second selectable voltage of the plurality of selectable voltage sources; the logic pull-up code generator is configured to receive an output signal from the first comparator and generate a pull-up code to calibrate a third pull-up driver and a fourth pull-up driver; and a second midpoint of the plurality of first midpoints couples the third pull-up driver and a second pull-down driver of the first set of pull-down drivers, the second comparator is configured to compare a voltage of the second midpoint to the second selectable voltage.

12. The circuit of any of claim 11, wherein, the circuit further comprises: a second set of pull-down drivers and a second external resistance and both coupled to a second resistor input, wherein the second resistor input is coupled to the first comparator, the logic pull-down code generator is configured to calibrate the second set of pull-down drivers.

13. The circuit of claim 12, wherein, the circuit further comprises: a fifth pull-up driver is coupled to a third set of pull-down drivers at a third midpoint of the plurality of first midpoints; wherein the second comparator is coupled to the third midpoint.

14. The circuit of claim 13, wherein, the third set of pull-down drivers is configured to be a copy of the second set of pull-down drivers and calibrated by the same calibration as the second set of pull-down drivers.

15. The circuit of claim 14, wherein, in the LPDDR4 mode, the first comparator is configured to compare a voltage of the second resistor input to the second selectable voltage of the plurality of selectable voltage sources; the logic pull-down code generator is configured to receive an output signal from the first comparator and generate a pull-down code to calibrate the second set of pull-down drivers; the second comparator is configured to compare a voltage of the third midpoint to the second selectable voltage; and the logic pull-up code generator is configured to receive an output signal from the second comparator and generate a pull-up code to calibrate the first set of pull-up drivers and the fifth pull-up driver.

16. The circuit of claim 12, wherein, the first external resistance is connected to ground and the second external resistance is connected to Vccq.

17. A memory, comprising: a memory array and a peripheral circuit coupled to the memory array, the peripheral circuit comprising the circuit for multi-mode ZQ calibration of any of claims 1 to 16.

18. The memory of claim 17, wherein, the memory comprises a three-dimensional (3D) NAND memory.

19. A method for ZQ calibration, comprising: in accordance with a first criterion, the method comprises: comparing, by a first comparator, a first voltage of a first resistor input to a first voltage of a first selectable voltage source; comparing, by a second comparator, a first voltage of a first midpoint to a first voltage of a second selectable voltage source; calibrating, based on a first comparison of the first comparator, a first pull-up driver, wherein the first pull-up driver is connected to the first resistor input; and calibrating, based on a second comparison of the second comparator, a first pull-down driver, wherein the first pull-down driver is connected to the first midpoint; and in accordance with a second criterion different from the first criterion, the method comprises: comparing, by the first comparator, a second voltage of the first resistor input to a second voltage of a first selectable voltage source, wherein the second voltage of the first selectable voltage source is different than the first voltage of the first selectable voltage source; comparing, by the second comparator, a second voltage of a second midpoint to a second voltage of a second selectable voltage source, wherein the second voltage of the second selectable voltage source is different than the first voltage of the second selectable voltage source; calibrating a second pull-up driver based on a third comparison of the first comparator, wherein the second pull-up driver is connected to the first resistor input; and calibrating a second pull-down driver based on a fourth comparison of the second comparator, wherein the second pull-down driver is connected to the second midpoint.

20. The method of claim 19, wherein, According to the first standard, the method further comprises: sending the first comparison of the first comparator to a logic pull-up code generator, wherein the logic pull-up code generator is configured to generate pull-up code to calibrate the first pull-up driver; and sending the second comparison of the second comparator to a logic pull-down code generator, wherein the logic pull-down code generator is configured to generate pull-down code to calibrate the first pull-down driver.

21. The method of claim 20, wherein, comparing, by the second comparator, a first voltage of the first midpoint to the first voltage of the second selectable voltage source after calibrating the first pull-up driver, and comparing, by the second comparator, a second voltage of the second midpoint to the second voltage of the second selectable voltage source after calibrating the second pull-up driver.

22. The method of claim 19, wherein, According to the second standard, the method further comprises: sending the third comparison of the first comparator to a logic pull-up code generator, wherein the logic pull-up code generator is configured to generate pull-up code to calibrate the second pull-up driver; and sending the fourth comparison of the second comparator to a logic pull-down code generator, wherein the logic pull-down code generator is configured to generate pull-down code to calibrate the second pull-down driver.

23. The method of claim 19, wherein, According to the first standard, the method further comprises: calibrating a third pull-up driver during calibration of the first pull-up driver, wherein the third pull-up driver is a copy of the first pull-up driver; wherein the first midpoint connects the third pull-up driver and the first pull-down driver.

24. The method of claim 19, wherein, According to the second standard, the method further comprises: calibrating a fourth pull-up driver during calibration of the second pull-up driver, wherein the fourth pull-up driver is a copy of the second pull-up driver; the second midpoint connects the fourth pull-up driver and the second pull-down driver.

25. The method of claim 19, wherein, the first standard comprises a DDR3 mode and the second standard comprises a LPDDR4 mode.

26. The method of claim 19, wherein, the first voltage of the first selectable voltage source is the same as the first voltage of the second selectable voltage source and the second voltage of the first selectable voltage source is the same as the second voltage of the second selectable voltage source.

27. The method of claim 19, wherein, the first standard calibrates for a Voh target of Vccq / 2 and the second standard calibrates for a Voh target of Vccq / 3 or Vccq / 2.

5.

28. The method of claim 19, wherein, The method further comprises: According to the second standard, the method comprises: comparing, by the first comparator, a first voltage of the second resistor input with a third voltage of the first selectable voltage source; comparing, by the second comparator, a third voltage of the third midpoint with a third voltage of the second selectable voltage source; calibrating a third pull-down driver based on a fifth comparison of the first comparator, wherein the third pull-down driver is connected to the second resistor input; and calibrating a fifth pull-up driver based on a sixth comparison of the second comparator, wherein the fifth pull-up driver is connected to the third midpoint.

29. The method of claim 28, wherein, The first standard comprises a DDR3 mode, and the second standard comprises a LPDDR4 mode.

30. The method of claim 28, wherein, According to the second standard, the method further comprises: calibrating a fourth pull-down driver during calibration of the third pull-down driver, wherein the fourth pull-down driver is a copy of the third pull-down driver, wherein the third midpoint connects the fourth pull-down driver and the fifth pull-up driver.

31. The method of claim 28, wherein, One end of the first resistor input is connected to a first external resistor, and one end of the second resistor input is connected to a second external resistor, the first external resistor is connected to ground, and the second external resistor is connected to Vccq.

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