Heterojunction cell without TCO layer on the front side, preparation method thereof and photovoltaic module

Abstract

The present invention relates to the field of photovoltaic technology, and in particular, to a heterojunction cell without a TCO layer on the front side, a preparation method thereof, and a photovoltaic module; the heterojunction cell comprises a silicon substrate having a first surface and a second surface that are oppositely distributed, a first passivation layer deposited on the first surface, a first doping layer deposited on the side of the first passivation layer away from the silicon substrate, an anti-reflection composite layer deposited on the side of the first doping layer away from the first passivation layer, a second passivation layer deposited on the second surface, a second doping layer deposited on the side of the second passivation layer away from the silicon substrate, a transparent conductive layer deposited on the side of the second doping layer away from the second passivation layer, a first electrode arranged on the anti-reflection composite layer, the first electrode being in contact with the first doping layer, and a second electrode arranged on the transparent conductive layer. The heterojunction cell without a TCO layer on the front side has higher conversion efficiency and fill factor.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a heterojunction battery without a TCO layer on the front side, a preparation method thereof, and a photovoltaic module. Background Art

[0002] Heterojunction solar cell (HJT) is a high-performance photovoltaic cell technology; its main feature is that it uses a combination of different types of semiconductor materials to form a heterojunction structure to improve the photoelectric conversion efficiency and stability of the cell. Moreover, due to its unique double-sided structure and the passivation effect of the intrinsic layer, heterojunction cells have many advantages such as high conversion efficiency, no light-induced degradation, good temperature characteristics, and a short manufacturing process. Therefore, heterojunction cells have great market potential.

[0003] However, the conversion efficiency and fill factor of heterojunction cells provided by related technologies still need to be improved. Summary of the invention

[0004] The object of the present invention is to provide a heterojunction cell without a TCO layer on the front side, a preparation method thereof and a photovoltaic module. The heterojunction cell without a TCO layer on the front side prepared by the preparation method can be used in a photovoltaic module, and the heterojunction cell without a TCO layer on the front side has higher conversion efficiency and fill factor.

[0005] The embodiment of the present invention is achieved as follows:

[0006] In a first aspect, the present invention provides a heterojunction battery without a TCO layer on the front side, comprising:

[0007] The silicon substrate has a first surface and a second surface that are arranged opposite to each other;

[0008] A first passivation layer, the first passivation layer is deposited on the first surface;

[0009] A first doping layer, the first doping layer is deposited on a side of the first passivation layer away from the silicon substrate;

[0010] An anti-reflection composite layer, which is deposited on a side of the first doping layer away from the first passivation layer;

[0011] A second passivation layer, the second passivation layer is deposited on the second surface;

[0012] A second doping layer, the second doping layer is deposited on a side of the second passivation layer away from the silicon substrate;

[0013] A transparent conductive layer, which is deposited on a side of the second doped layer away from the second passivation layer;

[0014] a first electrode, the first electrode being disposed on the anti-reflection recombination layer and contacting the first doping layer; and

[0015] The second electrode is arranged on the transparent conductive layer.

[0016] In an optional embodiment, the anti-reflection composite layer includes a silicon oxide protective layer and an anti-reflection layer, the silicon oxide protective layer is deposited on a side of the first doped layer away from the first passivation layer, and the anti-reflection layer is deposited on a side of the silicon oxide protective layer away from the first doped layer;

[0017] The first electrode is arranged on the anti-reflection layer and passes through the anti-reflection layer to contact the silicon oxide protection layer and the first doping layer.

[0018] In an optional embodiment, the anti-reflection layer includes a first anti-reflection film, a second anti-reflection film and a third anti-reflection film stacked in sequence, wherein the first anti-reflection film is arranged on a side of the silicon oxide protective layer away from the first doping layer.

[0019] In an optional embodiment, the refractive indexes of the first anti-reflection film, the second anti-reflection film and the third anti-reflection film decrease successively, wherein the refractive index of the first anti-reflection film is 2.3~2.8, the refractive index of the second anti-reflection film is 2.1~2.4, and the refractive index of the third anti-reflection film is 1.8~2.2.

[0020] In an optional embodiment, the thickness of the first anti-reflection film is 10-35 nm, the thickness of the second anti-reflection film is 10-35 nm, and the thickness of the third anti-reflection film is 20-55 nm.

[0021] In an optional embodiment, the thicknesses of the first anti-reflection film, the second anti-reflection film, and the third anti-reflection film increase sequentially.

[0022] In an optional embodiment, the thickness of the silicon oxide protective layer is 1-5 nm.

[0023] In an optional embodiment, the thickness of the first doping layer is 20-60 nm, and the thickness of the second doping layer is 15-45 nm.

[0024] In an optional embodiment, the thickness of the first doping layer is greater than the thickness of the second doping layer.

[0025] In an optional embodiment, at least one of the first passivation layer and the second passivation layer has a thickness of 5-15 nm.

[0026] In an optional embodiment, the transparent conductive layer has a thickness of 80-140 nm.

[0027] In an alternative embodiment, the thickness of the silicon substrate is 80-180 μm.

[0028] In an optional embodiment, the first passivation layer includes a first amorphous silicon film layer, a second amorphous silicon film layer and a hydrogenated amorphous silicon passivation film layer stacked in sequence; wherein the first amorphous silicon film layer is deposited on the first surface.

[0029] In an optional embodiment, the first doped layer includes a microcrystalline silicon seed layer and a microcrystalline silicon doped layer stacked in sequence, and the microcrystalline silicon seed layer is deposited on a side of the first passivation layer away from the silicon substrate.

[0030] In an optional embodiment, the microcrystalline silicon doping layer includes at least three sub-doping layers stacked sequentially.

[0031] In a second aspect, the present invention provides a photovoltaic module, comprising a heterojunction cell without a TCO layer on the front side according to any one of the aforementioned embodiments.

[0032] In a third aspect, the present invention provides a method for preparing a heterojunction battery without a TCO layer on the front side, wherein the method for preparing a heterojunction battery without a TCO layer on the front side is used to prepare a heterojunction battery without a TCO layer on the front side according to any one of the aforementioned embodiments;

[0033] The preparation method of a heterojunction cell without a TCO layer on the front side includes:

[0034] Texturing is performed on a first surface and a second surface of the silicon substrate which are arranged opposite to each other;

[0035] Depositing a first passivation layer on the first surface, and depositing a second passivation layer on the second surface;

[0036] Depositing a first doping layer on the first passivation layer, and depositing a second doping layer on the second passivation layer;

[0037] Depositing an anti-reflection composite layer on the first doping layer, and depositing a transparent conductive layer on the second doping layer;

[0038] Disposing a first electrode on the anti-reflection composite layer, and allowing the first electrode to pass through the anti-reflection composite layer and contact the first doping layer;

[0039] A second electrode is disposed on the transparent conductive layer.

[0040] In an optional embodiment, the step of depositing an anti-reflection composite layer on the first doping layer specifically includes:

[0041] A silicon oxide protective layer is deposited on the first doped layer, and an anti-reflection layer is deposited on the silicon oxide protective layer.

[0042] In an optional embodiment, the step of depositing a silicon oxide protective layer on the first doping layer specifically includes:

[0043] Atomic deposition was performed at 200-250°C using silicon source and ozone as deposition materials; the pre-waiting time before the reaction started was 50-70s, and the reaction cycle corresponded to the characteristic times of Si pulse time 0.05-0.15s, Si purge time 0.5-1.5s, O 3 Pulse time 0.5-1.5s, O 3 The purge time is 0.5-1.5s and the plasma power is 2-4kW.

[0044] In an optional embodiment, the step of depositing a first passivation layer on the first surface specifically includes:

[0045] With SiH 4 By means of VHF plasma chemical vapor deposition, at a vacuum pressure of less than or equal to 0.015 mbar and a silicon substrate temperature of 160-200°C, SiH 4 The flow rate is 115-135sccm, the pressure is 0.4-0.6torr, and the deposition power is 30-40mW / cm 2 Under the conditions, a first amorphous silicon film layer is deposited on the first surface;

[0046] With SiH 4 By means of VHF plasma chemical vapor deposition, at a vacuum pressure of less than or equal to 0.015 mbar and a silicon substrate temperature of 160-200°C, SiH 4 The flow rate is 115-135sccm, the pressure is 0.3-0.4torr, and the deposition power is 10-20mW / cm 2 Under the following conditions, a second amorphous silicon film layer is deposited on the first amorphous silicon film layer;

[0047] With SiH 4 and H 2 By means of VHF plasma chemical vapor deposition, at a vacuum pressure of less than or equal to 0.015 mbar and a silicon substrate temperature of 160-200°C, SiH 4 The flow rate is 140-160sccm, H 2 The flow rate is 140-160sccm, the pressure is 0.4-0.6torr, and the deposition power is 8-12 mW / cm 2 Under the conditions, a hydrogenated amorphous silicon passivation film layer is deposited on the second amorphous silicon film layer.

[0048] In an optional embodiment, the step of depositing a first doping layer on the first passivation layer specifically includes:

[0049] With SiH 4 , H 2 and a volume concentration of 5-7% PH 3The gas is deposited by VHF plasma chemical vapor deposition at a vacuum pressure of less than or equal to 0.015 mbar and a silicon substrate temperature of 210-250°C. 4 The flow rate is 18-22sccm, H 2 The flow rate is 500-600sccm, PH 3 The flow rate is 16-20sccm, the pressure is 3-7torr, and the deposition power is 230-270mW / cm 2 Under the following conditions, a microcrystalline silicon seed layer is deposited on the first passivation layer, and the microcrystalline silicon seed layer is an N-type amorphous silicon layer;

[0050] A microcrystalline silicon doping layer is deposited on the microcrystalline silicon seed layer.

[0051] In an optional embodiment, the step of depositing a microcrystalline silicon doping layer on the microcrystalline silicon seed layer specifically includes:

[0052] With SiH 4 , H 2 and a volume concentration of 5-7% PH 3 The gas is deposited by VHF plasma chemical vapor deposition at a vacuum pressure of less than or equal to 0.015 mbar, a silicon substrate temperature of 210-250°C, a pressure of 4-6 torr, and a deposition power of 230-270 mW / cm 2 Under the conditions, at least three sub-doped layers are sequentially deposited, and the sub-doped layers are N-type microcrystalline silicon doped layers; wherein,

[0053] When the sub-doping layer is deposited on the side of the microcrystalline silicon seed layer away from the first passivation layer, PH 3 Gas flow rate and SiH 4 The flow ratio is (0.8~1.2): (0.8~1.2), SiH 4 The flow rate is 13-17sccm, H 2 The flow rate is 500-600sccm; the subsequent deposition of other sub-doped layers of SiH 4 The flow rate gradually increases.

[0054] In an optional embodiment, when depositing the sub-doping layer, argon gas is added, and the flow rate of the argon gas is SiH 4 5~15 times the traffic.

[0055] The beneficial effects of the heterojunction battery without a TCO layer on the front side of the embodiment of the present invention include: the front side of the heterojunction battery without a TCO layer provided by the embodiment of the present invention eliminates the TCO (transparent conductive layer) and only retains the transparent conductive layer on the back side, so that the contact resistance between the front TCO and the first doping layer is erased, and the excellent majority carrier conductivity of the first doping layer under light and the low contact resistivity of the first electrode provided in the anti-reflection composite film and the first doping layer are used to ensure low series resistance and high fill factor, and ensure the high conversion efficiency of the heterojunction battery without a TCO layer on the front side. Moreover, eliminating the front TCO layer can also reduce parasitic absorption, reduce the loss of light energy, and improve the light transmittance and the short-circuit current of the battery.

[0056] The photovoltaic module of the embodiment of the present invention includes all the beneficial effects of the aforementioned heterojunction cell without a TCO layer on the front side, such as: low series resistance, high fill factor, and high conversion efficiency, and reduces parasitic absorption, reduces light energy loss, and improves light transmittance and the short-circuit current of the cell.

[0057] The beneficial effects of the method for preparing a heterojunction battery without a TCO layer on the front side of the embodiment of the present invention include: the heterojunction battery without a TCO layer on the front side prepared by the method for preparing a heterojunction battery without a TCO layer on the front side provided by the embodiment of the present invention has the TCO (transparent conductive layer) eliminated on the front side, and only the transparent conductive layer is retained on the back side, so that the contact resistance between the front TCO and the first doping layer is erased, and the excellent majority carrier conductivity of the first doping layer under light, and the low contact resistivity of the first electrode provided in the anti-reflection composite film and the contact with the first doping layer are used to ensure low series resistance and high fill factor, and ensure the high conversion efficiency of the heterojunction battery without a TCO layer on the front side. Moreover, eliminating the front TCO layer can also reduce parasitic absorption, reduce the loss of light energy, and improve the light transmittance and the short-circuit current of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0059] Figure 1 A cross-sectional view of a heterojunction cell without a TCO layer on the front side according to an embodiment of the present invention Figure 1 ;

[0060] Figure 2 A cross-sectional view of a heterojunction cell without a TCO layer on the front side according to an embodiment of the present invention Figure 2 .

[0061] Icon: 010-heterojunction cell without TCO layer on the front; 100-silicon substrate; 210-first passivation layer; 211-first amorphous silicon film layer; 212-second amorphous silicon film layer; 213-hydrogenated amorphous silicon passivation film layer; 220-first doping layer; 221-microcrystalline silicon seed layer; 222-microcrystalline silicon doping layer; 2221-sub-doping layer; 230-anti-reflection composite layer; 231-silicon oxide protective layer; 232-anti-reflection layer; 2321-first anti-reflection film; 2322-second anti-reflection film; 2323-third anti-reflection film; 310-second passivation layer; 320-second doping layer; 330-transparent conductive layer; 410-first electrode; 420-second electrode. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0063] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0064] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0065] In the description of the present invention, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the invented product is usually placed when in use, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0066] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0067] Please refer to Figure 1 This embodiment provides a photovoltaic module, which includes a heterojunction cell 010 without a TCO layer on the front side.

[0068] The heterojunction cell 010 without a TCO layer on the front side comprises a silicon substrate 100, a first passivation layer 210, a first doping layer 220, a second passivation layer 310, a second doping layer 320, an anti-reflection recombination layer 230, a transparent conductive layer 330, a first electrode 410 and a second electrode 420, wherein the silicon substrate 100 has a first surface and a second surface that are opposite to each other; the first passivation layer 210 is deposited on the first surface; the first doping layer 220 is deposited on a side of the first passivation layer 210 that is away from the silicon substrate 100; The anti-reflection recombination layer 230 is deposited on the side of the first doped layer 220 away from the first passivation layer 210; the second passivation layer 310 is deposited on the second surface; the second doped layer 320 is deposited on the side of the second passivation layer 310 away from the silicon substrate 100; the transparent conductive layer 330 is deposited on the side of the second doped layer 320 away from the second passivation layer 310; the first electrode 410 is arranged on the anti-reflection recombination layer 230 and contacts the first doped layer 220; the second electrode 420 is arranged on the transparent conductive layer 330.

[0069] The front side of the heterojunction battery 010 without TCO layer has the TCO (transparent conductive layer) removed, and only the transparent conductive layer 330 is retained on the back side, so that the contact resistance between the front TCO and the first doping layer 220 is erased, and the excellent majority carrier conductivity of the first doping layer 220 under light, and the low contact resistivity of the first electrode 410 disposed on the anti-reflection composite film and the first doping layer 220 are used to ensure low series resistance and high fill factor, and ensure the high conversion efficiency of the heterojunction battery 010 without TCO layer on the front side. In addition, the removal of the front TCO layer can also reduce parasitic absorption, reduce the loss of light energy, and improve the light transmittance and the short-circuit current of the battery.

[0070] Furthermore, the anti-reflection composite layer 230 includes a silicon oxide protective layer 231 and an anti-reflection layer 232, the silicon oxide protective layer 231 is deposited on the side of the first doping layer 220 away from the first passivation layer 210, and the anti-reflection layer 232 is deposited on the side of the silicon oxide protective layer 231 away from the first doping layer 220; the first electrode 410 is arranged on the anti-reflection layer 232, and passes through the anti-reflection layer 232 to contact the silicon oxide protective layer 231 and the first doping layer 220.

[0071] By setting the silicon oxide protective layer 231, it is possible to prevent the first electrode 410 from entering the first passivation layer 210 or even entering the silicon substrate 100, thereby effectively improving the problem of deterioration of passivation quality when TCO is cancelled on the front side of the heterojunction battery; moreover, the silicon oxide protective layer 231 has an electron selective contact effect (when light is irradiated onto the battery, photons are absorbed and electron-hole pairs are generated. The role of electron selective contact is to ensure that these photogenerated electrons can be efficiently transmitted from the light absorption layer of the battery to the electrode, while reducing the recombination of electrons and holes during the transmission process, thereby reducing energy loss), which helps to improve the performance of the battery, especially to improve the photoelectric conversion efficiency and fill factor.

[0072] The provision of the anti-reflection layer 232 can improve the adverse effects on the heterojunction cell caused by the elimination of TCO on the front side, that is, the anti-reflection layer 232 can be used to ensure that more light can penetrate the surface of the cell and be absorbed, so as to improve the conversion efficiency of the cell. Moreover, since more light can be absorbed, it can also directly lead to an increase in the short-circuit current density (Isc) of the cell. The parasitic absorption performance of the anti-reflection layer 232 is better than that of TCO, that is, the anti-reflection layer 232 has lower parasitic performance, and can also ensure that the cell has a higher short-circuit current density (Isc) and conversion efficiency.

[0073] Optionally, the silicon oxide protective layer 231 is SiO x Layer, for example: SiO 2 etc., which are not specifically limited here. SiO x The SiO layer can effectively prevent the metal ions of the first electrode 410 from entering the first passivation layer 210 and the silicon substrate 100 to prevent the passivation effect from deteriorating. x The layer has good electron selective contact effect.

[0074] Further, the thickness of the silicon oxide protective layer 231 is 1-5 nm, for example, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, 2.3 nm, 2.5 nm, 2.8 nm, 3 nm, 3.2 nm, 3.5 nm, 3.8 nm, 4 nm, 4.2 nm, 4.5 nm, 4.7 nm, 5 nm, etc., which are not specifically limited here. By setting a thinner silicon oxide protective layer 231, the purpose of preventing the passivation layer from deteriorating can be achieved.

[0075] Optionally, the anti-reflection layer 232 is SiN x Layer, for example: Si 3 N 4 etc., which are not specifically limited here. x As the anti-reflection layer 232, the excellent parasitic absorption performance and anti-reflection performance of the material can be fully utilized to improve the conversion efficiency and short-circuit current density of the battery.

[0076] Of course, in other embodiments, the anti-reflection layer 232 may also be made of aluminum oxide (Al 2 O 3 )、MgO、MgF 2 ), zinc sulfide (ZnS), zinc oxide (ZnO), strontium titanate (SrTiO 3 ), calcium fluoride (CaF 2 ) etc., are not specifically limited here.

[0077] Optionally, see Figure 1 and Figure 2 The anti-reflection layer 232 includes a first anti-reflection film 2321 , a second anti-reflection film 2322 and a third anti-reflection film 2323 stacked in sequence, wherein the first anti-reflection film 2321 is disposed on a side of the silicon oxide protective layer 231 away from the first doping layer 220 . The setting of the multilayer anti-reflection film includes the following beneficial effects: 1. It is conducive to achieving a wider spectral range design, so as to achieve anti-reflection of light from the ultraviolet to near-infrared bands, thereby improving the light absorption efficiency in the entire spectral range; 2. It is conducive to reducing light reflection at different incident angles, and is conducive to improving the photoelectric conversion efficiency of the battery at different times and seasons of the day; 3. It can reduce the parasitic absorption of the anti-reflection film itself, ensuring that more light energy is absorbed by the active layer of the battery rather than lost in the anti-reflection layer 232; 4. The multilayer structure can provide better surface quality and reduce surface defects, thereby reducing the recombination of carriers on the surface and improving the open circuit voltage of the battery; 5. The multilayer anti-reflection film is conducive to providing additional physical and chemical stability, reducing the impact of environmental factors (such as moisture and pollution) on the battery, and improving the long-term performance and reliability of the battery; 6. The stacked anti-reflection film can optimize the interface matching between the battery surface and the air, reduce reflection and scattering, and at the same time reduce the interface reflection between the internal layers, thereby improving the transmission efficiency of the carriers.

[0078] Furthermore, the refractive indexes of the first anti-reflection film 2321, the second anti-reflection film 2322 and the third anti-reflection film 2323 decrease successively, wherein the refractive index of the first anti-reflection film 2321 is 2.3~2.8 (for example: 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, etc., not specifically limited herein), the refractive index of the second anti-reflection film 2322 is 2.1~2.4 (for example: 2.1, 2.2, 2.3, 2.4, etc., not specifically limited herein), and the refractive index of the third anti-reflection film 2323 is 1.8~2.2 (for example: 1.8, 1.9, 2.0, 2.1, 2.2, etc., not specifically limited herein). Such an arrangement minimizes the refractive index of the top anti-reflection film, which is conducive to forming a smaller refractive index difference between the top anti-reflection film and the air, so as to reduce the reflection of the incident light at this interface; the gradient refractive index between multiple anti-reflection film layers can reduce the reflection of light at each interface, ensuring that more light can penetrate into the battery; the use of multi-layer anti-reflection film layers with gradient refractive index can also improve the light absorption efficiency in the entire spectral range, reduce light reflection at different incident angles, and improve the photoelectric conversion efficiency of the battery under different lighting conditions; moreover, when light is reflected outward from the silicon substrate 100, this multi-layer structure with decreasing refractive index from bottom to top can also reduce internal reflection, help capture more light inside the battery, and improve light absorption efficiency.

[0079] It should be noted that the refractive index of each of the above anti-reflection films can be controlled by changing the silicon-nitrogen ratio, and the higher the silicon content, the greater the refractive index.

[0080] Optionally, the thickness of the first anti-reflection film 2321 is 10-35nm (for example: 10nm, 12nm, 15nm, 18nm, 20nm, 22nm, 25nm, 28nm, 30nm, 33nm, 35nm, etc., not specifically limited herein), the thickness of the second anti-reflection film 2322 is 10-35nm (for example: 10nm, 12nm, 15nm, 18nm, 20nm, 22nm, 25nm, 28nm, 30nm, 33nm, 35nm, etc., not specifically limited herein), and the thickness of the third anti-reflection film 2323 is 20-55nm (for example: 20nm, 22nm, 25nm, 28nm, 30nm, 33nm, 35nm, 37nm, 40nm, 43nm, 45nm, 47nm, 50nm, etc., not specifically limited herein).

[0081] Furthermore, the thicknesses of the first anti-reflection film 2321, the second anti-reflection film 2322 and the third anti-reflection film 2323 increase in sequence. In this way, it is possible to ensure that the thickness and refractive index of each anti-reflection film match.

[0082] Optionally, the thickness of the first doping layer 220 is 20-60 nm, for example, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, etc., which is not specifically limited here; the thickness of the second doping layer 320 is 15-45 nm, for example, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, etc., which is not specifically limited here. By optimizing the thickness of the doping layer, a good passivation effect can be ensured.

[0083] Furthermore, the thickness of the first doping layer 220 is greater than the thickness of the second doping layer 320. The first doping layer 220 is the front doping layer of the heterojunction battery, and the second doping layer 320 is the back doping layer of the heterojunction battery. In this way, the first doping layer 220 can be used to ensure the passivation quality, and the lateral conduction of the first doping layer 220 can be fully utilized to replace the TCO for conduction when the front TCO is removed, thereby ensuring good conversion efficiency and high fill factor of the heterojunction battery.

[0084] Moreover, setting the front doping layer of the heterojunction battery thicker than the back doping layer also includes the following beneficial effects: 1. Carrier collection efficiency: A thicker front doping layer can ensure the concentration gradient of the doping layer, so that it can collect photogenerated electrons more effectively, reduce the chance of electron recombination before reaching the front electrode, improve the electron collection efficiency, and help improve the short-circuit current (Isc) and fill factor (FF) of the battery; 2. Electric field optimization: A thicker front doping layer helps to form a stronger electric field, which is conducive to the rapid separation and directional transmission of photogenerated carriers, reduces the recombination of carriers at the interface, and thus improves the open circuit voltage (Voc) of the battery; 3. Current density improvement: Increasing the thickness of the front doping layer can reduce surface recombination and increase the carrier transmission rate, thereby increasing the current density of the battery and improving the overall efficiency; 4. Carrier selectivity: A thicker front doping layer can enhance the selective transmission of electrons and reduce the penetration of holes, thereby reducing back recombination and improving battery efficiency; 5. Cost and efficiency balance: By optimizing the thickness of the front doping layer, the battery efficiency can be improved without significantly increasing the cost.

[0085] Optionally, see Figure 1 and Figure 2 The first doped layer 220 includes a microcrystalline silicon seed layer 221 and a microcrystalline silicon doped layer 222 stacked in sequence, and the microcrystalline silicon seed layer 221 is deposited on the side of the first passivation layer 210 away from the silicon substrate 100. The microcrystalline silicon doped layer 222 can effectively replace the cancelled front TCO for lateral conduction, and the microcrystalline silicon doped layer 222 as the only lateral conduction layer has excellent majority carrier conductivity and low contact resistivity with the first electrode 410, ensuring low series resistance and high fill factor.

[0086] The microcrystalline silicon doping layer 222 includes at least three sequentially stacked sub-doping layers 2221 , for example, 3 layers, 4 layers, 5 layers, etc., which are not specifically limited herein. The first electrode 410 is in contact with at least the topmost sub-doping layer 2221 . At least three layers of sub-doped layers 2221 stacked in sequence include the following beneficial effects: 1. Optimizing the selective transport of carriers; 2. Enhancing the electric field distribution: the composite doping layer can optimize the electric field distribution inside the battery by controlling the doping concentration and thickness of each layer, promote the separation and transport of carriers, and reduce the recombination of carriers at the interface; 3. Improving interface matching, reducing the contact resistance at the interface, and improving the current transmission efficiency; 4. Reducing parasitic absorption: by optimizing the thickness of the layer, etc., the composite doping layer can reduce its own absorption of incident light, thereby reducing parasitic absorption and improving the utilization efficiency of light; 5. Improving stability: multiple layers of composite doping layers can provide better chemical and mechanical stability, protect the battery from environmental factors, and improve the long-term performance and reliability of the battery; 6. Optimizing the passivation effect: some layers in the composite doping layer can provide additional surface passivation effects, reduce surface recombination centers, and increase the open circuit voltage (Voc).

[0087] It should be noted that the structure of the second doping layer 320 is similar to that of the first doping layer 220 , which will not be described in detail herein.

[0088] Optionally, at least one of the first passivation layer 210 and the second passivation layer 310 has a thickness of 5-15 nm, for example, 5 nm, 7 nm, 9 nm, 11 nm, 13 nm, 15 nm, etc., which is not specifically limited herein.

[0089] Optionally, the first passivation layer 210 includes a first amorphous silicon film layer 211, a second amorphous silicon film layer 212, and a hydrogenated amorphous silicon passivation film layer 213, which are sequentially stacked; wherein the first amorphous silicon film layer 211 is deposited on the first surface of the silicon substrate 100. The first amorphous silicon film layer 211, as the contact surface between the passivation layer and the silicon substrate 100, can achieve the passivation effect while preventing interface defects caused by epitaxial growth; the hydrogenated amorphous silicon passivation layer, as the main structure of the passivation layer, is rich in hydrogen bonds, and can passivate the silicon substrate 100 through the first amorphous silicon film layer 211 and the second amorphous silicon film layer 212 to ensure a good passivation effect.

[0090] It should be noted that the structure of the second passivation layer 310 is similar to that of the first passivation layer 210 , which will not be described in detail herein.

[0091] Optionally, the thickness of the transparent conductive layer 330 is 80-140 nm, for example, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, etc., which is not specifically limited here. The transparent conductive layer 330 disposed on the back of the heterojunction cell is used for efficient hole transport.

[0092] Optionally, the thickness of the silicon substrate 100 is 80-180 μm, for example, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, etc., which is not specifically limited here.

[0093] This embodiment also provides a method for preparing a heterojunction battery 010 without a TCO layer on the front side, comprising:

[0094] Texturing is performed on the first and second surfaces of the silicon substrate 100 which are arranged opposite to each other; a first passivation layer 210 is deposited on the first surface, and a second passivation layer 310 is deposited on the second surface; a first doping layer 220 is deposited on the first passivation layer 210, and a second doping layer 320 is deposited on the second passivation layer 310; an anti-reflection composite layer 230 is deposited on the first doping layer 220, and a transparent conductive layer 330 is deposited on the second doping layer 320; a first electrode 410 is arranged on the anti-reflection composite layer 230, and the first electrode 410 passes through the anti-reflection composite layer 230 and contacts with the first doping layer 220; a second electrode 420 is arranged on the transparent conductive layer 330.

[0095] The preparation method produces a heterojunction battery 010 without a TCO layer on the front side, in which the TCO (transparent conductive layer 330) is eliminated on the front side, and only the transparent conductive layer 330 is retained on the back side, so that the contact resistance between the front TCO and the first doping layer 220 is eliminated. In addition, the excellent majority carrier conductivity of the first doping layer 220 under light and the low contact resistivity of the contact between the first electrode 410 arranged on the anti-reflection composite film and the first doping layer 220 are utilized to ensure low series resistance and high fill factor, and ensure a high conversion efficiency of the heterojunction battery 010 without a TCO layer on the front side.

[0096] Optionally, the specific preparation processes of the first passivation layer and the second passivation layer 310 are similar, and only the process of the first passivation layer 210 is taken as an example for detailed description.

[0097] The step of depositing a first passivation layer 210 on the first surface specifically includes:

[0098] 1. Use SiH 4 The amorphous silicon layer is grown at a high speed by very high frequency plasma chemical vapor deposition (VHF-PECVD); wherein the vacuum pressure is less than or equal to 0.015 mbar (for example, 0.015 mbar, 0.014 mbar, 0.013 mbar, etc., not specifically limited here), the temperature of the silicon substrate 100 is 160-200° C. (for example, 160° C., 170° C., 180° C., 190° C., 200° C., etc., not specifically limited here), and the SiH 4The flow rate is 115-135sccm (for example: 115sccm, 120sccm, 125sccm, 130sccm, 135sccm, etc., not specifically limited here), the pressure is 0.4-0.6torr (for example: 0.4torr, 0.5torr, 0.6torr, etc., not specifically limited here), and the deposition power is 30-40mW / cm 2 (For example: 30mW / cm 2 、32mW / cm 2 、35mW / cm 2 、38mW / cm 2 , 40mW / cm 2 The first amorphous silicon film layer 211 formed by the deposition of the silicon substrate 100 is deposited on the first surface of the silicon substrate 100. In this way, the first amorphous silicon film layer 211 grown by deposition can ensure the passivation effect while preventing the interface defects caused by the epitaxial growth.

[0099] 2. Use SiH 4 The amorphous silicon layer is grown at a low speed by very high frequency plasma chemical vapor deposition; wherein the vacuum pressure is less than or equal to 0.015 mbar (for example: 0.015 mbar, 0.014 mbar, 0.013 mbar, etc., not specifically limited here), the temperature of the silicon substrate 100 is 160-200° C. (for example: 160° C., 170° C., 180° C., 190° C., 200° C., etc., not specifically limited here), and SiH 4 The flow rate is 115-135sccm (for example: 115sccm, 120sccm, 125sccm, 130sccm, 135sccm, etc., not specifically limited here), the pressure is 0.3-0.4torr (for example: 0.3torr, 0.35torr, 0.4torr, etc., not specifically limited here), and the deposition power is 10-20mW / cm 2 (For example: 10mW / cm 2 , 12mW / cm 2 、15mW / cm 2 、18mW / cm 2 , 20mW / cm 2 The second amorphous silicon film layer 212 is deposited and grown on the side of the first amorphous silicon film layer 211 away from the silicon substrate 100. The low-speed deposition can ensure the structure and quality of the second amorphous silicon film layer 212.

[0100] 3. Use SiH 4 and H 2A hydrogenated amorphous silicon passivation film is grown on the surface of the amorphous silicon layer by very high frequency plasma chemical vapor deposition; wherein the vacuum pressure is less than or equal to 0.015 mbar (for example, 0.015 mbar, 0.014 mbar, 0.013 mbar, etc., not specifically limited herein), the temperature of the silicon substrate 100 is 160-200° C. (for example, 160° C., 170° C., 180° C., 190° C., 200° C., etc., not specifically limited herein), and SiH 4 The flow rate is 140-160sccm (for example: 140sccm, 145sccm, 150sccm, 155sccm, 160sccm, etc., not specifically limited here), H 2 The flow rate is 140-160sccm (for example: 140sccm, 145sccm, 150sccm, 155sccm, 160sccm, etc., not specifically limited here), the pressure is 0.4-0.6torr (for example: 0.4torr, 0.5torr, 0.6torr, etc., not specifically limited here), and the deposition power is 8-12mW / cm 2 (For example: 8mW / cm 2 , 9mW / cm 2 、10mW / cm 2 、11mW / cm 2 , 12mW / cm 2 The hydrogenated amorphous silicon passivation film layer 213 is deposited and grown on the side of the second amorphous silicon film layer 212 away from the first amorphous silicon film layer 211. The hydrogenated amorphous structure prepared by adding hydrogen on the original basis is the main structure of the passivation layer, which is rich in hydrogen bonds and can passivate the silicon substrate 100 through the first two layers, but this layer structure is unstable, so it needs to be built on the first two layers.

[0101] Optionally, the step of depositing the first doping layer 220 on the first passivation layer 210 specifically includes:

[0102] With SiH 4 , H 2 and a pH of 5-7% (e.g., 5%, 6%, 7%, etc., not specifically limited here) by volume 3 The gas is N-type doped by very high frequency plasma chemical vapor deposition; wherein the vacuum pressure is less than or equal to 0.015 mbar (for example: 0.015 mbar, 0.014 mbar, 0.013 mbar, etc., not specifically limited here), the temperature of the silicon substrate 100 is 210-250° C. (for example: 210° C., 220° C., 230° C., 240° C., 250° C., etc., not specifically limited here), SiH 4The flow rate is 18-22 sccm (for example: 18 sccm, 19 sccm, 20 sccm, 21 sccm, 22 sccm, etc., not specifically limited here), H 2 The flow rate is 500-600sccm (for example: 500sccm, 520sccm, 530sccm, 540sccm, 550sccm, 560sccm, 570sccm, 580sccm, 590sccm, 600sccm, etc., not specifically limited here), PH 3 The flow rate is 16-20sccm (for example: 16sccm, 17sccm, 18sccm, 19sccm, 20sccm, etc., not specifically limited here), the pressure is 3-7torr (for example: 3torr, 4torr, 5torr, 6torr, 7torr, etc., not specifically limited here), and the deposition power is 230-270mW / cm 2 (For example: 230mW / cm 2 、240mW / cm 2 、250mW / cm 2 、260mW / cm 2 、270mW / cm 2 The microcrystalline silicon seed layer 221 is deposited on the side of the first passivation layer 210 away from the silicon substrate 100, and the microcrystalline silicon seed layer 221 is an N-type amorphous silicon layer; the microcrystalline silicon doping layer 222 is deposited on the microcrystalline silicon seed layer 221.

[0103] Furthermore, the step of depositing the microcrystalline silicon doping layer 222 on the microcrystalline silicon seed layer 221 specifically includes:

[0104] With SiH 4 , H 2 and a pH of 5-7% (e.g., 5%, 6%, 7%, etc., not specifically limited here) by volume 3 The gas is doped with N-type microcrystalline silicon by very high frequency plasma chemical vapor deposition; wherein, when the vacuum pressure is less than or equal to 0.015 mbar (for example: 0.015 mbar, 0.014 mbar, 0.013 mbar, etc., not specifically limited here), the temperature of the silicon substrate 100 is 210-250° C. (for example: 210° C., 220° C., 230° C., 240° C., 250° C., etc., not specifically limited here), the pressure is 4-6 torr (for example: 4 torr, 5 torr, 6 torr, etc., not specifically limited here), and the deposition power is 230-270 mW / cm 2 (For example: 230mW / cm 2 、240mW / cm 2 、250mW / cm2 、260mW / cm 2 、270mW / cm 2 Under conditions such as , etc., which are not specifically limited herein), at least three sub-doped layers 2221 are sequentially deposited, and the sub-doped layers 2221 are N-type microcrystalline silicon doped layers 222.

[0105] When the sub-doping layer 2221 is deposited on the side of the microcrystalline silicon seed layer 221 away from the first passivation layer 210, PH 3 Gas flow rate and SiH 4 The flow ratio of SiH is (0.8~1.2):(0.8~1.2) (for example: 1:1, 1:1.2, 1:0.8, 0.8:1, 1.2:1, etc., not specifically limited here), 4 The flow rate is 13-17sccm (for example: 13sccm, 14sccm, 15sccm, 16sccm, 17sccm, etc., not specifically limited here), H 2 The flow rate is 500-600sccm (for example, 500sccm, 520sccm, 530sccm, 540sccm, 550sccm, 560sccm, 570sccm, 580sccm, 590sccm, 600sccm, etc., which are not specifically limited here); the SiH of other sub-doping layers 2221 is subsequently deposited. 4 The flow rate gradually increases.

[0106] Taking the preparation of three-layer doped sub-layer 2221 as an example, when depositing the first layer of doped sub-layer 2221, SiH 4 The flow rate is 13-17sccm; when depositing the second sub-doping layer 2221, SiH 4 The flow rate is 1.1-1.5 times that of depositing the first sub-doped layer 2221; when depositing the third sub-doped layer 2221, SiH 4 The flow rate is 1.5-2 times that of depositing the second sub-doped layer 2221.

[0107] Optionally, when depositing the doping layer, Ar can be used to improve the crystallization rate of the doping layer, that is, when depositing the sub-doping layer 2221, argon Ar is added, and the flow rate of the argon gas is SiH 45 to 15 times the flow rate, for example: 5 times, 6 times, 7 times, 10 times, 13 times, 15 times, etc., not specifically limited here. Compared with amorphous silicon, microcrystalline silicon has improved optical and electrical properties, and the increase in crystallization rate has significantly improved the optical properties, conductive properties, doping efficiency and bandgap width of the microcrystals; among them, the use of Ar mainly includes the following functions: 1. Ar gas can be ionized in a plasma environment to form a large number of free electrons and ions. These charged particles can enhance the activation of reactant molecules and accelerate chemical reactions, thereby increasing the deposition rate and crystallization efficiency; 2. As an inert gas, Ar gas can play a dilution role in the reaction chamber, helping to control the concentration of the reactant gas and avoid the degradation of the deposited layer quality due to excessive reactant concentration; 3. The Ar ions and electrons in the plasma have high kinetic energy. When they collide with the substrate or the surface of the deposited layer, they can provide additional heat energy, which helps to promote the crystallization process and improve the crystallization rate; 4. The physical bombardment of Ar ions can clean up impurities or adsorbates on the deposition surface, provide a cleaner deposition surface, and help improve the quality and crystallization rate of the deposited layer; 5. The bombardment of Ar ions can also promote the migration of atoms or molecules on the surface, help to form a more complete lattice structure, and improve the crystallization rate; 6. Through the plasma action of Ar gas, defects in the deposition process, such as vacancies and grain boundaries, can be reduced, thereby improving the crystallization quality and crystallization rate of the deposited layer.

[0108] Optionally, the second doped layer is a P-type microcrystalline silicon doped layer 222 , and its preparation process is similar to related processes and will not be described in detail herein.

[0109] Optionally, the step of depositing the anti-reflection composite layer 230 on the first doping layer 220 specifically includes: depositing a silicon oxide protective layer 231 on the first doping layer 220 , and depositing an anti-reflection layer 232 on the silicon oxide protective layer 231 .

[0110] Further, the step of depositing the silicon oxide protective layer 231 on the first doping layer 220 specifically includes: using silicon source and ozone as deposition raw materials, performing atomic deposition at a temperature of 200-250° C. (for example, 200° C., 210° C., 220° C., 230° C., 240° C., 250° C., etc., not specifically limited herein); wherein the pre-waiting time before the reaction starts is 50-70 seconds (for example, 50 seconds, 55 seconds, 60 seconds, 65 seconds); s, 70s, etc., not specifically limited here), the reaction cycle corresponds to each characteristic time of Si pulse time 0.05-0.15s (for example: 0.05s, 0.07s, 0.09s, 0.1s, 0.12s, 0.15s, etc., not specifically limited here), Si purge time 0.5-1.5s (for example: 0.5, 0.7s, 0.9s, 1.0s, 1.2s, 1.5s, etc., not specifically limited here), O 3Pulse time 0.5-1.5s (for example: 0.5, 0.7s, 0.9s, 1.0s, 1.2s, 1.5s, etc., not specifically limited here), O 3 The purge time is 0.5-1.5s (for example: 0.5, 0.7s, 0.9s, 1.0s, 1.2s, 1.5s, etc., not specifically limited here), and the plasma power is 2-4kW (for example: 2kW, 2.5kW, 3kW, 3.5kW, 4kW, etc., not specifically limited here). The silicon oxide protective layer 231 prepared under this process can effectively prevent the metal ions of the electrode from penetrating into the passivation layer and even the silicon substrate 100, and can avoid adverse effects on the conversion efficiency and fill factor of the battery.

[0111] Optionally, the reaction cycles are 10-150, for example 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 140, 150, etc., which are not specifically limited here.

[0112] It should be noted that the process of depositing the anti-reflection layer 232 is similar to related technologies and will not be described in detail herein.

[0113] It should also be noted that the process temperature used in the entire preparation method of the present invention is relatively low, so it will not cause damage to the passivation layer, and can ensure good conversion efficiency and high fill factor of the heterojunction battery.

[0114] The present invention is further described in detail below with reference to specific embodiments.

[0115] Example 1

[0116] 1. After the silicon substrate is cleaned, the organic dirt, metal impurities and surface damage layer on the surface are removed; the thickness of the silicon substrate is 110μm, and the side length of the silicon substrate is 210×105mm.

[0117] 2. After cleaning, the silicon substrate is textured to form a velvet layer on the front and back sides.

[0118] 3. Use VHF-PECVD equipment to deposit the velvet layer on the front and back of the silicon substrate to form a passivation layer. 1) The first layer is formed at a vacuum pressure of 0.015mbar, a silicon substrate temperature of 180℃, and SiH 4 The flow rate is 125sccm, the pressure is 0.5torr, and the deposition power is 35mW / cm 2 The first amorphous silicon film layer was deposited under the following conditions with a thickness of 1.5 nm; 2) the second layer was deposited under the following conditions with a vacuum pressure of 0.015 mbar, a silicon substrate temperature of 180 °C, and SiH 4The flow rate is 125sccm, the pressure is 0.35torr, and the deposition power is 15mW / cm 2 Under the conditions, a second amorphous silicon film layer with a thickness of 2.5 nm is deposited; 3) a hydrogenated amorphous silicon passivation film with a thickness of 3.5 nm is grown on the surface of the amorphous silicon layer. The deposition conditions are: vacuum pressure 0.015 mbar, silicon substrate temperature 180 °C, SiH 4 The flow rate is 150sccm, H 2 The flow rate is 150sccm, the pressure is 0.5torr, and the deposition power is 10mW / cm 2 .

[0119] 4. Use VHF-PECVD equipment to deposit and grow doping layers on the two passivation layers. The process of growing the microcrystalline silicon doping layer on the front passivation layer is as follows: 1) The first layer is deposited at a vacuum pressure of 0.015mbar, a silicon substrate temperature of 230℃, and SiH 4 The flow rate is 20sccm, H 2 The flow rate is 550sccm, PH 3 (volume concentration is 6%), the flow rate is 18sccm, the pressure is 5torr, and the deposition power is 250mW / cm 2 Under the conditions, the N-type amorphous silicon layer deposited on the passivation layer is used as the microcrystalline silicon seed layer with a thickness of 1.2nm; 2) The second layer is a sub-doping layer of the three-layer substrate deposited on the microcrystalline silicon seed layer. The first sub-doping layer is at a vacuum pressure of 0.015mbar, a silicon substrate temperature of 230℃, and a PH 3 (Volume concentration is 6%) Gas flow rate and SiH 4 The flow ratio is 1:1, SiH 4 The flow rate is 15 sccm, H 2 The flow rate is 550sccm, the pressure is 5torr, and the deposition power is 250mW / cm 2 The deposition process of the second sub-doping layer is different from that of the first sub-doping layer in that the gas flow rate of the second sub-doping layer is 1.2 times that of the first sub-doping layer and the thickness is 10nm. The process of the third sub-doping layer is different from that of the first sub-doping layer in that the third sub-doping layer SiH 4 The gas flow rate is 1.5 times that of the first doped layer, and the thickness is 7nm.

[0120] The thickness of the doped layer (P-type microcrystalline silicon doped layer) on the back side is 22 nm.

[0121] 5. Deposit a silicon oxide protective layer on the front doping layer (N-type microcrystalline silicon doping layer); use tri(dimethylamino)silane TDMAS (C6H18N3Si) as the silicon source and ozone (O3 ) as the oxygen source, the reaction temperature was set to 225 °C, the pre-waiting time before the reaction started was 60 s, and the reaction cycle corresponding to each characteristic time was Si pulse time 0.1 s, Si purge time 1 s, O 3 Pulse time 1s, O 3 The purge time is 1s and the plasma power is 3kW. The specific process is that the silicon source precursor TDMAS is directly delivered into the ALD reaction chamber in the form of pulses by carrier gas (Ar gas flux 120sccm). 3 External high purity O 2 (purity 99.999%) was introduced into an ozone generator. Ar gas was introduced into the reaction chamber to blow away the excess TDMAS precursor on the surface; O 3 Introduce it into the ALD reaction chamber to react with the TDMAS precursor adsorbed on the surface; introduce Ar gas again to remove the unreacted O 3 After 100 cycles, 5 nm SiO 2 layer.

[0122] 6. Deposit anti-reflection film on the silicon oxide protective layer (Si 3 N 4 ); wherein, the refractive indices of the three layers of anti-reflection films from top to bottom are 1.95, 2.15 and 2.3, respectively, and the corresponding film thicknesses are 50nm, 25mn and 10nm.

[0123] 7. Deposit a TCO layer on the doped layer (P-type microcrystalline silicon doped layer) on the back side (i.e., coat a transparent conductive film on the back side) using PVD technology, with the target material being In 2 O 3 / SnO 2 , mass ratio is 97:3, film forming temperature is 200℃, and film thickness is 120nm.

[0124] 8. Metallization

[0125] 1) Metallization is done by screen printing, and the front side burns through the surface anti-reflection layer to contact the silicon oxide protective layer and the front side doping layer.

[0126] 2) The HJT battery pattern adopts a multi-busbar technology solution, and the number of busbars in the battery is 18BB.

[0127] Example 2

[0128] 1. After the silicon substrate is cleaned, the organic dirt, metal impurities and surface damage layer on the surface are removed; the thickness of the silicon substrate is 110μm, and the side length of the silicon substrate is 210×105mm.

[0129] 2. After cleaning, the silicon substrate is textured to form a velvet layer on the front and back sides.

[0130] 3. Use VHF-PECVD equipment to deposit the velvet layer on the front and back of the silicon substrate to form a passivation layer. 1) The first layer is formed at a vacuum pressure of 0.013mbar, a silicon substrate temperature of 150℃, and SiH 4 The flow rate is 115sccm, the pressure is 0.4torr, and the deposition power is 30mW / cm 2 The first amorphous silicon film layer was deposited under the following conditions with a thickness of 1.0 nm; 2) the second layer was deposited under the following conditions with a vacuum pressure of 0.013 mbar, a silicon substrate temperature of 160 °C, and SiH 4 The flow rate is 115sccm, the pressure is 0.30torr, and the deposition power is 10mW / cm 2 Under the conditions, a second amorphous silicon film layer with a thickness of 1.5 nm is deposited; 3) a hydrogenated amorphous silicon passivation film with a thickness of 2.5 nm is grown on the surface of the amorphous silicon layer. The deposition conditions are: vacuum pressure 0.013 mbar, silicon substrate temperature 160 ° C, SiH 4 The flow rate is 140sccm, H 2 The flow rate is 140sccm, the pressure is 0.4torr, and the deposition power is 8mW / cm 2 .

[0131] 4. Use VHF-PECVD equipment to deposit and grow doping layers on the two passivation layers. The process of growing the microcrystalline silicon doping layer on the front passivation layer is as follows: 1) The first layer is deposited at a vacuum pressure of 0.013mbar, a silicon substrate temperature of 210℃, and SiH 4 The flow rate is 18 sccm, H 2 The flow rate is 500sccm, PH 3 (volume concentration is 5%), the flow rate is 16sccm, the pressure is 4torr, and the deposition power is 230mW / cm 2 Under the conditions, the N-type amorphous silicon layer deposited on the passivation layer is used as the microcrystalline silicon seed layer with a thickness of 1.0 nm; 2) The second layer is a sub-doping layer of the three-layer substrate deposited on the microcrystalline silicon seed layer. The first sub-doping layer is at a vacuum pressure of 0.013 mbar, a silicon substrate temperature of 210 ° C, and a PH 3 (Volume concentration is 5%) Gas flow rate and SiH 4 The flow ratio is 0.8:1, SiH 4 The flow rate is 13 sccm, H 2 The flow rate is 500sccm, the pressure is 4torr, and the deposition power is 230mW / cm 2The deposition process of the second sub-doping layer is different from that of the first sub-doping layer in that the gas flow rate of the second sub-doping layer is 1.5 times that of the first sub-doping layer and the thickness is 9nm. The process of the third sub-doping layer is different from that of the first sub-doping layer in that the third sub-doping layer SiH 4 The gas flow rate is twice that of the first doped layer and the thickness is 5nm.

[0132] The thickness of the doped layer (P-type microcrystalline silicon doped layer) on the back side is 20 nm.

[0133] 5. Deposit a silicon oxide protective layer on the front doping layer (N-type microcrystalline silicon doping layer); use tri(dimethylamino)silane TDMAS (C6H18N3Si) as the silicon source and ozone (O 3 ) as the oxygen source, the reaction temperature was set to 200 °C, the pre-waiting time before the reaction started was 50 s, and the reaction cycle corresponding to each characteristic time was Si pulse time 0.05 s, Si purge time 0.5 s, O 3 Pulse time 0.5s, O 3 The purge time is 0.5s and the plasma power is 2kW. The specific process is that the silicon source precursor TDMAS is directly delivered into the ALD reaction chamber in the form of pulses by the carrier gas (Ar gas flux 120sccm). 3 External high purity O 2 (purity 99.999%) was introduced into an ozone generator. Ar gas was introduced into the reaction chamber to blow away the excess TDMAS precursor on the surface; O 3 Introduce it into the ALD reaction chamber to react with the TDMAS precursor adsorbed on the surface; introduce Ar gas again to remove the unreacted O 3 After 20 cycles, 1 nm SiO 2 layer.

[0134] 6. Deposit anti-reflection film on the silicon oxide protective layer (Si 3 N 4 ), the structure, refractive index and thickness of the anti-reflection film refer to Example 1.

[0135] 7. Deposit a TCO layer on the doped layer (P-type microcrystalline silicon doped layer) on the back side (i.e., coat a transparent conductive film on the back side) using PVD technology, with the target material being In 2 O 3 / SnO 2 , the mass ratio is 97:3, and the film forming temperature and film thickness refer to Example 1.

[0136] 8. Metallization

[0137] 1) Metallization is done by screen printing, and the front side burns through the surface anti-reflection layer to contact the silicon oxide protective layer and the front side doping layer.

[0138] 2) The HJT battery pattern adopts a multi-busbar technology solution, and the number of busbars in the battery is 18BB.

[0139] Example 3

[0140] 1. After the silicon substrate is cleaned, the organic dirt, metal impurities and surface damage layer on the surface are removed; the thickness of the silicon substrate is 110μm, and the side length of the silicon substrate is 210×105mm.

[0141] 2. After cleaning, the silicon substrate is textured to form a velvet layer on the front and back sides.

[0142] 3. Use VHF-PECVD equipment to deposit the velvet layer on the front and back of the silicon substrate to form a passivation layer. 1) The first layer is formed at a vacuum pressure of 0.015mbar, a silicon substrate temperature of 200℃, and SiH 4 The flow rate is 135sccm, the pressure is 0.6torr, and the deposition power is 40mW / cm 2 The first amorphous silicon film layer was deposited under the following conditions with a thickness of 2 nm; 2) the second layer was deposited under the following conditions with a vacuum pressure of 0.015 mbar, a silicon substrate temperature of 200 °C, and SiH 4 The flow rate is 135sccm, the pressure is 0.4torr, and the deposition power is 20mW / cm 2 Under the conditions, a second amorphous silicon film layer with a thickness of 3.5 nm is deposited; 3) a hydrogenated amorphous silicon passivation film with a thickness of 4.5 nm is grown on the surface of the amorphous silicon layer. The deposition conditions are: vacuum pressure 0.015 mbar, silicon substrate temperature 200 °C, SiH 4 The flow rate is 160sccm, H 2 The flow rate is 160sccm, the pressure is 0.6torr, and the deposition power is 12mW / cm 2 .

[0143] 4. Use VHF-PECVD equipment to deposit and grow doping layers on the two passivation layers. The process of growing the microcrystalline silicon doping layer on the front passivation layer is as follows: 1) The first layer is deposited at a vacuum pressure of 0.015mbar, a silicon substrate temperature of 250℃, and SiH 4 The flow rate is 22sccm, H 2 The flow rate is 600sccm, PH 3 (volume concentration is 7%), the flow rate is 20sccm, the pressure is 6torr, and the deposition power is 270mW / cm 2Under the conditions, the N-type amorphous silicon layer deposited on the passivation layer is used as the microcrystalline silicon seed layer with a thickness of 1.5nm; 2) The second layer is a sub-doping layer of the three-layer substrate deposited on the microcrystalline silicon seed layer. The first sub-doping layer is at a vacuum pressure of 0.015mbar, the temperature of the silicon substrate is 250℃, and the PH 3 (Volume concentration is 7%) Gas flow rate and SiH 4 The flow ratio is 1.2:0.8, SiH 4 The flow rate is 17 sccm, H 2 The flow rate is 600sccm, the pressure is 6torr, and the deposition power is 270mW / cm 2 The deposition process of the second sub-doping layer is different from that of the first sub-doping layer in that the gas flow rate of the second sub-doping layer is 1.3 times that of the first sub-doping layer and the thickness is 12nm. The process of the third sub-doping layer is different from that of the first sub-doping layer in that the third sub-doping layer SiH 4 The gas flow rate is 1.8 times that of the first doped layer, and the thickness is 9nm.

[0144] The thickness of the doped layer (P-type microcrystalline silicon doped layer) on the back side is 25 nm.

[0145] 5. Deposit a silicon oxide protective layer on the front doping layer (N-type microcrystalline silicon doping layer); use tri(dimethylamino)silane TDMAS (C6H18N3Si) as the silicon source and ozone (O 3 ) as the oxygen source, the reaction temperature was set to 250 °C, the pre-waiting time before the reaction started was 70 s, and the reaction cycle corresponding to each characteristic time was Si pulse time 0.15 s, Si purge time 1.5 s, O 3 Pulse time 1.5s, O 3 The purge time is 1.5s and the plasma power is 4kW. The specific process is that the silicon source precursor TDMAS is directly delivered into the ALD reaction chamber in the form of pulses by carrier gas (Ar gas flux 120sccm). 3 External high purity O 2 (purity 99.999%) was introduced into an ozone generator. Ar gas was introduced into the reaction chamber to blow away the excess TDMAS precursor on the surface; O 3 Introduce it into the ALD reaction chamber to react with the TDMAS precursor adsorbed on the surface; introduce Ar gas again to remove the unreacted O 3 After 80 cycles, 3 nm SiO 2 layer.

[0146] 6. Deposit anti-reflection film on the silicon oxide protective layer (Si 3 N 4), the structure, refractive index and thickness of the anti-reflection film refer to Example 1.

[0147] 7. Deposit a TCO layer on the doped layer (P-type microcrystalline silicon doped layer) on the back side (i.e., coat a transparent conductive film on the back side) using PVD technology, with the target material being In 2 O 3 / SnO 2 , the mass ratio is 97:3, and the film forming temperature and film thickness refer to Example 1.

[0148] 8. Metallization

[0149] 1) Metallization is done by screen printing, and the front side burns through the surface anti-reflection layer to contact the silicon oxide protective layer and the front side doping layer.

[0150] 2) The HJT battery pattern adopts a multi-busbar technology solution, and the number of busbars in the battery is 18BB.

[0151] Example 4

[0152] 1. After the silicon substrate is cleaned, the organic dirt, metal impurities and surface damage layer on the surface are removed; the thickness of the silicon substrate is 110μm, and the side length of the silicon substrate is 210×105mm.

[0153] 2. After cleaning, the silicon substrate is textured to form a velvet layer on the front and back sides.

[0154] 3. Use VHF-PECVD equipment to deposit the velvet layer on the front and back of the silicon substrate to form a passivation layer. 1) The first layer is formed at a vacuum pressure of 0.015mbar, a silicon substrate temperature of 180℃, and SiH 4 The flow rate is 120sccm, the pressure is 0.5torr, and the deposition power is 35mW / cm 2 The first amorphous silicon film layer was deposited under the following conditions with a thickness of 2 nm; 2) the second layer was deposited under the following conditions with a vacuum pressure of 0.015 mbar, a silicon substrate temperature of 180 °C, and SiH 4 The flow rate is 120sccm, the pressure is 0.35torr, and the deposition power is 15mW / cm 2 Under the conditions, a second amorphous silicon film layer with a thickness of 3 nm is deposited; 3) a hydrogenated amorphous silicon passivation film with a thickness of 5 nm is grown on the surface of the amorphous silicon layer. The deposition conditions are: vacuum pressure 0.015 mbar, silicon substrate temperature 180 ° C, SiH 4 The flow rate is 155sccm, H 2 The flow rate is 155sccm, the pressure is 0.5torr, and the deposition power is 11mW / cm 2 .

[0155] 4. Use VHF-PECVD equipment to deposit and grow doping layers on the two passivation layers. The process of growing the microcrystalline silicon doping layer on the front passivation layer is as follows: 1) The first layer is deposited at a vacuum pressure of 0.015mbar, a silicon substrate temperature of 230℃, and SiH 4 The flow rate is 21 sccm, H 2 The flow rate is 555sccm, PH 3 (volume concentration is 6%), the flow rate is 18sccm, the pressure is 5torr, and the deposition power is 255mW / cm 2 Under the conditions, the N-type amorphous silicon layer deposited on the passivation layer is used as the microcrystalline silicon seed layer with a thickness of 2nm; 2) The second layer is a sub-doping layer of a five-layer substrate deposited on the microcrystalline silicon seed layer. The first sub-doping layer is at a vacuum pressure of 0.015mbar, a silicon substrate temperature of 230℃, and a PH 3 (Volume concentration is 6%) Gas flow rate and SiH 4 The flow ratio is 1:1.2, SiH 4 The flow rate is 15 sccm, H 2 The flow rate is 550sccm, the pressure is 5torr, and the deposition power is 255mW / cm 2 The second sub-doping layer is formed by deposition under the following conditions, with a thickness of 5nm. The difference between the process of the second sub-doping layer and the first sub-doping layer is that the gas flow rate of the second sub-doping layer is 1.2 times that of the first sub-doping layer, and the thickness is 5nm. The difference between the process of the third sub-doping layer and the first sub-doping layer is that the third doping layer SiH 4 The gas flow rate of the first doped layer is 1.6 times that of the first doped layer, and the thickness is 5nm; the gas flow rate of the fourth sub-doped layer is 1.8 times that of the first doped layer, and the thickness is 6nm; the gas flow rate of the fifth sub-doped layer is 2 times that of the first doped layer, and the thickness is 3nm.

[0156] The thickness of the doped layer (P-type microcrystalline silicon doped layer) on the back side is 28 nm.

[0157] 5. Deposit a silicon oxide protective layer on the front doping layer (N-type microcrystalline silicon doping layer); use tri(dimethylamino)silane TDMAS (C6H18N3Si) as the silicon source and ozone (O 3 ) as the oxygen source, the reaction temperature was set to 225 °C, the pre-waiting time before the reaction started was 65 s, and the reaction cycle corresponding to each characteristic time was Si pulse time 0.12 s, Si purge time 1.2 s, O 3 Pulse time 1.2s, O 3 The purge time is 1.2s and the plasma power is 3kW. The specific process is that the silicon source precursor TDMAS is directly delivered into the ALD reaction chamber in the form of pulses by the carrier gas (Ar gas flux 120sccm). 3External high purity O 2 (purity 99.999%) was introduced into an ozone generator. Ar gas was introduced into the reaction chamber to blow away the excess TDMAS precursor on the surface; O 3 Introduce it into the ALD reaction chamber to react with the TDMAS precursor adsorbed on the surface; introduce Ar gas again to remove the unreacted O 3 After 30 cycles, 3 nm SiO 2 layer.

[0158] 6. Deposit anti-reflection film on the silicon oxide protective layer (Si 3 N 4 ), the structure, refractive index and thickness of the anti-reflection film refer to Example 1.

[0159] 7. Deposit a TCO layer on the doped layer (P-type microcrystalline silicon doped layer) on the back side (i.e., coat a transparent conductive film on the back side) using PVD technology, with the target material being In 2 O 3 / SnO 2 , the mass ratio is 97:3, and the film forming temperature and film thickness refer to Example 1.

[0160] 8. Metallization

[0161] 1) Metallization is done by screen printing, and the front side burns through the surface anti-reflection layer to contact the silicon oxide protective layer and the front side doping layer.

[0162] 2) The HJT battery pattern adopts a multi-busbar technology solution, and the number of busbars in the battery is 18BB.

[0163] Example 5

[0164] Example 5 is similar to Example 1, except that:

[0165] When depositing each sub-doped layer, argon gas is added, and the flow rate of argon gas is SiH 4 5 times the flow rate.

[0166] The other processes refer to Example 1.

[0167] Example 6

[0168] Example 6 is similar to Example 1, except that:

[0169] When depositing each sub-doped layer, argon gas is added, and the flow rate of argon gas is SiH 4 10 times the flow rate.

[0170] The other processes refer to Example 1.

[0171] Example 7

[0172] Example 7 is similar to Example 1, except that:

[0173] When depositing each sub-doped layer, argon gas is added, and the flow rate of argon gas is SiH 4 15 times the traffic.

[0174] The other processes refer to Example 1.

[0175] Comparative Example 1

[0176] The difference between Comparative Example 1 and Example 1 is that no silicon oxide protective layer is provided, and other process parameters refer to Example 1.

[0177] Comparative Example 2

[0178] The difference between Comparative Example 2 and Example 1 is that the thickness of the silicon oxide protective layer is 0.5 nm, and other process parameters refer to Example 1.

[0179] Comparative Example 3

[0180] The difference between Comparative Example 3 and Example 1 is that when preparing the passivation layer, only one amorphous silicon layer is deposited, and a hydrogenated amorphous silicon passivation film is deposited on the amorphous silicon layer. The other process parameters refer to Example 1.

[0181] Comparative Example 4

[0182] The difference between Comparative Example 4 and Example 1 is that when preparing the front doping layer, only the first N-type microcrystalline silicon sub-doping layer is deposited on the microcrystalline silicon seed layer, and other process parameters refer to Example 1.

[0183] Comparative Example 5

[0184] The difference between Comparative Example 5 and Example 1 is that when preparing the front doping layer, only the first and second N-type microcrystalline silicon sub-doping layers are deposited on the microcrystalline silicon seed layer, and other process parameters refer to Example 1.

[0185] Comparative Example 6

[0186] The difference between Comparative Example 6 and Example 1 is that the thickness of the prepared front doping layer is the same as the thickness of the back doping layer, both of which are 15 nm. The other process parameters refer to Example 1.

[0187] Comparative Example 7

[0188] The difference between Comparative Example 7 and Example 1 is that the silicon substrate temperature for preparing the first amorphous silicon layer of the passivation layer is 120°C and the deposition power is 20 mW / cm 2 , other process parameters refer to Example 1.

[0189] Comparative Example 8

[0190] The difference between Comparative Example 8 and Example 1 is that the silicon substrate temperature for preparing the second amorphous silicon layer of the passivation layer is 120°C and the deposition power is 5 mW / cm 2 , other process parameters refer to Example 1.

[0191] Comparative Example 9

[0192] The difference between Comparative Example 9 and Example 1 is that the silicon substrate temperature for preparing the hydrogenated amorphous silicon passivation film of the passivation layer is 120°C and the deposition power is 5 mW / cm 2 , other process parameters refer to Example 1.

[0193] Comparative Example 10

[0194] The difference between Comparative Example 10 and Example 1 is that when preparing the three-layer doping of the front doping layer, SiH 4 The gas flow ratio is 1:1:1, and other process parameters refer to Example 1.

[0195] Comparative Example 11

[0196] The difference between Comparative Example 11 and Example 1 is that when preparing the three-layer doping of the front doping layer, SiH 4 The gas flow ratio is 1:1.2:1.2, and other process parameters refer to Example 1.

[0197] Comparative Example 12

[0198] The difference between Comparative Example 12 and Example 1 is that when preparing the microcrystalline silicon seed layer of the front doping layer, the temperature of the silicon substrate is 180°C and the deposition power is 200 mW / cm 2 , other process parameters refer to Example 1.

[0199] Comparative Example 13

[0200] The difference between Comparative Example 13 and Example 1 is that when preparing the sub-doping layer of the front doping layer, the temperature of the silicon substrate is 180°C and the deposition power is 200 mW / cm 2 , other process parameters refer to Example 1.

[0201] The electrical properties of the batteries of Examples 1-7 and Comparative Examples 1-13 were tested; the results are shown in Table 1.

[0202] Table 1

[0203] Short circuit current (Isc) average Open circuit voltage (Voc) average Fill Factor (FF) Mean Conversion efficiency (Eff) average repeat Example 1 8.885 0.754 86.43 26.15 10 Example 2 8.880 0.752 86.16 26.11 10 Example 3 8.883 0.751 86.32 26.13 10 Example 4 8.882 0.754 86.41 26.14 10 Example 5 8.881 0.754 86.49 26.18 10 Example 6 8.899 0.754 86.57 26.26 10 Example 7 8.883 0.754 86.45 26.16 10 Comparative Example 1 8.835 0.751 86.11 26.01 10 Comparative Example 2 8.880 0.752 86.06 26.08 10 Comparative Example 3 8.819 0.748 85.54 25.69 10 Comparative Example 4 8.828 0.749 85.44 25.64 10 Comparative Example 5 8.824 0.750 85.59 25.73 10 Comparative Example 6 8.832 0.753 86.17 26.05 10 Comparative Example 7 8.848 0.750 85.74 25.84 10 Comparative Example 8 8.837 0.749 85.77 25.81 10 Comparative Example 9 8.827 0.75 85.31 25.61 10 Comparative Example 10 8.870 0.752 85.96 25.97 10 Comparative Example 11 8.863 0.752 85.97 25.99 10 Comparative Example 12 8.846 0.751 85.72 25.83 10 Comparative Example 13 8.832 0.751 85.91 25.84 10

[0204] According to Examples 1-7 in Table 1, when depositing to form a sub-doped layer, adding Ar helps to improve the crystallization rate, thereby improving the fill factor and conversion efficiency of the prepared heterojunction battery; in particular, when the flow rate of Ar is the corresponding SiH 4 When the flow rate is 10 times that of the conventional method, the fill factor and conversion efficiency are significantly improved.

[0205] By comparing the embodiment and comparative example 1, it can be seen that the short-circuit current, fill factor and conversion efficiency can be significantly improved by providing a silicon oxide protective layer.

[0206] By comparing the embodiment and comparative example 2, it can be seen that when the thickness of the silicon oxide protective layer is too thin, it is difficult to significantly improve the filling factor and conversion efficiency. Only when the thickness of the silicon oxide protective layer is optimized can the filling factor and conversion efficiency be significantly improved.

[0207] By comparing the embodiment and comparative example 3, it can be seen that the deposition of the amorphous silicon layer (i.e., the front passivation layer) of the present invention can effectively improve the short-circuit current, open-circuit voltage, fill factor and conversion efficiency of the heterojunction battery compared to depositing only one amorphous silicon layer.

[0208] By comparing the embodiment and comparative examples 4 and 5, it can be seen that the deposition of the multi-layer sub-doping layer of the present invention can effectively improve the short-circuit current, open-circuit voltage, fill factor and conversion efficiency of the heterojunction battery.

[0209] By comparing the embodiment and comparative example 6, it can be seen that when the thickness of the front doping layer is less than 20 nm, it is difficult to improve the short-circuit current, open-circuit voltage, fill factor and conversion efficiency.

[0210] By comparing the embodiment and comparative examples 7, 8 and 9, it can be seen that depositing an amorphous silicon layer (ie, a front passivation layer) by the preparation method of the present invention can improve short-circuit current, fill factor and conversion efficiency.

[0211] By comparing the embodiment and comparative examples 10, 11, 12 and 13, it can be seen that depositing the front doping layer by the preparation method of the present invention can improve the short-circuit current, fill factor and conversion efficiency.

[0212] In summary, the heterojunction cell 010 without a TCO layer on the front side prepared by the preparation method of the present invention can be used in photovoltaic modules, and the heterojunction cell 010 without a TCO layer on the front side has higher conversion efficiency and fill factor.

[0213] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A heterojunction battery without a TCO layer on the front side, characterized in that: include: A silicon substrate (100); the silicon substrate (100) has a first surface and a second surface that are arranged opposite to each other; A first passivation layer (210), wherein the first passivation layer (210) is deposited on the first surface; a first doping layer (220), the first doping layer (220) being deposited on a side of the first passivation layer (210) facing away from the silicon substrate (100); an anti-reflection composite layer (230), the anti-reflection composite layer (230) being deposited on a side of the first doping layer (220) facing away from the first passivation layer (210); A second passivation layer (310), the second passivation layer (310) being deposited on the second surface; a second doping layer (320), the second doping layer (320) being deposited on a side of the second passivation layer (310) facing away from the silicon substrate (100); a transparent conductive layer (330), the transparent conductive layer (330) being deposited on a side of the second doped layer (320) facing away from the second passivation layer (310); a first electrode (410), the first electrode (410) being disposed on the anti-reflection recombination layer (230) and in contact with the first doping layer (220); and, A second electrode (420), the second electrode (420) being arranged on the transparent conductive layer (330); The anti-reflection composite layer (230) comprises a silicon oxide protective layer (231) and an anti-reflection layer (232); the silicon oxide protective layer (231) is deposited on a side of the first doping layer (220) away from the first passivation layer (210); and the anti-reflection layer (232) is deposited on a side of the silicon oxide protective layer (231) away from the first doping layer (220); The first electrode (410) is arranged on the anti-reflection layer (232), and passes through the anti-reflection layer (232) to contact the silicon oxide protective layer (231) and the first doping layer (220); The step of depositing a first passivation layer (210) on the first surface specifically comprises: SiH4 is deposited by very high frequency plasma chemical vapor deposition at a vacuum pressure of less than or equal to 0.015 mbar, the temperature of the silicon substrate (100) is 160-200° C., the flow rate of SiH4 is 115-135 sccm, the pressure is 0.4-0.6 torr, and the deposition power is 30-40 mW / cm 2 Under certain conditions, a first amorphous silicon film layer (211) is deposited on the first surface; SiH4 is deposited by very high frequency plasma chemical vapor deposition at a vacuum pressure less than or equal to 0.015 mbar, the temperature of the silicon substrate (100) is 160-200° C., the flow rate of SiH4 is 115-135 sccm, the pressure is 0.3-0.4 torr, and the deposition power is 10-20 mW / cm 2 Under the following conditions, a second amorphous silicon film layer (212) is deposited on the first amorphous silicon film layer (211); SiH4 and H2 are deposited by very high frequency plasma chemical vapor deposition in a vacuum pressure less than or equal to 0.015 mbar, the temperature of the silicon substrate (100) is 160-200° C., the flow rate of SiH4 is 140-160 sccm, the flow rate of H2 is 140-160 sccm, the pressure is 0.4-0.6 torr, and the deposition power is 8-12 mW / cm 2 Under the following conditions, a hydrogenated amorphous silicon passivation film layer (213) is deposited on the second amorphous silicon film layer (212); The step of depositing a first doping layer (220) on the first passivation layer (210) specifically comprises: SiH4, H2 and PH3 gas with a volume concentration of 5-7% are used in a very high frequency plasma chemical vapor deposition method, at a vacuum pressure less than or equal to 0.015 mbar, the temperature of the silicon substrate (100) is 210-250° C., the flow rate of SiH4 is 18-22 sccm, the flow rate of H2 is 500-600 sccm, the flow rate of PH3 is 16-20 sccm, the pressure is 3-7 torr, and the deposition power is 230-270 mW / cm 2 Under certain conditions, a microcrystalline silicon seed layer (221) is deposited on the first passivation layer (210), and the microcrystalline silicon seed layer (221) is an N-type amorphous silicon layer; and a microcrystalline silicon doping layer (222) is deposited on the microcrystalline silicon seed layer (221); The step of depositing a microcrystalline silicon doping layer (222) on the microcrystalline silicon seed layer (221) specifically comprises: SiH4, H2 and PH3 gas with a volume concentration of 5-7% are used in a very high frequency plasma chemical vapor deposition method, at a vacuum pressure less than or equal to 0.015 mbar, the temperature of the silicon substrate (100) is 210-250° C., the pressure is 4-6 torr, and the deposition power is 230-270 mW / cm 2 Under the following conditions, at least three sub-doped layers (2221) are sequentially deposited, and the sub-doped layers (2221) are N-type microcrystalline silicon doped layers (222); when depositing the sub-doped layer (2221) attached to the side of the microcrystalline silicon seed layer (221) away from the first passivation layer (210), the ratio of the flow rate of PH3 gas to the flow rate of SiH4 is (0.8-1.2): (0.8-1.2), the flow rate of SiH4 is 13-17 sccm, and the flow rate of H2 is 500-600 sccm; the flow rate of SiH4 for the subsequent deposition of other sub-doped layers (2221) is gradually increased; when depositing the sub-doped layer (2221), argon gas is added, and the flow rate of the argon gas is 5-15 times the flow rate of SiH4 when depositing the sub-doped layer (2221).

2. The heterojunction cell without a TCO layer on the front side according to claim 1, characterized in that: The anti-reflection layer (232) comprises a first anti-reflection film (2321), a second anti-reflection film (2322), and a third anti-reflection film (2323) stacked in sequence, wherein the first anti-reflection film (2321) is arranged on a side of the silicon oxide protective layer (231) away from the first doping layer (220).

3. The heterojunction cell without a TCO layer on the front side according to claim 2, characterized in that: The refractive indexes of the first anti-reflection film (2321), the second anti-reflection film (2322) and the third anti-reflection film (2323) decrease successively, wherein the refractive index of the first anti-reflection film (2321) is 2.3~2.8, the refractive index of the second anti-reflection film (2322) is 2.1~2.4, and the refractive index of the third anti-reflection film (2323) is 1.8~2.

2.

4. The heterojunction cell without a TCO layer on the front side according to claim 2, characterized in that: The thickness of the first anti-reflection film (2321) is 10-35 nm, the thickness of the second anti-reflection film (2322) is 10-35 nm, and the thickness of the third anti-reflection film (2323) is 20-55 nm.

5. The heterojunction cell without a TCO layer on the front side according to claim 4, characterized in that: The thicknesses of the first anti-reflection film (2321), the second anti-reflection film (2322), and the third anti-reflection film (2323) increase sequentially.

6. The heterojunction cell without a TCO layer on the front side according to claim 1, characterized in that: The thickness of the silicon oxide protective layer (231) is 1-5 nm.

7. The heterojunction cell without a TCO layer on the front side according to claim 1, characterized in that: The thickness of the first doping layer (220) is 20-60 nm, and the thickness of the second doping layer (320) is 15-45 nm.

8. The heterojunction cell without a TCO layer on the front side according to claim 7, characterized in that: The thickness of the first doping layer (220) is greater than the thickness of the second doping layer (320).

9. The heterojunction cell without a TCO layer on the front side according to claim 1, characterized in that: The thickness of at least one of the first passivation layer (210) and the second passivation layer (310) is 5-15 nm; The thickness of the transparent conductive layer (330) is 80-140 nm; The thickness of the silicon substrate (100) is 80-180 μm.

10. A photovoltaic module, characterized in that: A heterojunction battery without a TCO layer on the front side comprising the method according to any one of claims 1 to 9.

11. A method for preparing a heterojunction battery without a TCO layer on the front side, characterized in that: The method for preparing a heterojunction battery without a TCO layer on the front side is used to prepare the heterojunction battery without a TCO layer on the front side according to any one of claims 1 to 9; The method for preparing the heterojunction battery without a TCO layer on the front side comprises: Texturing on a first surface and a second surface of a silicon substrate (100) that are arranged opposite to each other; Depositing a first passivation layer (210) on the first surface, and depositing a second passivation layer (310) on the second surface; Depositing a first doping layer (220) on the first passivation layer (210), and depositing a second doping layer (320) on the second passivation layer (310); Depositing the first doping layer (220) to form an anti-reflection composite layer (230), and depositing the second doping layer (320) to form a transparent conductive layer (330); A first electrode (410) is arranged on the anti-reflection recombination layer (230), and the first electrode (410) passes through the anti-reflection recombination layer (230) to contact the first doping layer (220); A second electrode (420) is provided on the transparent conductive layer (330); The step of depositing an anti-reflection composite layer (230) on the first doping layer (220) specifically comprises: depositing a silicon oxide protective layer (231) on the first doping layer (220), and depositing an anti-reflection layer (232) on the silicon oxide protective layer (231); The step of depositing a first passivation layer (210) on the first surface specifically comprises: SiH4 is deposited by very high frequency plasma chemical vapor deposition at a vacuum pressure of less than or equal to 0.015 mbar, the temperature of the silicon substrate (100) is 160-200° C., the flow rate of SiH4 is 115-135 sccm, the pressure is 0.4-0.6 torr, and the deposition power is 30-40 mW / cm 2 Under certain conditions, a first amorphous silicon film layer (211) is deposited on the first surface; SiH4 is deposited by very high frequency plasma chemical vapor deposition at a vacuum pressure less than or equal to 0.015 mbar, the temperature of the silicon substrate (100) is 160-200°C, the flow rate of SiH4 is 115-135 sccm, the pressure is 0.3-0.4 torr, and the deposition power is 10-20 mW / cm 2 Under the following conditions, a second amorphous silicon film layer (212) is deposited on the first amorphous silicon film layer (211); SiH4 and H2 are deposited by very high frequency plasma chemical vapor deposition in a vacuum pressure less than or equal to 0.015 mbar, the temperature of the silicon substrate (100) is 160-200° C., the flow rate of SiH4 is 140-160 sccm, the flow rate of H2 is 140-160 sccm, the pressure is 0.4-0.6 torr, and the deposition power is 8-12 mW / cm 2 Under the following conditions, a hydrogenated amorphous silicon passivation film layer (213) is deposited on the second amorphous silicon film layer (212); The step of depositing a first doping layer (220) on the first passivation layer (210) specifically comprises: SiH4, H2 and PH3 gas with a volume concentration of 5-7% are used in a very high frequency plasma chemical vapor deposition method, at a vacuum pressure less than or equal to 0.015 mbar, the temperature of the silicon substrate (100) is 210-250° C., the flow rate of SiH4 is 18-22 sccm, the flow rate of H2 is 500-600 sccm, the flow rate of PH3 is 16-20 sccm, the pressure is 3-7 torr, and the deposition power is 230-270 mW / cm 2 Under certain conditions, a microcrystalline silicon seed layer (221) is deposited on the first passivation layer (210), and the microcrystalline silicon seed layer (221) is an N-type amorphous silicon layer; and a microcrystalline silicon doping layer (222) is deposited on the microcrystalline silicon seed layer (221); The step of depositing a microcrystalline silicon doping layer (222) on the microcrystalline silicon seed layer (221) specifically comprises: SiH4, H2 and PH3 gas with a volume concentration of 5-7% are used in a very high frequency plasma chemical vapor deposition method, at a vacuum pressure less than or equal to 0.015 mbar, the temperature of the silicon substrate (100) is 210-250° C., the pressure is 4-6 torr, and the deposition power is 230-270 mW / cm 2 Under the following conditions, at least three sub-doped layers (2221) are sequentially deposited, and the sub-doped layers (2221) are N-type microcrystalline silicon doped layers (222); when depositing the sub-doped layer (2221) attached to the side of the microcrystalline silicon seed layer (221) away from the first passivation layer (210), the ratio of the flow rate of PH3 gas to the flow rate of SiH4 is (0.8-1.2): (0.8-1.2), the flow rate of SiH4 is 13-17 sccm, and the flow rate of H2 is 500-600 sccm; the flow rate of SiH4 for the subsequent deposition of other sub-doped layers (2221) is gradually increased; when depositing the sub-doped layer (2221), argon gas is added, and the flow rate of the argon gas is 5-15 times the flow rate of SiH4 when depositing the sub-doped layer (2221).

12. The method for preparing a heterojunction battery without a TCO layer on the front side according to claim 11, characterized in that: The step of depositing a silicon oxide protective layer (231) on the first doping layer (220) specifically comprises: Atomic deposition is carried out at a temperature of 200-250°C using silicon source and ozone as deposition raw materials; the pre-waiting time before the start of the reaction is 50-70s, and the reaction cycle corresponds to the characteristic times of Si pulse time 0.05-0.15s, Si purge time 0.5-1.5s, O3 pulse time 0.5-1.5s, O3 purge time 0.5-1.5s, and plasma power 2-4kW.

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