A method and device for reducing lightweight LDPC hard decoding read latency for TLC-type NAND Flash

Abstract

A method and device for reducing read latency of lightweight LDPC hard decoding for TLC-type NAND Flash, relating to the field of solid-state storage. In order to solve the technical problem in the prior art that when the original bit error rate of data in the flash memory is high, LDPC code decoding requires not only more perception levels but also a large number of decoding iterations, thereby causing serious read latency problems, the technical solution provided by the present invention is: a method for reducing read latency, the method comprising: collecting block numbers in a storage device and determining feature word line numbers; reading LSB page data of feature word lines and recording the number of iterations; calculating the voltage offset of at least one overlapping area according to the number of iterations; adjusting the read reference voltage position according to the voltage offset, and reading all data. A method for reducing read latency of hard decoding implemented according to the read latency reduction method. Suitable for application in lightweight LDPC hard decoding of TLC-type NAND Flash.

Description

Technical Field

[0001] The present invention relates to the field of solid-state storage, and in particular to a method for reducing hard decoding read latency. Background Art

[0002] NAND flash memory has been widely used due to its advantages such as non-volatility, fast read and write speed, large storage capacity and low power consumption. However, with the continuous improvement of storage density, the problem of data reliability has become more serious. LDPC code, as a technology that can reduce the noise interference of flash memory channels, is currently widely used in NAND flash memory to improve data reliability. When using LDPC code, hard decision decoding is first adopted. If the hard decision decoding fails, soft decision decoding is used instead. However, soft decision decoding requires a large number of perception levels, which causes serious reading delays. Therefore, hard decision decoding should be guaranteed to be successful as much as possible. LDPC hard decoding, as the first decoding method used in the decoding process, can be used in the entire stage of flash memory use. However, when the RBER of the data is high, the LDPC code not only requires more perception levels, but also requires a large number of iterations, which causes serious reading delay problems. Therefore, how to reduce the reading delay of NAND flash memory has become an important research topic to improve the performance of flash memory. Summary of the invention

[0003] In order to solve the technical problem in the prior art that when the original bit error rate of data in the flash memory is high, LDPC code decoding requires not only more perception levels but also a large number of decoding iterations, thereby causing serious read delay problems, the technical solution provided by the present invention is:

[0004] A method for reducing read latency, the method comprising:

[0005] The step of collecting the block number in the storage and determining the characteristic word line number;

[0006] Read the LSB page data of the feature word line and record the number of iterations;

[0007] A step of calculating a voltage offset of at least one overlapping region according to the number of iterations;

[0008] According to the voltage offset, the read reference voltage position is adjusted, and all data are read.

[0009] Furthermore, a preferred embodiment is provided, in which the LSB page data of the characteristic word line is read by hard decision.

[0010] Furthermore, a preferred embodiment is provided to calculate the voltage offsets of the seven overlapping regions.

[0011] Furthermore, a preferred embodiment is provided, wherein the voltage offset is read by hard decision.

[0012] A read latency reduction device, the device comprising:

[0013] A module for collecting block numbers in storage and determining characteristic word line numbers;

[0014] A module that reads the LSB page data of a feature word line and records the number of iterations;

[0015] A module for calculating a voltage offset of at least one overlapping region according to the number of iterations;

[0016] According to the voltage offset, the read reference voltage position is adjusted, and all data modules are read.

[0017] A method for reducing lightweight LDPC hard decoding read latency for TLC-type NAND Flash, the method comprising:

[0018] The step of collecting a read reference voltage in a memory and a number of iterations at an optimal read reference voltage;

[0019] The step of establishing a linear function model of the number of iterations and the voltage offset according to the difference between the number of iterations under the read reference voltage and the optimal read reference voltage;

[0020] When data needs to be read, the method is used to process the data according to the linear function model of the number of iterations and the voltage offset.

[0021] A device for reducing read latency of lightweight LDPC hard decoding for TLC-type NAND Flash, the device comprising:

[0022] A module for collecting a read reference voltage in a storage and a number of iterations under an optimal read reference voltage;

[0023] A module for establishing a linear function model of the number of iterations and the voltage offset according to the difference between the number of iterations under the read reference voltage and the optimal read reference voltage;

[0024] When data needs to be read, a module for processing data using the device is used according to the linear function model of the number of iterations and the voltage offset.

[0025] A computer storage medium is used to store a computer program. When the computer program is read by a computer, the method for reducing the read latency is implemented.

[0026] A computer includes a processor and a storage medium. When the processor reads a computer program stored in the storage medium, the read latency reduction method is implemented.

[0027] A computer program product, when read by a processor, implements the read latency reduction method.

[0028] Compared with the prior art, the technical solution provided by the present invention is beneficial in that:

[0029] The present invention provides a method for reducing read latency of lightweight LDPC hard decoding for TLC-type NAND Flash, which achieves the effect of accurately predicting voltage offset by establishing a function model of the number of iterations and the read reference voltage offset. Compared with the traditional LDPC soft decoding method that requires multiple read and write operations and senses multiple voltage levels, the model of the present invention can be applied online in real time, and the optimal voltage offset can be obtained through a small number of iterations, thereby greatly reducing the read latency.

[0030] The present invention provides a method for reducing the read latency of a lightweight LDPC hard decoding for TLC-type NAND Flash, which achieves the effect of reducing the amount of data read by selecting a characteristic word line or page, reading a small amount of data and recording the number of iterations, and then calculating the voltage offset according to the model. The existing method needs to read the data of all word lines and pages and sense more voltage levels, while the present invention reduces the reading operation and the sensing level through the selection of characteristic word lines and pages, significantly reducing the read latency and hardware overhead.

[0031] The present invention provides a method for reducing read latency of lightweight LDPC hard decoding for TLC-type NAND Flash. In the offline stage, the difference between the number of iterations of the default and optimal read reference voltages under different P / E times and dwell times is tested, and a linear model of the number of iterations and the read reference voltage offset is established, thereby achieving the effect of improving decoding efficiency. Compared with traditional methods, the offline model establishment of the present invention provides accurate voltage offset prediction, improves LDPC hard decoding efficiency, and reduces read latency.

[0032] The present invention provides a method for reducing the read latency of a lightweight LDPC hard decoding for TLC-type NAND Flash. By using a scenario-based application model, a single characteristic word line is used to characterize the voltage characteristics of the entire block when reading a large amount of data, and a single page is used to characterize the voltage characteristics of the word line when reading a small amount of random data, thereby achieving the effect of adapting to different reading requirements. The traditional method uses a unified processing method for all data reading scenarios, which lacks flexibility, while the present invention optimizes different scenarios and improves the overall performance of the system.

[0033] The present invention provides a method for reducing read latency of lightweight LDPC hard decoding for TLC-type NAND Flash. In the online stage, by reading specific page data of characteristic word lines and recording the number of iterations, the voltage offset is calculated using the model established offline and the reference voltage position is adjusted, thereby reducing the read and write operations. The existing method requires more read and write operations when randomly reading a small amount of data, while the present invention characterizes a large range of data characteristics by reading a small amount of data, reducing the read and write operations and improving the system response speed.

[0034] The present invention provides a lightweight LDPC hard decoding read latency reduction method for TLC NAND Flash, which greatly reduces the read latency by reducing the number of iterations and perception voltage levels required for LDPC hard decoding. Compared with the existing LDPC soft decoding method that requires multiple perceptions and iterations, the present invention reduces the number of iterations and perception levels by accurately predicting the optimal read reference voltage offset, significantly improving the decoding efficiency.

[0035] The present invention provides a method for reducing read latency of lightweight LDPC hard decoding for TLC-type NAND Flash, which reduces unnecessary read and write operations and hardware complexity by using the reading of a small amount of data to characterize the characteristics of a large range of data, thereby achieving the effect of reducing hardware overhead. The existing method requires a large amount of hardware resources to support multiple read and write operations, while the present invention reduces hardware overhead and improves the flexibility and efficiency of the system by optimizing the reading method.

[0036] The present invention provides a method for reducing read latency of a lightweight LDPC hard decoding for a TLC-type NAND Flash, which is suitable for application in lightweight LDPC hard decoding work of a TLC-type NAND Flash. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 To establish the overall flow chart of the function model of decoding iteration number and read reference voltage offset;

[0038] Figure 2 This is a brief overall flow chart of the online operation of the lightweight LDPC hard decoding read latency reduction method for TLC NAND Flash;

[0039] Figure 3 The relationship between the number of decoding iterations and RBER is shown in the figure. The top is the LSB page, the middle is the CSB page, and the bottom is the MSB page.

[0040] Figure 4 Schematic diagram of 7 overlapping areas of TLC NAND flash memory;

[0041] Figure 5Figure 2 is a diagram of the fitting function model of the number of decoding iterations and the hard decision voltage offset, where (a) is LSB4, (b) is CSB2, (c) is CSB6, (d) is MSB1, (e) is MSB3, (f) is MSB5, and (g) is MSB7.

[0042] Figure 6 The workflow diagram of the lightweight read latency reduction method for reading a large amount of data;

[0043] Figure 7 This is a workflow diagram of the lightweight latency reduction method for the scenario of randomly reading a small amount of data;

[0044] Figure 8 This is a comparison chart of the latency reduction of the lightweight LDPC hard decoding read latency reduction method compared to the traditional method, where the left side is the LSB page, the middle is the CSB page, and the right side is the MSB page;

[0045] Fig. 9 This is a diagram showing the latency reduction effect of the single-page read method compared to the single-word line read method in the scenario of randomly reading a small amount of data. DETAILED DESCRIPTION

[0046] In order to make the advantages and benefits of the technical solution provided by the present invention more clearly reflected, the technical solution provided by the present invention is now further described in detail with reference to the accompanying drawings, specifically:

[0047] Embodiment 1: This embodiment provides a method for reducing read latency, the method comprising:

[0048] The step of collecting the block number in the storage and determining the characteristic word line number;

[0049] Read the LSB page data of the feature word line and record the number of iterations;

[0050] A step of calculating a voltage offset of at least one overlapping region according to the number of iterations;

[0051] According to the voltage offset, the read reference voltage position is adjusted, and all data are read.

[0052] Specific:

[0053] The technical solution provided in this embodiment aims to reduce the lightweight read latency and includes the following steps:

[0054] Characteristic word line determination: Determine the characteristic word line number according to the block number.

[0055] Data reading and recording: Hard decision reads the LSB, CSB and MSB page data of the feature word line and records the number of iterations.

[0056] Voltage offset calculation: Calculate the hard decision voltage offset of the 7 overlapping areas according to the number of iterations.

[0057] Reference voltage adjustment: adjust the read reference voltage position and read all data.

[0058] Decoding and output: If the decoding is successful, the result is output; if it fails, soft decision is intervened.

[0059] Embodiment 2: This embodiment further limits the read latency reduction method provided in Embodiment 1, and reads the LSB page data of the feature word line through hard decision.

[0060] Implementation method three: This implementation method further limits the read latency reduction method provided in implementation method one, and calculates the voltage offset of the seven overlapping areas.

[0061] Embodiment 4: This embodiment further limits the read latency reduction method provided in embodiment 3, and the voltage offset is read by hard decision.

[0062] Embodiment 5: This embodiment provides a device for reducing read latency, the device comprising:

[0063] A module for collecting block numbers in storage and determining characteristic word line numbers;

[0064] A module that reads the LSB page data of a feature word line and records the number of iterations;

[0065] A module for calculating a voltage offset of at least one overlapping region according to the number of iterations;

[0066] According to the voltage offset, the read reference voltage position is adjusted, and all data modules are read.

[0067] Embodiment 6: This embodiment provides a method for reducing lightweight LDPC hard decoding read latency for TLC-type NAND Flash, the method comprising:

[0068] The step of collecting a read reference voltage in a memory and a number of iterations at an optimal read reference voltage;

[0069] The step of establishing a linear function model of the number of iterations and the voltage offset according to the difference between the number of iterations under the read reference voltage and the optimal read reference voltage;

[0070] When data needs to be read, the method provided in the first embodiment is used to process the data according to the linear function model of the number of iterations and the voltage offset.

[0071] Specifically, the technical solution provided by this embodiment is as follows:

[0072] Step 1: Identify the problem

[0073] In the case of high RBER, LDPC code decoding of TLC NAND Flash causes severe read delay.

[0074] TLC NAND Flash is widely used, but its high storage density brings data reliability issues.

[0075] LDPC codes improve data reliability, but high RBER requires more sensing levels and decoding iterations, resulting in severe read latency.

[0076] Step 2: Build the model

[0077] The read latency is reduced by using a function model of the number of iterations and the read reference voltage offset.

[0078] process:

[0079] Data collection: The number of iterations at the default read reference voltage and the optimal read reference voltage are measured at different P / E (program / erase) times and dwell times.

[0080] Difference calculation: Calculate the difference between the optimal and default number of iterations.

[0081] Model construction: Establish a linear function model of the number of iterations and voltage offset.

[0082] Step 3: Offline Phase

[0083] Complete the establishment of the function model of the number of iterations and the hard decision read reference voltage offset.

[0084] process:

[0085] Chip testing: Test the chip at different P / E times and dwell times.

[0086] Data Logging: Reads data using the default read reference voltage and records the number of iterations.

[0087] Optimal Voltage Offset: Searches for the optimal read reference voltage offset and records the number of iterations under the optimal condition.

[0088] Model building: Calculate the difference between the optimal and default number of iterations and build a function model.

[0089] Step 4: Online stage (reading large amounts of data)

[0090] Achieve lightweight read latency reduction.

[0091] process:

[0092] Characteristic word line determination: Determine the characteristic word line number according to the block number.

[0093] Data reading and recording: Hard decision reads the LSB, CSB and MSB page data of the feature word line and records the number of iterations.

[0094] Voltage offset calculation: Calculate the hard decision voltage offset of the 7 overlapping areas according to the number of iterations.

[0095] Reference voltage adjustment: adjust the read reference voltage position and read all data.

[0096] Decoding and output: If the decoding is successful, the result is output; if it fails, soft decision is intervened.

[0097] In step 4, it is necessary to calculate the read reference voltage offset through the model established in step 3 according to the number of iterations of the data actually read.

[0098] By applying the model in step 3 online, the read reference voltage can be quickly adjusted, thereby reducing the number of required iterations and lowering the read latency.

[0099] Step 5: Online phase (randomly reading a small amount of data)

[0100] Achieve lightweight read latency reduction.

[0101] process:

[0102] Word line determination: Determine the word line number based on the block number.

[0103] Data reading and recording: Hard decision reads the LSB page of the selected word line and records the iteration number.

[0104] Voltage offset calculation: Calculate the hard decision voltage offset of other pages according to the number of iterations of the LSB page.

[0105] Reference voltage adjustment: adjust the read reference voltage position and read all data.

[0106] Decoding and output: If the decoding is successful, the result is output; if it fails, soft decision is intervened.

[0107] The block number is:

[0108] NAND Flash memory organizes data according to a certain architecture, and the entire memory consists of multiple blocks. When designing the memory, the manufacturer assigns a number to each block according to a specific arrangement. In actual use, the file system or firmware maps these physical block numbers to logical block numbers to manage data storage and retrieval more efficiently.

[0109] The application of block number is:

[0110] When reading a large amount of data (step 4), the characteristic word line number is determined by the block number. The characteristic word line refers to a specific word line used to characterize the voltage offset characteristics of the entire block.

[0111] When a small amount of data is randomly read (step 5), a specific word line is selected for the read operation according to the block number.

[0112] Through the above steps, this implementation effectively solves the read latency problem of TLC NAND Flash:

[0113] In the process of model building, the number of iterations is used to characterize the RBER, and a linear function model of the number of iterations and the voltage offset is created.

[0114] During the scene adaptation process, lightweight methods were designed for reading large amounts of data and random reading of small amounts of data, reducing reading latency.

[0115] In the process of improving efficiency, in actual applications, there is no need to store redundant information. A large range of data characteristics can be represented by reading a small amount of data, which significantly reduces the read latency.

[0116] Embodiment 7: This embodiment provides a lightweight LDPC hard decoding read latency reduction device for TLC type NAND Flash, the device comprising:

[0117] A module for collecting a read reference voltage in a storage and a number of iterations under an optimal read reference voltage;

[0118] A module for establishing a linear function model of the number of iterations and the voltage offset according to the difference between the number of iterations under the read reference voltage and the optimal read reference voltage;

[0119] When data needs to be read, a module for processing data using the device provided in the fifth implementation mode is used according to the linear function model of the number of iterations and the voltage offset.

[0120] Embodiment 8: This embodiment provides a computer storage medium for storing a computer program. When the computer program is read by a computer, the method provided in embodiment 1 is implemented.

[0121] Embodiment 9: This embodiment provides a computer, including a processor and a storage medium. When the processor reads the computer program stored in the storage medium, the method provided in embodiment 1 is implemented.

[0122] Embodiment 10: This embodiment provides a computer program product. When the product is read by a processor, the method provided in embodiment 1 is implemented.

[0123] Implementation Method XI: Combination Figure 1-9The present implementation method is described in detail and completely through specific examples. Specifically:

[0124] This embodiment provides a method for reducing the read latency of lightweight LDPC hard decoding for TLC NAND Flash, which is mainly divided into two operation stages: offline stage and online stage. The offline stage mainly completes the establishment of the function model of the number of LDPC decoding iterations and the hard decision read reference voltage offset. The detailed workflow of this stage is as follows: Figure 1 shown.

[0125] The online stage mainly completes the implementation of lightweight read latency reduction methods in scenarios where large amounts of data are read or small amounts of data are randomly read. Fig. 9 It is shown that the performance of the read latency reduction method in the two scenarios when reading 100 word lines is similar. Therefore, this embodiment uses reading 100 word lines as the basis for judging the scenario of reading a large amount of data or randomly reading a small amount of data. The overall brief workflow of the online stage is as follows: Figure 2 shown.

[0126] Establish a functional model of decoding iteration number and read reference voltage offset

[0127] For LDPC decoding, people usually pay more attention to RBER information, but this parameter needs to be obtained by comparing the read data with the initial written data. In actual use, it is impossible to know the initial written data in advance, so it is not feasible to directly use RBER information. However, there is another key parameter in the decoding result, that is, the number of iterations, which does not require the knowledge of the initial written data and can be accurately obtained in actual use scenarios. Therefore, this embodiment first characterizes the relationship between the number of LDPC decoding iterations and RBER, such as Figure 3 As shown in the figure, it can be seen that for the LSB (least significant bit), CSB (central significant bit) and MSB (most significant bit) pages, as the RBER increases, the number of iterations also increases, so the number of iterations can be used as a representation of the RBER.

[0128] according to Figure 1The offline process experimental flow of establishing the decoding iteration number and voltage offset function model shown in the figure first tests the chip according to the program / erase (P / E) number and dwell time, and reads the data with the default read reference voltage, decodes and records the default iteration number, and at the same time searches for the offset of the optimal read reference voltage, reads the data with the optimal read reference voltage, and decodes and records the iteration number under the optimal read reference voltage. Then calculate the difference between the optimal and default iteration numbers, and finally establish the iteration number and offset function model.

[0129] According to the above process, this embodiment is aimed at Figure 4 The seven overlapping areas of the TLC NAND flash memory shown in the figure are respectively constructed Figure 5 The functional model of the relationship between the number of iterations and the read reference voltage offset is shown in FIG. Figure 5 From (a) to (g), it can be seen that the number of iterations in each overlapping region and the read reference voltage offset are approximately in a linear function relationship.

[0130] Figure 5 In the above, the model of 7 different overlapping areas in a word line has been constructed. The fitting functions of each overlapping area are linear, so any one of the fitting functions can be used to characterize the other fitting function models. However, the LSB page only needs one read level. Therefore, in this embodiment, for the scenario of randomly reading a small amount of data, only the fitting function of the LSB page is used as a standard to characterize the fitting functions of other pages, so that the reading overhead can be greatly improved. Formula (1) is the characterization function. When the fitting function of LSB4 is known, the fitting functions of the other 6 overlapping areas can be calculated using formula (1). F in formula (1) j represents the fitting function of the other six overlapping regions, α j and β j Respectively represent their respective fitting coefficients, Y LSB4 is the fitting function of the LSB page.

[0131] F j (Y j )=α j ·Y LSB4 +β j (j=1, 2, 3, 5, 6, 7) (1)

[0132] Lightweight read latency reduction method

[0133] After completing the construction of the function model between the number of iterations and the hard decision voltage offset, the lightweight read latency reduction method can be used in the data reading stage, that is, in the online process. This implementation method designs lightweight read latency reduction methods for scenarios of reading a large amount of data and randomly reading a small amount of data, which will be described in detail below.

[0134] (1) Lightweight read latency reduction method for reading large amounts of data

[0135] In the scenario of reading a large amount of data, this embodiment proposes a single word line lightweight read latency reduction method that uses only one word line to characterize the characteristics of other word lines in a block. Figure 6 The following is a detailed workflow diagram of this method.

[0136] from Figure 6 It can be seen that in the scenario of reading a large amount of data, when a read request is received, it is first necessary to determine the block numbers of the data to be read, and determine the initial read feature word line number in each block based on the block number. Then use hard decision to read the data of the LSB, CSB and MSB pages of the selected feature word line. After decoding and recording the number of iterations, the function model of the number of iterations and offset of each page is found, and the hard decision voltage offset of each of the 7 overlapping areas in the TLC flash memory is calculated according to the number of iterations. Then, the position of the read reference voltage is adjusted according to the calculated hard decision voltage offset of each overlapping area, and all the data is read. After reading all the data, if the decoding is successful, the decoding result is output. If the decoding fails, soft decision intervention is required. However, when using the method proposed in this embodiment, decoding can be successful in most cases, and the effect is very significant.

[0137] (2) Lightweight latency reduction method for random reading of small amounts of data

[0138] In the scenario of randomly reading a small amount of data, this embodiment proposes a method for reducing the single-page lightweight read latency by using only the LSB page in one word line to represent other word lines in a block. Figure 7 The following is a detailed workflow diagram of this method.

[0139] from Figure 7It can be seen that in the scenario of randomly reading a small amount of data, when a read request is received, the block number of the read data is first determined, and the word line number to be read is determined based on the block number. Then, only the LSB page of the selected word line is read and decoded by hard decision, the number of decoding iterations is recorded, and the number of iterations and the offset function model of the LSB page are found. Then, the hard decision voltage offset of the LSB page is calculated according to the model, and the hard decision voltage offsets of other pages are calculated based on the LSB page. Then all data is read according to the offset. Finally, if the decoding is successful, the decoding result is output. If the decoding fails, soft decision decoding intervenes. However, when using the method proposed in this embodiment, decoding can be successful in most cases, and the effect is very significant.

[0140] (3) Lightweight LDPC hard decoding read latency reduction effect

[0141] Figure 8 This is a latency performance comparison chart of the LSB, CSB, and MSB pages using the lightweight LDPC hard decoding read latency reduction method proposed in this embodiment and the traditional method when the entire block data is read 600 times with different dwell times. Here, the latency used by the traditional method is used as a unified benchmark and recorded as 100%. From this figure, it can be seen that whether it is a single word line read method suitable for reading a large amount of data or a single page read method suitable for randomly reading a small amount of data, the latency reduction is very obvious.

[0142] Fig. 9 This is a diagram showing the latency reduction effect of the single page read method compared to the single word line read method in the scenario of random reading of a small amount of data. From this figure, it can be seen that the single page read method proposed in this embodiment, which is suitable for random reading of a small amount of data, has significantly better latency performance than the single word line read method when reading a small amount of data.

[0143] In this implementation, the advantages are:

[0144] The LDPC hard decoding read latency reduction method is applicable to the entire life cycle of TLC NAND flash memory, and is also applicable to a variety of scenarios such as reading a large amount of data and randomly reading a small amount of data;

[0145] The LDPC hard decoding read latency reduction method uses the number of hard decision decoding iterations to characterize the RBER, so that redundant information does not need to be stored to obtain the RBER information, and the storage overhead is extremely small;

[0146] The LDPC hard decoding read latency reduction method uses a single word line to represent a block or a single page to represent other overlapping areas in a word line, and lightweight reads prior information, greatly reducing the read latency overhead;

[0147] The LDPC hard decoding read latency reduction method can fundamentally reduce the read errors of the flash memory, thereby reducing the number of LDPC perception levels under the same conditions, thereby reducing the read latency.

[0148] The technical solution provided by the present invention is further described in detail above through several specific implementation modes in order to highlight the advantages and benefits of the technical solution provided by the present invention. However, the several specific implementation modes described above are not intended to be used as limitations on the present invention. Any reasonable modification and improvement of the present invention, combination of implementation modes and equivalent substitution within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0149] In the description of this specification, only the preferred embodiments of the present invention are provided, and the scope of the rights of the present invention cannot be limited by this. In addition, the description of the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or N embodiments or examples in a suitable manner. In addition, the technical personnel in this field can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "N" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. Any process or method description in the flowchart or otherwise described herein can be understood to represent a module, fragment or portion of code including one or more executable instructions for implementing the steps of a custom logic function or process, and the scope of the preferred embodiment of the present invention includes other implementations, in which the functions may not be performed in the order shown or discussed, including in a substantially simultaneous manner or in a reverse order according to the functions involved, which should be understood by a person skilled in the art of the art to which the embodiments of the present invention belong. The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logic function, can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or device (such as a computer-based system, a system including a processor or other system that can fetch instructions from an instruction execution system, device or device and execute instructions), or in combination with these instruction execution systems, devices or devices. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit programs for use by an instruction execution system, device or device or in combination with these instruction execution systems, devices or devices. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection having one or N wirings (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM).In addition, the computer readable medium can even be paper or other suitable medium on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, then editing, interpreting or processing in other suitable ways as necessary, and then storing it in a computer memory. It should be understood that the various parts of the present invention can be implemented with hardware, software, firmware, or a combination thereof. In the above-mentioned embodiment, N steps or methods can be implemented with software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented with hardware, as in another embodiment, any one of the following technologies known in the art or their combination can be used to implement: a discrete logic circuit with a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit with a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0150] A person of ordinary skill in the art can understand that all or part of the steps carried by the method of the above-mentioned embodiment can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium, and the program, when executed, includes one or a combination of the steps of the method embodiment. In addition, each functional unit in each embodiment of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

Claims

1. A method for reducing lightweight LDPC hard decoding read latency for TLC-type NAND Flash, characterized in that: The method comprises: The step of collecting a read reference voltage in a memory and a number of iterations at an optimal read reference voltage; The step of establishing a linear function model of the number of iterations and the voltage offset according to the difference between the number of iterations under the read reference voltage and the optimal read reference voltage; When data needs to be read, the following method is used to process the data according to the linear function model of the number of iterations and the voltage offset: Methods include: The step of collecting the block number in the storage and determining the characteristic word line number; Read the LSB page data of the feature word line and record the number of iterations; A step of calculating a voltage offset of at least one overlapping region according to the number of iterations; According to the voltage offset, the read reference voltage position is adjusted, and all data are read.

2. A lightweight LDPC hard decoding read latency reduction device for TLC-type NAND Flash, characterized in that: The device comprises: A module for collecting a read reference voltage in a storage and a number of iterations under an optimal read reference voltage; A module for establishing a linear function model of the number of iterations and the voltage offset according to the difference between the number of iterations under the read reference voltage and the optimal read reference voltage; When data needs to be read, a module for processing data using the following device is used according to the linear function model of the number of iterations and the voltage offset: The device includes: A module for collecting block numbers in storage and determining characteristic word line numbers; A module that reads the LSB page data of a feature word line and records the number of iterations; A module for calculating a voltage offset of at least one overlapping region according to the number of iterations; According to the voltage offset, the read reference voltage position is adjusted, and all data modules are read.

3. A computer storage medium for storing a computer program, characterized in that: When the computer program is read by a computer, the method according to claim 1 is implemented.

4. A computer, comprising a processor and a storage medium, characterized in that: When the processor reads the computer program stored in the storage medium, the method of claim 1 is implemented.

5. A computer program product, characterized in that When the product is read by a processor, the method of claim 1 is implemented.

Images