A trench type SiC MOSFET device

Abstract

The present application relates to a kind of trench type SiC MOSFET devices, by introducing integrated schottky diode area and bipolar current enhancement area in trench type SiC MOSFET, effectively reduce the opening voltage when device reverse conduction, and simultaneously enhance the surge capacity of high-density bipolar current of device reverse conduction.The device structure of the present application and preparation are simple, compatible with the preparation process of conventional trench type SiC MOSFET, and can realize the production of high-performance, batched trench type SiC MOSFET devices.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor component preparation, and particularly relates to a trench type SiC MOSFET device. BACKGROUND

[0002] Silicon carbide (SiC) is a third-generation semiconductor material, which has excellent characteristics such as large band gap, high critical breakdown field strength and high thermal conductivity. The power device prepared based on the SiC material has excellent performances such as high breakdown voltage, high power density and high working frequency. Among them, the SiC MOSFET is a voltage-controlled switching device, which has competitiveness in high-temperature, high-frequency, high-voltage and high-power application occasions. In order to exert the advantages of the SiC MOSFET, further reduce the switching loss of the device and improve the ability of the device to conduct large current are important problems to be solved in the device design work.

[0003] The SiC MOSFET device structure contains a parasitic p-n diode, also known as a body diode. When the device is reversely turned on and the channel is closed, the current only flows through the body diode. Since the body diode works in a bipolar conduction mode, the turn-on voltage is large and the turn-off is slow. Therefore, integrating a Schottky diode in the SiC MOSFET device structure has become a common design scheme for reducing the switching loss of the device. However, although the integrated Schottky diode can significantly improve the switching capability of the device, it reduces the total area of the body diode in the device, weakens the ability of the device to reversely conduct high-density current, and greatly affects the reliability of the device. SUMMARY

[0004] The purpose of the present application is to provide a trench type SiC MOSFET device which not only utilizes the low turn-on voltage advantage of the integrated Schottky diode, but also further enhances the ability of the device to reversely conduct high-density current.

[0005] In order to achieve the above-mentioned purpose, the technical scheme adopted by the present application is as follows: a trench type SiC MOSFET device, comprising:

[0006] a heavily doped substrate of a first doping type;

[0007] a lightly doped first epitaxial layer of the first doping type, located on the upper surface of the substrate;

[0008] a first source trench, a gate trench and a second source trench, which are arranged on the epitaxial layer in a spaced manner;

[0009] a well region of a second doping type, located on the first epitaxial layer and on both sides of the gate trench;

[0010] a source region of the first doping type, located on the well region;

[0011] a contact region of a second doping type on the first epitaxial layer between the well region and the first source trench or the well region and the second source trench;

[0012] a gate dielectric layer on an inner surface of the gate trench;

[0013] a polysilicon layer of a first doping type on the gate dielectric layer, filling the gate trench;

[0014] a source ohmic contact layer on an upper surface of the first doping type source region and the second doping type contact region;

[0015] a Schottky contact layer on the first epitaxial layer in the first source trench;

[0016] a drain ohmic contact layer on a lower surface of the substrate;

[0017] a bipolar current enhancement region on the first epitaxial layer in the second source trench;

[0018] a bipolar current enhancement region contact layer on the bipolar current enhancement region in the second source trench.

[0019] Further, the first doping type is N-type and the second doping type is P-type.

[0020] Further, the first doping type is P-type and the second doping type is N-type.

[0021] Further, the bipolar current enhancement region contact layer is shorted to the source ohmic contact layer.

[0022] Further, the bipolar current enhancement region is integrated with the adjacent contact region.

[0023] The present application also provides another trench type SiC MOSFET device, comprising:

[0024] a heavily doped substrate of a first doping type;

[0025] a lightly doped first epitaxial layer of the first doping type on an upper surface of the substrate;

[0026] a first source trench, a gate trench, and a second source trench are spaced apart on the epitaxial layer;

[0027] a well region of a second doping type on the first epitaxial layer on one side of the gate trench;

[0028] a source region of the first doping type on the well region;

[0029] a contact region of a second doping type between the first epitaxial layer and the first source trench;

[0030] a gate dielectric layer on an inner surface of the gate trench;

[0031] a polysilicon layer of a first doping type on the gate dielectric layer, filling the gate trench;

[0032] a source ohmic contact layer on an upper surface of the source region of the first doping type and the contact region of the second doping type;

[0033] a Schottky contact layer in the first source trench on the first epitaxial layer;

[0034] a drain ohmic contact layer on a lower surface of the substrate;

[0035] a bipolar current enhancement region in and on both sides of the second source trench on the first epitaxial layer;

[0036] a bipolar current enhancement region contact layer on the bipolar current enhancement region 118.

[0037] Further, the bipolar current enhancement region extends to below the gate trench and the gate dielectric layer.

[0038] Compared with the prior art, the present application has the following beneficial effects: the present application provides a trench type SiC MOSFET device, which introduces an integrated Schottky diode region and a bipolar current enhancement region, effectively reduces the turn-on voltage when the device is reversely turned on, and at the same time enhances the surge capacity of high-density bipolar current when the device is reversely turned on. The device structure and preparation of the present application are simple, compatible with the preparation process of the conventional trench type SiC MOSFET, and can realize high-performance, batch-type trench type SiC MOSFET device production, which has great market potential and wide application prospect. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 is a cross-sectional structure schematic diagram of a trench type SiC MOSFET device of an embodiment of the present application;

[0040] Figure 2 is a cross-sectional structure schematic diagram of a trench type SiC MOSFET device of an embodiment of the present application;

[0041] Figure 3 is a cross-sectional structure schematic diagram of a trench type SiC MOSFET device of an embodiment of the present application. DETAILED DESCRIPTION

[0042] The present application will be further described below in combination with the drawings and embodiments.

[0043] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0044] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0045] like Figure 1 As shown, the first embodiment of the present invention provides a trench SiC MOSFET device, including:

[0046] A heavily doped substrate 101 of a first doping type;

[0047] A lightly doped first epitaxial layer 102 of a first doping type, located on the upper surface of the substrate 101;

[0048] A first source trench 104 , a gate trench 103 , and a second source trench 105 are spaced apart and opened on the epitaxial layer 102 ;

[0049] A well region 106 of the second doping type is located on the first epitaxial layer 102 and on both sides of the gate trench 103;

[0050] A source region 107 of a first doping type, located on the well region 106;

[0051] A contact region 108 of the second doping type is located on the first epitaxial layer 102 and between the well region 106 and the first source trench 104 or between the well region 106 and the second source trench 105 ;

[0052] a gate dielectric layer 109 , located on the inner surface of the gate trench 103 ;

[0053] A polysilicon layer 110 of a first doping type, located on the gate dielectric layer 109 and filling the gate trench 103;

[0054] A source ohmic contact layer 111 is located on the upper surfaces of the source region 107 of the first doping type and the contact region 108 of the second doping type;

[0055] a Schottky contact layer 112 , located on the first source trench 104 and the first epitaxial layer 102 ;

[0056] A drain ohmic contact layer 113 is located on the lower surface of the substrate 101;

[0057] a bipolar current enhancement region 114 located in the second source trench 105 and on the first epitaxial layer 102;

[0058] The bipolar current enhancement region contact layer 115 is located on the bipolar current enhancement region 114 and in the second source trench 105 .

[0059] The first doping type may be N-type, and the corresponding second doping type may be P-type. The first doping type may also be P-type, and the corresponding second doping type may be N-type.

[0060] The depth of the bipolar current enhancement region 114 may be shallower, deeper, or equal to that of the contact region 108 , and the doping concentration may be lower, higher, or equal to that of the contact region 108 .

[0061] The bipolar current enhancement region contact layer 115 may be short-circuited with the source ohmic contact layer 111 .

[0062] like Figure 2 As shown, the second embodiment of the present invention provides another trench SiC MOSFET device. Figure 1 The difference between the illustrated embodiments is that, in the second embodiment, the bipolar current enhancement region 116 is integrated with the adjacent contact region, and the bipolar current enhancement region contact layer 117 is integrated with the source region and the source ohmic contact layer on the upper surface of the contact region.

[0063] exist Figure 2 In the illustrated embodiment, the bipolar current enhancement region 116 may not be integrally connected to the adjacent contact region, or the bipolar current enhancement region contact layer 117 may not be integrally connected to the source region or the source ohmic contact layer on the upper surface of the contact region.

[0064] like Figure 3 As shown, the third embodiment of the present invention provides another trench SiC MOSFET device, including:

[0065] A heavily doped substrate 101 of a first doping type;

[0066] A lightly doped first epitaxial layer 102 of a first doping type, located on the upper surface of the substrate 101;

[0067] A first source trench 104 , a gate trench 103 , and a second source trench 105 are spaced apart and located on the epitaxial layer 102 ;

[0068] A well region 106 of the second doping type is located on the first epitaxial layer 102 and on one side of the gate trench 103;

[0069] a source region 107 of a first doping type on the well region 106;

[0070] a contact region 108 of a second doping type on the first epitaxial layer 102 between the well region 106 and the first source trench 104;

[0071] a gate dielectric layer 109 on the inner surface of the gate trench 103;

[0072] a polysilicon layer 110 of the first doping type on the gate dielectric layer 109, filling the gate trench 103;

[0073] a source ohmic contact layer 111 on the upper surface of the source region 107 of the first doping type and the contact region 108 of the second doping type;

[0074] a Schottky contact layer 112 in the first source trench 104 on the first epitaxial layer 102;

[0075] a drain ohmic contact layer 113 on the lower surface of the substrate 101;

[0076] a bipolar current enhancement region 118 on the first epitaxial layer 102 in the second source trench 105 and on both sides thereof;

[0077] a bipolar current enhancement region contact layer 119 on the bipolar current enhancement region 118.

[0078] The bipolar current enhancement region contact layer 119 can be located in the second source trench 105 or on the bipolar current enhancement region 118 between the second source trench 105 and the gate trench 103.

[0079] The bipolar current enhancement region 108 can extend below the gate trench 103 and the gate dielectric layer 109 to further enhance the ability of the region to conduct a high-density bipolar current and to protect the gate trench and shield a high electric field.

[0080] The present application provides a trench type SiC MOSFET device, by introducing an integrated Schottky diode region and a bipolar current enhancement region, effectively reducing the opening voltage when the device is reversely turned on, and at the same time enhancing the surge capacity of the high-density bipolar current when the device is reversely turned on. The device structure and preparation method of the present application are simple, compatible with the traditional trench type SiC MOSFET preparation process, can realize high-performance, batch production of trench type SiC MOSFET devices, has great market potential and wide application prospect.

[0081] The above merely describes preferred embodiments of the present application, but does not limit the present application in other forms, and any skilled person in the art can modify or change the above disclosed technical content into equivalent embodiments with equivalent changes. However, any simple modification, equivalent change and modification made on the above embodiments without departing from the technical solution content of the present application and according to the technical essence of the present application still belongs to the protection scope of the technical solution of the present application.

Claims

1. A trench SiC MOSFET device, characterized in that: include: a heavily doped substrate of a first dopant type; A lightly doped first epitaxial layer of a first doping type is located on the upper surface of the substrate; A first source trench, a gate trench, and a second source trench are spaced apart and arranged on the first epitaxial layer; A well region of the second doping type is located on the first epitaxial layer and on both sides of the gate trench; a source region of a first doping type, located on the well region; a contact region of the second doping type, located on the first epitaxial layer and between the well region and the first source trench or between the well region and the second source trench; a gate dielectric layer, located on an inner surface of the gate trench; a polysilicon layer of a first doping type, located on the gate dielectric layer and filling the gate trench; A source ohmic contact layer is located on the upper surfaces of the source region of the first doping type and the contact region of the second doping type; a Schottky contact layer, located in the first source trench and on the first epitaxial layer; a drain ohmic contact layer, located on the lower surface of the substrate; a bipolar current enhancement region, located in the second source trench and on the first epitaxial layer; The bipolar current enhancement region contact layer is located on the bipolar current enhancement region and in the second source trench.

2. A trench SiC MOSFET device according to claim 1, characterized in that: The first doping type is N-type, and the second doping type is P-type.

3. A trench SiC MOSFET device according to claim 1, characterized in that: The first doping type is P type, and the second doping type is N type.

4. A trench SiC MOSFET device according to claim 1, characterized in that: The bipolar current enhancement region contact layer is short-circuited with the source ohmic contact layer.

5. The trench SiC MOSFET device according to claim 1, wherein: The bipolar current enhancement region is connected to the adjacent contact region as a whole.

6. A trench SiC MOSFET device, characterized in that: include: a heavily doped substrate of a first dopant type; A lightly doped first epitaxial layer of a first doping type is located on the upper surface of the substrate; A first source trench, a gate trench, and a second source trench are spaced apart and arranged on the first epitaxial layer; A well region of the second doping type, located on the first epitaxial layer and on one side of the gate trench; a source region of a first doping type, located on the well region; a contact region of a second doping type, located on the first epitaxial layer and between the well region and the first source trench; a gate dielectric layer, located on an inner surface of the gate trench; a polysilicon layer of a first doping type, located on the gate dielectric layer and filling the gate trench; A source ohmic contact layer is located on the upper surfaces of the source region of the first doping type and the contact region of the second doping type; a Schottky contact layer, located in the first source trench and on the first epitaxial layer; a drain ohmic contact layer, located on the lower surface of the substrate; a bipolar current enhancement region, located in and on both sides of the second source trench and on the first epitaxial layer; The bipolar current enhancement region contact layer is located on the bipolar current enhancement region.

7. A trench SiC MOSFET device according to claim 6, characterized in that: The first doping type is N-type, and the second doping type is P-type.

8. The trench SiC MOSFET device according to claim 6, wherein: The first doping type is P type, and the second doping type is N type.

9. The trench SiC MOSFET device according to claim 6, wherein: The bipolar current enhancement region extends to below the gate trench and the gate dielectric layer.

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