Multilevel Inverter Modulation Method with Active Control and Common-Mode Voltage Suppression

Abstract

The present invention relates to the technical field of multilevel inverters, and specifically relates to a modulation method for a multilevel inverter with active control and common-mode voltage suppression. This method changes the sector division method based on the SVPWM space vector diagram, determines the large sectors and small regions by calculating the amplitude and angle of the reference vector; synthesizes the virtual vectors required for each sector based on the virtual vector synthesis principle; selects different virtual vector synthesis schemes based on the neutral point voltage deviation; calculates the action time of the virtual voltage vector according to the volt-second balance equation and distributes it to each basic voltage vector. The present invention can perform neutral point voltage balance control for any large sector and small region, and all controls are implemented through software without adding any hardware facilities, greatly reducing the control cost.

Description

Technical Field

[0001] The present invention relates to the technical field of multilevel inverters, and particularly to a modulation method for a multilevel inverter with active control and common-mode voltage suppression. Background Art

[0002] Multilevel inverters have been widely used in high-voltage and high-power scenarios such as AC motor drives and wind power converters due to their excellent output quality and low voltage step characteristics. Among them, the three-level neutral-point clamped (NPC) inverter has become one of the most popular multilevel inverter topologies with its unique advantages. However, during the operation of the NPC inverter, the balance problem of the neutral-point voltage has become a key factor restricting the further improvement of its performance. The imbalance of the midpoint (NP) voltage will lead to an increase in harmonic content, thereby reducing the quality of the output electrical energy, causing additional overstress to the switching devices and even damage, and at the same time increasing the capacitance burden of the filter in the power system. In addition, the imbalance of the midpoint voltage may also cause the generation of low-order harmonics on the motor side, threatening the stable operation of the overall system.

[0003] Therefore, maintaining the balance of the NP voltage is crucial for the stable operation of the NPC inverter. At present, the solutions to the midpoint voltage balance problem can be mainly divided into two categories: hardware control and software control. Hardware control methods include connecting a pair of DC power supplies with the same specifications at both ends of the upper and lower capacitors of the bus, extracting or injecting the midpoint current by applying an additional voltage at the midpoint, adopting a back-to-back structure, and adding a balance circuit at the front end. Although these methods have a significant inhibitory effect on the midpoint potential, due to the need to additionally increase complex hardware circuits, they lead to an increase in the system volume and cost. Therefore, the hardware control method is usually only applicable to specific occasions with extremely high requirements for midpoint potential balance and insensitive to volume and cost.

[0004] In practical applications, in order to avoid the volume and cost problems brought by the hardware control method, the software control method is usually adopted to solve the midpoint voltage balance problem. The software control method has the advantages of high flexibility and low cost, and has been widely promoted and applied in the application of NPC inverters.

[0005] The NPC converter has an inherent neutral-point (NP) imbalance problem, which may have a negative impact on the output electrical energy quality, cause additional overstress phenomena, and even damage the switching equipment. Therefore, quickly and effectively controlling the neutral-point balance is particularly important in the application of NPC three-level converters.

[0006] Regarding the challenge of NP voltage balance, an active control SVPWM method has been proposed. This method analyzes the three-phase current situation in real time and selects appropriate small vectors to compensate for the unbalanced charges generated by the medium vector. However, as the modulation ratio increases, the proportion of the medium vector gradually increases and its action time is correspondingly extended, making the compensation ability of the small vector seem inadequate. Therefore, in the case of high modulation index (MI) and low power factor (PF), the balance ability of this method is significantly limited and cannot maintain the stability of the NP voltage in the entire working range.

[0007] To achieve the goal of stably maintaining the NP voltage in the entire working range, a virtual vector PWM modulation method (VSVPWM) has been proposed. However, this method lacks active control ability and cannot take active measures to restore the balance when the NP voltage is unbalanced. In addition, neither of the above two methods considers the influence of the common-mode voltage. Excessive common-mode voltage may cause damage to the motor insulation, increase leakage current, and intensify electromagnetic interference.

[0008] In view of this, it is particularly urgent and important to propose a new method that can actively control the NP voltage in the entire working range while effectively suppressing the common-mode voltage. Summary of the Invention

[0009] Aiming at the deficiencies of the existing technology, the present invention discloses a multi-level inverter modulation method with active control and common-mode voltage suppression to solve the above problems.

[0010] The present invention is achieved through the following technical solutions:

[0011] The present invention provides a multi-level inverter modulation method with active control and common-mode voltage suppression, including the following steps:

[0012] Obtain the voltage SVPWM space vector diagram of the NPC three-level inverter;

[0013] Calculate the amplitude and angle of the reference vector, and judge the large sector and small region based on this;

[0014] Based on the virtual vector synthesis principle, synthesize the virtual vectors required for each sector;

[0015] Select the virtual vector synthesis scheme based on the neutral point voltage deviation;

[0016] Calculate the action time of the virtual voltage vector according to the volt-second balance equation;

[0017] Allocate to each basic voltage vector to achieve voltage output and neutral point voltage balance control.

[0018] Furthermore, in this method, the virtual vector synthesis scheme includes Scheme I, Scheme II, Scheme III, and Scheme IV.

[0019] Furthermore, in the method, Scheme I uses the following formula:

[0020]

[0021] V Vs1 = V s1(POO)

[0022] V Vs2 = V s2(OON)

[0023] Scheme II uses the following formula:

[0024]

[0025] V Vs1 = V s1(POO)

[0026] V Vs2 = V s2(OON)

[0027] Scheme III uses the following formula:

[0028]

[0029] V Vs1 = V s1(POO)

[0030] V Vs2 = V s2(OON)

[0031] Scheme IV uses the following formula:

[0032]

[0033] where O, P, N represent the switch states 0, positive, and negative respectively; V S1 , V S2 are virtual small vectors, V M1 is a virtual medium vector, V L1 , V L2 , V L3 , V L6 are all virtual long vectors.

[0034] Furthermore, in the method, when the capacitor voltage difference ΔV < 0, a positive current needs to flow out from the neutral point. When the currents ia > 0, ib > 0, and ic < 0, Schemes II and IV are selected, where ia, ib, and ic are three-phase currents.

[0035] Furthermore, in the method, when there is no corresponding NP equivalent current for the three-phase currents, such as when ia > 0, ib < 0, and ic > 0, Scheme IV is selected for the current situation.

[0036] Furthermore, in the method, when the three-phase load current meets the requirement of controlling the NP voltage, the negative small vector is directly used; if the requirement is not met, the virtual small vector synthesized by two large vectors is used.

[0037] Furthermore, in the method, the action time of the nearest three vectors used in each small region is calculated according to the volt-second balance equation. The calculation of Region0 is as follows:

[0038]

[0039] The calculation of Region1 is as follows:

[0040]

[0041] The calculation of Region2 is as follows:

[0042]

[0043]

[0044] The calculation of Region3 is as follows:

[0045]

[0046] The calculation of Region4 is as follows:

[0047]

[0048] Where T S is the switching period and m is the modulation index.

[0049]

[0050] After the switching action time of the nearest three vectors in each small region is calculated, the action time is allocated according to different virtual vector synthesis schemes. Where TV ref is the action time of the synthesized vector, V dc is the supply voltage, TV S1 , TV S2 is the virtual small vector, TV M1 is the virtual medium vector, TV L1 , TV L2 is the action time of the virtual long vector, V0 is the zero vector, θ is the phase, V S1 , V S2 is the virtual small vector, V M1 is the virtual medium vector, V L1 , V L2 is the virtual long vector.

[0051] The beneficial effects of the present invention are as follows:

[0052] The solution of the present invention proposes an innovative virtual vector synthesis method, aiming to effectively suppress the common-mode voltage. This method has the ability to control the neutral point voltage balance for any large sector and small area. All its control processes are implemented through software, without the need to add additional hardware facilities, significantly reducing the control cost. By carefully selecting appropriate switching states to synthesize virtual small vectors and virtual medium vectors, this method can effectively maintain the balance of the neutral point voltage within the entire working range. At the same time, this method can also actively regulate the balance of the neutral point voltage and effectively suppress the common-mode voltage, thus significantly improving the practicality of the NPC inverter. Description of the Drawings

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0054] Figure 1 is the topology diagram of the multilevel NPC inverter;

[0055] Figure 2 is the space vector diagram of the multilevel NPC inverter;

[0056] Figure 3 is the influence diagram of different switching states on the NP voltage;

[0057] Figure 4 is the virtual space vector diagram of the first sector;

[0058] Figure 5 is the flow chart of the AVSVPWM method;

[0059] Figure 6 is the space vector diagram after re-dividing the sectors;

[0060] Figure 7 is the diagram of virtual medium vector synthesis schemes Ⅰ-Ⅲ and virtual small vector synthesis scheme Ⅰ;

[0061] Figure 8 is the diagram of virtual medium vector synthesis scheme Ⅳ and virtual small vector synthesis scheme Ⅱ;

[0062] Figure 9 is the steady-state diagram of SVPWM (m = 0.3), (cosφ = 0.95);

[0063] Figure 10 is the steady-state diagram of SVPWM (m = 0.8), (cosφ = 0.95);

[0064] Figure 11 It is the steady-state diagram of VSVPWM (m = 0.3), (cosφ = 0.95);

[0065] Figure 12 It is the steady-state diagram of VSVPWM (m = 0.8), (cosφ = 0.95);

[0066] Figure 13 It is the steady-state diagram of AVSVPWM (m = 0.3), (cosφ = 0.95);

[0067] Figure 14 It is the steady-state diagram of AVSVPWM (m = 0.3), (cosφ = 0.95);

[0068] Figure 15 It is the steady-state diagram of SVPWM (m = 0.3), (cosφ = 0.35);

[0069] Figure 16 It is the steady-state diagram of SVPWM (m = 0.8), (cosφ = 0.35);

[0070] Figure 17 It is the steady-state diagram of VSVPWM (m = 0.3), (cosφ = 0.35);

[0071] Figure 18 It is the steady-state diagram of VSVPWM (m = 0.8), (cosφ = 0.35);

[0072] Figure 19 It is the steady-state diagram of AVSVPWM (m = 0.3), (cosφ = 0.35);

[0073] Figure 20 It is the steady-state diagram of AVSVPWM (m = 0.3), (cosφ = 0.35);

[0074] Figure 21 It is the comparison diagram of the dynamic situation of the NP voltage recovery (m = 0.3, cosφ = 0.95);

[0075] Figure 22 It is the comparison diagram of the dynamic situation of the NP voltage recovery (m = 0.8, cosφ = 0.95);

[0076] Figure 23 It is the comparison diagram of the dynamic situation of the NP voltage recovery (m = 0.3, cosφ = 0.35);

[0077] Figure 24It is a diagram comparing the dynamic situation of the NP voltage recovery (m = 0.8, cosφ = 0.35);

[0078] Figure 25 It is a diagram comparing the effective values of the common - mode voltage. Specific implementation manners

[0079] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0080] In one embodiment, a multi - level inverter modulation method with active control and common - mode voltage suppression is provided, including the following steps:

[0081] Obtain the voltage SVPWM space vector diagram of the NPC three - level inverter;

[0082] Calculate the amplitude and angle of the reference vector, and judge the large sector and small region based on this;

[0083] Based on the virtual vector synthesis principle, synthesize the virtual vectors required for each sector;

[0084] Select the virtual vector synthesis scheme based on the neutral - point voltage deviation;

[0085] Calculate the action time of the virtual voltage vector according to the volt - second balance equation;

[0086] Allocate to each basic voltage vector to achieve voltage output and neutral - point voltage balance control

[0087] After the above steps are completed, the inverter has successfully been modulated according to the virtual vector synthesis principle and achieved the balance control of the neutral - point voltage. However, this is only part of the modulation process. To further improve the stability and efficiency of the system, more refined control of the inverter is required.

[0088] First, according to the action time of each basic voltage vector, calculate and determine the switching sequence of the NPC three - level inverter. This process needs to fully consider various factors such as the working state of the inverter, load changes, and grid conditions to ensure that the switching sequence can effectively achieve voltage output and suppress the common - mode voltage.

[0089] Secondly, optimize the switching sequence. The goal of the optimization process is to reduce the number of switchings, lower the switching losses, and improve the efficiency of the inverter. This can be achieved by adopting advanced control algorithms and strategies, such as predictive control, fuzzy control, etc.

[0090] Then, apply the optimized switching sequence to the NPC three-level inverter to achieve its active control. By precisely controlling the switching states of the inverter, precise regulation of the output voltage can be realized, thus meeting the requirements of the load.

[0091] Finally, monitor and evaluate the operating status of the NPC three-level inverter in real time. By monitoring parameters such as the working status of the inverter, output voltage, current, and midpoint voltage, potential problems can be detected and solved in a timely manner to ensure the stable operation of the inverter. At the same time, according to the evaluation results of the operating status, the modulation method can be adjusted and optimized accordingly to further improve the performance and efficiency of the inverter.

[0092] In summary, the modulation method of this multilevel inverter realizes the precise modulation and efficient operation of the NPC three-level inverter by combining active control and common-mode voltage suppression technology. By continuously optimizing and improving the modulation method, the performance and stability of the inverter can be further enhanced to meet the requirements of various complex application scenarios.

[0093] This embodiment introduces the structure of an NPC-type three-level inverter. Each phase includes four power devices (SX1 to SX4) and two clamping diodes (Dx1 and Dx2), as Figure 1 shown. This design reduces the voltage stress of the switching devices by half compared to the two-level inverter. The DC side is composed of two identical capacitors (C1 and C2) connected in series and then paralleled with the DC power supply. Each phase is connected to the neutral point of the DC link through the clamping diodes, but this also leads to the problem that the capacitor voltages may be unbalanced.

[0094] Each phase of the NPC three-level inverter has three effective switching states, corresponding to three different voltage levels, as shown in Table 1. Among them, the conducting state of the power device is marked as 1, and the off state is marked as 0. When SX1 and SX2 are conducting simultaneously, it corresponds to state P, and at this time the output voltage of this phase is Vdc / 2; if SX2 and SX3 are conducting simultaneously, it is state O, and the output voltage is zero at this time; while when SX3 and SX4 are conducting simultaneously, it corresponds to state N, and the output voltage level is -Vdc / 2. It should be noted that to ensure the normal operation of the upper and lower bridge arms, SX1 and SX3 need to switch complementarily, and the switching method of SX2 and SX4 should also be the same.

[0095] Table 1 Switching functions of the multilevel NPC inverter

[0096]

[0097] The three-phase voltages output by the inverter are Va, Vb, and Vc. These phase voltages are 120° out of phase with each other in space. Express these phase voltages using sine functions:

[0098]

[0099] Perform vector addition on the above three-phase space voltage vectors to obtain the resultant vector Vref

[0100]

[0101] Substitute From formula (2), we get:

[0102] Substitute into

[0103]

[0104] Each phase of the NPC three-level inverter can output three levels: P, O, and N. A total of 27 level combinations can be output for the three phases. Substitute these combination methods into formula (3) to obtain Table 2. The following rules can be obtained from the calculation:

[0105] (1) Calculate the space vectors corresponding to all switch states. It is found that these space vectors can be divided into four categories according to the magnitude of the amplitude: The amplitude of 0 is defined as the zero vector, the amplitude of [amplitude value 1] is defined as the small vector, the amplitude of [amplitude value 2] is defined as the medium vector, and the amplitude of [amplitude value 3] is defined as the large vector.

[0106] (2) Among the basic vectors, there are 6 small vectors, 6 medium vectors, and 6 large vectors, and only 1 zero vector. The total number of basic vectors is 19, and the vectors of the same type are 60° out of phase with each other in space.

[0107] (3) The space vectors corresponding to some switch states are the same, such as [PPP], [OOO], [NNN], etc. The vector corresponding to one space vector with multiple switch states is called a redundant vector. If a vector corresponds to n switch states, the redundancy of this vector is called n. For example: the redundancy of the zero vector is 3, the redundancy of the small vector is 2, and the redundancy of the medium vector and the large vector is 1.

[0108] Table 2 Space vectors corresponding to each switch state

[0109]

[0110]

[0111] In this embodiment, the above 19 basic vectors and 27 switch states are plotted together in a rectangular coordinate system. The four types of vectors can divide each large sector into four small triangular regions. Its space vector diagram is asFigure 2 As shown in the figure. Among them, the small vectors correspond to the direction of the NP current according to the switching state, and are divided into positive small vectors and negative small vectors.

[0112] The balance of the DC-side NP voltage in this embodiment is crucial for the normal operation of the NPC inverter and is affected by the NP current. Different switching states determine the direction and magnitude of the NP current, specifically as Figure 1 shown. In the circuit corresponding to the large vectors, the phase current is directly connected to the positive and negative poles of the DC side, so no neutral point current will be generated, and the zero vectors will not affect the capacitor balance either. The voltage difference between the upper and lower capacitors is denoted as ΔV.

[0113] ΔV = V C1 -V C2

[0114] In the circuits corresponding to the medium vectors and small vectors, some of the phase currents are connected to the neutral point, as Figure 3 shown. In the figure, (a) is [PNN], (b) is [PON], (c) is [ONN], and (d) is [POO]. Therefore, NP current will inevitably be generated, causing the capacitor voltage to shift.

[0115] In order to achieve effective control of the NP voltage and reasonably use various switching states, Busquet-Monge et al. proposed a SVPWM method based on virtual space vectors, namely the VSVPWM method. This strategy cleverly uses redundant small vectors and medium vectors to construct virtual medium vectors and virtual small vectors, thereby ensuring that the average value of the neutral point current is zero within each switching period. On this basis, the researchers further optimized the synthesis scheme of the virtual vectors by selecting vectors in different sectors to construct virtual vectors, aiming to reduce the common-mode voltage and maintain the stability of the NP voltage.

[0116] Specifically, the VSVPWM modulation method forms new virtual medium vectors and virtual small vectors by combining the original vectors, and these vectors have no impact on the neutral point voltage. The main implementation approach is to incorporate two small vectors close to the medium vector into the construction process of the virtual medium vector and use the small vectors to compensate for the offset of the neutral point potential, thereby meeting the requirement of balancing the neutral point potential.

[0117] When deeply studying the VSVPWM method, its implementation steps are the same as those of the traditional SVPWM method. Taking the first sector as an example, a theoretical analysis of the newly constructed virtual vectors is carried out. As Figure 4 shown, the first sector is reallocated, and the original four small sectors are refined into five small sectors. Through the volt-second balance principle, the action time of each vector in each small sector can be accurately calculated to ensure the stable operation of the entire system.

[0118] Among them, VV0 is the virtual zero vector, VVS1 and VVS2 are the virtual small vectors, VVM1 is the virtual medium vector, and VVL1 and VVL2 are the virtual long vectors. The positions of the virtual zero vector, small vectors, and long vectors are the same as those of the traditional space vectors, and the position of the medium vector becomes the center of the triangle in the first sector. The zero vector has no influence on the midpoint voltage of the DC side. VV0 has the same position as the basic zero vector V0 in the traditional SVPWM method. Therefore, VV0 is defined as shown in formula (4).

[0119] V0 = V V0 (4)

[0120] The midpoint potential fluctuations caused by the two switching states corresponding to the basic small vectors in this embodiment are equal in value and opposite in direction, which are virtual small vectors.

[0121] They are synthesized by the positive and negative small vectors corresponding to these two switching states acting for equal time, and VVS1 and VVS2 are defined as shown in formula (5) and formula (6). The last "0" and "1" in VS10 and VS11 represent the switching states that cause different midpoint currents for the same small vector, and the corresponding switching states are POO and ONN respectively. The midpoint current generated by the synthesized virtual small vector in one cycle is 0. Therefore, the stability of the midpoint potential can be guaranteed.

[0122]

[0123] Compared with the medium vector VM1 in the traditional SVPWM modulation method, there are significant differences in the distribution positions of the virtual medium vector VVM1. It should be noted that VM1 lacks redundant switching states, resulting in the midpoint potential fluctuations caused by it being unable to be effectively controlled. In order to achieve the goal that the key current of the virtual medium vector VVM1 is zero in a complete cycle, we use the basic small vectors VVS1 and VVS2 and the basic medium vector VM1 for synthesis to construct the virtual medium vector. The specific synthesis method is shown in formula (7).

[0124] In the formula, VM1 represents the space voltage vector corresponding to the switching state PON, and the midpoint current generated by this vector is ib. The midpoint currents generated by VS11 and VS21 are ia and ic respectively. For a three-phase symmetrical circuit, the sum of the three-phase currents is always equal to zero. Therefore, the total current flowing into and out of the midpoint by the virtual medium vector in one cycle is zero. In addition, the direction of the virtual medium vector is the same as that of the basic space voltage medium vector, and its modulus is 2 / 3 of the basic medium vector.

[0125]

[0126] The distribution positions of the virtual large vectors are the same as those of the traditional SVPWM large vectors, and the large vectors do not generate midpoint current and have no influence on the midpoint potential. Therefore, the original basic large vectors are taken as the virtual large vectors, as shown in Formulas (8) and (9).

[0127] V VL1 =V L1 (8)

[0128] V VL2 =V L2 (9)

[0129] By using Figure 11 to calculate the action time of the virtual vectors, which does not correspond to the real switching states. Therefore, it is necessary to further transform it into the action time of the basic vectors, as shown in Formulas (10) to (14).

[0130]

[0131] T0 = T V0 (14)

[0132] Through the above in-depth analysis, the traditional virtual space vector modulation algorithm realizes the mutual cancellation of the midpoint current through the carefully designed switching state configuration, and then constructs effective virtual space vectors to complete the modulation process. This ensures that the sum of the midpoint currents within each switching period remains zero, thus effectively controlling the balance of the midpoint potential. This method not only optimizes the application effect of the virtual vectors, but also promotes the further development of the SVPWM technology.

[0133] Although the VSVPWM method can effectively control the NP voltage of the NPC inverter within the entire modulation index and power factor range, its application still has certain limitations. Specifically, this method mainly focuses on the performance optimization under steady-state conditions, while in the face of dynamic situations such as system disturbances or initial capacitor voltage imbalance, its active control ability is insufficient, which to a certain extent limits its wide promotion in practical applications.

[0134] In addition, it is worth noting that both of the above two methods show obvious deficiencies in dealing with the common-mode voltage problem of the NPC inverter. Excessive common-mode voltage will not only cause potential damage to the motor insulation, but also may lead to an increase in leakage current and an intensification of electromagnetic interference, all of which pose serious threats to the stable operation of the system. Therefore, in future research, we need to further explore how to effectively solve the common-mode voltage problem of the NPC inverter to further improve its performance in practical applications.

[0135] The common-mode voltage (CMV) in this embodiment is the voltage between the midpoint of the load and the DC link NP point. The definition of the common-mode voltage of the inverter under the PWM modulation method is shown in Equation (15):

[0136]

[0137] where VAO, VBO, and VCO are the phase voltages with respect to the NP potential.

[0138] In this embodiment, the common-mode voltage is composed of a series of DC voltages. As the main source of bearing current in the motor drive, its existence may cause the following problems: First, the risk of insulation failure. When the common-mode voltage exceeds the insulation tolerance range of electrical equipment, it may lead to a decrease in the insulation performance of the equipment, and then cause faults or safety hazards; Second, the electromagnetic interference problem. This interference will affect the performance and stability of the system operation, may interfere with the normal operation of other electronic devices, and have an adverse impact on wireless communication or other sensitive devices; Third, the voltage imbalance phenomenon. It may reduce the overall performance of the power system, cause overload or damage to power equipment, and have an adverse impact on other devices in the system; Fourth, the additional power loss. Since the common-mode voltage will cause additional current flow, resulting in an increase in power loss in the system.

[0139] In this embodiment, to effectively reduce the adverse effects of the common-mode voltage, the following measures can be taken: First, by selecting appropriate filters and isolation devices to reduce the level of the common-mode voltage; Second, adopt electromagnetic interference control measures such as ground wires and shielding to reduce the interference of the common-mode voltage on surrounding devices. However, a more convenient method is to optimize the system design to reduce the generation of the common-mode voltage from the source, such as by reasonably selecting the switching state.

[0140] The common-mode voltages corresponding to different switching states of the NPC three-level inverter are shown in Table 3. Observing the table, it can be seen that both the zero vector and the small vector have switching states with relatively high common-mode voltages, and their maximum peaks reach Vdc / 2 and Vdc / 3 respectively. When other vectors are used for PWM modulation, the common-mode voltage can be controlled at a lower level. In particular, when selecting the switching state with a common-mode voltage peak of Vdc / 6, the magnitude of the common-mode voltage can be significantly suppressed, thereby improving the stability and reliability of the system.

[0141] Table 3 Common-mode voltage table corresponding to different switching states

[0142]

[0143] In one embodiment, the present invention discloses a neutral point voltage balance control method for an NPC three-level inverter. The method mainly includes the following steps: First, based on the SVPWM space vector diagram, the sector division method is optimized and improved; Second, by accurately calculating the amplitude and angle of the reference vector, the specific ranges of the large sectors and small regions are accurately judged; Then, based on the virtual vector synthesis principle, the virtual vectors required for each sector are synthesized; Next, according to the neutral point voltage deviation situation, a suitable virtual vector synthesis scheme is selected; Finally, according to the volt-second balance equation, the action time of the virtual voltage vector is accurately calculated and reasonably distributed to each basic voltage vector.

[0144] The present invention can perform neutral point voltage balance control on any large sector and small region, and all its control processes are implemented through software programming without adding any additional hardware facilities, thus greatly reducing the control cost and improving the overall performance of the system.

[0145] According to the foregoing content, in order to achieve the goal that the influence on the NP voltage is zero at the end of a switching cycle, the traditional virtual vector modulation method only selects three vectors, namely ONN, PON, and PPO, for synthesizing the virtual middle vector. To further expand this idea, taking the first sector as an example, when the virtual middle vector is composed of three vectors, there are four different synthesis methods. Each synthesis method will have its own unique influence on the NP voltage, and the specific details are shown in Table 4.

[0146] Table 4 Alternative synthesis schemes for the virtual middle vector

[0147]

[0148] The switching states with relatively high common-mode voltage in Table 4 have been bolded. Without considering the case where the equivalent NP current is 0, it can be seen that only in Scheme II and Scheme III of the proposed method do there exist some switching states with relatively high common-mode voltage.

[0149] If the synthesized virtual vector only has a fixed influence on the NP voltage, then the synthesized virtual middle vector becomes an uncontrollable vector and cannot achieve active control of the NP voltage. Therefore, it is necessary to introduce a new synthesis method again. By using the middle vector across sectors to synthesize the virtual middle vector, the NP voltage can still be maintained stable. Taking the first sector as an example, it is specifically shown in Equation (16).

[0150]

[0151] For virtual small vectors, only the switching states corresponding to negative small vectors satisfy that the peak value of the common-mode voltage is less than Vdc / 3. Using only one switching state cannot actively control the NP voltage. Therefore, virtual small vectors must be introduced additionally. Taking the first sector as an example, its synthesis method is shown in Eqs. (17) and (18). This synthesis method is composed of two adjacent large vectors respectively, and the corresponding common-mode voltage is Vdc / 6. The virtual small vector synthesized by the two can significantly reduce the common-mode voltage. In addition, neither of the two states generates NP current. Therefore, the NP voltage can be kept stable.

[0152]

[0153] To sum up, there are two strategies for the implementation of virtual small vectors. When the three-phase load current meets the requirement of controlling the NP voltage, negative small vectors are directly adopted; if the requirement cannot be met, two large vectors are combined to form virtual small vectors to avoid additional influence on the NP voltage.

[0154] Through the above analysis, we can clarify that both virtual medium vectors and virtual small vectors have diverse synthesis strategies. It is particularly worth noting that among all these schemes, only two synthesis methods of virtual medium vectors involve switching states with a relatively high peak value of the common-mode voltage, so they can effectively meet the requirement of suppressing the common-mode voltage during the operation of the NPC inverter. Regarding the technical solution of the present invention, its space vector diagram is shown in Figure 6 as follows.

[0155] In this embodiment, through the above analysis, there are four synthesis schemes for virtual medium vectors and two schemes for virtual small vectors. When the ability to actively control the NP voltage is satisfied, the synthesis scheme shown in Figure 7 is adopted. When it is not satisfied, the synthesis scheme shown in Figure 8 is adopted.

[0156] In this embodiment, considering the characteristics of the real-time change of the three-phase current, the three-phase current must be introduced as a control parameter. Simply relying on the voltage difference between the two groups of capacitors to select the equivalent NP current to control the voltage balance, its accuracy obviously cannot meet the actual requirements. The directions of the NP current and the three-phase load current both follow the positive direction definition shown in Figure 1 , and there are six possible combinations of the magnitudes of the three-phase load currents, which are listed in detail in Table 5.

[0157] Taking the first sector as an example for in-depth analysis, when the capacitor voltage difference ΔV is less than zero, it indicates that a positive current needs to flow out from the neutral point. In this case, if both ia and ib are greater than zero and ic is less than zero, then Scheme II and Scheme IV become optional. Under these two schemes, the equivalent NP current of the virtual medium vector both shows a positive current flowing out, and the rest of the cases can be deduced by analogy.

[0158] To further optimize the scheme selection, the influence of the common-mode voltage needs to be fully considered. During the screening process, those switching states with all low common-mode voltages in the synthesis scheme should be preferentially selected. Taking Scheme IV as an example, its switching states are all the peak value of the common-mode voltage Vdc / 6. Therefore, on the premise that both Scheme II and Scheme IV can meet the requirement of controlling the NP voltage, Scheme IV is preferentially selected.

[0159] In addition, it is worth noting that in some special cases, such as when the three-phase currents cannot find the corresponding NP equivalent currents (for example, ia is greater than zero, ib is less than zero, ic is greater than zero), Scheme IV should be selected to avoid additional influence on the NP point potential. At this time, other schemes can be selected in the next cycle or small vectors in other sectors can be relied on to participate in the control together to ensure the stability and accuracy of the system operation.

[0160] Table 5 Specific selection method of the synthesis scheme of the virtual middle vector

[0161]

[0162]

[0163] In any region of this embodiment, there is at least one controllable vector to adjust the NP voltage, which is also the reason why this method can adjust the NP voltage within the full modulation index range, thereby improving the robustness of the system.

[0164] This embodiment takes the first large sector as an example. First, calculate the action time of the nearest three vectors used in each small region according to the volt-second balance equation. The calculation of Region0 is as follows:

[0165]

[0166] The calculation of Region1 is as follows:

[0167]

[0168]

[0169] The calculation of Region2 is as follows:

[0170]

[0171] The calculation of Region3 is as follows:

[0172]

[0173] The calculation of Region4 is as follows:

[0174]

[0175] Where T S is the switching period, and m is the modulation index.

[0176]

[0177] In this embodiment, after the switch action time of the three nearest vectors in each small area is calculated, the action time is allocated according to different virtual vector synthesis schemes, and the ultimate goal is to allocate the action time to 27 switch states.

[0178] In this embodiment, the so-called steady state specifically refers to a working state in which the upper and lower capacitor voltages maintain the same value in the initial stage. Figures 9 to 20 The steady-state performance comparison between the technical solution of the present invention and the existing SVPWM and VSVPWM technologies under various power factor and modulation ratio conditions is shown in detail. Through in-depth analysis of the graphical data, it can be clearly observed that under low modulation ratio conditions, the three methods can effectively control the NP voltage and show good steady-state characteristics.

[0179] However, as the modulation ratio gradually increases, the SVPWM technical solution shows a significant AC component in controlling the NP voltage, and its performance is significantly inferior to the other two methods. In addition, when examining the suppression effect of the common mode voltage (CMV), the technical solution of the present invention shows the best performance. It is particularly worth mentioning that when the modulation ratio is lower than 0.5, the technical solution of the present invention successfully controls the peak value of CMV within Vdc / 6, which fully demonstrates its efficient and stable voltage control capability.

[0180] In this embodiment, if Figures 21 to 24 As shown in the figure, we compare the NP voltage recovery of the technical solution of the present invention with the existing SVPWM and VSVPWM technologies under different modulation ratios and different power factors. By observing the comparison results, we can clearly see that the VSVPWM technology does not have the ability to actively control the NP voltage balance. However, in the actual application scenario of the inverter, due to non-ideal factors such as the insertion of dead time, the propagation delay of the gate signal, and the difference in the upper and lower capacitor values, the balance of the NP voltage is easily destroyed. Once the balance is broken, it will lead to the collapse of the entire system.

[0181] Although SVPWM technology has the ability to actively control NP voltage balance, its performance is affected by the modulation ratio and load power factor. When it exceeds the controllable area, including the NP recovery period, SVPWM technology will still have a large amount of AC ripple.

[0182] In contrast, the AVSVPWM technology of the present invention shows significant advantages. It is not affected by the load power factor and modulation ratio, and has active control capabilities in the entire working range. This means that the AVSVPWM technology can still effectively maintain the balance of NP voltage under the influence of non-ideal factors, without AC ripple and DC bias. Therefore, in practical applications, the AVSVPWM technology significantly improves the anti-interference ability of the inverter.

[0183] In this embodiment, if Figure 25 As shown in the figure, we have conducted a quantitative analysis of the advantages of the technical solution of the present invention in terms of CMV. Through simulation calculations, we compared the effective values ​​of the common-mode voltage under different modulation ratios and compared them with the other two methods. It can be clearly seen from the figure that within the entire modulation ratio range, the effective value of the common-mode voltage of AVSVPWM remains at the lowest level. This result fully verifies the correctness of the above theoretical analysis, thereby further highlighting the advantages of the technical solution of the present invention.

[0184] In summary, the scheme of the present invention proposes an innovative virtual vector synthesis method, which aims to effectively suppress the common-mode voltage. This method has the ability to balance the neutral point voltage of any large sector and small area. All control processes are implemented through software, without the need for additional hardware facilities, which significantly reduces the control cost. By carefully selecting appropriate switching states and synthesizing virtual small vectors and virtual middle vectors, this method can effectively maintain the balance of the midpoint voltage within the entire working range. At the same time, this method can also actively regulate the balance of the midpoint voltage and effectively suppress the common-mode voltage, thereby significantly improving the practicality of the NPC inverter.

[0185] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-level inverter modulation method with active control and common mode voltage suppression, characterized in that: The following steps are involved: Get the voltage SVPWM space vector diagram of the NPC three-level inverter; Calculate the amplitude and angle of the reference vector and use it to determine large sectors and small areas; Based on the principle of virtual vector synthesis, synthesize the virtual vectors required by each sector; Select a virtual vector synthesis scheme based on the neutral point voltage deviation; Calculate the action time of the virtual voltage vector according to the volt-second balance equation; Distributed to each basic voltage vector to achieve voltage output and midpoint voltage balance control; According to the action time of each vector and the synthesis scheme of the virtual vector, the specific action time corresponding to each switch state participating in the synthesis vector is determined to achieve voltage output and midpoint voltage balance control and common mode voltage suppression; The virtual vector synthesis schemes include scheme I, scheme II, scheme III and scheme IV; Scheme I uses the following formula: ， Scheme II uses the following formula: ， Scheme III uses the following formula: ， Scheme IV uses the following formula: ， Where O, P, and N represent the switch states 0, positive, and negative respectively; V S1（ONN） , V S1（POO） ,V S1（OPN） ,V S2（PPO） ,V S2（PNO） ,V S2（OON） is a virtual small vector, V VS1 , V VS2 V is a synthetic virtual small vector; M1(PON) is the virtual mean vector, V vM1 is the synthetic virtual middle vector voltage; V L1(PNN) , V L2（PPN） , V L3（NPN） , V L6（PNP） All are virtual large vectors; 。 2. The multi-level inverter modulation method with active control and common mode voltage suppression according to claim 1, characterized in that: In the method, The action time of the nearest three vectors used in each small area is calculated according to the volt-second balance equation, where: The calculation of region Region0 is as follows: The calculation for region Region1 is as follows: The calculation of region Region2 is as follows: The calculation of region Region3 is as follows: The calculation of region Region4 is as follows: Where T S is the switching period, m is the modulation index After the switching action time of the nearest three vectors in each small area is calculated, the action time is allocated according to different virtual vector synthesis schemes, where V ref is the reference vector, V dc is the supply voltage, T VS1 , T VS2 is the virtual small vector action time, T VM1 is the virtual vector action time, T VL1 , T VL2 is the virtual large vector action time, V0 is the zero vector, V V0 is the synthetic zero vector, T V0 is the zero vector action time, θ is the phase, V S1 , V S2 is a virtual small vector, V M1 is the virtual mean vector, V L1 , V L2 is a virtual large vector; V VS1 , V VS2 V is a synthetic virtual small vector; vM1 is the synthetic virtual middle vector voltage; V VL1 , V VL2 To synthesize a virtual large vector.

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