A virtual vector modulation method for dual inverters

Abstract

The present invention relates to the technical field of dual inverters, and specifically to a dual inverter virtual vector modulation method, which utilizes redundant small vectors and a middle vector to construct a virtual middle vector, combines them into a basic vector group, and synthesizes a reference vector; determines the position of the reference vector, selects adjacent non-zero voltage vectors and calculates the action time; calculates the action time of the zero vector, and synthesizes the final modulation signal according to the action time of each vector; determines the switching state of each basic vector, and distributes the corresponding switching actions according to the action sequence and time. The present invention improves the DC bus voltage utilization rate of the floating capacitor dual inverter with a voltage ratio of 1:0.5, expands the motor speed regulation range, enhances competitive advantages, can reduce capacitor voltage ripple, reduce the required capacitance value, reduce the volume and mass of the drive system, improve power density and reduce costs, and has significant advantages. It greatly improves the capacitor voltage balancing speed, copes with complex working conditions, and improves system stability and reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of dual inverters, and in particular to a dual inverter virtual vector modulation method. Background Art

[0002] Multilevel inverters have been widely used in the field of motor drives. Their low harmonic output waveform and high voltage tolerance have significant advantages over two-level inverters. Currently, a variety of multilevel inverter topologies have emerged, including cascaded H-bridge, flying capacitor and diode clamped inverter. In recent years, dual inverters have also received widespread attention.

[0003] The dual inverter is composed of two standard two-level voltage inverters connected together, and has broad application prospects in the electric vehicle and more electric aircraft industries. Its advantages are mainly reflected in excellent fault tolerance, rich switching state redundancy, and a wider voltage supply range than traditional two-level and three-level inverters. In addition, the dual inverter can also improve the power quality by increasing the number of output levels.

[0004] According to the different power supply modes of the auxiliary inverter, the dual inverter can be divided into three configurations: isolated power supply type dual inverter, common bus type dual inverter and floating capacitor type dual inverter. Among them, the floating capacitor type dual inverter has higher system reliability and lower cost advantages because it is not affected by zero-sequence current and does not require two isolated power supplies. However, its fault tolerance is limited, and maintaining capacitor voltage balance is a challenge that needs to be solved urgently.

[0005] At present, the common voltage ratios of suspended capacitor dual inverters include 1:1, 1:0.5 and 1:0.33. This study focuses on the suspended capacitor dual inverter with a voltage ratio of 1:0.5, aiming to improve the DC bus voltage utilization and reduce the capacitor voltage ripple, thereby providing strong support for technological progress in this field. Summary of the invention

[0006] In view of the deficiencies in the prior art, the present invention discloses a dual-inverter virtual vector modulation method for solving the above problems.

[0007] The present invention is achieved through the following technical solutions:

[0008] In a first aspect, the present invention provides a dual-inverter virtual vector modulation method, the method comprising the following steps:

[0009] The redundant small vectors and the middle vector are used to construct a virtual middle vector, which is combined into a basic vector group and a reference vector.

[0010] Determine the position of the reference vector, select the adjacent non-zero voltage vector and calculate the action time;

[0011] Calculate the action time of the zero vector, and synthesize the final modulation signal according to the action time of each vector;

[0012] Determine the switching state of each basic vector and assign the corresponding switching actions according to the action sequence and time.

[0013] Furthermore, in the method, the action time of each vector is calculated based on the volt-second balance.

[0014] Furthermore, in the method, when calculating the reference vector, the following formula is used to calculate the action time of each vector according to the volt-second balance equation:

[0015]

[0016]

[0017] Substituting the modulus and angle of the three vectors into equation (1) yields the action time of each vector in region 2, where m is the modulation ratio, θ is the angle of the reference vector, and V dc is the DC bus voltage:

[0018]

[0019]

[0020] T s is the action time of a switching cycle, V ref is the reference space vector or the target space vector to be synthesized; V2, V3, V9, and V0 are all vectors;

[0021] , , , is the space vector V ref ,V2,V3,V9 in vector form, with real and imaginary parts; T a 、T b 、T c are the action times of vectors V2, V3, and V0 respectively;

[0022] U2, U3, U0 are vectors obtained from the corresponding duty cycles of V2, V3, V0 in a switching cycle, and are used to synthesize V ref .

[0023] Furthermore, in the method, when the capacitor voltage is stable, the capacitor ripple is reduced by selecting a switch state with opposite current direction in the full modulation region.

[0024] Furthermore, in the method, in the incomplete modulation region, the type III vector and the type II vector are converted into a type IV vector containing multiple phase currents through virtual vector synthesis.

[0025] Furthermore, in the method, when basic vectors are combined into a reference vector, the nearest three vectors principle is used to select three vectors constituting the smallest area to synthesize the reference vector.

[0026] Furthermore, in the method, the small area and the nearest three vectors and the vector action time are determined according to the position of the reference vector, and the current flowing through the capacitor is controlled according to the required state selected according to the corresponding three vectors to achieve control of the capacitor voltage.

[0027] Furthermore, in the method, the charge required to maintain voltage balance is Q req Indicates that capacitance is represented by C, T II and I fc_TII Respectively represent the dwell time of the type II vector and the current flowing through the capacitor, V fc is the current capacitor voltage value, V fcref is the reference value of the capacitor voltage and t is the action time of the type II vector in one switching cycle:

[0028]

[0029] In a second aspect, the present invention provides a dual inverter, which uses the dual inverter virtual vector modulation method described in the first aspect to maintain good power quality while achieving high voltage utilization, and the dual inverter is used in electric vehicles and more-electric aircraft.

[0030] The beneficial effects of the present invention are:

[0031] The present invention significantly improves the maximum DC bus voltage utilization rate of the suspended capacitor dual inverter with a voltage ratio of 1:0.5, thereby effectively widening its motor speed regulation range and significantly enhancing its advantage in market competition.

[0032] The present invention can effectively reduce capacitor voltage ripple in all kinds of working environments, thereby reducing the capacitance value required by the suspended capacitor dual inverter. This not only reduces the volume and mass of the capacitor required for the drive system, but also significantly improves the system power density and reduces the overall cost, showing significant application value.

[0033] In addition, the present invention also greatly improves the balancing speed of capacitor voltage under unbalanced working conditions, so that the system can better cope with complex and changeable working conditions, thereby significantly enhancing the stability and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 It is a schematic diagram of dual inverter space vector synthesis;

[0036] Figure 2 It is a space vector diagram of dual inverter with voltage ratio 1:0.5;

[0037] Figure 3 is a schematic diagram of the synthesis of dual inverter reference vectors;

[0038] Figure 4 is the current acting on the capacitor and its state diagram;

[0039] Figure 5 It is the vector classification diagram of the first sector of the floating capacitor dual inverter with voltage ratio 1:0.5;

[0040] Figure 6 This is the flow chart when the first sector uses the traditional method;

[0041] Figure 7 is the normalized waveform of the current in the first sector;

[0042] Figure 8 It is the vector diagram of the original method space;

[0043] Fig. 9 It is the capacitance voltage fluctuation diagram when only virtual vector is used in the full modulation area;

[0044] Fig.10 is the vector V 10 and vector V 22 The synthesis principle diagram of

[0045] Fig.11 It is a diagram of the current contained in each vector after synthesizing the virtual vector. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] In one embodiment, a dual inverter virtual vector modulation method is provided, the method comprising the following steps:

[0048] Firstly, a virtual middle vector is constructed by using redundant small vectors and middle vectors, and a basic vector group is formed by combining them, and then a reference vector is further synthesized.

[0049] Secondly, according to the position information of the reference vector, adjacent non-zero voltage vectors are selected and their respective action times are calculated.

[0050] Then, we calculate the action time of the zero vector and synthesize the final modulation signal based on the action time of each vector.

[0051] Finally, the switching status of each basic vector is determined, and the corresponding switching actions are accurately performed according to the action sequence and time distribution.

[0052] This embodiment aims to deeply analyze the influence of the switch state on the capacitor voltage and realize effective regulation of the capacitor voltage by accurately controlling the current flowing through the capacitor. In the application of traditional methods, there are certain limitations and challenges due to the lack of sufficient redundant states in the incomplete modulation area to support the regulation of the capacitor voltage.

[0053] To this end, this embodiment proposes an innovative solution, that is, to break through this technical bottleneck by constructing a virtual vector. As an advanced control strategy, virtual SVPWM technology has been widely used in the modulation process of three-level neutral point clamped inverters. Its core principle is to synthesize a virtual vector with specific properties by linearly combining the real vectors corresponding to specific switching states.

[0054] Under the condition that the capacitor voltage remains stable, by reasonably selecting the switch state with the opposite current direction, the present invention can effectively reduce the capacitor ripple in the complete modulation area, thereby significantly improving the quality of the output electric energy. At the same time, in the incomplete modulation area, the originally uncontrollable vector is converted into a controllable vector by synthesizing a virtual vector, which not only increases the number of redundant states, but also significantly enhances the capacitor voltage regulation capability in the incomplete control area. The application of this innovative technology not only helps to improve the utilization rate of the DC bus voltage, but also effectively reduces the capacitor ripple, speeds up the balancing speed of the capacitor voltage, and provides a strong guarantee for the stable operation of the power system.

[0055] Regarding the dual inverter, this embodiment is further described as follows: the output voltage of the dual inverter is obtained by the difference between the output voltages of the main inverter and the auxiliary inverter. Therefore, the space vector diagram of the dual inverter can be regarded as the difference between the space vector diagrams of the main inverter and the auxiliary inverter, such as Figure 1As shown in the figure, each point represents a vector, which may correspond to one or more switching states (i.e., redundant states). For a two-level inverter, there are 8 switching states, which form 7 different vectors on the plane. For a dual inverter, since the main inverter and the auxiliary inverter each have 8 switching states, there are a total of 8*8=64 switching states, but only 49 of them are valid states.

[0056] According to the dual inverter space vector synthesis diagram, we obtain the space vector diagram of the suspended capacitor dual inverter with a voltage ratio of 1:0.5, as shown in Figure 2 As shown. Figure 3 In the figure, switching state 14' represents the combination of main inverter switching state 1 (100) and auxiliary inverter switching state 4 (011). Under the condition of voltage ratio of 1:0.5, the dual inverter generates 37 effective vectors in 64 switching states, and the maximum output level of line voltage applied to the motor is four levels.

[0057] In this embodiment, according to the space vector diagram of the suspended capacitor dual inverter with a voltage ratio of 1:0.5, we can observe that the first sector contains 9 small areas, 10 vectors and 20 switching states, some of which show redundant characteristics. In the process of generating modulation signals by the dual inverter, its steps are consistent with those of the two-level inverter.

[0058] First, we need to determine the large sector to which the reference vector belongs; then, we further determine the specific small area in the large sector where the reference vector is located, so as to clarify which basic vectors the reference vector is composed of (in the synthesis process, we follow the principle of the nearest three vectors); then, we select the three vectors that constitute the area to synthesize the reference vector; based on the volt-second balance principle, we calculate the action time of each vector; then, based on the selected SVPWM algorithm, we determine the duration of each switching state and output the corresponding signal; finally, we control the conduction state of each device of the dual inverter through signals to achieve the required voltage output by the motor.

[0059] This embodiment specifically discloses a calculation formula, Figure 3 This is a synthetic diagram when the reference vector is located in region 0, T a , T b , T c They are the action time of vectors V2, V3, and V0 respectively. The action time of each vector can be calculated according to the volt-second balance equation:

[0060]

[0061]

[0062] In this embodiment, the modulus length and angle of the three vectors are substituted into formula (1) to obtain the action time of each vector in region 2 (where m is the modulation ratio, θ is the angle of the reference vector, V dc is the DC bus voltage), T s is the action time of a switching cycle, V ref is the reference space vector or the target space vector to be synthesized; V2, V3, V9, and V0 are all vectors;

[0063] , , , is the space vector V ref ,V2,V3,V9 in vector form, with real and imaginary parts; T a , T b , T c are the action times of vectors V2, V3, and V0 respectively;

[0064] U2, U3, U0 are vectors obtained from the corresponding duty cycles of V2, V3, V0 in a switching cycle, and are used to synthesize V ref ;

[0065]

[0066] In this embodiment, Table 1 lists the switching sequence of the first sector of the floating capacitor dual inverter with a voltage ratio of 1:0.5 when the five-segment SVPWM algorithm is used. It can be seen from the SVPWM algorithm that the time for maintaining the five switching states in region 0 is T a / 2, T b / 2, T c , T b / 2, T a / 2.

[0067] Table 1: Example of five-stage switching sequence for the first sector

[0068]

[0069] In one embodiment, during the modulation process, when the current flows through the capacitor, the capacitor voltage will fluctuate. If appropriate control measures are not taken, the capacitor voltage will be out of control. Since the vector can be composed of multiple states, according to the current characteristics contained in the vector, we divide the 37 vectors of the suspended capacitor dual inverter with a voltage ratio of 1:0.5 into four types: first, containing two currents of the same phase; second, containing only a single current; third, containing no current state; fourth, containing currents of different phases.

[0070] like Figure 4 As shown, when the capacitor current is ±i aThe switching state of the auxiliary inverter is clearly shown, and the current i a The figure shows that in state (1'), the current i a flows into the “+” polarity end of the capacitor; while in state (4'), the current i a When the auxiliary inverter switches to states (3') and (6'), the current i b flows through the “+” and “-” polarity ends of the capacitor respectively; when switching to states (2') and (5'), the current i c The current flowing through the capacitor is 0 in states (0') and (7'). Through this classification and graphic analysis, we can better understand and control the fluctuation of capacitor voltage during modulation.

[0071] like Figure 5 As shown, the vectors contained in the first sector and the corresponding states of the vectors and the current flowing through the capacitor (± only represents the direction of the current flowing into the capacitor and does not represent the positive or negative current). In the complete modulation area (grid area), there are only Class I vectors and Class III vectors. The incomplete modulation area (white area) contains Class II vectors (uncontrollable vectors, no redundant states). Class II vectors are the key to causing capacitor voltage fluctuations.

[0072] In one embodiment, a conventional method is adopted, that is, based on a floating capacitor dual inverter with a voltage ratio of 1:0.5, a space vector modulation scheme with current feedback is proposed by quantitatively analyzing the influence of the switch state and the load power factor on the capacitor voltage. The scheme aims to realize active control of the floating capacitor voltage, thereby improving the utilization rate of the DC bus voltage.

[0073] However, since the redundancy of the suspended capacitor dual inverter with a voltage ratio of 1:0.5 is limited in the incomplete modulation area, there are many uncontrollable vectors. When the reference vector is in the incomplete modulation area, the capacitor voltage cannot be adjusted as required, resulting in low DC bus voltage utilization and large capacitor voltage ripple.

[0074] To further analyze this traditional method, we select the first sector as a representative for analysis based on symmetry, and the treatment of other sectors follows the same principle. The core idea of ​​this method is to maintain the balance of capacitor voltage by selecting appropriate redundant states. The key information required to achieve this goal includes: reference vector V ref , reference capacitor voltage V fcref , actual capacitor voltage V fc and three-phase current.

[0075] In the specific implementation process, we first determine the small area where the reference vector is located based on its position, and find the three vectors closest to the small area (following the principle of the nearest three vectors). Then, we control the current flowing through the capacitor based on the action time of these three vectors (based on the volt-second balance principle) and their corresponding states, thereby achieving the purpose of controlling the capacitor voltage. It is worth noting that type I and type IV vectors have redundant states and can therefore be used to regulate the FC voltage. Although type II and type III vectors themselves are not redundant, type II vectors (i.e., uncontrollable vectors) will have an impact on the FC voltage, and this impact needs to be compensated. Therefore, we need to calculate the specific impact of the charge generated by the type II vector on the capacitor voltage.

[0076] Finally, if Figure 6 As shown, in order to maintain voltage balance, we need to determine the required charge Q req , combined with the capacitance of capacitor C and the dwell time T of type II vector II and the current I flowing through the capacitor fc_TII For precise calculation and control.

[0077]

[0078] In this embodiment, Figure 7 The content shown is the normalized current waveform of the first sector, where the x-axis represents the value of (θ+φ), θ refers to the angle of the reference vector, and φ represents the power factor angle, which is used to express i a The current waveform in the figure is drawn based on its phase information. a According to the positive and negative properties of the current, it can be divided into three different schemes; at the same time, according to the charging and discharging characteristics of the capacitor voltage, it can be further divided into two situations.

[0079] Therefore, the traditional solution includes 2 times 3, which equals 6 different switch state combinations. These combinations allow us to flexibly select the appropriate switch state combination according to the actual adjustment requirements of the capacitor voltage.

[0080] As shown in Table 2, due to the existence of type II vectors, there are a lot of omissions in the selection of switch states in the incomplete modulation area. For example, when the capacitor needs to flow current, it is forced to choose the switch state in which the current flows out of the capacitor, which cannot meet the normal regulation needs of the capacitor voltage. Regions 4, 5, 7, and 8 also have type III vectors without regulation capabilities. Therefore, under the action of these two types of vectors, we cannot maintain the capacitor voltage stability as expected, resulting in a low DC bus voltage utilization rate.

[0081] Table 2: Vector state selection for the first sector incomplete modulation area

[0082]

[0083] Table 3 First sector region 4 vector state selection

[0084]

[0085] As shown in Table 3, in the first sector area, vector V 20 、Vector V 21 In half of the cases, the normal control capacitor voltage demand cannot be met and even the original state cannot be maintained. The Vector V8 has no voltage regulation capability and can only maintain the original state of the capacitor voltage, and cannot control the capacitor voltage.

[0086] In one implementation case, a PWM strategy based on the concept of virtual space vector is proposed. This strategy constructs a virtual middle vector by cleverly utilizing redundant small vectors and middle vectors to ensure that the average value of the midpoint current is maintained at zero in each switching cycle. This modulation method has significant advantages. It can achieve precise control of the midpoint voltage of the NPC inverter over the entire modulation index and power factor range, thereby improving the stability and performance of the system.

[0087] This embodiment will take the first sector as an example to explain in detail how to use virtual vector technology to optimize the performance of a floating capacitor dual inverter with a voltage ratio of 1:0.5. Figure 8 As shown, the type I vector V2 covers two currents ±i a When the reference vector needs to be synthesized by V2, the switch state with the opposite current direction should be selected to ensure that the algebraic sum of the charges acting on the capacitor in one switching cycle is as close to zero as possible. For example, when the reference vector is in area 0, vectors V1, V2, and V3 need to be synthesized together. Among them, V2 should select state 11 (i a ) and 04 (-i a ); V3 should select state 22 (-i c ) and 05(i c ); and the V1 vector selects state 00. Finally, the switching sequence synthesized into the reference vector is 04'-05'-00'-11'-22'. Ideally, through this switching sequence, the total current flowing through the capacitor during the switching cycle can be made zero, thereby keeping the capacitor voltage stable.

[0088] like Fig. 9As shown in the figure, the simulation results show that when the virtual vector method is applied in the full modulation area, the fluctuation of the capacitor voltage is not constant, but shows a fluctuation trend in a certain direction. If enough time is given, the capacitor voltage will far exceed the initial voltage level. This is mainly due to the changing characteristics of the three-phase current. Although the action time of each vector is short and the current change is relatively small within a switching cycle, it will still have a certain impact on the capacitor voltage. Therefore, when the use of virtual vector technology causes the capacitor voltage offset to reach a preset threshold, it is necessary to switch to the traditional method in time to maintain the balance of the capacitor voltage, such as using a 04'-05'-00' sequence in the switching state of small area 0. By effectively combining these two methods, the capacitor ripple can be significantly reduced, so that when the reference vector is in the full modulation area, the capacitor voltage ripple is less than the level under the traditional method.

[0089] In one embodiment, in the first sector, we adopt a rigorous and safe strategy to combine vector V9 with vector V 37 Select half of each, and under the premise of ensuring the same current state, synthesize the virtual vector V by reasonably selecting the switch state. V1 This is intended to integrate the current i into the vector V8 b Similarly, for the vector V 19 and vector V 21 We also adopt the same strategy, select half of each and synthesize the switch state through the same current state to generate a virtual vector V V2 , so that the vector V8 also contains the current i c After this processing, the vector V8 has the ability to provide three types of current (i b 、i c , 0) capabilities.

[0090] Further, we continue the above method and add vector V9 to vector V 24 Take half of each, and under the premise of keeping the current state consistent, synthesize the virtual vector V through appropriate switch state combination V3 To ensure that the vector V 10 The current-i b At the same time, the vector V 11 With vector V 22 After similar processing, the virtual vector V is synthesized V4 , so that the vector V 10 It also contains the current -i a . Thus, the vector V 10 It can also provide three currents (-i a 、-i b , 0).

[0091] Therefore, after the above series of synthesis operations, vectors V8 and V 10The original type III vector is transformed into a type IV vector with adjustment capability, that is, a controllable vector. In addition, we also target the uncontrollable vector V 21 The optimization process is carried out and it is combined with the vector V 23 Take half of each and perform linear synthesis to obtain the virtual vector V V5 , so that the vector V 22 The current i c Similarly, V 21 It is also possible to synthesize a virtual vector V V6 Contains current-i a After this transformation, vector V 21 and V 22 It is also transformed into a controllable vector containing two currents.

[0092] The following formula is the synthesis formula of each virtual vector in the first sector:

[0093]

[0094] Fig.10 Display Vector V 10 、V 22 The synthesis principle of V8, V 21 And the same goes for other sectors)

[0095] Table 4 Comparison of currents contained in each vector of the first sector before and after synthesizing the virtual vector

[0096]

[0097] The more selectable currents each vector contains, the more beneficial it is to capacitor voltage control.

[0098] In this embodiment, if Figure 1 As shown in the figure, the area inside the black line frame is defined as the complete modulation area, while the area outside the frame is defined as the incomplete modulation area. In the figure, the synthesized virtual vector is presented in the form of a larger circle. Figure 8 and Fig.11 By comparative analysis, it can be clearly observed that the introduction of synthetic virtual vectors provides redundant states for multiple vectors, effectively filling in some missing states that may occur when adjusting the capacitor voltage, thereby more comprehensively meeting the capacitor voltage adjustment requirements.

[0099] Therefore, by introducing the virtual vector, not only the utilization rate of the DC bus voltage is significantly improved, but also the capacitor ripple is effectively reduced, and the capacitor voltage balance speed is accelerated. When the redundant state is relatively rich and the capacitor voltage regulation requirements are met, the system selects a larger current value by comparing the current values ​​to obtain the required charge Q as quickly as possible. req, which further speeds up the adjustment speed when the capacitor voltage is unbalanced. When the capacitor voltage adjustment demand cannot be met even with the redundant state, the system selects a smaller current value by comparing the current values ​​to avoid large voltage fluctuations, thereby achieving the purpose of reducing the capacitor voltage ripple.

[0100] In one implementation case, a floating capacitor dual inverter with a voltage ratio of 1:0.5 was implemented using a virtual vector method, which significantly improved the voltage utilization while maintaining high-quality power quality. This feature makes this type of dual inverter show great application potential in the transportation field, especially in application scenarios such as more electric aircraft and electric vehicles.

[0101] It should be noted that all simulation waveforms in this embodiment follow fixed frequency settings, namely, fm=60Hz, fs=12000Hz. In order to deeply compare the DC bus voltage utilization of different methods, this study is achieved by comparing the capacitor ripple characteristics at different power factors under the same modulation ratio.

[0102] Specifically, when the power factor PF=0.3 and MI=0.9, the capacitor ripple performance of the two schemes is compared to evaluate their control capabilities on capacitor voltage balance, and based on this, the maximum voltage utilization rate that each method can achieve is inferred. The results show that the scheme that can effectively stabilize the capacitor voltage has a higher voltage utilization rate.

[0103] Similarly, under different working conditions such as power factor PF=0.5, MI=0.88, PF=0.8, MI=0.81, and PF=0.95, MI=0.76, this study also analyzed the performance of the two schemes in controlling capacitor voltage balance and improving voltage utilization by comparing capacitor ripple characteristics.

[0104] In this embodiment, as the power factor increases, the maximum modulation ratio of the conventional method in controlling the capacitor voltage shows a downward trend. In contrast, the virtual vector method shows a wider modulation range under different power factors. Even when the conventional method cannot effectively control the capacitor voltage, the virtual vector method can still achieve stable control of the capacitor voltage. Therefore, in the incomplete modulation area, the virtual vector method shows a higher DC bus voltage utilization rate than the conventional method within the full power factor range.

[0105] In one embodiment, we conduct a comparative analysis on capacitor voltage ripple and capacitor voltage balancing time under different power factors and modulation ratios to evaluate the capacitor voltage control capabilities of the two methods.

[0106] This embodiment mainly focuses on the comparison of the capacitor voltage control ability when the reference vector is in the full modulation area. When the modulation ratio is 0.5, the reference vector is in the full modulation area. In this case, the capacitor ripple using the virtual vector method is lower than the traditional method at various power factors. Specifically, when the power factor PF is 0.3, the capacitor ripple is reduced by 63%; when the PF is 0.8, the capacitor ripple is reduced by 32.3%. Since the available charging and discharging switch states are the same when the reference vector is in the full modulation area, when the capacitor voltage is unbalanced, the balancing speed using the virtual vector method is the same as that of the traditional method.

[0107] In addition, this embodiment also compares the difference in capacitor voltage control ability when the reference vector is in the incomplete modulation area. We pay special attention to the comparison between the two cases where PF is 0.7 and the modulation ratio MI is 0.78, and PF is 0.3 and MI is 0.8. Whether at low power factor or high power factor, when the reference vector is in the incomplete modulation area, the capacitor ripple using the virtual vector method is lower. Specifically, when PF is 0.7 and MI is 0.78, the capacitor ripple is reduced by 25.9%; when PF is 0.3 and MI is 0.8, the capacitor ripple is reduced by 16.9%. In addition, when the capacitor voltage is unbalanced, the balancing speed using the virtual vector method is faster.

[0108] In summary, by introducing virtual vectors, we can improve the maximum DC bus voltage utilization of the suspended capacitor dual inverter with a voltage ratio of 1:0.5, reduce the capacitor voltage ripple under various power factors, and improve the capacitor voltage balancing speed when the reference vector is in the incomplete modulation area. This method is of great significance for optimizing the capacitor voltage control performance.

[0109] The present invention significantly improves the utilization rate of the maximum DC bus voltage in the application of the floating capacitor dual inverter with a voltage ratio of 1:0.5, thereby effectively expanding the speed regulation range of the motor, making the inverter have a stronger competitive advantage in multiple application scenarios.

[0110] First, regarding the improvement of voltage utilization, the present invention optimizes the internal working mechanism of the inverter so that under the same voltage conditions, the DC bus voltage can be more fully utilized, thereby improving the energy conversion efficiency of the system. This optimization not only helps to improve the performance of the motor, but also reduces energy consumption and energy waste.

[0111] Secondly, under various complex working conditions, the present invention can effectively reduce capacitor voltage ripple. Capacitor voltage ripple is a common phenomenon in the operation of the inverter, and its size directly affects the stability and service life of the system. Through the optimization of the present invention, the capacitance value required for the suspended capacitor type dual inverter is significantly reduced, thereby reducing the capacitor volume and mass required for the drive system. This not only makes the entire system more compact, but also improves the power density of the system and reduces the system cost.

[0112] In addition, the present invention also greatly improves the balancing speed of the capacitor voltage in an unbalanced state. In practical applications, the capacitor voltage may be unbalanced due to various reasons. If this imbalance is not corrected in time, it will have a serious impact on the stability and reliability of the system. Through the optimization of the present invention, the system can better cope with such complex working conditions and quickly balance the capacitor voltage, thereby improving the stability and reliability of the system.

[0113] In general, the present invention has significant application advantages in improving the performance of the floating capacitor dual inverter with a voltage ratio of 1:0.5, reducing system costs, and improving system stability and reliability. With the continuous development of science and technology, this inverter will be widely used in more fields, making important contributions to promoting energy conservation, emission reduction and sustainable development in industries such as industry and transportation. The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the aforementioned embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A dual inverter virtual vector modulation method, characterized in that: The method comprises the following steps: The redundant small vectors and the middle vector are used to construct a virtual middle vector, which is combined into a basic vector group and a reference vector. Determine the position of the reference vector, select the adjacent non-zero voltage vector and calculate the action time; Calculate the action time of the zero vector, and synthesize the final modulation signal according to the action time of each vector; Determine the switch status of each basic vector and assign corresponding switch actions according to the action sequence and time; Among them, under the condition that the capacitor voltage remains stable, the capacitor ripple is effectively reduced in the full modulation area by selecting the switch state with the opposite current direction; In the incomplete modulation area, the originally uncontrollable vector is converted into a controllable vector by synthesizing a virtual vector, the number of redundant states is increased, and the capacitor voltage regulation capability in the incomplete control area is enhanced; When the capacitor voltage is stable, the capacitor ripple is reduced by selecting the switch state with opposite current direction in the full modulation region; In the incomplete modulation area, the type III vector and type II vector are transformed into a type IV vector containing multiple phase currents through virtual vector synthesis.

2. A dual inverter virtual vector modulation method according to claim 1, characterized in that: In the method, the action time of each vector is calculated according to the volt-second balance.

3. A dual inverter virtual vector modulation method according to claim 2, characterized in that: In the method, the reference vector action time is calculated using the following formula, and the action time of each vector can be calculated according to the volt-second balance equation: T a +T b +T c =T S (2) Where m is the modulation ratio, θ is the angle of the reference vector, v dc is the DC bus voltage; T a =1-3msinθ T c =T s -T a -T b T s is the action time of a switching cycle, v ref is the reference space vector or the target space vector to be synthesized; V2, V3, V9, and V0 are all vectors; is the space vector V ref , V2, V3, V9 in vector form, with real and imaginary parts; T a , T b , T c are the action times of vectors V2, V3, and V0 respectively; U2, U3, U0 are vectors obtained from the corresponding duty cycles of V2, V3, V0 in a switching cycle, and are used to synthesize V ref .

4. A dual inverter virtual vector modulation method according to claim 1, characterized in that: In the method, when basic vectors are combined into a reference vector, the nearest three vectors principle is used to select three vectors constituting the smallest area to synthesize the reference vector.

5. A dual inverter virtual vector modulation method according to claim 1, characterized in that: In the method, the small area and the nearest three vectors and the vector action time are determined according to the position of the reference vector, and the current flowing through the capacitor is controlled according to the required state selected according to the corresponding three vectors to achieve the control of the capacitor voltage.

6. A dual inverter virtual vector modulation method according to claim 1, characterized in that: In the method, the charge required to maintain voltage balance is Q req Indicates that capacitance is represented by C, T II and I fc_TII Respectively represent the dwell time of the type II vector and the current flowing through the capacitor, V fc is the current capacitor voltage value, V fcref is the reference value of the capacitor voltage, t is the action time of the type II vector in one switching cycle;

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