A pulse amplitude modulation forward equalization circuit

Abstract

The present invention discloses a pulse amplitude modulation forward equalization circuit, which relates to the field of high-speed interface technology, and includes: a delay circuit, which is used to delay the output of a signal of a first preset number of input delay circuits; a thermometer circuit, which is used to convert a signal of a second preset number of input thermometer circuits into thermometer codes and output them; a digital-to-analog conversion circuit, which is used to perform digital-to-analog conversion on the signals output by the delay circuit and the thermometer circuit; a filter circuit, which is used to filter the analog signal output by the digital-to-analog conversion circuit; a numerical interpolation circuit, which is used to perform numerical interpolation on the analog signal output by the filter circuit; and a multiplexing circuit, which is used to output the analog signals of each channel output by the numerical interpolation circuit one by one in sequence. The circuit can solve the interference between adjacent signals, improve the anti-interference ability of signal transmission, enhance the quantization accuracy, and improve the smoothness of the signal.

Description

Technical Field

[0001] The invention relates to the technical field of high-speed interfaces, and in particular to a pulse amplitude modulation forward equalization circuit. Background Art

[0002] The demand for data traffic in high-computing application scenarios such as data centers is increasing, and higher transmission rates are required for single application channels, such as 56G or 112G. However, the channel loss and reflection introduction costs of 56G and 112G signals are very high, and the tolerance for channel crosstalk is greatly reduced. In response to this situation, the industry introduced PAM4 technology to solve it. PAM4 is a type of PAM (Pulse Amplitude Modulation) modulation technology, which is usually implemented using an analog-based Combine method. Considering that the protocol layer is often a digital signal during interface interaction, this method requires the addition of circuits such as digital-to-analog conversion. At the same time, compared with digital signals, analog signals are easily affected by loss factors such as noise and crosstalk during transmission, which deteriorates the signal transmission quality and makes it difficult to meet the target BER performance specified by the system. The signals processed by traditional PAM4 FFE (Feed Feedback Equalization) are analog signals, which are easily affected by loss factors such as noise and crosstalk, and the link performance is subject to certain limitations. Moreover, the internal FFE structure is linear, and there is a large tailing phenomenon between adjacent signals, which directly affects the amplitude of the current signal, increases the bit error rate, and deteriorates the transmission quality.

[0003] Therefore, how to solve the above technical defects has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] The purpose of the present invention is to provide a pulse amplitude modulation forward equalization circuit, which can solve the interference between adjacent signals, improve the anti-interference ability of signal transmission, enhance the quantization accuracy, and improve the smoothness of the signal.

[0005] In order to solve the above technical problems, the present invention provides a pulse amplitude modulation forward equalization circuit, comprising:

[0006] A delay circuit, used for delaying and outputting a first preset number of signals input into the delay circuit;

[0007] A thermometer circuit, used for converting a second preset number of signals input into the thermometer circuit into a thermometer code and outputting the code;

[0008] A digital-to-analog conversion circuit, used for performing digital-to-analog conversion on the signals output by the delay circuit and the thermometer circuit;

[0009] A filter circuit, used for filtering the analog signal output by the digital-to-analog conversion circuit;

[0010] A numerical interpolation circuit, used for performing numerical interpolation on the analog signal output by the filtering circuit;

[0011] The multiplexing circuit is used to output the analog signals output by the numerical interpolation circuit one by one in sequence.

[0012] In some embodiments, the delay circuit is specifically used to delay the output of four signals input into the delay circuit.

[0013] In some embodiments, the thermometer circuit is specifically used to convert three signals input into the thermometer circuit into seven thermometer codes and output them.

[0014] In some embodiments, the digital-to-analog conversion circuit comprises:

[0015] N digital-to-analog conversion branches; N is equal to the sum of the number of signals output by the delay circuit and the number of signals output by the thermometer circuit; the digital-to-analog conversion branch includes: a first switch tube, a second switch tube and a third switch tube; the first end of the first switch tube is connected to a reference voltage, the second end of the first switch tube is grounded, the third end of the first switch tube is connected to the second end of the second switch tube and the second end of the third switch tube, the first end of the second switch tube is connected to the positive end of the input signal, the third end of the second switch tube is connected to the negative end of the output signal, the negative end of the output signal is connected to the filter circuit, the first end of the third switch tube is connected to the negative end of the input signal, the third end of the third switch tube is connected to the positive end of the output signal, and the positive end of the output signal is connected to the filter circuit.

[0016] In some embodiments, the digital-to-analog conversion circuit includes eleven digital-to-analog conversion branches; wherein four of the digital-to-analog conversion branches are used to perform digital-to-analog conversion on four signals output by the delay circuit, and seven of the digital-to-analog conversion branches are used to perform digital-to-analog conversion on seven signals output by the thermometer circuit.

[0017] In some embodiments, the first switch tube, the second switch tube and the third switch tube are NMOS tubes; the first end of the first switch tube, the first end of the second switch tube and the first end of the third switch tube are gates of the NMOS tube, the second end of the first switch tube, the second end of the second switch tube and the second end of the third switch tube are sources of the NMOS tube, and the third end of the first switch tube, the third end of the second switch tube and the third end of the third switch tube are drains of the NMOS tube.

[0018] In some embodiments, the filtering circuit comprises:

[0019] a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube, a ninth switch tube, a first capacitor and a second capacitor; a first end of the fourth switch tube is connected to a controllable voltage, a second end of the fourth switch tube is grounded, a third end of the fourth switch tube is connected to the second end of the fifth switch tube, the first end of the fifth switch tube, the first end of the sixth switch tube and one end of the first capacitor, a third end of the fifth switch tube is connected to the third end of the sixth switch tube, the third end of the seventh switch tube and the third end of the eighth switch tube, a second end of the sixth switch tube is connected to the negative end of the output signal of the digital-to-analog conversion circuit, the other end of the first capacitor is grounded, a second end of the seventh switch tube is connected to the positive end of the output signal of the digital-to-analog conversion circuit, a first end of the seventh switch tube is connected to the first end of the eighth switch tube, the second end of the eighth switch tube, the third end of the ninth switch tube and one end of the second capacitor, a second end of the ninth switch tube is grounded, a first end of the ninth switch tube is connected to a controllable voltage, and the other end of the second capacitor is grounded.

[0020] In some embodiments, the fourth switch tube and the ninth switch tube are NMOS tubes, the first end of the fourth switch tube and the first end of the ninth switch tube are the gate of the NMOS tube, the second end of the fourth switch tube and the second end of the ninth switch tube are the source of the NMOS tube, and the third end of the fourth switch tube and the third end of the ninth switch tube are the drain of the NMOS tube; the fifth switch tube, the sixth switch tube, the seventh switch tube and the eighth switch tube are PMOS tubes, the first end of the fifth switch tube, the first end of the sixth switch tube, the first end of the seventh switch tube and the first end of the eighth switch tube are the gate of the PMOS tube, the second end of the fifth switch tube, the second end of the sixth switch tube, the second end of the seventh switch tube and the second end of the eighth switch tube are the drain of the PMOS tube, and the third end of the fifth switch tube, the third end of the sixth switch tube, the third end of the seventh switch tube and the third end of the eighth switch tube are the source of the PMOS tube.

[0021] In some embodiments, the numerical interpolation circuit comprises:

[0022] A delay unit and a multi-channel resistor, each of which is connected in series; the input end of the delay unit is connected to the output end of the digital-to-analog conversion circuit, the output end of the delay unit is connected to the resistor at one end of each resistor connected in series, and the resistor at the other end of each resistor connected in series is connected to the output end of the digital-to-analog conversion circuit.

[0023] In some embodiments, the delay unit includes a buffer.

[0024] In some embodiments, the numerical interpolation circuit includes four resistors connected in series, and the numerical interpolation circuit outputs four signals.

[0025] In some embodiments, the multiplexing circuit comprises:

[0026] M-way two-to-one circuit; M*2 is equal to the number of ways of signals output by the numerical interpolation circuit; the two-to-one circuit includes a tenth switch tube, an eleventh switch tube, a twelfth switch tube, a thirteenth switch tube, a fourteenth switch tube, a fifteenth switch tube, a sixteenth switch tube, a first resistor and a second resistor; the first end of the tenth switch tube is connected to the positive end of the first input signal, the second end of the tenth switch tube is connected to one end of the first resistor and the negative end of the output signal, the third end of the tenth switch tube is connected to the third end of the eleventh switch tube and the second end of the fourteenth switch tube, the first end of the eleventh switch tube is connected to the negative end of the first input signal, the second end of the eleventh switch tube is connected to one end of the second resistor and the positive end of the output signal, and the first end of the fourteenth switch tube is connected to the positive end of the clock signal , the third end of the fourteenth switch tube is connected to the second end of the sixteenth switch tube, the first end of the sixteenth switch tube is connected to the reference voltage, the third end of the sixteenth switch tube is grounded, the first end of the twelfth switch tube is connected to the positive end of the second input signal, the second end of the twenty-second switch tube is connected to the negative end of the output signal, the third end of the twelfth switch tube is connected to the third end of the thirteenth switch tube and the second end of the fifteenth switch tube, the first end of the thirteenth switch tube is connected to the negative end of the second input signal, the second end of the thirteenth switch tube is connected to the positive end of the output signal, the first end of the fifteenth switch tube is connected to the negative end of the clock signal, the third end of the fifteenth switch tube is connected to the second end of the sixteenth switch tube, and the other end of the first resistor and the other end of the second resistor are connected to a power supply.

[0027] In some embodiments, the multiplexing circuit includes two of the two-to-one circuits.

[0028] In some embodiments, the tenth switch tube, the eleventh switch tube, the twelfth switch tube, the thirteenth switch tube, the fourteenth switch tube, the fifteenth switch tube and the sixteenth switch tube are NMOS tubes; the first end of the tenth switch tube, the first end of the eleventh switch tube, the first end of the twelfth switch tube, the first end of the thirteenth switch tube, the first end of the fourteenth switch tube, the first end of the fifteenth switch tube and the first end of the sixteenth switch tube are gates of the NMOS tubes, the second end of the tenth switch tube, the second end of the eleventh switch tube, the second end of the twelfth switch tube, the second end of the thirteenth switch tube, the second end of the fourteenth switch tube, the second end of the fifteenth switch tube and the second end of the sixteenth switch tube are drains of the NMOS tubes, and the third end of the tenth switch tube, the third end of the eleventh switch tube, the third end of the twelfth switch tube, the third end of the thirteenth switch tube, the third end of the fourteenth switch tube, the third end of the fifteenth switch tube and the third end of the sixteenth switch tube are sources of the NMOS tubes.

[0029] In some embodiments, it also includes:

[0030] The weighting circuit is used to amplify or reduce the input signal, and output the processed signals of the first preset number of paths in parallel to the delay circuit, and output the processed signals of the second preset number of paths in parallel to the thermometer circuit.

[0031] In some embodiments, the weighting circuit comprises:

[0032] Multiple D flip-flops and weight circuits; each of the D flip-flops is connected in series, and the output end of each of the D flip-flops is respectively connected to one of the weight circuits; the D flip-flops are used to sample and hold the input signal, and the weight circuit is used to multiply the signal output by the corresponding D flip-flop by a weighting coefficient and then output it.

[0033] In some embodiments, the weighting circuit includes seven D flip-flops and seven weight circuits.

[0034] In some embodiments, the D flip-flop comprises:

[0035] A master latch and a slave latch; the master latch is connected to the positive end and the negative end of the input signal, and the slave latch is connected to the master latch and the positive end and the negative end of the output signal.

[0036] In some embodiments, the weight circuit comprises:

[0037] A seventeenth switch tube, an eighteenth switch tube, a nineteenth switch tube, a third resistor and a fourth resistor; the first end of the seventeenth switch tube is connected to the positive end of the input signal, the second end of the seventeenth switch tube is connected to the third end of the eighteenth switch tube, the third end of the seventeenth switch tube is connected to one end of the third resistor and the negative end of the output signal, the first end of the eighteenth switch tube is connected to a controllable voltage, the second end of the eighteenth switch tube is grounded, the first end of the nineteenth switch tube is connected to the negative end of the input signal, the second end of the nineteenth switch tube is connected to the third end of the eighteenth switch tube, the third end of the nineteenth switch tube is connected to one end of the fourth resistor and the positive end of the output signal, and the other end of the third resistor and the other end of the fourth resistor are connected to a power supply.

[0038] In some embodiments, the seventeenth switch tube, the eighteenth switch tube and the nineteenth switch tube are NMOS tubes, the first end of the seventeenth switch tube, the first end of the eighteenth switch tube and the first end of the nineteenth switch tube are gates of the NMOS tube, the second end of the seventeenth switch tube, the second end of the eighteenth switch tube and the second end of the nineteenth switch tube are sources of the NMOS tube, and the third end of the seventeenth switch tube, the third end of the eighteenth switch tube and the third end of the nineteenth switch tube are drains of the NMOS tube.

[0039] The pulse amplitude modulation forward equalization circuit provided by the present invention includes: a delay circuit, which is used to delay the output of a first preset number of signals input into the delay circuit; a thermometer circuit, which is used to convert a second preset number of signals input into the thermometer circuit into a thermometer code and output it; a digital-to-analog conversion circuit, which is used to perform digital-to-analog conversion on the signals output by the delay circuit and the thermometer circuit; a filtering circuit, which is used to filter the analog signal output by the digital-to-analog conversion circuit; a numerical interpolation circuit, which is used to perform numerical interpolation on the analog signal output by the filtering circuit; and a multiplexing circuit, which is used to output the analog signals output by the numerical interpolation circuit one by one in sequence.

[0040] It can be seen that the pulse amplitude modulation forward equalization circuit provided by the present invention converts the signal into an analog signal through a digital-to-analog conversion circuit, solves the interference between adjacent signals, and compensates for the signal attenuation caused by the channel. The filtering circuit can suppress the quantization noise in the quantized signal and improve the anti-interference ability of the transmission signal. The amplitude of the quantized signal of the digital-to-analog conversion circuit is equally divided by a numerical interpolation circuit to enhance the quantization accuracy and improve the smoothness of the signal. The circuit can support different transmission rates under the chiplet link and is fully suitable for various interconnection interfaces such as C2C (Chip-to-Chip, chip to chip), D2D (Die-to-Die, die to die). BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the prior art and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 A schematic diagram of a pulse amplitude modulation forward equalization circuit provided by an embodiment of the present invention;

[0043] Figure 2 A schematic diagram of a specific pulse amplitude modulation forward equalization circuit provided by an embodiment of the present invention;

[0044] Figure 3 A schematic diagram of a digital-to-analog conversion circuit provided by an embodiment of the present invention;

[0045] Figure 4 A schematic diagram of a numerical interpolation circuit provided by an embodiment of the present invention;

[0046] Figure 5 A schematic diagram of a two-choice circuit provided by an embodiment of the present invention;

[0047] Figure 6 A schematic diagram of a multiplexing circuit provided by an embodiment of the present invention;

[0048] Figure 7 A schematic diagram of a D flip-flop provided by an embodiment of the present invention;

[0049] Figure 8 A schematic diagram of a weight circuit provided by an embodiment of the present invention;

[0050] Fig. 9 A schematic diagram of an output signal provided by an embodiment of the present invention;

[0051] Fig.10 A schematic diagram of another output signal provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The core of the present invention is to provide a pulse amplitude modulation forward equalization circuit, which can solve the interference between adjacent signals, improve the anti-interference ability of signal transmission, enhance the quantization accuracy, and improve the smoothness of the signal.

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] Please refer to Figure 1 , Figure 1 A schematic diagram of a pulse amplitude modulation forward equalization circuit provided by an embodiment of the present invention, referring to Figure 1 As shown, the circuit includes:

[0055] The delay circuit 10 is used to delay and output a signal of a first preset number of inputs to the delay circuit 10;

[0056] The thermometer circuit 20 is used to convert the signal of the second preset number of inputs into the thermometer circuit 20 into a thermometer code and output it;

[0057] A digital-to-analog conversion circuit 30, used for performing digital-to-analog conversion on the signals output by the delay circuit 10 and the thermometer circuit 20;

[0058] A filter circuit 40, used for filtering the analog signal output by the digital-to-analog conversion circuit 30;

[0059] A numerical interpolation circuit 50, used for performing numerical interpolation on the analog signal output by the filtering circuit 40;

[0060] The multiplexing circuit 60 is used to output the analog signals output by the numerical interpolation circuit 50 one by one in sequence.

[0061] The signals of the first preset number of paths are input in parallel to the delay circuit 10, and the signals of the second preset number of paths are input in parallel to the thermometer circuit 20. The delay circuit 10 outputs the signals of the first preset number of paths with a delay, and the thermometer circuit 20 converts the signals of the second preset number of paths into thermometer codes and outputs them. The delay time of the delay circuit 10 is equal to the transmission time of the thermometer circuit 20, that is, after the signals of the first preset number of paths and the signals of the second preset number of paths are input into the delay circuit 10 and the thermometer circuit 20 respectively at the same time, the delay circuit 10 and the thermometer circuit 20 output signals at the same time.

[0062] In some embodiments, the delay circuit 10 is specifically used to delay and output four signals input to the delay circuit 10. The thermometer circuit 20 is specifically used to convert three signals input to the thermometer circuit 20 into seven thermometer codes and output them.

[0063] In this embodiment, four signals are input to the delay circuit 10, and three signals are input to the thermometer circuit 20. The three signals input to the thermometer circuit 20 are converted into seven thermometer codes by the thermometer circuit 20. Figure 2 As shown, the signal x 1 、x 2 、x 3 、x 4 Input delay circuit 10, delay circuit 10 delays output V 1 、V 2 , V 3 , V 4 . Signal x 5 、x 6 、x 7 Input the thermometer circuit 20, the thermometer circuit 20 converts the input signal into a thermometer code and outputs V 5 To V 11 The conversion relationship between the three-way signal and the seven-way thermometer code is shown in Table 1.

[0064] Table 1

[0065]

[0066] That is, if x 5 、x 6 、x 7 If x is 0, then the seven-way thermometer code is 0. 5 With x 6 is 0, x 7 If it is 1, then V 11 is 1, and the rest are 0. 5 With x 7 is 0, x 6 If it is 1, then V 10 With V 11 is 1, and the rest are 0. 6 With x 7 is 1, x 5 If V in the seven-way thermometer code is 0, 9 To V 11 is 1, and the rest are 0. 6 With x 7 is 0, x 5 If it is 1, then V 8 To V 11 is 1, and the rest are 0. 5 With x 7 is 1, x 6 If V in the seven-way thermometer code is 0, 7 To V 11 is 1, and the rest are 0. 5 With x 6is 1, x 7 If V in the seven-way thermometer code is 0, 6 To V 11 is 1, and the rest are 0. 5 、x 6 、x 7 If all are 1, then the seven thermometer codes are all 1.

[0067] The delay circuit 10 may include a buffer, which delays the input four-way signal and outputs it. The thermometer circuit 20 may include a processing chip. The processing chip outputs corresponding seven-way signals according to the input three-way signals.

[0068] The digital-to-analog conversion circuit 30 performs digital-to-analog conversion on the signals output by the delay circuit 10 and the thermometer circuit 20 , and outputs analog signals.

[0069] In some embodiments, the digital-to-analog conversion circuit 30 includes:

[0070] N digital-to-analog conversion branches; N is equal to the sum of the number of signals output by the delay circuit 10 and the number of signals output by the thermometer circuit 20; the digital-to-analog conversion branch includes: a first switch tube M1, a second switch tube M2 and a third switch tube M3; the first end of the first switch tube M1 is connected to a reference voltage, the second end of the first switch tube M1 is grounded, the third end of the first switch tube M1 is connected to the second end of the second switch tube M2 and the second end of the third switch tube M3, the first end of the second switch tube M2 is connected to the positive end of the input signal, the third end of the second switch tube M2 is connected to the negative end of the output signal, the negative end of the output signal is connected to the filter circuit 40, the first end of the third switch tube M3 is connected to the negative end of the input signal, the third end of the third switch tube M3 is connected to the positive end of the output signal, and the positive end of the output signal is connected to the filter circuit 40.

[0071] In this embodiment, the digital-to-analog conversion circuit 30 includes N digital-to-analog conversion branches, where N is equal to the sum of the number of signals output by the delay circuit 10 and the number of signals output by the thermometer circuit 20. Each digital-to-analog conversion branch includes three switch tubes.

[0072] In some embodiments, the digital-to-analog conversion circuit 30 includes eleven digital-to-analog conversion branches; among them, four of the digital-to-analog conversion branches are used to perform digital-to-analog conversion on four signals output by the delay circuit 10, and seven of the digital-to-analog conversion branches are used to perform digital-to-analog conversion on seven signals output by the thermometer circuit 20.

[0073] Corresponding to the embodiment in which the delay circuit 10 is specifically used to delay the output of the four-way signal input to the delay circuit 10. The thermometer circuit 20 is specifically used to convert the three-way signal input to the thermometer circuit 20 into seven-way thermometer codes and output them, the digital-to-analog conversion circuit 30 includes eleven digital-to-analog conversion branches, four of which are used to perform digital-to-analog conversion on the four-way signal output from the delay circuit 10, and seven digital-to-analog conversion branches are used to perform digital-to-analog conversion on the seven-way signal output from the thermometer circuit 20.

[0074] In addition, in some embodiments, the first switch tube M1, the second switch tube M2 and the third switch tube M3 are NMOS tubes; the first end of the first switch tube M1, the first end of the second switch tube M2 and the first end of the third switch tube M3 are gates of the NMOS tubes, the second end of the first switch tube M1, the second end of the second switch tube M2 and the second end of the third switch tube M3 are sources of the NMOS tubes, and the third end of the first switch tube M1, the third end of the second switch tube M2 and the third end of the third switch tube M3 are drains of the NMOS tubes.

[0075] That is, a first switch tube M1, a second switch tube M2 and a third switch tube M3; the gate of the first switch tube M1 is connected to a reference voltage, the source of the first switch tube M1 is grounded, the drain of the first switch tube M1 is connected to the source of the second switch tube M2 and the source of the third switch tube M3, the gate of the second switch tube M2 is connected to the positive end of the input signal, the drain of the second switch tube M2 is connected to the negative end of the output signal, the negative end of the output signal is connected to the filter circuit 40, the gate of the third switch tube M3 is connected to the negative end of the input signal, the drain of the third switch tube M3 is connected to the positive end of the output signal, and the positive end of the output signal is connected to the filter circuit 40.

[0076] The digital-to-analog conversion circuit 30 receives eleven signals V 1 ~V 11 , the corresponding current size is 1X, 2X, 4X, 8X, 16X, ..., 16X. Signal V 1 ~ V 11 It can change the conduction and shutdown of the NMOS tube to a certain amplitude. There are 127 (2 7 ) amplitude. Figure 3 As shown, Figure 3 Where Vb represents the reference voltage, V 1p With V 1n Respectively represent the signal V 1 The positive and negative terminals, V 2p With V 2n Respectively represent the signal V 2 The positive and negative ends of V 11pWith V 11n Respectively represent the signal V 1 The positive and negative terminals. Figure 3 Medium V on With V op Respectively represent the negative end and the positive end of the output signal. The quantization bit number of the general digital-to-analog conversion circuit is less than 12 bits.

[0077] During the digital-to-analog conversion process, the filter circuit 40 is responsible for filtering out quantization noise.

[0078] In some embodiments, the filtering circuit 40 includes:

[0079] a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7, an eighth switch tube M8, a ninth switch tube M9, a first capacitor C1 and a second capacitor C2; a first end of the fourth switch tube M4 is connected to a controllable voltage, a second end of the fourth switch tube M4 is grounded, a third end of the fourth switch tube M4 is connected to a second end of the fifth switch tube M5, a first end of the fifth switch tube M5, a first end of the sixth switch tube M6 and one end of the first capacitor C1, a third end of the fifth switch tube M5 is connected to a third end of the sixth switch tube M6, a third end of the seventh switch tube M7 and the The third end of the eighth switch tube M8 and the second end of the sixth switch tube M6 are connected to the negative end of the output signal of the digital-to-analog conversion circuit 30, the other end of the first capacitor C1 is grounded, the second end of the seventh switch tube is connected to the positive end of the output signal of the digital-to-analog conversion circuit 30, the first end of the seventh switch tube M7 is connected to the first end of the eighth switch tube M8, the second end of the eighth switch tube M8, the third end of the ninth switch tube M9 and one end of the second capacitor C2, the second end of the ninth switch tube M9 is grounded, the first end of the ninth switch tube M9 is connected to the controllable voltage, and the other end of the second capacitor C2 is grounded.

[0080] During the digital-to-analog conversion process, this embodiment uses an active filter circuit 40 composed of a switch tube and a capacitor to filter out quantization noise between adjacent levels.

[0081] In some embodiments, the fourth switch tube M4 and the ninth switch tube M9 are NMOS tubes, the first end of the fourth switch tube M4 and the first end of the ninth switch tube M9 are the gate of the NMOS tube, the second end of the fourth switch tube M4 and the second end of the ninth switch tube M9 are the source of the NMOS tube, the third end of the fourth switch tube M4 and the third end of the ninth switch tube M9 are the drain of the NMOS tube; the fifth switch tube M5, the sixth switch tube M6, the seventh switch tube M7 and the eighth switch tube M8 are PMOS tubes, The first end of the fifth switch tube M5, the first end of the sixth switch tube M6, the first end of the seventh switch tube M7 and the first end of the eighth switch tube M8 are gates of the PMOS tube, the second end of the fifth switch tube M5, the second end of the sixth switch tube M6, the second end of the seventh switch tube M7 and the second end of the eighth switch tube M8 are drains of the PMOS tube, and the third end of the fifth switch tube M5, the third end of the sixth switch tube M6, the third end of the seventh switch tube M7 and the third end of the eighth switch tube M8 are sources of the PMOS tube.

[0082] That is, the gate of the fourth switch tube M4 is connected to the controllable voltage, the source of the fourth switch tube M4 is grounded, the drain of the fourth switch tube M4 is connected to the drain of the fifth switch tube M5, the gate of the fifth switch tube M5, the gate of the sixth switch tube M6 and one end of the first capacitor C1, the source of the fifth switch tube M5 is connected to the source of the sixth switch tube M6, the source of the seventh switch tube M7 and the source of the eighth switch tube M8, the drain of the sixth switch tube M6 is connected to the negative end of the output signal of the digital-to-analog conversion circuit 30, the other end of the first capacitor C1 is grounded, the drain of the seventh switch tube is connected to the positive end of the output signal of the digital-to-analog conversion circuit 30, the gate of the seventh switch tube M7 is connected to the gate of the eighth switch tube M8, the drain of the eighth switch tube M8, the drain of the ninth switch tube M9 and one end of the second capacitor C2, the source of the ninth switch tube M9 is grounded, the gate of the ninth switch tube M9 is connected to the controllable voltage, and the other end of the second capacitor C2 is grounded.

[0083] refer to Figure 3 As shown, in this embodiment, the filter circuit 40 is composed of a PMOS tube and a capacitor. Figure 3 Vb1 represents a controllable voltage. The cutoff frequency of the filter circuit 40 can be changed by the controllable voltage to suppress the quantization noise in the quantized signal and improve the anti-interference ability of the transmission signal.

[0084] The numerical interpolation circuit 50 performs numerical interpolation on the analog signal output by the filtering circuit 40 and further subdivides each amplitude to enhance the smoothness of the signal.

[0085] In some embodiments, the numerical interpolation circuit 50 comprises:

[0086] The delay unit and the multi-channel resistors are connected in series; the input end of the delay unit is connected to the output end of the digital-to-analog conversion circuit 30, the output end of the delay unit is connected to the resistor at one end of each resistor connected in series, and the resistor at the other end of each resistor connected in series is connected to the output end of the digital-to-analog conversion circuit 30.

[0087] In this embodiment, the numerical interpolation circuit 50 includes a delay unit and a plurality of resistors, and each resistor is connected in series. The delay unit delays a signal cycle. The signal output by the digital-to-analog conversion circuit 30 at the previous moment and the signal output at the current moment are the high and low levels of the numerical interpolation circuit 50, and the numerical interpolation circuit 50 divides the high and low level difference into several parts.

[0088] In some embodiments, the delay unit includes a buffer. In some embodiments, the numerical interpolation circuit 50 includes four resistors connected in series, and the numerical interpolation circuit 50 outputs four signals.

[0089] refer to Figure 4 As shown, in this embodiment, the numerical interpolation circuit 50 includes four resistors (Ra, Rb, Rc, and Rd), each of which is connected in series, one end of Ra is connected to the output end of the delay unit, and one end of Rd is connected to the output of the digital-to-analog conversion circuit 30. The signal output by the digital-to-analog conversion circuit 30 at the previous moment and the signal output at the current moment are the high and low levels of the numerical interpolation circuit 50. The numerical interpolation circuit 50 divides the high and low level difference into four parts and outputs U1 to U4. 1 ~ V 11 Change the conduction and shutdown of the NMOS tube to a certain amplitude, a total of 127 (2 7 ) amplitude, each amplitude is further subdivided by a numerical interpolation circuit 50, and there are 2 9 That is 2 7 *4 amplitude sizes.

[0090] The multiplexing circuit 60 outputs the analog signals output by the numerical interpolation circuit 50 one by one in sequence.

[0091] In some embodiments, the multiplexing circuit 60 includes:

[0092] M-way two-to-one circuit; M*2 is equal to the number of ways of the signal output by the numerical interpolation circuit 50; the two-to-one circuit includes a tenth switch tube M10, an eleventh switch tube M11, a twelfth switch tube M12, a thirteenth switch tube M13, a fourteenth switch tube M14, a fifteenth switch tube M15, a sixteenth switch tube M16, a first resistor R1 and a second resistor R2; the first end of the tenth switch tube M10 is connected to the positive end of the first input signal, the second end of the tenth switch tube M10 is connected to one end of the first resistor R1 and the negative end of the output signal, the third end of the tenth switch tube M10 is connected to the third end of the eleventh switch tube M11 and the second end of the fourteenth switch tube M14, the first end of the eleventh switch tube M11 is connected to the negative end of the first input signal, the second end of the eleventh switch tube M11 is connected to one end of the second resistor R2 and the positive end of the output signal, and the first end of the fourteenth switch tube M14 is connected to the positive end of the first input signal. The third end of the fourteenth switch tube M14 is connected to the second end of the sixteenth switch tube M16, the first end of the sixteenth switch tube M16 is connected to the reference voltage, the third end of the sixteenth switch tube M16 is grounded, the first end of the twelfth switch tube M12 is connected to the positive end of the second input signal, the second end of the twenty-second switch tube is connected to the negative end of the output signal, the third end of the twelfth switch tube M12 is connected to the third end of the thirteenth switch tube M13 and the second end of the fifteenth switch tube M15, the first end of the thirteenth switch tube M13 is connected to the negative end of the second input signal, the second end of the thirteenth switch tube M13 is connected to the positive end of the output signal, the first end of the fifteenth switch tube M15 is connected to the negative end of the clock signal, the third end of the fifteenth switch tube M15 is connected to the second end of the sixteenth switch tube M16, and the other end of the first resistor R1 and the other end of the second resistor R2 are connected to a power supply.

[0093] In this embodiment, the multiplexing circuit 60 is implemented by using a plurality of 2:1 multiplexing units, that is, a two-choose-one circuit. Each multiplexing unit adopts a CML circuit structure, which can meet the high-speed transmission requirements.

[0094] In some embodiments, the multiplexing circuit 60 includes two of the two-select-one circuits.

[0095] When the numerical interpolation circuit 50 divides the difference between the high and low levels of the signal output by the digital-to-analog conversion circuit 30 at the previous moment and the signal output at the current moment into four equal parts and outputs four signals U1 to U4, the corresponding multiplexing circuit 60 includes two multiplexing units, and the two multiplexing units constitute a 4:1 multiplexing circuit 60.

[0096] In addition, in some embodiments, the tenth switch tube M10, the eleventh switch tube M11, the twelfth switch tube M12, the thirteenth switch tube M13, the fourteenth switch tube M14, the fifteenth switch tube M15, and the sixteenth switch tube M16 are NMOS tubes; the first end of the tenth switch tube M10, the first end of the eleventh switch tube M11, the first end of the twelfth switch tube M12, the first end of the thirteenth switch tube M13, the first end of the fourteenth switch tube M14, the first end of the fifteenth switch tube M15, and the first end of the sixteenth switch tube M16 are gates of NMOS tubes, and the tenth switch tube M10 The second end of the eleventh switch tube M11, the second end of the twelfth switch tube M12, the second end of the thirteenth switch tube M13, the second end of the fourteenth switch tube M14, the second end of the fifteenth switch tube M15 and the second end of the sixteenth switch tube M16 are drains of the NMOS tube, and the third end of the tenth switch tube M10, the third end of the eleventh switch tube M11, the third end of the twelfth switch tube M12, the third end of the thirteenth switch tube M13, the third end of the fourteenth switch tube M14, the third end of the fifteenth switch tube M15 and the third end of the sixteenth switch tube M16 are sources of the NMOS tube.

[0097] That is, the gate of the tenth switch tube M10 is connected to the positive end of the first input signal, the drain of the tenth switch tube M10 is connected to one end of the first resistor R1 and the negative end of the output signal, the source of the tenth switch tube M10 is connected to the source of the eleventh switch tube M11 and the drain of the fourteenth switch tube M14, the gate of the eleventh switch tube M11 is connected to the negative end of the first input signal, the second section of the eleventh switch tube M11 is connected to one end of the second resistor R2 and the positive end of the output signal, the gate of the fourteenth switch tube M14 is connected to the positive end of the clock signal, the source of the fourteenth switch tube M14 is connected to the drain of the sixteenth switch tube M16, and the gate of the sixteenth switch tube M16 is connected to the reference voltage The source of the sixteenth switch tube M16 is grounded, the gate of the twelfth switch tube M12 is connected to the positive end of the second input signal, the drain of the twenty-second switch tube is connected to the negative end of the output signal, the source of the twelfth switch tube M12 is connected to the source of the thirteenth switch tube M13 and the drain of the fifteenth switch tube M15, the gate of the thirteenth switch tube M13 is connected to the negative end of the second input signal, the drain of the thirteenth switch tube M13 is connected to the positive end of the output signal, the gate of the fifteenth switch tube M15 is connected to the negative end of the clock signal, the source of the fifteenth switch tube M15 is connected to the drain of the sixteenth switch tube M16, and the other end of the first resistor R1 and the other end of the second resistor R2 are connected to a power supply.

[0098] refer to Figure 5 As shown, Figure 5 Medium V inp1 and V inn1 They are the positive and negative ends of the input signal, V inp2 and V inn2 They are the positive and negative ends of an input signal. outp and V outn They are the positive and negative ends of the output signal respectively. p and clk n It is the positive and negative end of the clock signal. M10~M16 are all NMOS tubes, among which M10~M3 are input tubes, M14 and M15 are clock control tubes, and M16 is a constant current tube. M16 is controlled by the reference voltage V b At a given voltage V b Under this condition, M16 provides a constant current. The conduction of M14 and M15 is controlled by the clock signal clk p and clk n When the clock signal clk p or clk n When M14 is turned on, the multiplexing circuit 60 selects V inp1 and V inn1 , and output; when M15 is turned on, the multiplexing circuit 60 selects V inp2 and V inn2 , and output it.

[0099] In some embodiments, it also includes:

[0100] The weighting circuit is used to amplify or reduce the input signal, and output the processed signals of the first preset number of paths in parallel to the delay circuit 10, and output the processed signals of the second preset number of paths in parallel to the thermometer circuit 20.

[0101] The weighted circuit based on row and column transmission lines pre-processes the input signal and multiplies it with the built-in coefficients in the weighted circuit in the order of input to achieve amplitude amplification or reduction. Figure 2 As shown, the signal V in The signals are input to the weighted circuit in a column manner, and the weighted circuit amplifies or reduces the input signals, and then outputs the processed signals in a row manner, i.e., in parallel. The signals of the first preset number of paths are output in parallel to the delay circuit 10, and the signals of the second preset number of paths are output in parallel to the thermometer circuit 20. Figure 2 Medium -3 to c 3 Represents the coefficient.

[0102] In some embodiments, the weighting circuit comprises:

[0103] Multiple D flip-flops and weight circuits; each of the D flip-flops is connected in series, and the output end of each of the D flip-flops is respectively connected to one of the weight circuits; the D flip-flops are used to sample and hold the input signal, and the weight circuit is used to multiply the signal output by the corresponding D flip-flop by a weighting coefficient and then output it.

[0104] In this embodiment, the weighting circuit includes a multi-channel D flip-flop and a weight circuit. The function of the D flip-flop is to implement sampling and holding of the input signal. The signal is first input into the first D flip-flop, and then the output of the first D flip-flop is input into the next D flip-flop, and so on. The function of the weight circuit is to multiply the signal output by the D flip-flop by the weight coefficient and then output it.

[0105] refer to Figure 6 As shown, in some embodiments, the weighting circuit includes seven D flip-flops and seven weight circuits.

[0106] In this embodiment, the weighting circuit includes seven D flip-flops and seven weighting circuits. The weighting circuit outputs seven signals, four of which are input to the delay circuit 10 and the other three are input to the thermometer circuit 20.

[0107] Wherein, in some embodiments, the D flip-flop includes:

[0108] A master latch and a slave latch; the master latch is connected to the positive end and the negative end of the input signal, and the slave latch is connected to the master latch and the positive end and the negative end of the output signal.

[0109] refer to Figure 7 As shown, the D flip-flop includes a master-slave two-stage latch. Figure 7 Medium V ip 、V in and V op 、V on They are input and output signals, clk p 、clk n is a differential clock signal, Q o is the output signal of the master latch, V bias is the bias voltage of the tail current tube. Both the master latch and the slave latch include resistors and NMOS tubes. The connection between each NMOS tube and resistor is as follows: Figure 7 As shown: The gate of NMOS tube Q1 is connected to the differential clock signal clk p The source of NMOS tube Q1 is connected to the drain of NMOS tube Q13, the drain of NMOS tube Q1 is connected to the source of NMOS tube Q2 and the source of NMOS tube Q3, and the gate of NMOS tube Q2 is connected to the input signal V ipThe drain of NMOS tube Q2 is connected to the resistor, the drain of NMOS tube Q4 and the gate of NMOS tube Q5, and the gate of NMOS tube Q3 is connected to the input signal V in The drain of NMOS tube Q3 is connected to the gate of NMOS tube Q4, the drain of NMOS tube Q5 and the resistor, the source of NMOS tube Q4 is connected to the source of NMOS tube Q5 and the drain of NMOS tube Q6, the gate of NMOS tube Q6 is connected to clkn, and the gate of NMOS tube Q13, i.e. the tail current tube, is connected to V bias The gate of NMOS tube Q7 is connected to the drain of NMOS tube Q3, the gate of NMOS tube Q4 and the drain of NMOS tube Q5. The drain of NMOS tube Q7 is connected to the resistor and the output signal V on The source of NMOS tube Q7 is connected to the source of NMOS tube Q8 and the drain of NMOS tube Q9, the gate of NMOS tube Q8 is connected to the drain of NMOS tube Q2, the drain of NMOS tube Q4 and the gate of NMOS tube Q5, and the drain of NMOS tube Q8 is connected to the resistor and the output signal V op The gate of NMOS tube Q9 is connected to clkn, the source of NMOS tube Q9 is connected to the drain of NMOS tube Q14, and the gate of NMOS tube Q10 is connected to the output signal V op , the drain of NMOS tube Q10 is connected to the output signal V on The source of NMOS tube Q10 is connected to the source of NMOS tube Q11 and the drain of NMOS tube Q12, and the drain of NMOS tube Q11 is connected to the output signal V op The gate of NMOS tube Q11 is connected to the output signal V on The gate of NMOS tube Q12 is connected to clk p The source of NMOS tube Q12 is connected to the drain of NMOS tube Q14, and the gate of NMOS tube Q14, i.e. the tail current tube, is connected to V bias .

[0110] In some embodiments, the weight circuit comprises:

[0111] a seventeenth switch tube M17, an eighteenth switch tube M18, a nineteenth switch tube M19, a third resistor R3 and a fourth resistor R4; a first end of the seventeenth switch tube M17 is connected to the positive end of the input signal, a second end of the seventeenth switch tube M17 is connected to the third end of the eighteenth switch tube M18, a third end of the seventeenth switch tube M17 is connected to one end of the third resistor R3 and a negative end of the output signal, a first end of the eighteenth switch tube M18 is connected to a controllable voltage, a second end of the eighteenth switch tube M18 is grounded, a first end of the nineteenth switch tube M19 is connected to the negative end of the input signal, a second end of the nineteenth switch tube M19 is connected to the third end of the eighteenth switch tube M18, a third end of the nineteenth switch tube M19 is connected to one end of the fourth resistor R4 and a positive end of the output signal, and the other end of the third resistor R3 and the other end of the fourth resistor R4 are connected to a power supply.

[0112] In this embodiment, the weight circuit includes a switch tube and a resistor. The resistor is used to represent different weighting coefficients. Different weighting coefficients correspond to different currents and thus to different voltages.

[0113] In some embodiments, the seventeenth switch tube M17, the eighteenth switch tube M18 and the nineteenth switch tube M19 are NMOS tubes, the first end of the seventeenth switch tube M17, the first end of the eighteenth switch tube M18 and the first end of the nineteenth switch tube M19 are gates of the NMOS tubes, the second end of the seventeenth switch tube M17, the second end of the eighteenth switch tube M18 and the second end of the nineteenth switch tube M19 are sources of the NMOS tubes, and the third end of the seventeenth switch tube M17, the third end of the eighteenth switch tube M18 and the third end of the nineteenth switch tube M19 are drains of the NMOS tubes.

[0114] That is, the gate of the seventeenth switch tube M17 is connected to the positive end of the input signal, the source of the seventeenth switch tube M17 is connected to the drain of the eighteenth switch tube M18, the drain of the seventeenth switch tube M17 is connected to one end of the third resistor R3 and the negative end of the output signal, the gate of the eighteenth switch tube M18 is connected to the controllable voltage, the source of the eighteenth switch tube M18 is grounded, the gate of the nineteenth switch tube M19 is connected to the negative end of the input signal, the source of the nineteenth switch tube M19 is connected to the drain of the eighteenth switch tube M18, the drain of the nineteenth switch tube M19 is connected to one end of the fourth resistor R4 and the positive end of the output signal, and the other end of the third resistor R3 and the other end of the fourth resistor R4 are connected to a power supply.

[0115] refer to Figure 8 As shown, Figure 8 Medium V inp and Vinn It is the positive and negative terminals of the input signal, V op 、V on It is the positive and negative end of the output signal. c is a controllable voltage used to provide current. The different weighting coefficients (c -3 ~c 3 ). Different weighting coefficients correspond to different currents, and thus to different voltages V c .

[0116] When no filtering and numerical interpolation are performed, the final output signal Vout is as follows: Fig. 9 As shown, 127 or 2 7 Digital signals constitute an analog signal. Fig. 9 It can be seen that the adjacent digital signals are in a step-like shape, with strong quantization errors and poor signal smoothness. After adding the filter circuit 40 and the numerical interpolation circuit 50, the final output signal V out like Fig.10 As shown, while the accuracy of the signal is enhanced, the signal smoothness is enhanced by reducing the difference between adjacent signals.

[0117] In summary, the pulse amplitude modulation forward equalization circuit provided by the present invention converts the signal into an analog signal through a digital-to-analog conversion circuit, solves the interference between adjacent signals, and compensates for the signal attenuation caused by the channel. The filtering circuit can suppress the quantization noise in the quantized signal and improve the anti-interference ability of the transmission signal. The amplitude of the quantized signal of the digital-to-analog conversion circuit is equally divided by a numerical interpolation circuit to enhance the quantization accuracy and improve the smoothness of the signal. The circuit can support different transmission rates under the chiplet link and is fully suitable for various interconnection interfaces such as C2C and D2D.

[0118] Because the situation is complicated, it is impossible to list them one by one for explanation. Those skilled in the art should be able to realize that there may be multiple examples based on the basic principles of the embodiments provided in this application and combined with actual conditions, and they should all be within the scope of this application without paying enough creative work.

[0119] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0120] The technical solution provided by the present application is described in detail above. The principle and implementation method of the present application are described in detail using specific examples herein, and the description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the present application.

[0121] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

Claims

1. A pulse amplitude modulation forward equalization circuit, characterized in that: include: A delay circuit, used for delaying and outputting a first preset number of signals input into the delay circuit; A thermometer circuit, used for converting a second preset number of signals input into the thermometer circuit into a thermometer code and outputting the code; A digital-to-analog conversion circuit, used for performing digital-to-analog conversion on the signals output by the delay circuit and the thermometer circuit; The digital-to-analog conversion circuit comprises: N digital-to-analog conversion branches; N is equal to the sum of the number of signals output by the delay circuit and the number of signals output by the thermometer circuit; A filter circuit, used for filtering the analog signal output by the digital-to-analog conversion circuit; A numerical interpolation circuit, used for performing numerical interpolation on the analog signal output by the filtering circuit; the numerical interpolation circuit comprises: a delay unit and a multi-channel resistor, each of which is connected in series; the input end of the delay unit is connected to the output end of the digital-to-analog conversion circuit, the output end of the delay unit is connected to the resistor at one end of each resistor connected in series, and the resistor at the other end of each resistor connected in series is connected to the output end of the digital-to-analog conversion circuit; A multiplexing circuit is used to output the analog signals output by the numerical interpolation circuit one by one in sequence; the multiplexing circuit includes: M-way two-choose-one circuits; M*2 is equal to the number of channels of signals output by the numerical interpolation circuit.

2. The pulse amplitude modulation forward equalization circuit according to claim 1, characterized in that: The delay circuit is specifically used to delay the output of four signals input into the delay circuit.

3. The pulse amplitude modulation forward equalization circuit according to claim 1, characterized in that: The thermometer circuit is specifically used to convert three-way signals input into the thermometer circuit into seven-way thermometer codes and output them.

4. The pulse amplitude modulation forward equalization circuit according to claim 1, characterized in that: The digital-to-analog conversion branch includes: a first switch tube, a second switch tube and a third switch tube; the first end of the first switch tube is connected to a reference voltage, the second end of the first switch tube is grounded, the third end of the first switch tube is connected to the second end of the second switch tube and the second end of the third switch tube, the first end of the second switch tube is connected to the positive end of the input signal, the third end of the second switch tube is connected to the negative end of the output signal, the negative end of the output signal is connected to the filter circuit, the first end of the third switch tube is connected to the negative end of the input signal, the third end of the third switch tube is connected to the positive end of the output signal, and the positive end of the output signal is connected to the filter circuit.

5. The pulse amplitude modulation forward equalization circuit according to claim 4, characterized in that: The digital-to-analog conversion circuit includes eleven digital-to-analog conversion branches; among them, four of the digital-to-analog conversion branches are used to perform digital-to-analog conversion on four signals output by the delay circuit, and seven of the digital-to-analog conversion branches are used to perform digital-to-analog conversion on seven signals output by the thermometer circuit.

6. The pulse amplitude modulation forward equalization circuit according to claim 4, characterized in that: The first switch tube, the second switch tube and the third switch tube are NMOS tubes; the first end of the first switch tube, the first end of the second switch tube and the first end of the third switch tube are gates of the NMOS tubes, the second end of the first switch tube, the second end of the second switch tube and the second end of the third switch tube are sources of the NMOS tubes, and the third end of the first switch tube, the third end of the second switch tube and the third end of the third switch tube are drains of the NMOS tubes.

7. The pulse amplitude modulation forward equalization circuit according to claim 1, characterized in that: The filtering circuit comprises: a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube, a ninth switch tube, a first capacitor and a second capacitor; a first end of the fourth switch tube is connected to a controllable voltage, a second end of the fourth switch tube is grounded, a third end of the fourth switch tube is connected to the second end of the fifth switch tube, the first end of the fifth switch tube, the first end of the sixth switch tube and one end of the first capacitor, a third end of the fifth switch tube is connected to the third end of the sixth switch tube, the third end of the seventh switch tube and the third end of the eighth switch tube, a second end of the sixth switch tube is connected to the negative end of the output signal of the digital-to-analog conversion circuit, the other end of the first capacitor is grounded, a second end of the seventh switch tube is connected to the positive end of the output signal of the digital-to-analog conversion circuit, a first end of the seventh switch tube is connected to the first end of the eighth switch tube, the second end of the eighth switch tube, the third end of the ninth switch tube and one end of the second capacitor, a second end of the ninth switch tube is grounded, a first end of the ninth switch tube is connected to a controllable voltage, and the other end of the second capacitor is grounded.

8. The pulse amplitude modulation forward equalization circuit according to claim 7, characterized in that: The fourth switch tube and the ninth switch tube are NMOS tubes, the first end of the fourth switch tube and the first end of the ninth switch tube are the gate of the NMOS tube, the second end of the fourth switch tube and the second end of the ninth switch tube are the source of the NMOS tube, and the third end of the fourth switch tube and the third end of the ninth switch tube are the drain of the NMOS tube; the fifth switch tube, the sixth switch tube, the seventh switch tube and the eighth switch tube are PMOS tubes, the first end of the fifth switch tube, the first end of the sixth switch tube, the first end of the seventh switch tube and the first end of the eighth switch tube are the gate of the PMOS tube, the second end of the fifth switch tube, the second end of the sixth switch tube, the second end of the seventh switch tube and the second end of the eighth switch tube are the drain of the PMOS tube, and the third end of the fifth switch tube, the third end of the sixth switch tube, the third end of the seventh switch tube and the third end of the eighth switch tube are the source of the PMOS tube.

9. The pulse amplitude modulation forward equalization circuit according to claim 1, characterized in that: The delay unit includes a buffer.

10. The pulse amplitude modulation forward equalization circuit according to claim 1, characterized in that: The numerical interpolation circuit comprises four resistors which are connected in series, and the numerical interpolation circuit outputs four signals.

11. The pulse amplitude modulation forward equalization circuit according to claim 1, characterized in that: The two-choice circuit includes a tenth switch tube, an eleventh switch tube, a twelfth switch tube, a thirteenth switch tube, a fourteenth switch tube, a fifteenth switch tube, a sixteenth switch tube, a first resistor and a second resistor; the first end of the tenth switch tube is connected to the positive end of the first input signal, the second end of the tenth switch tube is connected to one end of the first resistor and the negative end of the output signal, the third end of the tenth switch tube is connected to the third end of the eleventh switch tube and the second end of the fourteenth switch tube, the first end of the eleventh switch tube is connected to the negative end of the first input signal, the second end of the eleventh switch tube is connected to one end of the second resistor and the positive end of the output signal, the first end of the fourteenth switch tube is connected to the positive end of the clock signal, and the third end of the fourteenth switch tube is connected to the positive end of the clock signal. The second end of the sixteenth switch tube is connected to the reference voltage, the third end of the sixteenth switch tube is grounded, the first end of the twelfth switch tube is connected to the positive end of the second input signal, the second end of the twelfth switch tube is connected to the negative end of the output signal, the third end of the twelfth switch tube is connected to the third end of the thirteenth switch tube and the second end of the fifteenth switch tube, the first end of the thirteenth switch tube is connected to the negative end of the second input signal, the second end of the thirteenth switch tube is connected to the positive end of the output signal, the first end of the fifteenth switch tube is connected to the negative end of the clock signal, the third end of the fifteenth switch tube is connected to the second end of the sixteenth switch tube, and the other end of the first resistor and the other end of the second resistor are connected to a power supply.

12. The pulse amplitude modulation forward equalization circuit according to claim 1, characterized in that: The multiplexing circuit includes two circuits of the two-choose-one circuit.

13. The pulse amplitude modulation forward equalization circuit according to claim 11, characterized in that: The tenth switch tube, the eleventh switch tube, the twelfth switch tube, the thirteenth switch tube, the fourteenth switch tube, the fifteenth switch tube and the sixteenth switch tube are NMOS tubes; the first end of the tenth switch tube, the first end of the eleventh switch tube, the first end of the twelfth switch tube, the first end of the thirteenth switch tube, the first end of the fourteenth switch tube, the first end of the fifteenth switch tube and the first end of the sixteenth switch tube are gates of the NMOS tubes, the second end of the tenth switch tube, the second end of the eleventh switch tube, the second end of the twelfth switch tube, the second end of the thirteenth switch tube, the second end of the fourteenth switch tube, the second end of the fifteenth switch tube and the second end of the sixteenth switch tube are drains of the NMOS tubes, and the third end of the tenth switch tube, the third end of the eleventh switch tube, the third end of the twelfth switch tube, the third end of the thirteenth switch tube, the third end of the fourteenth switch tube, the third end of the fifteenth switch tube and the third end of the sixteenth switch tube are sources of the NMOS tubes.

14. The pulse amplitude modulation forward equalization circuit according to claim 1, characterized in that: Also includes: The weighting circuit is used to amplify or reduce the input signal, and output the processed signals of the first preset number of paths in parallel to the delay circuit, and output the processed signals of the second preset number of paths in parallel to the thermometer circuit.

15. The pulse amplitude modulation forward equalization circuit according to claim 14, characterized in that: The weighting circuit comprises: Multiple D flip-flops and weight circuits; each of the D flip-flops is connected in series, and the output end of each of the D flip-flops is respectively connected to one of the weight circuits; the D flip-flops are used to sample and hold the input signal, and the weight circuit is used to multiply the signal output by the corresponding D flip-flop by a weighting coefficient and then output it.

16. The pulse amplitude modulation forward equalization circuit according to claim 15, characterized in that: The weighted circuit includes seven D flip-flops and seven weight circuits.

17. The pulse amplitude modulation forward equalization circuit according to claim 15, characterized in that: The D flip-flop comprises: A master latch and a slave latch; the master latch is connected to the positive end and the negative end of the input signal, and the slave latch is connected to the master latch and the positive end and the negative end of the output signal.

18. The pulse amplitude modulation forward equalization circuit according to claim 15, characterized in that: The weight circuit comprises: A seventeenth switch tube, an eighteenth switch tube, a nineteenth switch tube, a third resistor and a fourth resistor; the first end of the seventeenth switch tube is connected to the positive end of the input signal, the second end of the seventeenth switch tube is connected to the third end of the eighteenth switch tube, the third end of the seventeenth switch tube is connected to one end of the third resistor and the negative end of the output signal, the first end of the eighteenth switch tube is connected to a controllable voltage, the second end of the eighteenth switch tube is grounded, the first end of the nineteenth switch tube is connected to the negative end of the input signal, the second end of the nineteenth switch tube is connected to the third end of the eighteenth switch tube, the third end of the nineteenth switch tube is connected to one end of the fourth resistor and the positive end of the output signal, and the other end of the third resistor and the other end of the fourth resistor are connected to a power supply.

19. The pulse amplitude modulation forward equalization circuit according to claim 18, characterized in that: The seventeenth switch tube, the eighteenth switch tube and the nineteenth switch tube are NMOS tubes, the first end of the seventeenth switch tube, the first end of the eighteenth switch tube and the first end of the nineteenth switch tube are gates of the NMOS tube, the second end of the seventeenth switch tube, the second end of the eighteenth switch tube and the second end of the nineteenth switch tube are sources of the NMOS tube, and the third end of the seventeenth switch tube, the third end of the eighteenth switch tube and the third end of the nineteenth switch tube are drains of the NMOS tube.

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