A positive and negative level conversion circuit

Abstract

The application relates to the technical field of radio frequency switches, and discloses a positive and negative level conversion circuit. The positive and negative level conversion circuit drives a positive voltage power input unit and a negative voltage power input unit through a first logic signal and a second logic signal, forms a first conversion signal with positive voltage and zero voltage alternately at a first output unit, and forms a second conversion signal with zero voltage and negative voltage alternately at a second output unit through a positive voltage inverter ring, a complementary logic circuit, a first switch, a second switch, a third switch, a fourth switch and a negative voltage inverter ring, so that the first output unit alternately works in a positive voltage domain and a ground voltage domain, and the second output unit alternately works in a negative voltage domain and the ground voltage domain. At this time, four layers of switches coexist on a current path, the risk that the switches bear 2 times of positive voltage is avoided, and the technical problem that the switches of the positive and negative level conversion circuit in the prior art have the risk of overvoltage is solved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of switch control technology, and in particular to a positive-negative level conversion circuit. Background Art

[0002] With the continuous iteration of integrated circuit design technology and manufacturing processes, the requirements for circuit performance are becoming increasingly higher. In the design of RF switches using SOI technology, in order to improve isolation, the low potential of the control logic needs to be in a negative voltage state so that the switch is in a highly isolated state when it is turned off. This requires the logic controlling the switch gate to output PVDD (positive power supply) when the switch is turned on and NVDD (negative power supply) when the switch is turned off.

[0003] Due to the 2VDD voltage difference between the positive and negative power supplies, the reliability design of the positive and negative level shifter circuits becomes a key concern. Traditional level shifter circuits consist of an input stage, a level shifter stage, and an output stage. A current path exists between the positive and negative power supply terminals. Across the entire module circuit, the rising and falling edge speeds of the differential control signal vary, and the MOS transistors (MOS transistors) may be subject to the 2VDD voltage. This poses significant risks to the reliability of the level shifter circuit and also introduces application risks to the preceding and subsequent circuits. Summary of the Invention

[0004] In view of the above problems, an embodiment of the present invention provides a positive-negative level conversion circuit, which is used to solve the technical problem of overvoltage risk in switches of the positive-negative level conversion circuit in the prior art.

[0005] According to one aspect of an embodiment of the present invention, a positive-negative level conversion circuit is provided, comprising:

[0006] a positive voltage power supply input unit, configured to receive a first logic signal and output a corresponding first control signal according to the first logic signal;

[0007] a negative voltage power supply input unit, configured to receive a second logic signal and output a corresponding second control signal according to the first logic signal;

[0008] a positive inverter ring, connected to the positive power input unit and the negative power input unit, respectively, and configured to calculate, through an internal logic circuit of the positive inverter ring, a first switch control signal, a second switch control signal, a first output signal, and a second output signal corresponding to the first control signal and the second control signal, and output them;

[0009] a complementary logic circuit, connected to the positive inverter ring, the positive voltage power input unit, and the negative voltage power input unit, respectively, and outputting a corresponding third control signal and a fourth control signal according to the first control signal and the second control signal;

[0010] a negative inverter ring, connected to the complementary logic circuit, and configured to calculate, through an internal logic circuit of the positive inverter ring, a third switch control signal, a fourth switch control signal, a third output signal, and a fourth output signal corresponding to the third control signal and the fourth control signal, and output them;

[0011] a first switch, connected to the positive voltage power input unit, the positive inverter ring, and the complementary logic circuit, respectively, and turned on or off according to the first switch control signal;

[0012] a second switch, connected to the positive voltage power input unit, the positive power inverter ring, and the complementary logic circuit, and turned on or off according to the second switch control signal;

[0013] a third switch, connected to the negative inverter ring and the complementary logic circuit respectively, and turned on or off according to the third switch control signal;

[0014] a fourth switch, connected to the negative inverter ring and the complementary logic circuit respectively, and turned on or off according to the fourth switch control signal;

[0015] a first output unit connected to the positive inverter ring and the negative inverter ring respectively, and outputting a corresponding first conversion signal according to the first output signal and the third output signal; and

[0016] The second output unit is connected to the positive inverter ring and the negative inverter ring respectively, and outputs a corresponding second conversion signal according to the second output signal and the fourth output signal.

[0017] In an optional manner, the positive inverter ring includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter and a sixth inverter, the power supply end of the first inverter, the power supply end of the third inverter, the power supply end of the fourth inverter and the power supply end of the sixth inverter are all connected to a forward voltage, the power supply end of the second inverter is connected to the second control signal, and the power supply end of the fifth inverter is connected to the first control signal; the ground end of the first inverter, the ground end of the second inverter, the ground end of the third inverter, the ground end of the fourth inverter, the ground end of the fifth inverter and the ground end of the sixth inverter are all grounded; the output of the fifth inverter is connected to the ground; The output terminal of the fourth inverter is connected to the input terminal of the fourth inverter, and receives the first control signal when the first switch is turned on; the output terminal of the fourth inverter is connected to the input terminal of the third inverter, and outputs the second switch control signal; the output terminal of the third inverter is connected to the input terminal of the second inverter, and outputs the second output signal; the output terminal of the second inverter is connected to the input terminal of the first inverter, and receives the second control signal when the second switch is turned on; the output terminal of the first inverter is connected to the input terminal of the sixth inverter, and outputs the first switch control signal; the output terminal of the sixth inverter is connected to the input terminal of the fifth inverter, and outputs the first output signal.

[0018] In an optional manner, the negative-charge inverter ring includes a fifteenth inverter, a sixteenth inverter, a seventeenth inverter, an eighteenth inverter, a nineteenth inverter and a twentieth inverter, the power supply end of the fifteenth inverter, the power supply end of the seventeenth inverter, the power supply end of the eighteenth inverter and the power supply end of the twentieth inverter are all connected to a negative voltage, the power supply end of the sixteenth inverter is connected to the third control signal, and the power supply end of the nineteenth inverter is connected to the fourth control signal; the ground end of the fifteenth inverter, the ground end of the sixteenth inverter, the ground end of the seventeenth inverter, the ground end of the eighteenth inverter, the ground end of the nineteenth inverter and the ground end of the twentieth inverter are all grounded; the ground end of the sixteenth inverter The output end of the seventeenth inverter is connected to the input end of the seventeenth inverter, and receives the third control signal when the third switch is turned on; the output end of the seventeenth inverter is connected to the input end of the eighteenth inverter, and outputs the fourth switch control signal; the output end of the eighteenth inverter is connected to the input end of the nineteenth inverter, and outputs the fourth output signal; the output end of the nineteenth inverter is connected to the input end of the twentieth inverter, and receives the fourth control signal when the fourth switch is turned on; the output end of the twentieth inverter is connected to the input end of the fifteenth inverter, and outputs the third switch control signal; the output end of the fifteenth inverter is connected to the input end of the sixteenth inverter, and outputs the third output signal.

[0019] In an optional manner, the complementary logic circuit includes a first resistor, a second resistor, a third capacitor tube, a fourth capacitor tube, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, a first low-pass transmission gate, and a second low-pass transmission gate. The power supply terminal of the eleventh inverter is connected to the first end of the third capacitor tube and is used to receive the first control signal. The ground terminal of the eleventh inverter is respectively connected to the second end of the third capacitor tube and the output terminal of the thirteenth inverter, and outputs the third control signal. The input terminal of the eleventh inverter is grounded, and the output terminal of the eleventh inverter is connected to the positive input terminal of the first low-pass transmission gate. The inverting input terminal of a low-pass transmission gate is grounded, the output terminal of the first low-pass transmission gate is connected to the input terminal of the twelfth inverter, the output terminal of the twelfth inverter is respectively connected to the power supply terminal of the fourteenth inverter and the first terminal of the fourth capacitor tube, and outputs the fourth control signal; the input terminal of the thirteenth inverter is connected to the output terminal of the second low-pass transmission gate; the inverting input terminal of the second low-pass transmission gate is grounded, the positive input terminal of the second low-pass transmission gate is connected to the output terminal of the fourteenth inverter; the input terminal of the fourteenth inverter is grounded, the ground terminal of the fourteenth inverter is connected to the second terminal of the fourth capacitor tube, and is used to obtain the second control signal.

[0020] In an optional manner, each inverter includes a third PMOS transistor and a seventh NMOS transistor, the gate of the third PMOS transistor is connected to the gate of the seventh NMOS transistor, forming the input end of the inverter, the source of the third PMOS transistor forms the power supply end of the inverter, the drain of the third PMOS transistor is connected to the drain of the seventh NMOS transistor, and forms the output end of the inverter; the source of the seventh NMOS transistor forms the ground end of the inverter.

[0021] In an optional manner, the first low-pass transmission gate and the second low-pass transmission gate each separately include a fifth NMOS tube and a sixth NMOS tube, the drain of the fifth NMOS tube is connected to the gate of the sixth NMOS tube, and the connection node thereof is the positive input terminal of the first low-pass transmission gate / the positive input terminal of the second low-pass transmission gate, the gate of the fifth NMOS tube is connected to the drain of the sixth NMOS tube, and the connection node thereof is the reverse input terminal of the first low-pass transmission gate / the reverse input terminal of the second low-pass transmission gate, and the source of the fifth NMOS tube is connected to the source of the sixth NMOS tube, and the connection node thereof is the output terminal of the first low-pass transmission gate / the output terminal of the second low-pass transmission gate.

[0022] In an optional manner, the first switch and the second switch are NMOS transistors.

[0023] In an optional manner, the third switch and the fourth switch are PMOS tubes.

[0024] In an optional manner, the positive voltage power input unit includes an eighth inverter and a positive voltage power supply terminal, the positive voltage power supply terminal obtains the first logic signal, the positive voltage power supply terminal is connected to the input terminal of the eighth inverter, and the output terminal of the eighth inverter outputs the first control signal;

[0025] The negative voltage power input unit includes a ninth inverter and a negative voltage power supply terminal. The negative voltage power supply terminal obtains the second logic signal. The negative voltage power supply terminal is connected to the input terminal of the ninth inverter. The output terminal of the ninth inverter outputs the second control signal.

[0026] In an optional manner, the first output unit includes a seventh inverter and a first output end, the input end of the seventh inverter is grounded, the power end of the seventh inverter is connected to the positive inverter ring, the ground end of the seventh inverter is connected to the negative inverter ring, and the output end of the seventh inverter is connected to the first output end and is used to output the first conversion signal;

[0027] The negative voltage power input unit includes a tenth inverter and a second output end, the input end of the tenth inverter is grounded, the power end of the tenth inverter is connected to the positive power inverter ring, the ground end of the seventh inverter is connected to the negative power inverter ring, and the output end of the tenth inverter is connected to the second output end and is used to output the second conversion signal.

[0028] The positive and negative level conversion circuit of the present application drives the positive voltage power input unit and the negative voltage power input unit through the first logic signal and the second logic signal, and forms a first conversion signal of alternating positive voltage and zero voltage in the first output unit and a second conversion signal of alternating zero voltage and negative voltage in the second output unit through the positive inverter ring, the complementary logic circuit, the first switch, the second switch, the third switch, the fourth switch and the negative inverter ring, so that the first output unit alternately works in the positive voltage domain and the ground voltage domain, and the second output unit alternately works in the negative voltage domain and the ground voltage domain. At this time, there are a total of 4 layers of switches in the current path between the positive voltage power input unit, the negative voltage power input unit and the first output unit and the second output unit station, which avoids the risk of the switch being subjected to twice the positive voltage, and solves the technical problem of overvoltage risk in the switch of the positive and negative level conversion circuit in the prior art.

[0029] The above description is only an overview of the technical solutions of the embodiments of the present invention. In order to more clearly understand the technical means of the embodiments of the present invention, they can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are only used to illustrate the embodiments and are not to be considered as limiting the present invention. In addition, the same reference symbols are used to represent the same components throughout the drawings. In the drawings:

[0031] Figure 1 A circuit diagram of a positive-negative level conversion circuit provided by the present invention is shown;

[0032] Figure 2 A logic diagram of a positive and negative voltage inverter in a positive and negative level conversion circuit provided by the present invention is shown;

[0033] Figure 3 A schematic diagram of a low-pass transmission gate in a positive-negative level conversion circuit provided by the present invention is shown;

[0034] Figure 4 A schematic diagram showing the voltages at the output terminals of each inverter in a working state in the positive-negative level conversion circuit provided by the present invention is shown;

[0035] Figure 5 A schematic diagram showing voltages at output terminals of each inverter in another working state of the positive-negative level conversion circuit provided by the present invention is shown. DETAILED DESCRIPTION

[0036] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0037] The present application proposes a positive-negative level conversion circuit, which is used to solve the technical problem of overvoltage risk in switches of the positive-negative level conversion circuit in the prior art.

[0038] In an alternative embodiment, referring to Figure 1 As shown, the positive and negative level conversion circuit includes:

[0039] A positive voltage power supply input unit, configured to receive a first logic signal and output a corresponding first control signal according to the first logic signal;

[0040] A negative voltage power supply input unit, configured to receive a second logic signal and output a corresponding second control signal according to the first logic signal;

[0041] The positive inverter ring 10 is connected to the positive power supply input unit and the negative power supply input unit, respectively, and is used to calculate the first switch control signal, the second switch control signal, the first output signal, and the second output signal corresponding to the first control signal and the second control signal through the internal logic circuit of the positive inverter ring 10 and output them;

[0042] The complementary logic circuit 20 is connected to the positive inverter ring 10, the positive power supply input unit, and the negative power supply input unit, respectively, and outputs a corresponding third control signal and a fourth control signal according to the first control signal and the second control signal;

[0043] The negative inverter ring 30 is connected to the complementary logic circuit 20 and is used to calculate the third switch control signal, the fourth switch control signal, the third output signal, and the fourth output signal corresponding to the third control signal and the fourth control signal through the internal logic circuit of the positive inverter ring 10 and output them;

[0044] The first switch 40 is connected to the positive voltage power input unit, the positive inverter ring 10 and the complementary logic circuit 20 respectively, and is turned on or off according to the control signal of the first switch 40;

[0045] The second switch 50 is connected to the positive power supply input unit, the positive inverter ring 10 and the complementary logic circuit 20 respectively, and is turned on or off according to the control signal of the second switch 50;

[0046] The third switch 60 is connected to the negative inverter ring 30 and the complementary logic circuit 20 respectively, and is turned on or off according to the control signal of the third switch 60;

[0047] The fourth switch 70 is connected to the negative inverter ring 30 and the complementary logic circuit 20 respectively, and is turned on or off according to the control signal of the fourth switch 70;

[0048] The first output unit is connected to the positive inverter ring 10 and the negative inverter ring 30 respectively, and outputs a corresponding first conversion signal according to the first output signal and the third output signal; and

[0049] The second output unit is connected to the positive inverter ring 10 and the negative inverter ring 30 respectively, and outputs a corresponding second conversion signal according to the second output signal and the fourth output signal.

[0050] The positive-negative level conversion circuit of the present application drives the positive voltage power input unit and the negative voltage power input unit through the first logic signal and the second logic signal, and forms a first conversion signal of alternating positive voltage and zero voltage in the first output unit and a second conversion signal of alternating zero voltage and negative voltage in the second output unit through the positive inverter ring 10, the complementary logic circuit 20, the first switch 40, the second switch 50, the third switch 60, the fourth switch 70 and the negative inverter ring 30, so that the first output unit alternately works in the positive voltage domain and the ground voltage domain, and the second output unit alternately works in the negative voltage domain and the ground voltage domain. At this time, there are a total of 4 layers of switches in the current path between the positive voltage power input unit, the negative voltage power input unit and the first output unit and the second output unit station, which avoids the risk of the switch being subjected to twice the positive voltage, and solves the technical problem of the overvoltage risk of the switch in the positive-negative level conversion circuit in the prior art.

[0051] In an optional embodiment, the positive inverter ring 10 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5 and a sixth inverter INV6. The power supply terminal of the first inverter INV1, the power supply terminal of the third inverter INV3, the power supply terminal of the fourth inverter INV4 and the power supply terminal of the sixth inverter INV6 are all connected to the forward voltage, the power supply terminal of the second inverter INV2 is connected to the second control signal, and the power supply terminal of the fifth inverter INV5 is connected to the first control signal; the ground terminal of the first inverter INV1, the ground terminal of the second inverter INV2, the ground terminal of the third inverter INV3, the ground terminal of the fourth inverter INV4, the ground terminal of the fifth inverter INV5 and the ground terminal of the sixth inverter INV6 are connected to the forward voltage. Both are grounded; the output end of the fifth inverter INV5 is connected to the input end of the fourth inverter INV4, and when the first switch 40 is turned on, the first control signal is connected; the output end of the fourth inverter INV4 is connected to the input end of the third inverter INV3, and outputs the second switch 50 control signal; the output end of the third inverter INV3 is connected to the input end of the second inverter INV2, and outputs the second output signal; the output end of the second inverter INV2 is connected to the input end of the first inverter INV1, and when the second switch 50 is turned on, the second control signal is connected; the output end of the first inverter INV1 is connected to the input end of the sixth inverter INV6, and outputs the first switch 40 control signal; the output end of the sixth inverter INV6 is connected to the input end of the fifth inverter INV5, and outputs the first output signal.

[0052] Among them, reference Figure 4 as well as Figure 5 As shown, the positive inverter ring 10 includes two working states:

[0053] In the first state, the first control signal is high, the second control signal is low, and the initial state of the first switch 40 is on. Therefore, at this time, the level of the output end of the fifth inverter INV5 is high, the level of the output end of the fourth inverter INV4 is negative, that is, the second switch 50 control signal is negative and turned on at this time, then the output end of the third inverter INV3 outputs a high level as the second output signal, the level of the output end of the second inverter INV2 is negative, the level of the output end of the first inverter INV1 is high, that is, the first switch 40 control signal is high at this time, and the first switch 40 is turned on at this time. Then the output end of the sixth inverter INV6 outputs a negative level as the first output signal. Through the above process, a variety of reverse processes of high negative level are realized, and the appropriate level is selected to participate in the final operation through the cooperation therein, and the on and off of each switch can be quickly feedback controlled, thereby avoiding the excessive level voltage difference of the final operation.

[0054] In the second state, the first control signal is low, the second control signal is high, and the initial state of the first switch 40 is on. Therefore, at this time, the level of the output end of the fifth inverter INV5 is low, the level of the output end of the fourth inverter INV4 is high, that is, the second switch 50 control signal at this time is high-level turned on, then the output end of the third inverter INV3 outputs a low level as the second output signal, the level of the output end of the second inverter INV2 is high, the level of the output end of the first inverter INV1 is low, that is, the first switch 40 control signal at this time is low, and the first switch 40 at this time is turned off. Then the output end of the sixth inverter INV6 outputs a high level as the first output signal. Through the above process, a variety of reverse processes of high negative level are realized, and the appropriate level is selected to participate in the final operation through the cooperation therein, and the on-off of each switch can be quickly fed back to control, thereby avoiding the excessive level voltage difference of the last operation.

[0055] In an optional embodiment, the negative inverter ring 30 includes a fifteenth inverter INV15, a sixteenth inverter INV16, a seventeenth inverter INV17, an eighteenth inverter INV18, a nineteenth inverter INV19 and a twentieth inverter INV20, the power supply terminal of the fifteenth inverter INV15, the power supply terminal of the seventeenth inverter INV17, the power supply terminal of the eighteenth inverter INV18 and the power supply terminal of the twentieth inverter INV20 are all connected to the negative voltage, the power supply terminal of the sixteenth inverter INV16 is connected to the third control signal, and the power supply terminal of the nineteenth inverter INV19 is connected to the fourth control signal; the ground terminal of the fifteenth inverter INV15, the ground terminal of the sixteenth inverter INV16, the ground terminal of the seventeenth inverter INV17, the ground terminal of the eighteenth inverter INV18, the ground terminal of the nineteenth inverter INV19 and the twentieth inverter The ground terminals of INV20 are all grounded; the output terminal of the sixteenth inverter INV16 is connected to the input terminal of the seventeenth inverter, and receives the third control signal when the third switch 60 is turned on; the output terminal of the seventeenth inverter INV17 is connected to the input terminal of the eighteenth inverter INV18, and outputs the fourth switch 70 control signal; the output terminal of the eighteenth inverter INV18 is connected to the input terminal of the nineteenth inverter INV19, and outputs the fourth output signal; the output terminal of the nineteenth inverter INV19 is connected to the input terminal of the twentieth inverter INV20, and receives the fourth control signal when the fourth switch 70 is turned on; the output terminal of the twentieth inverter INV20 is connected to the input terminal of the fifteenth inverter INV15, and outputs the third switch 60 control signal; the output terminal of the fifteenth inverter INV15 is connected to the input terminal of the sixteenth inverter INV16, and outputs the third output signal.

[0056] Among them, reference Figure 4 as well as Figure 5 As shown, the negative inverter ring 30 includes two working states:

[0057] In the first state, the third control signal is a negative level, the fourth control signal is a low level, and the initial state of the third switch 60 is on. Therefore, at this time, the level of the output end of the sixteenth inverter INV16 is a negative level, the level of the output end of the seventeenth inverter INV17 is a low level, that is, the fourth switch 70 control signal is low-level and turned on at this time, then the output end of the eighteenth inverter INV18 outputs a negative level as the fourth output signal, the level of the output end of the nineteenth inverter INV19 is a low level, the level of the output end of the twentieth inverter INV20 is a negative level, that is, the third switch 60 control signal is negative at this time, and the first switch 40 is turned on at this time. Then, the output end of the fifteenth inverter INV15 outputs a low level as the third output signal. Through the above process, a variety of reverse processes of high negative level are realized, and the appropriate level is selected to participate in the final operation through the cooperation therein, and the on and off of each switch can be quickly feedback-controlled, thereby avoiding the excessive level voltage difference of the final operation.

[0058] In the second state, the third control signal is low, the fourth control signal is negative, and the initial state of the third switch 60 is on. Therefore, at this time, the level of the output end of the sixteenth inverter INV16 is low, the level of the output end of the seventeenth inverter INV17 is negative, that is, the fourth switch 70 control signal is negative and turned on at this time, then the output end of the eighteenth inverter INV18 outputs a low level as the fourth output signal, the level of the output end of the nineteenth inverter INV19 is negative, the level of the output end of the twentieth inverter INV20 is low, that is, the third switch 60 control signal is low at this time, and the third switch 60 is turned off at this time. Then the output end of the fifteenth inverter INV15 outputs a negative level as the third output signal. Through the above process, a variety of reverse processes of high negative level are realized, and the appropriate level is selected to participate in the final operation through the cooperation therein, and the on and off of each switch can be quickly feedback-controlled, thereby avoiding the excessive level voltage difference of the final operation.

[0059] In an optional embodiment, the complementary logic circuit 20 includes a first resistor R1, a second resistor R2, a third capacitor MN3, a fourth capacitor MN4, an eleventh inverter INV11, a twelfth inverter INV12, a thirteenth inverter INV13, a fourteenth inverter INV14, a first low-pass transmission gate LP1, and a second low-pass transmission gate LP2. The power supply terminal of the eleventh inverter INV11 is connected to the first terminal of the third capacitor MN3 and is used to receive the first control signal. The ground terminal of the eleventh inverter INV11 is respectively connected to the second terminal of the third capacitor MN3 and the output terminal of the thirteenth inverter INV13, and outputs the third control signal. The input terminal of the eleventh inverter INV11 is grounded, and the output terminal of the eleventh inverter INV11 is connected to the first low-pass transmission gate LP1. The positive input terminal of the first low-pass transmission gate LP1 is connected; the reverse input terminal of the first low-pass transmission gate LP1 is grounded, the output terminal of the first low-pass transmission gate LP1 is connected to the input terminal of the twelfth inverter INV12, the output terminal of the twelfth inverter INV12 is respectively connected to the power supply terminal of the fourteenth inverter INV14 and the first terminal of the fourth capacitor tube MN4, and outputs the fourth control signal; the input terminal of the thirteenth inverter is connected to the output terminal of the second low-pass transmission gate LP2; the reverse input terminal of the second low-pass transmission gate LP2 is grounded, the positive input terminal of the second low-pass transmission gate LP2 is connected to the output terminal of the fourteenth inverter INV14; the input terminal of the fourteenth inverter INV14 is grounded, the ground terminal of the fourteenth inverter INV14 is connected to the second terminal of the fourth capacitor tube MN4, and is used to obtain the second control signal.

[0060] Among them, reference Figure 4 as well as Figure 5 As shown, the complementary logic circuit 20 includes two working states:

[0061] In the first state, the first control signal is at a low level and the second control signal is at a high level. After the low level flows through the power supply terminal of the fourteenth inverter INV14, the fourteenth inverter INV14 outputs a high level to the second low-pass transmission gate LP2, causing the signal to pass through the second low-pass transmission gate LP2 and the thirteenth inverter INV13 and output a fourth control signal at a negative level. After the negative level flows through the power supply terminal of the fourteenth inverter INV14, the fourteenth inverter INV14 outputs a negative level to the first low-pass transmission gate LP1, causing the signal to pass through the second low-pass transmission gate LP2 and the thirteenth inverter INV13 and output a third control signal at a negative level.

[0062] In the second state, the first control signal is at a high level and the second control signal is at a negative level. After the high level flows through the power supply terminal of the eleventh inverter INV11, the eleventh inverter INV11 outputs a high level to the first low-pass transmission gate LP1, causing the signal to pass through the first low-pass transmission gate LP1 and the twelfth inverter INV12 and output a fourth control signal at a negative level. After the negative level flows through the power supply terminal of the fourteenth inverter INV14, the fourteenth inverter INV14 outputs a negative level to the first low-pass transmission gate LP1, causing the signal to pass through the second low-pass transmission gate LP2 and the thirteenth inverter INV13 and output a third control signal at a low level.

[0063] In an alternative embodiment, referring to Figure 2 As shown in Figure 1-(a), each inverter includes a third PMOS transistor MP3 and a seventh NMOS transistor MN7. The gate of the third PMOS transistor MP3 is connected to the gate of the seventh NMOS transistor MN7, forming the input terminal of the inverter. The source of the third PMOS transistor MP3 forms the power supply terminal of the inverter. The drain of the third PMOS transistor MP3 is connected to the drain of the seventh NMOS transistor MN7, forming the output terminal of the inverter. The source of the seventh NMOS transistor MN7 forms the ground terminal of the inverter. The corresponding input-output logic reference Figure 2 -(b) shows.

[0064] In an alternative embodiment, referring to Figure 3 -(a), each low-pass transmission gate includes a fifth NMOS tube and a sixth NMOS tube, that is, the first low-pass transmission gate and the second low-pass transmission gate each include a fifth NMOS tube and a sixth NMOS tube, the drain of the fifth NMOS tube is connected to the gate of the sixth NMOS tube, and the connection node is the positive input terminal of the first low-pass transmission gate / the positive input terminal of the second low-pass transmission gate, the gate of the fifth NMOS tube is connected to the drain of the sixth NMOS tube, and the connection node is the reverse input terminal of the first low-pass transmission gate / the reverse input terminal of the second low-pass transmission gate, the source of the fifth NMOS tube is connected to the source of the sixth NMOS tube, and the connection node is the output terminal of the first low-pass transmission gate / the output terminal of the second low-pass transmission gate. The corresponding input-output logic reference Figure 3 -(b) shows.

[0065] Optionally, the first switch 40 is an NMOS transistor MN1 , and the second switch 50 is an NMOS transistor MN2 .

[0066] Optionally, the third switch 60 is a PMOS transistor MP1 , and the fourth switch 70 is a PMOS transistor MP2 .

[0067] Optionally, the positive voltage power input unit includes an eighth inverter INV8 and a positive voltage power terminal CLK, the positive voltage power terminal CLK obtains a first logic signal, the positive voltage power terminal CLK is connected to the input terminal of the eighth inverter INV8, and the output terminal of the eighth inverter INV8 outputs a first control signal.

[0068] When the first logic signal is at a high level, the first control signal is at a low level. When the first logic signal is at a low level, the first control signal is at a negative level.

[0069] Optionally, the negative voltage power input unit includes a ninth inverter INV9 and a negative voltage power terminal CLKN, the negative voltage power terminal CLKN obtains a second logic signal, the negative voltage power terminal CLKN is connected to the input terminal of the ninth inverter INV9, and the output terminal of the ninth inverter INV9 outputs a second control signal.

[0070] When the second logic signal is at a high level, the second control signal is at a low level. When the second logic signal is at a low level, the second control signal is at a high level.

[0071] Optionally, the first output unit includes a seventh inverter INV7 and a first output terminal OUT, the input terminal of the seventh inverter INV7 is grounded, the power supply terminal of the seventh inverter INV7 is connected to the positive inverter ring 10, the ground terminal of the seventh inverter INV7 is connected to the negative inverter ring 30, and the output terminal of the seventh inverter INV7 is connected to the first output terminal OUT and is used to output the first conversion signal.

[0072] Optionally, the negative voltage power input unit includes a tenth inverter INV10 and a second output terminal OUTN, the input terminal of the tenth inverter INV10 is grounded, the power terminal of the tenth inverter INV10 is connected to the positive power inverter ring 10, the ground terminal of the seventh inverter INV7 is connected to the negative power inverter ring 30, and the output terminal of the tenth inverter INV10 is connected to the second output terminal OUTN and is used to output a second conversion signal.

[0073] Optionally, the high level is 1, the low level is 0, and the negative level is -1.

[0074] The following combination Figure 1-Figure 5 The principle of this application is explained:

[0075] When the positive power supply terminal CLK and the negative power supply terminal CLKN of the positive-negative level conversion circuit are both powered on, that is, the positive power supply terminal CLK is connected to the positive voltage VDD, and the negative power supply terminal CLKN is connected to the negative voltage NVDD, the positive-negative level conversion circuit enters a normal working state. If a high level is input to the positive signal input terminal of the positive-negative level conversion circuit, the high level passes through the eighth inverter INV8, the power supply terminal of the fifth inverter INV5 is low, the negative signal input terminal is low, the power supply terminal of the second inverter INV2 is high, and the input terminal of the fourteenth inverter INV14 is connected to the GND of the positive-negative level conversion circuit. The output is a high level, and after passing through the second low-pass transmission gate LP2, the input of the thirteenth inverter INV13 is a low level. After passing through the thirteenth inverter INV13, the ground terminal of the eleventh inverter INV11 is a negative level NVDD. At this time, the power supply terminal of the eleventh inverter INV11 is a low level GND, the input terminal of the eleventh inverter INV11 is connected to the GND of the positive-negative level conversion circuit, and the output is a negative level NVDD. After passing through the first low-pass transmission gate LP1, the input of the twelfth inverter INV12 is a negative level NVDD. After passing through the twelfth inverter INV12, the ground terminal of the fourteenth inverter INV14 is a low level.

[0076] At this time, the ground terminals of the sixteenth inverter INV16 and the nineteenth inverter INV19 are the negative level NVDD and the low level GND, respectively. The output terminal of the nineteenth inverter INV19 is at a low level. After passing through the twentieth inverter INV20, the input terminal of the fifteenth inverter INV15 is at a negative level NVDD. After passing through the fifteenth inverter INV15, the input terminal of the sixteenth inverter INV16 is at a low level. After passing through the sixteenth inverter INV16, the input terminal of the seventeenth inverter INV17 is at a negative level NVDD. After passing through the seventeenth inverter INV17, the input terminal of the eighteenth inverter INV18 is at a low level. After passing through the eighteenth inverter INV18, the input terminal of the nineteenth inverter INV19 is at a negative level NVDD.

[0077] At this time, the power supply terminals of the fifth inverter INV5 and the second inverter INV2 are low level GND and high level VDD respectively, the output terminal of the fifth inverter INV5 is low level, the input terminal of the third inverter INV3 is high level after passing through the fourth inverter INV4, the input terminal of the second inverter INV2 is low level after passing through the third inverter INV3, the input terminal of the first inverter INV1 is high level after passing through the second inverter INV2, the input terminal of the sixth inverter INV6 is low level after passing through the first inverter INV1, and the input terminal of the fifth inverter INV5 is high level after passing through the sixth inverter INV6.

[0078] At this time, the power supply terminal and ground terminal of the seventh inverter INV7 are high level VDD and low level GND respectively, the input terminal is connected to the GND of the positive and negative level conversion circuit, and the output terminal is connected to the positive signal output terminal of the positive and negative level conversion circuit, and the positive signal output terminal is high level VDD.

[0079] At this time, the power supply terminal and ground terminal of the tenth inverter INV10 are low level GND and negative level NVDD respectively, the input terminal is connected to the GND of the positive-negative level conversion circuit, and the output terminal is connected to the positive signal output terminal of the positive-negative level conversion circuit, and the positive signal output terminal is negative level NVDD.

[0080] The advantage of this patent is that it reduces the risk of MOS overvoltage and suppresses the DC path, greatly improving the reliability and switching response speed of the circuit. In the positive and negative level paths, the NMOS tube of the sixth inverter INV6, the PMOS tube of the seventh inverter INV7 and the fifteenth inverter INV15 coexist, and the four-stage MOS tube does not have the risk of voltage breakdown under the voltage difference of 2VDD. The same is true for the branch where the tenth inverter INV10 is located.

[0081] The advantages of this patent are enhanced signal anti-interference capability and accelerated switching speed. The eleventh inverter INV11, the first low-pass transmission gate LP1, the twelfth inverter INV12, the fourteenth inverter INV14, the second low-pass transmission gate LP2 and the thirteenth inverter INV13 form a complementary logic circuit, which greatly improves the switching speed of the positive inverter ring composed of the first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, and the sixth inverter INV6 and the negative inverter ring 30 composed of the fifteenth inverter INV15, the sixteenth inverter INV16, the seventeenth inverter INV17, the eighteenth inverter INV18, the nineteenth inverter INV19, and the twentieth inverter INV20. The complementary logic circuit 20 has stronger anti-interference ability and can increase the switching speed.

[0082] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the present invention may be practiced without these specific details. Similarly, in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of embodiments of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. The claims that follow the detailed description are hereby expressly incorporated into that detailed description, with each claim itself serving as a separate embodiment of the present invention.

[0083] Those skilled in the art will appreciate that the modules in the devices of the embodiments can be adaptively changed and installed in one or more devices different from the embodiments. The modules, units, or components in the embodiments can be combined into one module, unit, or component, and furthermore, they can be divided into multiple submodules, subunits, or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive.

[0084] It should be noted that the above embodiments illustrate rather than limit the invention, and that alternative embodiments may be devised by a person skilled in the art without departing from the scope of the appended claims. In the claims, any reference signs placed between brackets should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising several different elements and by means of appropriately programmed computers. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names. The steps in the above embodiments should not be understood as limiting the order of execution unless otherwise specified.

Claims

1. A positive-negative level conversion circuit, characterized in that: include: a positive voltage power supply input unit, configured to receive a first logic signal and output a corresponding first control signal according to the first logic signal; a negative voltage power supply input unit, configured to receive a second logic signal and output a corresponding second control signal according to the second logic signal; a positive inverter ring, connected to the positive power input unit and the negative power input unit, respectively, and configured to calculate, through an internal logic circuit of the positive inverter ring, a first switch control signal, a second switch control signal, a first output signal, and a second output signal corresponding to the first control signal and the second control signal, and output them; a complementary logic circuit, connected to the positive inverter ring, the positive voltage power input unit, and the negative voltage power input unit, respectively, and outputting a corresponding third control signal and a fourth control signal according to the first control signal and the second control signal; a negative power inverter ring, connected to the complementary logic circuit, and configured to calculate, through an internal logic circuit of the negative power inverter ring, a third switch control signal, a fourth switch control signal, a third output signal, and a fourth output signal corresponding to the third control signal and the fourth control signal, and output them; a first switch, connected to the positive voltage power input unit, the positive inverter ring, and the complementary logic circuit, respectively, and turned on or off according to the first switch control signal; a second switch, connected to the positive voltage power input unit, the positive power inverter ring, and the complementary logic circuit, respectively, and turned on or off according to the second switch control signal; a third switch, connected to the negative inverter ring and the complementary logic circuit respectively, and turned on or off according to the third switch control signal; a fourth switch, connected to the negative inverter ring and the complementary logic circuit respectively, and turned on or off according to the fourth switch control signal; a first output unit connected to the positive inverter ring and the negative inverter ring respectively, and outputting a corresponding first conversion signal according to the first output signal and the third output signal; and The second output unit is connected to the positive inverter ring and the negative inverter ring respectively, and outputs a corresponding second conversion signal according to the second output signal and the fourth output signal.

2. The positive-negative level conversion circuit according to claim 1, wherein: The positive inverter ring includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, and a sixth inverter, wherein the power supply terminal of the first inverter, the power supply terminal of the third inverter, the power supply terminal of the fourth inverter, and the power supply terminal of the sixth inverter are all connected to a forward voltage, the power supply terminal of the second inverter is connected to the second control signal, and the power supply terminal of the fifth inverter is connected to the first control signal; The ground terminal of the first inverter, the ground terminal of the second inverter, the ground terminal of the third inverter, the ground terminal of the fourth inverter, the ground terminal of the fifth inverter, and the ground terminal of the sixth inverter are all grounded; the output terminal of the fifth inverter is connected to the input terminal of the fourth inverter, and receives the first control signal when the first switch is turned on; the output terminal of the fourth inverter is connected to the input terminal of the third inverter, and outputs the second switch control signal; The output end of the third inverter is connected to the input end of the second inverter and outputs the second output signal; the output end of the second inverter is connected to the input end of the first inverter and receives the second control signal when the second switch is turned on; the output end of the first inverter is connected to the input end of the sixth inverter and outputs the first switch control signal; the output end of the sixth inverter is connected to the input end of the fifth inverter and outputs the first output signal.

3. The positive-negative level conversion circuit according to claim 1, wherein: The negative-charge inverter ring includes a fifteenth inverter, a sixteenth inverter, a seventeenth inverter, an eighteenth inverter, a nineteenth inverter, and a twentieth inverter. The power supply terminal of the fifteenth inverter, the power supply terminal of the seventeenth inverter, the power supply terminal of the eighteenth inverter, and the power supply terminal of the twentieth inverter are all connected to a negative voltage. The power supply terminal of the sixteenth inverter is connected to the third control signal, and the power supply terminal of the nineteenth inverter is connected to the fourth control signal. The ground terminal of the fifteenth inverter, the ground terminal of the sixteenth inverter, the ground terminal of the seventeenth inverter, the ground terminal of the eighteenth inverter, the ground terminal of the nineteenth inverter, and the ground terminal of the twentieth inverter are all grounded. The output terminal of the sixteenth inverter is connected to the input terminal of the seventeenth inverter and is connected to the third control signal when the third switch is turned on. The output terminal of the seventeenth inverter is connected to the input terminal of the eighteenth inverter and outputs the fourth switch control signal. The output end of the eighteenth inverter is connected to the input end of the nineteenth inverter and outputs the fourth output signal; the output end of the nineteenth inverter is connected to the input end of the twentieth inverter and receives the fourth control signal when the fourth switch is turned on; the output end of the 20th inverter is connected to the input end of the fifteenth inverter and outputs the third switch control signal; the output end of the fifteenth inverter is connected to the input end of the sixteenth inverter and outputs the third output signal.

4. The positive-negative level conversion circuit according to claim 1, wherein: The complementary logic circuit includes a first resistor, a second resistor, a third capacitor, a fourth capacitor, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, a first low-pass transmission gate, and a second low-pass transmission gate. The power supply terminal of the eleventh inverter is connected to the first terminal of the third capacitor and is used to receive the first control signal. The ground terminal of the eleventh inverter is respectively connected to the second terminal of the third capacitor and the output terminal of the thirteenth inverter, and outputs the third control signal. The input terminal of the eleventh inverter is grounded, and the output terminal of the eleventh inverter is connected to the positive input terminal of the first low-pass transmission gate. The inverting input terminal of the first low-pass transmission gate is grounded, the output terminal of the first low-pass transmission gate is connected to the input terminal of the twelfth inverter, the output terminal of the twelfth inverter is respectively connected to the power supply terminal of the fourteenth inverter and the first terminal of the fourth capacitor tube, and outputs the fourth control signal; the input terminal of the thirteenth inverter is connected to the output terminal of the second low-pass transmission gate; the inverting input terminal of the second low-pass transmission gate is grounded, the positive input terminal of the second low-pass transmission gate is connected to the output terminal of the fourteenth inverter; the input terminal of the fourteenth inverter is grounded, the ground terminal of the fourteenth inverter is connected to the second terminal of the fourth capacitor tube, and is used to obtain the second control signal.

5. The positive-negative level conversion circuit according to any one of claims 2 to 4, characterized in that: Each inverter includes a third PMOS transistor and a seventh NMOS transistor. The gate of the third PMOS transistor is connected to the gate of the seventh NMOS transistor, forming the input terminal of the inverter. The source of the third PMOS transistor forms the power supply terminal of the inverter. The drain of the third PMOS transistor is connected to the drain of the seventh NMOS transistor, forming the output terminal of the inverter. The source of the seventh NMOS transistor forms the ground terminal of the inverter.

6. The positive-negative level conversion circuit according to claim 4, wherein: The first low-pass transmission gate and the second low-pass transmission gate each separately include a fifth NMOS transistor and a sixth NMOS transistor. The drain of the fifth NMOS transistor is connected to the gate of the sixth NMOS transistor, and the connection node thereof is the positive input terminal of the first low-pass transmission gate / the positive input terminal of the second low-pass transmission gate. The gate of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, and the connection node thereof is the reverse input terminal of the first low-pass transmission gate / the reverse input terminal of the second low-pass transmission gate. The source of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor, and the connection node thereof is the output terminal of the first low-pass transmission gate / the output terminal of the second low-pass transmission gate.

7. The positive-to-negative level conversion circuit according to claim 1, wherein: The first switch and the second switch are NMOS transistors.

8. The positive-to-negative level conversion circuit according to claim 1, wherein: The third switch and the fourth switch are PMOS tubes.

9. The positive-negative level conversion circuit according to claim 1, wherein: The positive voltage power input unit includes an eighth inverter and a positive voltage power supply terminal, the positive voltage power supply terminal obtains the first logic signal, the positive voltage power supply terminal is connected to the input terminal of the eighth inverter, and the output terminal of the eighth inverter outputs the first control signal; The negative voltage power input unit includes a ninth inverter and a negative voltage power supply terminal. The negative voltage power supply terminal obtains the second logic signal. The negative voltage power supply terminal is connected to the input terminal of the ninth inverter. The output terminal of the ninth inverter outputs the second control signal.

10. The positive-to-negative level conversion circuit according to claim 1, wherein: The first output unit includes a seventh inverter and a first output terminal, the input terminal of the seventh inverter is grounded, the power terminal of the seventh inverter is connected to the positive inverter ring, the ground terminal of the seventh inverter is connected to the negative inverter ring, and the output terminal of the seventh inverter is connected to the first output terminal and is used to output the first conversion signal; The negative voltage power input unit includes a tenth inverter and a second output end, the input end of the tenth inverter is grounded, the power end of the tenth inverter is connected to the positive power inverter ring, the ground end of the seventh inverter is connected to the negative power inverter ring, and the output end of the tenth inverter is connected to the second output end and is used to output the second conversion signal.

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