A simulation system for battery micro-short circuit

Abstract

The present invention discloses a simulation system for battery micro-short circuit, comprising: a master control module, which is connected in parallel across the instrument under test; a frequency selection module, which is connected to the master control module; a micro-short circuit degree selection module, which is connected to the frequency selection module through a first inverter; wherein, the frequency selection module includes a first capacitor combination, the first capacitor combination includes a plurality of capacitors with different capacitance values, and the occurrence frequency of the micro-short circuit decreases as the capacitance value of the capacitor increases; the micro-short circuit degree selection module includes a second capacitor combination, a delay circuit and a discharge circuit; the second capacitor combination is connected to the discharge circuit through a selection switch; the second capacitor combination includes a plurality of capacitors with different capacitance values; the occurrence degree of the micro-short circuit increases as the capacitance value of the capacitor increases. The simulation system for micro-short circuit provided by the present invention can accurately control the interval of the first simulated micro-short circuit occurrence; at the same time, it can simulate the occurrence times and severity of the micro-short circuit for easy adjustment.

Description

Technical Field

[0001] The present invention relates to the technical field of batteries, and in particular to a battery micro-short circuit simulation system. Background Art

[0002] Battery micro-short circuit refers to some tiny defects such as dust and scratches mixed inside the battery, especially between the positive and negative poles of a single battery cell. These tiny defects will form a tiny conductive path inside the battery, but unlike a complete short circuit, a battery with a micro-short circuit can still be used normally for a short period of time, but compared with a normal battery, the performance of a battery with a micro-short circuit will decline rapidly.

[0003] At present, the calibration device of the traditional battery micro short circuit detector mainly relies on Figure 1 The circuit system shown in the figure, where Cx is the simulated test product; Cm is a capacitor combination; Rm is a discharge resistor; S is a switch device; HV is a high-voltage circuit. When high voltage is applied to both ends of Cx, S is closed for a short time and then disconnected, and Cm is suddenly connected to the high-voltage circuit from the zero state, thereby simulating the phenomenon of a battery micro-short circuit.

[0004] The battery charging process can be divided into a constant current stage (CC) and a constant voltage (CV) stage. The battery micro-short circuit detector should be able to distinguish the micro-short circuit occurrence interval, and the difference in equivalent capacitance between batteries will also cause the CC (CV) stage duration of different batteries to be different. In the traditional solution, there is no synchronization mechanism between the high-voltage circuit and the micro-short circuit simulation circuit, making it difficult to control the location of the first micro-short circuit and the frequency of micro-short circuits during the test, which is not conducive to calibrating the detection capability of the battery micro-short circuit tester as a standard signal source.

[0005] In summary, it is now necessary to design a battery micro-short circuit simulation system to solve the above-mentioned problems in the prior art. Summary of the invention

[0006] In order to solve the above-mentioned problems in the prior art, the present invention provides a battery micro-short circuit simulation system, which solves the problem that the existing micro-short circuit simulation circuit has no synchronization mechanism with the high-voltage circuit, and cannot control the location of the first micro-short circuit and the frequency and degree of micro-short circuit during the test.

[0007] In order to achieve the above object, the present invention adopts the following technical scheme:

[0008] A battery micro-short circuit simulation system, comprising:

[0009] A master control module, which is connected in parallel at both ends of the instrument under test;

[0010] A frequency selection module connected to the master control module;

[0011] A micro-short circuit degree selection module, which is connected to the frequency selection module through a first inverter;

[0012] Wherein, the frequency selection module includes a first capacitor combination, the first capacitor combination includes a plurality of capacitors with different capacitance values, and the frequency of occurrence of micro short circuits decreases as the capacitance values ​​of the capacitors increase;

[0013] The micro-short circuit degree selection module includes a second capacitor combination, a delay circuit and a discharge circuit; the second capacitor combination is connected to the discharge circuit through a selection switch; the second capacitor combination includes multiple capacitors with different capacitance values; the degree of micro-short circuit occurrence increases with the increase of the capacitance value of the capacitor.

[0014] In some embodiments of the present invention, the delay circuit is connected to the discharge circuit through a transistor; when the second capacitor is disconnected from the high voltage, the discharge circuit is started; the micro-short circuit degree selection module also includes a relay, and when the relay is in the on state, the transistor is in the off state.

[0015] In some embodiments of the present invention, one end of the coil of the relay is connected to the output end of the first inverter, and the other end of the coil is connected to the emitter of the first PNP transistor.

[0016] In some embodiments of the present invention, the delay circuit includes a second inverter, the output end of the second inverter is connected to the second capacitor through a resistor and a diode; the second capacitor is connected to the cathode of the diode; the anode of the diode is connected to the output end of the second inverter, and the output end of the second inverter is connected to the base of the first PNP transistor and the gate of the transistor through different diodes respectively.

[0017] In some embodiments of the present invention, the base of the first PNP transistor is also connected to the second capacitor and then grounded; the base of the first PNP transistor is also connected to the emitter of the second PNP transistor through a resistor; the base of the second PNP transistor is connected to the output end of the second inverter; and the collector of the second PNP transistor is grounded.

[0018] In some embodiments of the present invention, in the reset state, the output end of the first inverter outputs a low level, the output end of the second inverter outputs a high level, the voltage at the first capacitor end is 0V, the second capacitor is in a full state, the first PNP transistor and the second PNP transistor are in a cut-off state, and the transistor is in a conducting state.

[0019] In some embodiments of the present invention, the output end of the first inverter is connected to the first capacitor via a resistor and a diode; when the system is started, the output end of the first inverter outputs a high level, the first capacitor starts to charge, and when charged to the flip threshold voltage of the second inverter, the second inverter outputs a low level.

[0020] In some embodiments of the present invention, when the second inverter outputs a low level, the second PNP transistor is turned on, the transistor is turned off, and the second capacitor begins to discharge along the path of the second PNP transistor. When the collector output current of the first PNP transistor reaches the action threshold of the relay control coil, the relay is turned on and the second capacitor combination is connected to the high voltage for charging.

[0021] In some embodiments of the present invention, when the output of the first inverter flips to a low level, the relay control coil loses power, the second capacitor combination is disconnected from the high voltage, and the first capacitor starts to discharge along the resistor.

[0022] In some embodiments of the present invention, when the voltage of the first capacitor drops to the flip threshold voltage of the second inverter, the second inverter outputs a high level, the second PNP transistor is turned off, the transistor is turned on, and the second capacitor combination begins to discharge; at the same time, the second capacitor begins to charge, and then the first PNP transistor is turned off; when the second capacitor C2 is fully charged, the circuit returns to a reset state.

[0023] The technical solution of the present invention has the following technical effects compared with the prior art:

[0024] The micro-short circuit simulation system provided by the present invention can accurately control the interval of the first simulated micro-short circuit occurrence; at the same time, it can simulate the number of micro-short circuit occurrences and the severity for easy adjustment. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0026] Figure 1 This is a schematic diagram of a battery micro-short circuit simulation circuit in the prior art.

[0027] Figure 2 Schematic diagram of the simulation system of battery micro-short circuit in the embodiment.

[0028] Figure 3 Schematic diagram of voltages at some nodes in the master control module and the frequency selection module in the embodiment.

[0029] Figure 4 Schematic diagram of voltages at some nodes in the micro-short circuit degree selection module described in the embodiment. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0032] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0033] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0034] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0035] The disclosure below provides many different embodiments or examples to implement different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0036] Reference Figure 2 As shown, a battery micro-short circuit simulation system includes:

[0037] A master control module, which is connected in parallel at both ends of the instrument under test;

[0038] A frequency selection module, which is connected to the master control module via a first selection switch S1;

[0039] A micro-short circuit degree selection module, which is connected to the frequency selection module via a first inverter NG50;

[0040] Wherein, the frequency selection module includes a first capacitor combination CM1, the first capacitor combination CM1 includes a plurality of capacitors with different capacitance values, each capacitor corresponding to a micro-short circuit occurrence frequency;

[0041] The micro-short circuit degree selection module includes a second capacitor combination CM2, a delay circuit and a discharge circuit; the second capacitor combination is connected to the discharge circuit through a selection switch; the second capacitor combination CM2 includes a plurality of capacitors with different capacitance values; each capacitor corresponds to a micro-short circuit occurrence degree;

[0042] The delay circuit is connected to the discharge circuit via transistor V2.

[0043] In some embodiments of the present invention, the master control module includes a voltage divider circuit and an enable switch circuit, wherein the voltage divider circuit is connected to the non-inverting input terminal of the operational amplifier U1; the enable switch circuit is connected to the inverting input terminal of the operational amplifier U1; and the output terminal of the operational amplifier U1 is connected to the selectable terminal of the first selection switch S1.

[0044] In some embodiments of the present invention, the enabling switch circuit includes a second selection switch S2 and multiple resistors; the fixed end of the second selection switch S2 is connected to the power supply through a resistor; the selectable end of the second selection switch S2 is connected to a resistor combination; wherein each resistor in the resistor combination corresponds to the time when the micro-short circuit phenomenon first occurs.

[0045] Specifically, continue to refer to Figure 1 As shown,

[0046] Resistors R10, R11 and R12 are connected in series and in parallel with Cx to form a high voltage voltage division branch, and the voltage across resistor R12 is the voltage after voltage division. One end of resistor R12 connected to resistor R11 is connected to the non-inverting input end of operational amplifier U1; one end of resistor R20 is connected to VCC, and the other end is connected to the fixed end of S2 and the inverting input end of operational amplifier U1 respectively; the selectable end of S2 is connected to resistor R21 and resistor R22 respectively, and the other ends of resistor R21 and resistor R22 are grounded; the output end of operational amplifier U1 is connected to the selectable end of the first selection switch S1, the other selectable end of the first selection switch S1 is grounded, and the fixed end of the first selection switch S1 is connected to the input ends of AN50 and AN53.

[0047] In some embodiments of the present invention, the frequency selection module includes a third selection switch S3 connected to the first capacitor combination CM1, and the third selection switch S3 is connected to the power supply through the charging and discharging circuit; the frequency selection module also includes a transistor N1, and the base of the transistor N1 is connected to the output end of the first inverter NG50;

[0048] When the voltage of the first capacitor combination CM1 is greater than 2 / 3 Vcc, the transistor N1 is turned on, and the first inverter NG50 outputs a low level.

[0049] In some embodiments of the present invention, in the frequency selection module, the input end of the first inverter NG50 is also connected to the trigger and the first selectable switch S1 through a NAND gate; when the first selector switch S1 is connected to the ground end, the NAND gate outputs a high level and the first inverter NG50 outputs a low level.

[0050] Specifically, one end of the resistor R23 is connected to VCC and the resistor R50, and the other end is respectively connected to the resistor R24, the anode of the diode D1 and the collector of the transistor N1; the other end of the resistor R24 ​​is connected to the cathode of the diode D2; the cathode of the diode D1 is connected to the anode of the diode D2, the inverting input terminal of the operational amplifier U50, the non-inverting input terminal of the operational amplifier U51, and the fixed end of the third selection switch S3; the selectable end of the third selection switch S3 is connected to the first capacitor combination CM1, and the other end of the first capacitor combination CM1 is grounded; the other end of the resistor R50 is connected to the resistor R51 and the non-inverting input terminal of the operational amplifier U50; the other end of the resistor R51 is connected to the resistor R52 and the non-inverting input terminal of the operational amplifier U51; the other end of the resistor R52 is connected to the emitter of N1 and grounded.

[0051] The NAND gate AN50 and the NAND gate AN51 form an RS trigger, the output end of the operational amplifier U50 is connected to the input end of the AN NAND gate 50, the output end of the operational amplifier U51 is connected to the input end of the NAND gate AN51, the output end of the resistor RS trigger is connected to the other input end of the NAND gate AN53, the output end of the NAND gate AN53 is connected to the input end of the first inverter NG50 and the resistor R53; the other end of the resistor R53 is connected to the base of N3.

[0052] In some embodiments of the present invention, reference Figure 3 As shown, after passing through the first inverter NG50, the square wave output can be realized during the battery charging process.

[0053] In some embodiments of the present invention, the micro-short circuit degree selection module also includes a relay, one end of the coil of the relay is connected to the output end of the first inverter, and the other end is connected to the emitter of the first PNP transistor; one end of the mechanical switch of the relay is connected to the high voltage side, and the other end is connected to the discharge circuit and the selection end of the fourth selection switch.

[0054] In some embodiments of the present invention, in the discharge circuit, a discharge resistor is connected to a source of a transistor; and a gate and a drain of the transistor are connected in parallel to the resistor.

[0055] Specifically, the output end of the first inverter NG50 is connected to the control coil of the relay SW1 and the resistor R36, the other end of the resistor R36 is connected to the anode of the diode D3, the other end of the control coil of the relay SW1 is connected to the emitter of the first PNP transistor P3, the mechanical switch of the relay SW1 is in the disconnected state in the reset state, one end of the relay SW1 is connected to the high voltage side of the HV, and the other end is connected to the fixed ends of the resistors R32 and S4, the other end of the resistor R32 is connected to the source of V2, and the resistor R32 functionally serves as the discharge resistor of the second capacitor combination CM2 to ensure that the selected capacitor is in the zero state before the second capacitor combination CM2 is connected to the high voltage, the 3 end of S4 is connected to the second capacitor combination CM2, and the other end of the second capacitor combination CM2 is grounded.

[0056] Since the moment when the high voltage is connected to the second capacitor combination CM2 is equivalent to a short circuit, the current flowing through the relay SW1 is large, so it is preferred to use a mechanical switch to implement this function. Semiconductors with switching functions will limit the current flow, which is not conducive to simulating the phenomenon of micro-short circuit.

[0057] In some embodiments of the present invention, in the delay circuit, the output end of the second inverter NG1 is also connected to the second capacitor C2 through a resistor and a diode; the second capacitor C2 is connected to the cathode of the diode; the anode of the diode is connected to the output end of the second inverter NG1, and the output end of the second inverter NG1 is respectively connected to the base of the first PNP transistor and the gate of the transistor V2 through different diodes.

[0058] In some embodiments of the present invention, the base of the first PNP transistor is also connected to the second capacitor and then grounded; the base of the first PNP transistor is also connected to the emitter of the second PNP transistor through a resistor; the base of the second PNP transistor is connected to the output end of the second inverter NG1; and the collector of the second PNP transistor is grounded.

[0059] In some embodiments of the present invention, in the reset state, the output end of the first inverter NG50 outputs a low level, the output end of the second inverter NG1 outputs a high level, the voltage at the first capacitor C1 is 0V, the second capacitor C2 is in a full state, the first PNP transistor P3 and the second PNP transistor P4 are in a cut-off state, and the transistor V2 is in a conducting state.

[0060] Specifically, the cathode of the diode D3 is connected to the first capacitor C1, the resistor R31, and the input end of the second inverter NG1, the other ends of the first capacitor C1 and the resistor R31 are grounded, the output end of the second inverter NG1 is connected to the resistor R35, the anode of the diode D5, and the base of the second PNP transistor P4, the other end of the resistor R35 is connected to the anode of the diode D4, the cathode of the diode D4 is connected to the second capacitor C2, the resistor R34, and the base of the first PNP transistor P3, the other end of the second capacitor C2 is grounded, the other end of the resistor R34 is connected to the cathode of the diode D5, the emitter of the second PNP transistor P4, the resistor R33, and the gate of the transistor V2, the collector of the second PNP transistor P4, the drain of the transistor V2, and the other end of the resistor R33 are grounded.

[0061] Reference Figure 2 As shown, the function of the first selection switch S1 is a master control switch. When its selectable end is grounded, the NAND gate AN53 outputs a high level, the second inverter NG1 outputs a low level, the relay SW1 is in a reset state, the voltage of the capacitor terminal of the first capacitor combination CM1 connected to the circuit is 0, and the micro-capacitor of the second capacitor combination CM2 is in a zero state. After the fixed end of the first selection switch S1 is connected to the output end of the operational amplifier U1, when U HV × resistance R12 / (resistance R10+resistance R11+resistance R12)>VCC×resistance R21 / (resistance R21+resistance R22), the output voltage V of the first inverter NG501G High level, the 2nd and 3rd terminals of the S diode D are turned on. Conventionally, the resistance values ​​of the resistors R50, R51 and R52 are equal. When the voltage at the capacitor terminal of the first capacitor combination CM1 connected to the circuit rises to more than 2 / 3Vcc, N1 is turned on, the first inverter NG50 outputs a low level, the second capacitor combination CM2 and the resistor R3 form a loop, and the capacitor connected to the circuit of the second capacitor combination CM2 is discharged to 0V. When the voltage of the first capacitor combination CM1 drops to less than 1 / 3VCC, N1 is turned off, and the above process is repeated.

[0062] The capacitance value of the circuit connected in the first capacitor combination CM1 determines the switching frequency of the relay SW1 and the transistor V2. This frequency determines the frequency of the simulated micro-short circuit during the period when the high voltage is applied to both ends of Cx. The larger the capacitance value, the lower the frequency of the simulated micro-short circuit. The resistor connected to the selectable end of the second selection switch S2 determines the time point when the first simulated micro-short circuit occurs. The capacitance value of the circuit connected in the second capacitor combination CM2 determines the severity of the simulated micro-short circuit. The larger the capacitance value, the greater the severity of the simulated micro-short circuit.

[0063] In order to ensure the consistency of the severity of the micro-short circuit, it is necessary to ensure that the duration of each time the micro-capacitor of the second capacitor combination CM2 is connected to high voltage is strictly equal, and the amount of charge charged into the selected capacitor of the second capacitor combination CM2 after connecting to high voltage is equal. Therefore, it is necessary to ensure that during its discharge period, its terminal voltage will drop to 0, and its discharge resistor R32 should preferably be a low-resistance and high-power resistor.

[0064] The timing of charging and discharging of the second capacitor combination CM2 needs to be strictly controlled. The principle is to ensure that the transistor V2 can be turned on for discharge only after the second capacitor combination CM2 is disconnected from the high voltage, and to ensure that the relay SW1 can be turned on only after the transistor V2 is turned off. The above is to ensure that the resistor R32 and the transistor V2 will not flow a large current for a long time. Since the mechanical relay has an uncontrollable mechanical action delay, in order to ensure that there is a certain dead time in the action between the charging control switch and the discharging control switch of the second capacitor combination CM2, the transistor V2 should preferably be a fast-acting electronic switch.

[0065] Reference Figure 4As shown, in order to realize the above functions, a special transistor V2 and relay SW1 driving circuit need to be set. In the reset state, the first inverter NG50 outputs a low level, the second inverter NG1 outputs a high level, the voltage at the first capacitor C1 is 0, the second capacitor C2 is in a full state, the first PNP transistor P3 and the second PNP transistor P4 are turned off, and the transistor V2 is turned on. At k0, the first inverter NG50 outputs a high level, the first capacitor C1 starts to charge, and when it is charged to the flip threshold voltage of the second inverter NG1, that is, at k1, the second inverter NG1 outputs a low level, the second PNP transistor P4 is turned on, the transistor V2 is turned off, and the second capacitor C2 starts to discharge along the path of the resistor R34 and the second PNP transistor P4, and the voltage of the second capacitor C2 drops. At k2, the collector output current of the first PNP transistor P3 reaches the action threshold of the relay SW1 control coil, the relay SW1 is turned on, and the second capacitor combination CM2 is connected to the high voltage; k3 At k4, the output of the first inverter NG50 flips to a low level, the relay SW1 control coil loses power, and the second capacitor combination CM2 is disconnected from the high voltage; the first capacitor C1 starts to discharge along the resistor R31, and at k4, the voltage of the first capacitor C1 drops to the flip threshold voltage of the second inverter NG1, the second inverter NG1 outputs a high level, the second PNP transistor P4 is turned off, the transistor V2 is turned on, and the second capacitor combination CM2 starts to discharge; at the same time, the second capacitor C2 starts to charge, and after a period of time, the first PNP transistor P3 is turned off. After the second capacitor C2 is fully charged, the entire circuit returns to a reset state.

[0066] The technical solution of the present invention has the following technical effects compared with the prior art:

[0067] The micro-short circuit simulation system provided by the present invention can accurately control the interval of the first simulated micro-short circuit; at the same time, it can simulate the number of micro-short circuit occurrences and the severity for easy adjustment.

[0068] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0069] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A battery micro-short circuit simulation system, characterized in that: include: A master control module, which is connected in parallel at both ends of the instrument under test; A frequency selection module connected to the master control module; A micro-short circuit degree selection module, which is connected to the frequency selection module through a first inverter; Wherein, the frequency selection module includes a first capacitor combination, the first capacitor combination includes a plurality of capacitors with different capacitance values, and the frequency of occurrence of micro short circuits decreases as the capacitance values ​​of the capacitors increase; The micro-short circuit degree selection module includes a second capacitor combination, a delay circuit and a discharge circuit; the second capacitor combination is connected to the discharge circuit through a selection switch; the second capacitor combination includes a plurality of capacitors with different capacitance values; the occurrence degree of the micro-short circuit increases with the increase of the capacitance value of the capacitor; The delay circuit is connected to the discharge circuit through a transistor; when the second capacitor combination is disconnected from the high voltage, the discharge circuit is started; the micro-short circuit degree selection module also includes a relay, and when the relay is in the on state, the transistor is in the off state; One end of the coil of the relay is connected to the output end of the first inverter, and the other end of the coil is connected to the emitter of the first PNP transistor.

2. A battery micro-short circuit simulation system according to claim 1, characterized in that: The delay circuit includes a second inverter, the output end of the second inverter is connected to the second capacitor through a resistor and a diode D4; the second capacitor is connected to the cathode of the diode D4; the anode of the diode D4 is connected to the output end of the second inverter, and the output end of the second inverter is connected to the base of the first PNP transistor and the gate of the transistor through the diode D4 and the diode D5 respectively; The output terminal of the first inverter is connected to the first capacitor via a resistor and a diode D3.

3. A battery micro-short circuit simulation system according to claim 2, characterized in that: The base of the first PNP transistor is also connected to the second capacitor and then grounded; the base of the first PNP transistor is also connected to the emitter of the second PNP transistor through a resistor; the base of the second PNP transistor is connected to the output end of the second inverter; and the collector of the second PNP transistor is grounded.

4. A battery micro-short circuit simulation system according to claim 3, characterized in that: In the reset state, the output end of the first inverter outputs a low level, the output end of the second inverter outputs a high level, the voltage of the first capacitor is 0V, the second capacitor is in a full state, the first PNP transistor and the second PNP transistor are in a cut-off state, and the transistor is in a conducting state.

5. A battery micro-short circuit simulation system according to claim 2, characterized in that: When the system is started, the output terminal of the first inverter outputs a high level, and the first capacitor starts to charge. When the capacitor is charged to the flip threshold voltage of the second inverter, the second inverter outputs a low level.

6. A battery micro-short circuit simulation system according to claim 3, characterized in that: When the second inverter outputs a low level, the second PNP transistor is turned on, the transistor is turned off, and the second capacitor begins to discharge along the path of the second PNP transistor. When the collector output current of the first PNP transistor reaches the action threshold of the relay control coil, the relay is turned on, and the second capacitor combination is connected to the high voltage for charging.

7. A battery micro-short circuit simulation system according to claim 2, characterized in that: When the output of the first inverter flips to a low level, the relay control coil loses power, the second capacitor combination is disconnected from the high voltage, and the first capacitor begins to discharge along the resistor.

8. A battery micro-short circuit simulation system according to claim 3, characterized in that: When the voltage of the first capacitor drops to the flip threshold voltage of the second inverter, the second inverter outputs a high level, the second PNP transistor is turned off, the transistor is turned on, and the second capacitor combination starts to discharge; at the same time, the second capacitor starts to charge, and then the first PNP transistor is turned off; when the second capacitor is fully charged, the circuit returns to the reset state.

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