Data access method and system on chip

Abstract

A data access method and a system on chip. The method is applied to a system on chip, the system on chip comprising a processor and a shared cache, the shared cache comprising a first MRAM and a second MRAM, the data retention of the first MRAM being higher than that of the second MRAM, the data writing speed of the first MRAM being lower than that of the second MRAM, the processor and the shared cache communicating through an on-chip network. The method comprises: for an access request from a first processor, sending it to a first MRAM process, and for an access request from a second processor, sending it to a second MRAM process.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a data access method and a system-on-a-chip. Background Technology

[0002] A system-on-a-chip (SoC) includes the processor cores and their caches. These caches include independent Level 1 and Level 2 caches used by each core, and may also include a shared Level 3 cache. All three caches—Level 1, Level 2, and Level 3—use static random access memory (SRAM).

[0003] As transistor technology continues to shrink under Moore's Law, the proportion of SRAM cache within SoCs and its energy consumption are gradually becoming significant bottlenecks limiting computing performance and power consumption. Summary of the Invention

[0004] This application provides a data memory access method and a system-on-a-chip (SoC) to reduce cache power consumption and improve data memory access performance.

[0005] In a first aspect, a data access method is provided, which can be applied to a system-on-a-chip (SoC). The SoC includes a processor and a shared cache. The shared cache includes a first magnetic random access memory (MRAM) and a second MRAM. The data retention capability of the first MRAM is higher than that of the second MRAM, and the data write speed of the first MRAM is lower than that of the second MRAM. The processor and the shared cache communicate with each other through an on-chip network.

[0006] The method may include: a first source router receiving a first memory access request from a first processor, setting routing information for the first memory access request, wherein the routing information for the first memory access request is used to route the first memory access request to a first destination router connected to the first MRAM or a network interface of the first source router connected to the first MRAM; a second source router receiving a second memory access request from a second processor, setting routing information for the second memory access request, wherein the routing information for the second memory access request is used to route the second memory access request to a second destination router connected to the second MRAM or a network interface of the second source router connected to the second MRAM; wherein the second processor has higher requirements for data processing latency than the first processor.

[0007] Optionally, the first memory access request is a data write command or a data read command, and the second memory access request is a data write command or a data read command.

[0008] In the above implementation, the memory access requests of the second processor are scheduled to be processed on the second MRAM. The second MRAM has a higher data write speed, which ensures the performance of the second processor in accessing data, where data processing latency requirements are high. The memory access requests of the first processor are scheduled to be processed on the first MRAM, which has higher data retention capacity, thus ensuring the stability of the data in the first processor. Therefore, by adopting the above embodiments of this application, data memory access performance can be improved.

[0009] In the above implementation, MRAM is a non-volatile memory, meaning data is not lost when power is off. Using MRAM as part of the cache can reduce cache power consumption. Furthermore, MRAM has higher data read / write capabilities, supporting large-capacity data storage, improving cache read / write speed, and increasing cache capacity. The first MRAM has high data retention, meaning data is less likely to change within it, reducing the bit error rate. The second MRAM has a high data write speed, enabling high-speed data writing.

[0010] In one possible implementation, the method further includes: when the data storage volume of the second MRAM reaches a set threshold, the second destination router migrates the data stored in the second MRAM to the first MRAM.

[0011] Optionally, some data in the second MRAM can be migrated to the first MRAM. For example, the data written first in the second MRAM can be migrated to the first MRAM, or data in the second MRAM with a read / write frequency lower than a threshold can be migrated to the first MRAM.

[0012] In the above implementation, when the data storage volume of the second MRAM reaches a set threshold, the data is migrated to the first MRAM. On the one hand, this increases the free space in the second MRAM so that data can be stored later. On the other hand, migrating the data to the first MRAM, which has a higher data retention capacity, can also improve the stability of data storage.

[0013] In one possible implementation, after the second destination router migrates the data stored in the second MRAM to the first MRAM, the method further includes: the second source router receiving a third memory access request from the second processor; if the third memory access request is a data write command, the second source router sets routing information for the third memory access request, the routing information for routing the third memory access request to the second destination router connected to the second MRAM or to the network interface of the second source router connected to the second MRAM; if the third memory access request is a data read command, the second source router sets routing information for the third memory access request, the routing information for routing the third memory access request to the first destination router connected to the first MRAM or to the network interface of the second source router connected to the first MRAM.

[0014] In the above implementation, after the data in the second MRAM is migrated to the first MRAM, when the router receives a memory access request from the second processor again, it can classify and match the data read command and the data write command, and allocate the data read operation to the first MRAM (high retention MRAM) for processing as much as possible, and allocate the data write operation to the second MRAM (high speed MRAM) for processing as much as possible, so as to ensure the performance of the data write operation.

[0015] Optionally, after the second source router receives the third memory access request from the second processor, the method further includes: the second source router setting the priority of the third memory access request, wherein the priority of the third memory access request is higher than the priority of the memory access request received by the first source router from the first processor.

[0016] In the above implementation, the second MRAM can handle memory access requests from both the first and second processors. By setting a priority, memory access requests from the second processor can be processed first, thereby ensuring the performance of the second processor in accessing data memory.

[0017] In one possible implementation, after the second source router receives a second memory access request from the second processor, the method further includes: the second source router setting a priority for the second memory access request, wherein the priority of the second memory access request is higher than the priority of the first memory access request.

[0018] In the above implementation, by setting a priority, memory access requests from the second processor can be processed first, thereby ensuring the performance of the second processor in accessing data memory.

[0019] In one possible implementation, the first processor includes a graphics processing unit (GPU), and the second processor includes a central processing unit (CPU) and / or a neural network processor (NPU).

[0020] In a second aspect, a system-on-a-chip (SoC) is provided, comprising a processor and a shared cache, wherein the processor and the shared cache communicate via an on-chip network; the shared cache comprises a first MRAM and a second MRAM, wherein the first MRAM has a higher data retention capability than the second MRAM and a lower data write speed than the second MRAM; the processor comprises a first processor and a second processor, wherein the second processor has a higher requirement for data processing latency than the first processor; the on-chip network comprises a first source router and a second source router; the first source router is configured to receive a first memory access request from the first processor, set routing information for the first memory access request, wherein the routing information for the first memory access request is used to route the first memory access request to a first destination router connected to the first MRAM or a network interface of the first source router connected to the first MRAM; the second source router is configured to receive a second memory access request from the second processor, set routing information for the second memory access request, wherein the routing information for the second memory access request is used to route the second memory access request to a second destination router connected to the second MRAM or a network interface of the second source router connected to the second MRAM.

[0021] In one possible implementation, the second destination router is specifically used to: migrate the data stored in the second MRAM to the first MRAM when the data storage volume of the second MRAM reaches a set threshold.

[0022] In one possible implementation, the second source router is further configured to: receive a third memory access request from the second processor after the second destination router has migrated the data stored in the second MRAM to the first MRAM; if the third memory access request is a data write command, then set routing information for the third memory access request, the routing information for the third memory access request being used to route the third memory access request to the second destination router connected to the second MRAM or to the network interface of the second source router connected to the second MRAM; if the third memory access request is a data read command, then set routing information for the third memory access request, the routing information for the third memory access request being used to route the third memory access request to the first destination router connected to the first MRAM or to the network interface of the second source router connected to the first MRAM.

[0023] In one possible implementation, the second source router is further configured to: after receiving a third memory access request from the second processor, set the priority of the third memory access request, wherein the priority of the third memory access request is higher than the priority of the memory access request received by the first source router from the first processor.

[0024] In one possible implementation, the second source router is further configured to: after receiving a second memory access request from the second processor, set the priority of the second memory access request, wherein the priority of the second memory access request is higher than the priority of the first memory access request.

[0025] In one possible implementation, the first processor includes a graphics processing unit (GPU), and the second processor includes a central processing unit (CPU) and / or a neural network processing unit (NPU).

[0026] Thirdly, a communication device is provided, the communication device comprising a system-on-a-chip as described in any one of the second aspects.

[0027] For the beneficial effects of the second and third aspects mentioned above, please refer to the beneficial effects of the first aspect, which will not be repeated here. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the structure of an MTJ according to an embodiment of this application;

[0029] Figure 2 This is a schematic diagram of the structure of a storage unit in an embodiment of this application;

[0030] Figure 3 This is a schematic diagram of a traditional xPU heterogeneous architecture;

[0031] Figure 4 This application provides a schematic diagram of the structure of a SoC;

[0032] Figure 5A This is a schematic diagram of a 2D packaging structure of a system-on-a-chip provided in an embodiment of this application;

[0033] Figure 5B A schematic diagram of a 3D packaging structure of a system-on-a-chip provided in an embodiment of this application;

[0034] Figure 5C This is a schematic diagram of another 3D packaging structure of a system-on-a-chip provided in an embodiment of this application;

[0035] Figure 5D A schematic diagram of a system-on-chip with a stacked structure of two or more layers provided for embodiments of this application;

[0036] Figure 6A schematic diagram of the xPU heterogeneous architecture provided in the embodiments of this application;

[0037] Figure 7 This is a schematic diagram of the NoC topology provided in an embodiment of this application;

[0038] Figure 8 This application provides a schematic diagram of a memory access request scheduling method.

[0039] Figure 9 This is another memory access request scheduling diagram provided in an embodiment of this application;

[0040] Figure 10 This is another memory access request scheduling diagram provided for an embodiment of this application. Detailed Implementation

[0041] Before introducing the data access method and on-chip system provided in this application, a memory involved in the embodiments of this application will be described first.

[0042] This application introduces a non-volatile memory—magnetic random access memory (MRAM). MRAM has both high-speed data read and write capabilities and supports large-capacity data storage.

[0043] MRAM primarily utilizes the magnetic tunnel junction (MTJ) to achieve data storage by exhibiting different resistance values ​​under different currents.

[0044] like Figure 1 As shown, a magnetic tunnel junction generally refers to a sandwich structure consisting of a ferromagnetic layer, a non-magnetic insulating layer, and a ferromagnetic layer. The bottom ferromagnetic layer is called the reference layer. The non-magnetic insulating layer is called the barrier layer. The top ferromagnetic layer is called the free layer. Typically, the reference layer has high magnetism, while the free layer has weak magnetism.

[0045] The MRAM used in this embodiment can be a common spin-torque-transfer MRAM (STT-MRAM), which has advantages over SRAM in terms of high density and low power consumption. At the same process node, STT-MRAM can achieve 2-3 times the density of SRAM; simultaneously, in most application scenarios, system simulation results show that the overall power consumption of STT-MRAM is half or even lower than that of SRAM. It should be understood that this embodiment does not limit the type of MRAM used. Here, STT-MRAM is used as an example to explain the working principle of MRAM.

[0046] In a STT (Sequential Transmission Thermoelectric) system, when current flows from the free layer of the MTJ (Medium Transmission Jet) towards the reference layer (the direction of electron movement is opposite to the direction of current), the electrons are polarized by the strong magnetism of the reference layer, forming a spin current carrying the same magnetization direction as the reference layer. This spin current is injected into the free layer. Because the free layer has weaker magnetism, its magnetization direction is deflected by the spin current, tending to align with the magnetization direction of the reference layer. In this case, the resistance of the MTJ is relatively low, which can be considered as writing data "0".

[0047] When current flows through the reference layer of an MTJ to the free layer, electrons, due to the weak magnetism of the free layer, are insufficient to polarize a spin current strong enough to change the magnetization direction of the reference layer. Upon reaching the surface of the reference layer, the stronger magnetism of the reference layer causes the spin state, opposite to its own magnetic moment, to bounce back into the free layer, forming a spin current opposite to the magnetization direction of the reference layer. Because the magnetism of the free layer is weak, its magnetization direction deflects under the influence of this spin current, tending to be opposite to the magnetization direction of the reference layer. In this case, the resistance of the MTJ is relatively high, which can be considered as writing data "1".

[0048] STT-MRAM comprises multiple memory cells, each of which mainly includes a metal oxide semiconductor field-effect transistor (MOSFET) and an MTJ.

[0049] This explanation uses an N-type field-effect transistor as an example. Figure 2 As shown, the gate of an N-type field-effect transistor (FET) is connected to the word line (WL). The WL controls whether the N-type FET is turned on or off, i.e., it controls the operating state of the N-type FET. The source (also called the drain) of the N-type FET is connected to the reference layer of the MTJ via the source line (SL). The connection on the free layer of the MTJ is the bit line (BL). Applying different voltages between the bit line and the source line generates a current flowing through the magnetic tunnel junction (MTJ) (this current can be called the write current). This write current changes the magnetization direction of the free layer of the MTJ, causing a change in the resistance of the MTJ, thus completing the writing of data "0" or "1" into the memory cell.

[0050] When reading data from the memory cell, the bit line inputs a read current to the MTJ (this read current is usually smaller than the write current input for writing data). This read current passes through the MTJ and the N-type field-effect transistor and is output from the source line. By detecting the voltage at the current input terminal and the current output terminal (this voltage is related to the resistance of the MTJ), it is determined whether the data in the memory cell is "0" or "1".

[0051] MRAM achieves data storage by ensuring the magnetization directions of the reference layer and the free layer in the MTJ are in the same or opposite directions. The data writing speed of MRAM depends on the rate at which the magnetization direction of the free layer in the MTJ changes. That is, when a write current is input to the MTJ, if the magnetization direction of the free layer in the MTJ can deflect in a short time, it means that data writing can be achieved quickly; if the magnetization direction of the free layer in the MTJ takes a long time to deflect, it means that the data writing speed is relatively slow.

[0052] To improve data write speed, some properties of the MTJ in MRAM can be modified. For example, the degree of oxidation at the interfaces above and below the free layer can be reduced. Another example is reducing the thickness of the free layer.

[0053] MRAM's data retention capability refers to its ability to maintain its value after data is written to the storage unit. This capability is related to the ease with which the magnetization direction of the free layer in the MTJ (Metal Lithium Jet) changes. In other words, if the magnetization direction of the free layer in the MTJ does not easily change over a long period after data is written, it indicates that the resistance of the MTJ will not easily change, the written data will not be altered, and the MRAM has strong data retention capability. Conversely, if the magnetization direction of the free layer in the MTJ is affected by environmental factors and changes again, it indicates that the resistance of the MTJ is prone to change, the written data is lost, and the MRAM has poor data retention capability.

[0054] To improve the data retention of MRAM, some properties of the MTJ in the MRAM can also be modified. For example, the degree of oxidation at the interfaces between the upper and lower layers of the free layer can be increased. Another example is increasing the thickness of the free layer. Yet another example is inserting a metal-based thin film or a metal oxide thin film into the middle of the free layer.

[0055] With the rise of fields such as machine learning, autonomous driving, and industrial simulation, general-purpose central processing units (CPUs) are facing increasingly obvious technical bottlenecks when processing massive amounts of computation, images, and data, such as low parallelism and insufficient bandwidth. To meet the diverse computing demands, more and more scenarios are introducing hardware acceleration units such as graphics processing units (GPUs), neural network processing units (NPUs), and field-programmable gate arrays (FPGAs) in addition to CPUs, making heterogeneous computing architectures a growing trend.

[0056] Currently, such as Figure 3 As shown, various xPUs are integrated through on-chip or packaged methods, sharing the system's DDR main memory. However, the last-level cache (LLC), which is one level above the main memory in the storage system, is usually private to each xPU and does not share data or maintain consistency with each other. In many application scenarios, heterogeneous xPU architecture processors can effectively reduce data copying and communication between different xPU processing units by sharing the last-level cache (LLC), while also effectively reducing data transfer between on-chip cache and off-chip double data rate (DDR) main memory.

[0057] Since data sharing between xPUs starts at the DDR level, in application scenarios where there are multiple repetitive data interactions between xPUs, the same data needs to be copied and modified multiple times in DDR, significantly increasing system memory usage and the probability of congestion on the system bus. Furthermore, the back-and-forth movement of data from cache to DDR increases data movement latency, directly impacting the speed and energy efficiency of xPU interaction and collaboration.

[0058] This application proposes an xPU heterogeneous system to address the above-mentioned problems. It replaces the last-level cache implemented by SRAM in the traditional architecture with MRAM technology, fully utilizing the large capacity of MRAM and the shared last-level cache architecture to improve the efficiency of system data sharing, thereby enhancing system computing performance and reducing system power consumption. Based on the heterogeneous system provided in this application, a data memory access method is also provided to improve data memory access performance.

[0059] This application involves two types of MRAM with different performance: one with relatively high data retention and the other with relatively high data write speed. The high data retention version is relatively easy to manufacture due to its higher device stability and higher process yield. The high-speed version, by sacrificing data retention, can achieve read / write latency comparable to SRAM, but requires higher manufacturing process requirements and stronger error correction circuit design.

[0060] It is understood that the comparison of data retention and data write speed here is limited to two types of MRAM. For ease of explanation, in this embodiment, the MRAM with relatively higher data retention is referred to as the first MRAM or high-retention-force MRAM, and the MRAM with relatively higher data write speed is referred to as the second MRAM or high-speed MRAM.

[0061] The data retention capability of high-speed MRAM (first MRAM) is relatively weak. In order to avoid the loss of data written in high-speed MRAM, an additional circuit can be configured for the high-speed MRAM in the embodiments of this application. The circuit can input refresh current to the high-speed MRAM to ensure that the magnetization direction of the free layer of MTJ in the high-speed MRAM remains unchanged after data is written.

[0062] To more accurately evaluate MRAM data retention capability, a retention capability threshold can be set. For example, this threshold can be a time value. If the time it takes for the data to change after being written to the MRAM exceeds this threshold, then the MRAM can be considered a high-retention-capability MRAM (first MRAM). Otherwise, the MRAM is considered to have low data retention capability and is classified as a low-retention-capability MRAM. Therefore, in this embodiment, the high-retention-capability MRAM is the MRAM with the longest time for data to change after being written to the MRAM. The above method for evaluating MRAM data retention capability is merely an example; this application does not limit the specific evaluation criteria for MRAM data retention capability or the method for setting the retention capability threshold.

[0063] Similarly, to more accurately evaluate the MRAM data write speed, a speed threshold can be set. For example, this speed threshold can be a speed value. If the data write speed in the MRAM is greater than this speed threshold, then the MRAM can be considered a high-speed MRAM (secondary MRAM). Otherwise, the MRAM is considered to have a low data write speed and is a low-speed MRAM. Therefore, in this embodiment, the high-speed MRAM is the MRAM with the highest data write speed among the two types of MRAM. The above method of evaluating MRAM data write speed is merely an example; this application does not limit the specific evaluation criteria for MRAM data write speed or the method of setting the speed threshold.

[0064] The on-chip system provided in the embodiments of this application will be described below, such as Figure 4 The diagram shown is a schematic representation of a SoC 10 according to an embodiment of this application. The SoC 10 includes a processing module 100 and a cache 200. The processing module 100 is used for data processing. The processing module 100 is capable of reading and writing data to the cache 200. That is, the processing module 100 can write data to or read data from the cache 200. For example, the data that the processing module 100 needs to process can be stored in the cache 200, and the processing module 100 can read data from the cache 200 when it needs to process the data. Alternatively, the processing module 100 can write the processed data into the cache 200. It can be understood that the processing module can also be referred to as a processor.

[0065] The embodiments of this application do not limit the specific form of the processing module 100. For example, the processing module 100 can be the core of a processor, that is, the processing module 100 can be the part of the on-chip system responsible for data processing. The embodiments of this application do not limit the type of processor, which can be a CPU, GPU, tensor processing unit (TPU), data processing unit (DPU), or NPU, etc.

[0066] The processing module 100 can also be implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0067] Cache 200 is the data storage module on the SoC 10 that is closest to the processing module 100. The processing module 100 will directly read and write data to cache 200.

[0068] Cache 200 comprises N levels of cache, where N is a positive integer greater than 2. When processing module 100 reads data from cache 200, it reads data from the cache in ascending order of level until a data hit is found. That is, processing module 100 first reads data from L1 cache 210. If data is hit in L1 cache 210, the data reading operation ends; if data is not hit in L1 cache 210, processing module 100 continues to read data from L2 cache 220. If data is hit in L2 cache 220, the data reading operation ends; if data is not hit in L2 cache 220, processing module 100 continues to read data from the next lower level cache; if processing module 100 still does not find data in the last level cache, processing module 100 will then read data from memory other than cache 200.

[0069] When processing module 100 writes data to cache 200, it also writes the data to first-level cache 210. In these N levels of cache, if a higher-level cache has no free space or cannot write data, it will migrate the data from that higher-level cache to the next lower-level cache so that the higher-level cache can continue writing data. The migrated data can be the first data written to the higher-level cache, or data whose read / write frequency is below a threshold. For example, when there is no free space in the first-level cache or it cannot write data, the data in the first-level cache will be migrated to the second-level cache to ensure that the first-level cache can continue writing data. When there is no free space in the second-level cache or it cannot write data, the data in the second-level cache will be migrated to the next lower-level cache to ensure that the second-level cache can continue writing data.

[0070] The embodiments of this application do not limit the number of processing modules 100. The system-on-a-chip 10 may include one processing module 100 or multiple processing modules 100.

[0071] When the system-on-a-chip 10 includes multiple processing modules 100, the multiple processing modules 100 can share the N levels of cache, that is, the multiple processing modules 100 can all read and write data to the N levels of cache.

[0072] The multiple processing modules 100 may also share only some levels of cache. For example, the multiple processing modules 100 may share only the last level cache or the last few levels cache among the N levels of cache. That is, each processing module 100 has a portion of the cache levels used independently, while the remaining portions of the cache levels can be shared by the multiple processing modules 100.

[0073] Taking N=3 as an example, each processing module 100 is configured with an independently used first-level cache 210 and second-level cache 220. Multiple processing modules 100 share the last-level cache 230.

[0074] like Figure 4 As shown, in this embodiment, the last-level cache (LLC) 230 in cache 200 includes MRAM 231. Compared to SRAM, MRAM 231 is a non-volatile memory. Data in MRAM 231 is not easily lost when the on-chip system 10 loses power, and there is no need to continuously input current into MRAM 231 to maintain the data. This effectively reduces power consumption. Furthermore, MRAM 231 can support large-capacity data storage. Compared to SRAM, MRAM 231 has a higher degree of integration; that is, for the same area, MRAM 231 has a larger storage space, thus increasing the storage space of cache 200.

[0075] In one possible SoC 10 provided in this application embodiment, the MRAM 231 includes a first MRAM 2311 (also referred to as a high retention MRAM 2311) and a second MRAM 2312 (also referred to as a high speed MRAM 2312).

[0076] The following description uses a system-on-a-chip (SoC) 10, which includes two processing modules 100 and a cache 200 comprising three levels of cache, as an example to illustrate the structure of an LLC 230 including MRAM. It should be understood that the main change in this embodiment is the structure of the last level cache 230 in the cache 200. Therefore, the LLC 230 structure provided in this embodiment is also applicable to SoCs 10 with different numbers of processing modules 100 or different levels of cache.

[0077] like Figure 5A As shown, an embodiment of this application provides a system-on-a-chip (SoC). The SoC 10 includes two processing modules 100 and a cache 200. Each processing module 100 independently uses a level 1 cache 210 and a level 2 cache 220. LLC 230 includes two different types of memory: a first MRAM 2311 (also known as a high-retention MRAM 2311) and a second MRAM 2312 (also known as a high-speed MRAM 2312).

[0078] In LLC 230, optionally, high-speed MRAM 2312 is used for writing data to LLC 230, and high-retention-force MRAM 2311 is used for reading data from LLC 230. That is, when writing data to LLC 230, it is preferentially written to high-speed MRAM 2312. If there is no free space in high-speed MRAM 2312 or data cannot be written further, data can be migrated to high-retention-force MRAM 2311, allowing high-speed MRAM 2312 to continue being written to subsequently. Thus, when processing module 100 needs to read data from LLC 230, it can read data from high-retention-force MRAM 2311. Since MRAM itself can support large-capacity data storage, high-speed MRAM 2312 can provide even more storage space, further increasing the capacity of LLC 230.

[0079] This application embodiment does not limit the area of ​​the high-speed MRAM 2312 in LLC 230 (that is, the area occupied by the high-speed MRAM 2312 in SoC 10) and the area ratio of the high-holding-force MRAM 2311. Considering the data reading supported by the high-holding-force MRAM 2311, the area of ​​the high-holding-force MRAM 2311 can be larger than the area of ​​the high-speed MRAM 2312.

[0080] The high-hold-force MRAM 2311, due to its high data retention capability, makes the data stored in it less susceptible to alteration, thus reducing the bit error rate. The resistance of the MTJ in the high-hold-force MRAM 2311 differs significantly when writing data 0 or data 1; only a lower read current is needed to determine the data written to the MTJ, reducing data read latency.

[0081] The high-speed MRAM 2312 improves its data write speed by reducing its data retention force. The write current when writing data to the high-speed MRAM 2312 is less than the write current when writing data to the high-retention force MRAM 2311. The pressure on the barrier layer of the MTJ in the high-speed MRAM 2312 is relatively smaller, making it less likely to be broken down, and the lifespan of the high-speed MRAM 2312 is also relatively longer.

[0082] Because high-speed MRAM 2312 has weak data retention, to prevent changes to the data written into it, a refresh circuit can be added to provide refresh current and maintain the data. While this increases power consumption to some extent, it is still less than the power consumption of SRAM.

[0083] like Figure 5A The system-on-a-chip (SoC) 10 shown has components that can lie on the same plane, representing a 2D packaging approach. The overall area of ​​the SoC 10 is limited by the area of ​​its individual components. Deploying a large number of processing modules 100 or a large cache 200 within the SoC 10 increases its overall area. To further reduce the overall area of ​​the SoC 10 while maintaining the number of processing modules 100 or the size of the cache 200, a 3D packaging approach is proposed. 3D packaging means that the components of the SoC 10 are no longer all located on the same plane. Instead, they are packaged together in a three-dimensional manner. These components can lie on different planes within the SoC 10.

[0084] The following are two examples of system-on-chips using 3D packaging.

[0085] like Figure 5B As shown, an embodiment of this application provides a system-on-a-chip (SoC) 10, which includes two processing modules 100 and a cache 200. Each processing module 100 independently uses a Level 1 cache 210 and a Level 2 cache 220. An LLC 230 includes two different types of memory: a high-speed MRAM 2312 and a high-retention-force MRAM 2311. The LLC 230 is located above the two processing modules 100, the Level 1 cache 210, and the Level 2 cache 220. That is, the LLC 230 can be located on a different plane from the processing modules 100. This packaging method can also be called on-chip integration, where the high-speed MRAM and the high-retention-force MRAM are on the same chip die.

[0086] Figure 5B In the LLC 230, the two types of MRAM can be grown on the same substrate (such as a silicon wafer), that is, a high-speed MRAM 2312 and a high-retention MRAM 2311 grown separately on the same substrate. The two processing modules 100, the L1 cache 210, and the L2 cache 220 can be located on another substrate. Figure 5BAs shown, a substrate on which high-speed MRAM 2312 and high-retention-force MRAM 2311 are grown is placed on another substrate on which processing module 100, L1 cache 210 and L2 cache 220 are deployed. This forms a 3D packaged system-on-chip 10.

[0087] like Figure 5C As shown, an embodiment of this application provides a system-on-a-chip (SoC) 10, which includes two processing modules 100 and a cache 200. Each processing module 100 independently uses a level 1 cache 210 and a level 2 cache 220. An LLC 230 includes two different types of memory: a high-speed MRAM 2312 and a high-retention-force MRAM 2311. The LLC 230 is located above the two processing modules 100, the level 1 cache 210, and the level 2 cache 220. That is, the LLC 230 can be located in a different plane from the processing modules 100.

[0088] and Figure 5B Unlike other systems, the LLC 230 includes two types of MRAMs grown on different substrates: one for high-speed MRAM 2312 and the other for high-retention MRAM 2311. Compared to growing both types of MRAMs on the same substrate, growing high-speed MRAM 2312 and high-retention MRAM 2311 on separate substrates improves the yield of the on-chip system and reduces costs.

[0089] These two substrates can be spliced ​​together, and the spliced ​​substrate can be placed on the substrate on which the processing module 100, the L1 cache 210 and the L2 cache 220 are deployed to form a 3D packaged system-on-a-chip 10.

[0090] It should be noted that this example illustrates LLC 230 growing on two substrates. In practical applications, to improve the overall process yield, LLC 230 can be grown on more than two substrates, which can be spliced ​​together to form LLC 230.

[0091] exist Figure 5B as well as Figure 5C In the system-on-a-chip 10 shown, LLC 230 is located on one layer (i.e., on the same plane), while the processing module 100 and other levels of cache 200 are located on another layer (i.e., on another plane). The system-on-a-chip 10 adopts a two-layer stacking method. In some scenarios, the system-on-a-chip 10 may also adopt a stacking method with more than two layers.

[0092] like Figure 5DAs shown, an embodiment of this application provides a system-on-a-chip (SoC) 10, which includes two processing modules 100 and a cache 200. Each processing module 100 independently uses a Level 1 cache 210 and a Level 2 cache 220. LLC 230 includes two different types of memory: a high-speed MRAM 2312 and a high-retention-force MRAM 2311. The high-speed MRAM 2312 and the high-retention-force MRAM 2311 are located on different planes. The high-speed MRAM 2312 and the processing module 100 are located on different planes, and the high-retention-force MRAM 2311 and the processing module 100 are located on different planes. It can be understood that in this packaging method, the high-speed MRAM and the high-retention-force MRAM are located on different chip chips.

[0093] and Figure 5B Similarly, the two types of MRAM included in LLC230 are grown on different substrates, that is, there are two substrates, one for growing high-speed MRAM 2312 and the other for growing high-retention MRAM 2311.

[0094] and Figure 5B Unlike other substrates, both substrates are located on top of a substrate where the processing module 100, L1 cache 210, and L2 cache 220 are deployed. These two substrates do not need to be joined together; instead, they are stacked on two different planes. To further reduce data write latency, the substrate with high-speed MRAM 2312 can be located on a layer closer to the processing module 100, while the substrate with high-retention MRAM 2311 can be located on a layer farther from the processing module 100.

[0095] It should be noted that this explanation uses LLC 230 grown on two substrates as an example. In practical applications, to improve the overall process yield, LLC 230 can be grown on more than two substrates. These substrates can be stacked on the processing module 100. Alternatively, the substrates can be partially spliced ​​and partially stacked on the processing module 100. That is, some of these substrates can be spliced ​​together on the same layer, while the remaining unspliced ​​substrates are stacked on different layers.

[0096] In the xPU heterogeneous architecture provided in this application embodiment, different processors (or processing modules, which can be represented as xPUs) share a large-capacity cache through a network-on-chip (NoC) network. The same data is operated on in different orders according to the computing load of different scenarios, thereby reducing the copying and duplication of the same data between different processors and caches in traditional heterogeneous architectures, improving computing efficiency and reducing system energy consumption.

[0097] Optionally, the cache can be the last-level cache implemented by MRAM, and the specific structure can be found in the foregoing embodiments. It should be understood that the cache implemented by MRAM in the embodiments of this application can also be other levels of cache. For example, when the processor only has a level 1 cache, this cache may also be implemented by MRAM.

[0098] The following embodiments of this application are described using the example of the cache being the last level cache and implemented through MRAM.

[0099] Figure 6 From the perspective of communication between the processor and the last-level shared cache via NoC, the xPU heterogeneous architecture provided in this application embodiment is illustrated by way of example. The last-level shared cache is implemented by MRAM, and the specific implementation method is as described in the foregoing embodiment, and will not be repeated here. Figure 7 The NoC topology in the xPU heterogeneous architecture provided in this application embodiment is illustrated by way of NoC topology.

[0100] like Figure 6 As shown, the NoC architecture mainly consists of resource nodes, communication nodes, resource network interfaces (or simply network interfaces), and channels. Resource nodes primarily include compute nodes and storage nodes. Compute nodes include processors (such as...) Figure 6 (CPU, NPU, and GPU in the system), and storage nodes contain caches at various levels, such as... Figure 6 The last level shared cache (LLC) shown is the communication node, also known as the routing node or router (the router is in...). Figure 6 The resource network interface (represented by a circle containing the letter R) is primarily responsible for data communication between resource nodes. In NoC, after a resource node generates a data packet, it sends it to the source router through a specific interface. The source router reads the address information in the packet header, calculates the optimal route using a specific routing algorithm, and then transmits the packet to the destination resource node. The function of the resource network interface is to act as an interface between communication nodes and functional nodes, performing packet encapsulation and decapsulation. In the source node's resource network interface, source and destination address information is encapsulated into the packet header; in the destination node's resource network interface, this information is removed. A channel is essentially a bidirectional metal link used to ensure data transmission between nodes. It is divided into internal channels and external channels. Internal channels are metal links between resource nodes and communication nodes, while external channels are metal links between communication nodes.

[0101] Each resource node is treated as an independent unit, connected to the router via a network interface, thus converting communication between resource nodes into communication between routers. In such cases... Figure 7In the NoC topology shown in (1), the on-chip network is constructed by routers connecting multiple point-to-point data links, allowing information to be forwarded from any source resource node (resource nodes are represented as boxes containing IP letters in the diagram) to any destination resource node through different links. A router can include multiple network interfaces to connect resource nodes and other routers. For example, as shown in (1), Figure 7 As shown in Figure (2), the network interface (NI) of router R1 (represented by a circle containing the letter R1 in the figure) is connected to the processor (such as a GPU). Router R1 is the on-chip network router on the GPU side; Figure 7 As shown in (3), the network interface of router R2 (represented as a circle containing the letter R2 in the figure) is connected to the first MRAM. Router 2 is the router of the on-chip network on the first MRAM side.

[0102] Understandable. Figure 7 This application only illustrates one 2D mesh topology. NoC can also use other topologies, such as 3D mesh topology, ring topology, etc. This application does not limit this.

[0103] Generally, processors such as CPUs and NPUs are latency-sensitive but have relatively low bandwidth requirements; conversely, processors such as GPUs have very high parallelism requirements for processing data but are relatively insensitive to latency. If memory access requests from GPUs are not restricted in any way, their huge bandwidth consumption will block memory access requests from CPUs and NPUs, affecting the overall system performance. To address this, some embodiments of this application optimize memory access request scheduling, thereby processing memory access requests from different processors differently to improve data memory access performance.

[0104] In the following description, processors that are not sensitive to latency but have high requirements for parallelism, i.e., high bandwidth requirements, are referred to as the first processor, such as GPUs. Processors that are sensitive to latency and have relatively low bandwidth requirements are referred to as the second processor, such as CPUs and NPUs. In other words, the second processor has higher requirements for data processing latency than the first processor, and the first processor has higher requirements for bandwidth than the second processor.

[0105] In the implementation of the first memory access request scheduling optimization scheme provided in this application embodiment, at the router's network interface, memory access requests from the processor are classified and matched according to data read commands and data write commands. Data read operations are allocated to the first MRAM (high retention MRAM) for processing as much as possible, and data write operations are allocated to the second MRAM (high speed MRAM) for processing as much as possible. For example, after the router's network interface receives a memory access request from the first processor, if the memory access request is a read command for requesting to obtain data, routing information is added to the memory access request so that the read command is routed to the first MRAM; if the memory access request is a write command for requesting to write data, routing information is added to the memory access request so that the read command is routed to the second MRAM for processing. For example, when the router's network interface receives a memory access request from the second processor, if the memory access request is a read command to request data retrieval, routing information is added to the memory access request so that the read command is routed to the first MRAM. If the memory access request is a write command to request data writing, routing information is added to the memory access request so that the read command is routed to the second MRAM for processing.

[0106] Optionally, the router's network interface can add routing information to the header of the memory access request.

[0107] It is understandable that when a router (referred to as the source router) receives a memory access request from the processor and adds routing information to the memory access request, the memory access request may be directly routed to the last-level shared cache (such as the first MRAM or the second MRAM); it may also be routed to another router connected to the last-level shared cache (referred to as the destination router), and then sent to the last-level shared cache by the destination router; or it may be routed to an intermediate router, and after one or more hops, the memory access request is routed to the destination router connected to the last-level shared cache, and then sent to the last-level shared cache by the destination router.

[0108] It is understandable that when the network interface of the router connected to the last-level shared cache (such as the first MRAM or the second MRAM) receives a memory access request containing routing information, it can delete the routing information in the memory access request so that the memory access request with the routing information deleted can be sent to the last-level shared cache for processing.

[0109] In the implementation of the second memory access request scheduling optimization scheme provided in the embodiments of this application, the priority of memory access requests from the second processor is increased, thereby ensuring that memory access requests from the second processor have a relatively higher priority than memory access requests from the first processor.

[0110] In one possible implementation of the second memory access request scheduling optimization scheme described above, after receiving a memory access request from the second processor at the router's network interface, priority information is set in the memory access request. This priority information indicates a higher priority than the memory access request from the first processor. After the memory access request containing the priority information is routed to the router connected to the last-level shared cache, the router can schedule the memory access request with priority based on the priority information contained in the memory access request.

[0111] In one possible implementation of the second memory access request scheduling optimization scheme mentioned above, after the last-level cache (such as the first MRAM or the second MRAM) receives a memory access request containing priority information, it can determine the processing priority of the memory access request based on the priority information contained in the memory access request. For example, memory access requests with higher priority can be processed first.

[0112] In another possible implementation of the second memory access request scheduling optimization scheme described above, when the router connected to the last-level shared cache (such as the first MRAM or the second MRAM) receives a memory access request, it determines whether the request originates from the first processor or the second processor. If it originates from the first processor, the request can be stored in the second queue; if it originates from the second processor, it can be stored in the first queue, with the first queue having a higher priority than the second queue. For example, the router can determine whether the memory access request originates from the first or second processor based on the source address information (such as the source address or source port number) in the header of the memory access request. When scheduling memory access requests in the first and second queues, the processor can prioritize scheduling requests in the first queue. For instance, it can schedule requests in the first queue first and then schedule requests in the second queue; or, for example, it can schedule every N (N is an integer greater than 1) memory access requests in the first queue before scheduling one memory access request in the second queue.

[0113] In one possible implementation of the second memory access request scheduling optimization scheme described above, after the last-level cache (such as the first MRAM or the second MRAM) receives a memory access request containing priority information, it can place the memory access request into different queues according to the priority information contained in the request. For example, if the priority of the memory access request is low, it can be placed in the second queue; if the priority of the memory access request is high, it can be placed in the first queue. The first queue has a higher priority than the second queue, and cache requests in the first queue can be processed first. For example, memory access requests in the first queue can be processed before memory access requests in the second queue; or, for example, after processing N (N is an integer greater than 1) memory access requests in the first queue, one memory access request in the second queue can be processed.

[0114] The first and second memory access request scheduling optimization schemes described above can be used in combination. An example of combining these two memory access request scheduling optimization schemes is as follows: Figure 8 As shown. Figure 8 As shown, at the network interface of the source router, if a memory access request is received from the first processor (e.g., GPU), priority information is set in the memory access request to indicate a second priority. If the memory access request is a data read command, routing information is added to the memory access request so that the memory access request can be routed to the first MRAM. If the memory access request is a data write command, routing information is added to the memory access request so that the memory access request can be routed to the second MRAM. At the network interface of the source router, if a memory access request is received from the second processor (e.g., CPU or NPU), priority information is set in the memory access request to indicate a first priority (the first priority is higher than the second priority). If the memory access request is a data read command, routing information is added to the memory access request so that the memory access request can be routed to the first MRAM. If the memory access request is a data write command, routing information is added to the memory access request so that the memory access request can be routed to the second MRAM.

[0115] In the first MRAM, read commands from the second processor have a higher priority than read commands from the first processor, therefore read commands from the second processor are processed first. In the second MRAM, write commands from the second processor have a higher priority than write commands from the first processor, therefore write commands from the second processor are processed first.

[0116] In the above implementation, the first MRAM has high data retention capability, and data in the first MRAM is not easily changed. Therefore, the above implementation can reduce the bit error rate. The second MRAM has high data write capability, enabling high-speed data writing. Prioritizing data writing to the second MRAM can ensure the data write speed.

[0117] In the implementation of the third memory access request scheduling optimization scheme provided in this application embodiment, at the network interface of the router, memory access requests from the processor are classified and matched according to the processor type. Memory access requests from the first processor are allocated to the first MRAM (high retention MRAM) for processing, and memory access requests from the second processor are allocated to the second MRAM (high speed MRAM) for processing.

[0118] For example, in a NoC architecture, the first source router is connected to the first processor, and the first destination router is connected to the first MRAM; or, the second source router is connected to the second processor, and the second destination router is connected to the second MRAM. After receiving a memory access request from the first processor, the first source router (or its network interface) sets the routing information for that first memory access request, such as adding routing information to the header of the first memory access request. Based on this routing information, the first memory access request can be routed to the first destination router. After receiving the first memory access request, the first destination router (or its network interface) can delete the routing information and send the first memory access request with the deleted routing information to the first MRAM for processing. Similarly, after receiving a second memory access request from the second processor, the second source router sets the routing information for that second memory access request, such as adding routing information to the header of the second memory access request. Based on this routing information, the second memory access request can be routed to the second destination router. After receiving the second memory access request, the second destination router can delete the routing information and send the second memory access request with the deleted routing information to the second MRAM for processing. The first memory access request can be a data read command or a data write command; the second memory access request can be a data read command or a data write command.

[0119] For example, in a NoC architecture, the first network interface of the first source router is connected to the first processor, and the second network interface is connected to the first MRAM; or, the first network interface of the second source router is connected to the second processor, and the second network interface is connected to the second MRAM. After receiving a memory access request from the first processor, the first network interface of the first source router sets the routing information for the first memory access request, such as adding routing information to the header of the first memory access request. Based on this routing information, the first memory access request can be routed to the second network interface of the first source router. The second network interface can delete the routing information and send the first memory access request with the deleted routing information to the first MRAM for processing. Similarly, after receiving a second memory access request from the second processor, the first network interface of the second source router sets the routing information for the second memory access request, such as adding routing information to the header of the second memory access request. Based on this routing information, the second memory access request can be routed to the second network interface of the second source router. The second network interface can delete the routing information and send the second memory access request with the deleted routing information to the second MRAM for processing. Here, the first memory access request can be a data read command or a data write command; the second memory access request can be a data read command or a data write command.

[0120] Figure 9 An example of employing the third memory access request scheduling optimization scheme described above is illustrated. For instance... Figure 9 As shown, the router's network interface receives memory access requests (such as data read commands and / or data write commands) from the processor. For a router connected to a first processor (such as a GPU), upon receiving a memory access request from the first processor, routing information is configured to route the memory access request to the first MRAM (high-holding-force MRAM); for a router connected to a second processor (such as a CPU or NPU), upon receiving a memory access request from the second processor, routing information is configured to route the memory access request to the second MRAM (high-speed MRAM).

[0121] In the above implementation, the memory access requests of the second processor are scheduled to be processed on the second MRAM. The second MRAM has a higher data write speed, which ensures the performance of the second processor in accessing data, where data processing latency requirements are high. The memory access requests of the first processor are scheduled to be processed on the first MRAM, which has higher data retention capacity, thus ensuring the stability of the data in the first processor. Therefore, by adopting the above embodiments of this application, data memory access performance can be improved.

[0122] Optionally, after receiving the second memory access request from the second processor, the second source router can also set the priority of the second memory access request. Similarly, after receiving the first memory access request from the first processor, the first source router can also set the priority of the first memory access request. The second memory access request has a higher priority than the first memory access request. This ensures that memory access requests from the second processor are processed with priority over those from the first processor. Since memory access requests from the second processor are more sensitive to latency, this method can guarantee the processing performance of services running on the second processor.

[0123] Optionally, when the data storage volume of the second MRAM reaches a set threshold, the data stored in the second MRAM can be migrated to the first MRAM. Optionally, a portion of the data in the second MRAM can be migrated to the first MRAM; for example, the data written first in the second MRAM can be migrated to the first MRAM, or data in the second MRAM with a read / write frequency below the threshold can be migrated to the first MRAM. This increases the free space in the second MRAM, allowing for subsequent data writing based on memory access requests from the second processor. Optionally, the data stored in the second MRAM can be migrated to the first MRAM via a second destination router connected to the second MRAM. Optionally, the second destination router can send a notification of the data migration to other routers.

[0124] Optionally, after migrating the data stored in the second MRAM to the first MRAM, when the second source router (or the network interface of the second source router connected to the second processor) receives a third memory access request from the second processor, if the third memory access request is a data write command, the second source router sets the routing information for the third memory access request. Based on this routing information, the third memory access request is routed to the second destination router connected to the second MRAM or to the network interface of the second source router connected to the second MRAM. If the third memory access request is a data read command, the second source router sets the routing information for the third memory access request. Based on this routing information, the third memory access request is routed to the first destination router connected to the first MRAM or to the network interface of the second source router connected to the first MRAM.

[0125] After the first source router receives the fourth memory access request from the first processor, the fourth memory access request is still routed to the first destination router connected to the first MRAM, or routed to the network interface of the first source router connected to the first MRAM, so that the fourth memory access request is processed on the first MRAM.

[0126] Optionally, after receiving a third memory access request from the second processor, the second source router can also set the priority of the third memory access request. Similarly, after receiving a fourth memory access request from the first processor, the first source router can also set the priority of the fourth memory access request. The third memory access request has a higher priority than the fourth memory access request. Since both read commands from the first processor and read commands from the second processor are scheduled for processing on the first MRAM, setting the priority of the read commands from the second processor to a higher priority allows for priority processing of read commands from the second processor on the first MRAM, thereby ensuring the processing performance of services running on the second processor.

[0127] Figure 10 An example is shown illustrating the processing flow after migrating data stored in the second MRAM to the first MRAM when employing the third memory access request scheduling optimization scheme described above. For example... Figure 10As shown, after migrating the data stored in the second MRAM to the first MRAM, the router's network interface receives memory access requests (such as data read commands and / or data write commands) from the processor. For a router connected to the first processor (such as a GPU), upon receiving a memory access request from the first processor, the priority of the memory access request is set to the second priority, and routing information is set so that the memory access request is routed to the first MRAM (high retention MRAM). For a router connected to the second processor (such as a CPU or NPU), upon receiving a memory access request from the second processor, the priority of the memory access request is set to the first priority (first priority is higher than second priority). If the memory access request is a data read command, routing information is set so that the memory access request is routed to the first MRAM (high retention MRAM); if the memory access request is a data write command, routing information is set so that the memory access request is routed to the second MRAM (high-speed MRAM). In the first MRAM, because the data read command from the second processor has a higher priority, it is processed first.

[0128] The above-described embodiments of this application, through the analysis of data access patterns, allocate data with different access characteristics to the last-level shared MRAM with different performance levels, thereby avoiding the potential impact of MRAM write latency and power consumption.

[0129] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A data access method, characterized in that, The method, applied to a system-on-a-chip (SoC), includes a processor shared cache, which comprises a first MRAM and a second MRAM. The first MRAM has higher data retention capacity than the second MRAM, and the first MRAM has lower data write speed than the second MRAM. The processor and the shared cache communicate via an on-chip network. The first source router receives a first memory access request from the first processor and sets routing information for the first memory access request. The routing information for the first memory access request is used to route the first memory access request to a first destination router connected to the first MRAM or a network interface of the first source router connected to the first MRAM. The second source router receives a second memory access request from the second processor and sets routing information for the second memory access request. The routing information for the second memory access request is used to route the second memory access request to the second destination router connected to the second MRAM or the network interface of the second source router connected to the second MRAM. The second processor has higher requirements for data processing latency than the first processor.

2. The method as described in claim 1, characterized in that, The method further includes: When the data storage volume of the second MRAM reaches a set threshold, the second destination router migrates the data stored in the second MRAM to the first MRAM.

3. The method as described in claim 2, characterized in that, After the second destination router migrates the data stored in the second MRAM to the first MRAM, the method further includes: The second source router receives a third memory access request from the second processor; If the third memory access request is a data write command, the second source router sets the routing information of the third memory access request. The routing information of the third memory access request is used to route the third memory access request to the second destination router connected to the second MRAM or to the network interface of the second source router connected to the second MRAM. If the third memory access request is a data read command, the second source router sets the routing information for the third memory access request. The routing information for the third memory access request is used to route the third memory access request to the first destination router connected to the first MRAM or to the network interface of the second source router connected to the first MRAM.

4. The method as described in claim 3, characterized in that, After the second source router receives a third memory access request from the second processor, the method further includes: The second source router sets the priority of the third memory access request, and the priority of the third memory access request is higher than the priority of the memory access request received by the first source router from the first processor.

5. The method as described in claim 1, characterized in that, After the second source router receives the second memory access request from the second processor, the method further includes: The second source router sets the priority of the second memory access request, and the priority of the second memory access request is higher than the priority of the first memory access request.

6. The method according to any one of claims 1-5, characterized in that, The first processor includes a graphics processing unit (GPU), and the second processor includes a central processing unit (CPU) and / or a neural network processing unit (NPU).

7. A system-on-a-chip, characterized in that, The system-on-a-chip includes a processor and a shared cache, and the processor and the shared cache communicate with each other via an on-chip network; The shared cache includes a first MRAM and a second MRAM, wherein the data retention capability of the first MRAM is higher than that of the second MRAM, and the data write speed of the first MRAM is lower than that of the second MRAM; The processor includes a first processor and a second processor, wherein the second processor has higher requirements for data processing latency than the first processor. The on-chip network includes a first source router and a second source router; A first source router is configured to receive a first memory access request from the first processor, set routing information for the first memory access request, and the routing information for the first memory access request is configured to route the first memory access request to a first destination router connected to the first MRAM or a network interface of the first source router connected to the first MRAM. The second source router is used to receive a second memory access request from the second processor, set routing information for the second memory access request, and the routing information for the second memory access request is used to route the second memory access request to a second destination router connected to the second MRAM or a network interface of the second source router connected to the second MRAM.

8. The system-on-a-chip as described in claim 7, characterized in that, The second destination router is specifically used for: When the data storage volume of the second MRAM reaches a set threshold, the data stored in the second MRAM is migrated to the first MRAM.

9. The system-on-a-chip as claimed in claim 8, characterized in that, The second source router is also used for: After the second destination router migrates the data stored in the second MRAM to the first MRAM, it receives a third memory access request from the second processor; If the third memory access request is a data write command, then the routing information of the third memory access request is set. The routing information of the third memory access request is used to route the third memory access request to the second destination router connected to the second MRAM or to the network interface of the second source router connected to the second MRAM. If the third memory access request is a data read command, then the routing information of the third memory access request is set. The routing information of the third memory access request is used to route the third memory access request to the first destination router connected to the first MRAM or to the network interface of the second source router connected to the first MRAM.

10. The system-on-a-chip as claimed in claim 9, characterized in that, The second source router is also used for: After receiving a third memory access request from the second processor, the priority of the third memory access request is set to be higher than the priority of the memory access request received by the first source router from the first processor.

11. The system-on-a-chip as claimed in claim 7, characterized in that, The second source router is also used for: After receiving a second memory access request from the second processor, the priority of the second memory access request is set to be higher than that of the first memory access request.

12. The system-on-a-chip as described in any one of claims 7-11, characterized in that, The first processor includes a graphics processing unit (GPU), and the second processor includes a central processing unit (CPU) and / or a neural network processing unit (NPU).

13. A communication device, characterized in that, The communication device includes a system-on-a-chip as described in any one of claims 7-12.

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