A chip, a chip and a chip debugging method

Abstract

The present disclosure provides a core particle, comprising: at least one core particle interconnection interface for connecting to at least one other core particle to communicate with at least one other core particle, a selection module connected to the at least one core particle interconnection interface, and a processing module connected to the selection module; at least one core particle interconnection interface receives second debugging information from at least one other core particle; the selection module is configured to receive at least one debugging information in the second debugging information and send it to the processing module; the processing module is configured to forward at least one debugging information in the core particle for debugging the core particle when it is determined that at least one debugging information is used for debugging the core particle, and send at least one debugging information to at least one core particle interconnection interface to send it to the corresponding at least one other core particle when it is determined that at least one debugging information is used for debugging the core particle. A chip and a chip debugging method are also provided.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a core particle, a chip, and a chip debugging method. Background Art

[0002] With the development of electronic technology, chip design has become more and more complex. A single chip can no longer meet all functional requirements, so multiple chips are needed to work together to achieve more complex functions. Chip debugging is an important part of the program development and chip design process. It aims to identify, isolate and repair errors in programs or chips.

[0003] In some related technologies, a "Joint Test Action Group (JTAG) daisy chain" method is used to debug multiple chips. Each chip is connected in series with its adjacent chip via a JTAG interface to form a chain. This method debugs all chips through a single JTAG interface. Once a single point failure occurs (failure of any chip or its JTAG interface in the chain), it will affect the debugging of all chips in the entire chain. In addition, the length of the "JTAG daisy chain" is limited by physical and electrical characteristics. A chain that is too long will affect signal integrity, such as causing signal attenuation and noise interference, limiting the scalability of the number of chips. In addition, the JTAG interface of each chip in the chain needs to be wired to ensure the correct signal path, which will increase the complexity and cost of printed circuit board (PCB) wiring in complex multi-chip designs and limit the packaging form. Summary of the invention

[0004] The present disclosure provides a chip, a chip and a chip debugging method.

[0005] In a first aspect, an embodiment of the present disclosure provides a core particle, comprising: at least one core particle interconnection interface for connecting to at least one other core particle to communicate with at least one other core particle, a selection module connected to the at least one core particle interconnection interface, and a processing module connected to the selection module, wherein: the at least one core particle interconnection interface is used to receive second tuning information from at least one other core particle; the selection module is configured to receive at least one tuning information in the second tuning information from the at least one core particle interconnection interface, and send the at least one tuning information to the processing module; the processing module is configured to, when it is determined that the at least one tuning information is tuning information for tuning the core particle, forward the at least one tuning information within the core particle for tuning the core particle, and when it is determined that the at least one tuning information is tuning information for tuning the at least one other core particle, send the at least one tuning information to the at least one core particle interconnection interface, so as to send the at least one tuning information to the corresponding at least one other core particle through the at least one core particle interconnection interface.

[0006] In a second aspect, an embodiment of the present disclosure provides a chip, comprising a first core particle and one or more second core particles, wherein: the first core particle comprises one or more core particle interconnection interfaces corresponding to each second core particle, each second core particle comprises its own core particle interconnection interface, and the core particle interconnection interface of each second core particle is connected to the corresponding core particle interconnection interface of the first core particle for communication between the first core particle and each second core particle; the chip comprises an external interface located on the first core particle, the external interface is used to connect to an external debugging device to receive first debugging information from the external debugging device; the first core particle also comprises a selection module and a processing module, wherein: the selection module of the first core particle is connected to the external interface and is configured to receive first debugging information from the external debugging device; A processing module for receiving first tuning information and sending the first tuning information to the first core particle; the processing module of the first core particle is connected to the selection module of the first core particle and one or more core particle interconnection interfaces of the first core particle, and is configured to, when it is determined that the first tuning information is tuning information for tuning the first core particle, forward the first tuning information within the first core particle for tuning the first core particle, and, when it is determined that the first tuning information is tuning information for tuning a second core particle among one or more second core particles, send the first tuning information to the core particle interconnection interface corresponding to the second core particle among the one or more core particle interconnection interfaces of the first core particle, so as to send the first tuning information to the second core particle for tuning the second core particle.

[0007] In a third aspect, an embodiment of the present disclosure provides a chip debugging method for debugging the chip in the second aspect or any possible embodiment of the second aspect, the method comprising: receiving first debugging information from an external debugging device through an external interface of the chip located on a first core particle; receiving the first debugging information from the external interface through a selection module of the first core particle and sending the first debugging information to a processing module of the first core particle; executing through the processing module of the first core particle: when it is determined that the first debugging information is debugging information for debugging the first core particle, forwarding the first debugging information within the first core particle for debugging the first core particle; when it is determined that the first debugging information is debugging information for debugging a second core particle among one or more second core particles, sending the first debugging information to an inter-core interconnection interface corresponding to the second core particle among one or more inter-core interconnection interfaces of the first core particle, so as to send the first debugging information to the second core particle for debugging the second core particle.

[0008] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, and when the computer program is executed by a processor, the third aspect and any possible embodiment of the third aspect are implemented.

[0009] In the embodiment of the present disclosure, a core particle can receive debugging information from at least one other core particle through at least one core particle interconnection interface connected to at least one other core particle, and the interaction of debugging information between core particles with communication connection can be realized through at least one core particle interconnection interface, which expands the way of obtaining debugging information and improves the transmission reliability of debugging information, thereby reducing or even eliminating the impact of single point failure. In addition, by adopting the method of the present disclosure, the "JTAG daisy chain" is no longer used to avoid signal integrity problems, and no additional dedicated debugging path wiring is required, which can reduce the complexity and cost of wiring. In theory, it can support the interconnection and debugging of any number of core particles and any topology structure, including high scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the accompanying drawings of the embodiments of the present disclosure:

[0011] Figure 1 A schematic diagram of debugging using a "JTAG daisy chain" method provided in an embodiment of the present disclosure;

[0012] Figure 2 A schematic diagram of the structure of a core particle provided in an embodiment of the present disclosure;

[0013] Figure 3 A schematic diagram of the structure of a chip provided in an embodiment of the present disclosure;

[0014] Figure 4 A flow chart of a chip debugging method provided by an embodiment of the present disclosure;

[0015] Figure 5 A schematic diagram of the structure of another core particle provided in an embodiment of the present disclosure;

[0016] Figure 6 A schematic diagram of the structure of another chip provided in an embodiment of the present disclosure;

[0017] Figure 7 A schematic diagram of the structure of another chip provided in an embodiment of the present disclosure;

[0018] Figure 8 A schematic diagram of the structure of another chip provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, a core particle, a chip, and a chip debugging method provided by an embodiment of the present disclosure are described in detail below with reference to the accompanying drawings.

[0020] The present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as being limited to the embodiments set forth below. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete, and will enable those skilled in the art to fully understand the scope of the present disclosure.

[0021] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification, and are used together with the detailed embodiments to explain the present disclosure, and do not constitute a limitation of the present disclosure. By describing the detailed embodiments with reference to the accompanying drawings, the above and other features and advantages will become more apparent to those skilled in the art.

[0022] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0023] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. The term "and / or" as used in the present disclosure includes any and all combinations of one or more related enumerated items. The singular forms "one" and "the" as used in the present disclosure are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "including", "made of..." as used in the present disclosure specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meanings as those commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as including meanings consistent with their meanings in the context of the relevant art and this disclosure, and will not be interpreted as including idealized or overly formal meanings unless explicitly defined in this disclosure.

[0025] Traditional system-on-chip (SoC) integrates different functional modules, such as processor core, memory controller, I / O interface, etc., on a single chip. SoC using chiplet architecture is an emerging system-on-chip. In this application, SoC using chiplet architecture is called chiplet SoC. Chiplet SoC uses chiplet technology to design multiple small, independent functional modules into independent chiplets. Each chiplet can be connected through a die-to-die (D2D) high-speed interconnect interface to form a complete system-on-chip.

[0026] The chiplet SoC architecture can not only significantly improve performance and efficiency in the design of baseband chips and server CPU chips, but also enhance design flexibility and scalability, while reducing manufacturing costs and complexity, and optimizing thermal management. These advantages make the chiplet SoC architecture an indispensable key technology in the design of baseband chips and server CPU chips.

[0027] With the development of semiconductor technology, the chiplet architecture is increasingly used in various types of chip design fields due to its many advantages. The chiplet architecture is not limited to CPU chips, but can also be applied to other types of chips. For example, graphics processing unit (GPU) chips, power management chips, sensor chips, etc. can all adopt the chiplet architecture. In this application, chips that adopt the chiplet architecture are referred to as chiplet architecture chips.

[0028] In some related technologies, the chiplet architecture chip is debugged using the "JTAG daisy chain" method. In this debugging method, each chiplet has an independent JTAG interface, and the JTAG interface of each chiplet is connected in series with the JTAG interface of the adjacent chiplet in sequence to form a chain, allowing all chiplets in the chiplet architecture chip to be debugged through a single JTAG interface. Figure 1, is a schematic diagram of debugging using a “JTAG daisy chain” method provided in an embodiment of the present disclosure, Figure 1 It is only a schematic diagram and does not constitute a limitation on the applicable scenarios of the technical solution provided in this application. Figure 1 The debugging process is explained by taking a chiplet architecture chip including two chiplets as an example. The test data input (Test Data In, TDI) pin of the external JTAG of the chiplet architecture chip is connected to a chiplet, and then the test data output (TestData Out, TDO) pin of the chiplet is connected to the TDI pin of the next chiplet, until the TDO pin of the last chiplet is connected from the chiplet architecture chip. Once a single point failure occurs in this method (failure of any chiplet or its JTAG interface in the chain), it will affect the debugging of all chiplets in the entire chain. Single point failures will increase the complexity of debugging and fault diagnosis, and will limit the reliability of chiplet architecture chip debugging.

[0029] In view of this, the present disclosure provides a core particle, a chip and a chip debugging method, which are described in detail below with reference to the accompanying drawings.

[0030] First, refer to the attached Figure 2 , is a schematic diagram of a core particle provided by an embodiment of the present disclosure. The core particle 200 can be applied to various types of chiplet architecture chips, such as a system-level chip using a chiplet architecture. The core particle 200 includes: at least one core particle interconnection interface 201_1~201_N, a selection module 202 and a processing module 203, wherein:

[0031] In the disclosed embodiment, 201_i is used to represent any chip interconnection interface, where i ranges from 1 to N, and N is an integer greater than or equal to 1.

[0032] In some embodiments, the selection module 202 , at least one inter-chip interconnection interface 201_1 - 201_N, and the processing module 203 are all connected to each other via a bus 204 .

[0033] In some embodiments, bus 204 may be a debug module interface (DMI) line, where the DMI line may be, for example, an Advanced Peripheral Bus (APB) of an Advanced RISC Machine (ARM) or a TileLink line of SiFive.

[0034] In the disclosed embodiment, at least one inter-chiplet interconnection interface 201_1~201_N is used to connect to at least one other chiplet to communicate with at least one other chiplet, the selection module 202 is connected to at least one inter-chiplet interconnection interface 201_1~201_N, and the processing module 203 is connected to the selection module 202.

[0035] In the disclosed embodiment, the present core particle can be connected to other core particles through an inter-core particle interconnection interface for communication, wherein the "connection" here includes both direct connection and indirect connection. The present core particle and other core particles are connected to each other through an inter-core particle interconnection interface for communication, which may include: the present core particle is directly connected to another core particle through the inter-core particle interconnection interface and communicates with it, or the present core particle is indirectly connected to another core particle through the inter-core particle interconnection interface via one or more intermediate core particles and communicates with it.

[0036] In the disclosed embodiment, other core particles refer to core particles other than the core particle 200 , which are different from the core particle 200 .

[0037] In the embodiment of the present disclosure, at least one inter-chip interconnection interface 201_1 to 201_N is used to receive second debugging information from at least one other chiplet. In one example, each inter-chip interconnection interface 201_i can be connected to one other chiplet, and each inter-chip interconnection interface 201_i can be used to receive second debugging information from one other chiplet corresponding thereto.

[0038] In the embodiment of the present disclosure, the selection module 202 is configured to receive at least one of the second debugging information from at least one inter-chip interconnection interface 201_1 to 201_N, and send the at least one debugging information to the processing module 203 .

[0039] In the embodiment of the present disclosure, the selection module 202 may be a multiplexer (MUX).

[0040] In some embodiments, the tuning information includes tuning data and / or tuning instructions.

[0041] In the embodiment of the present disclosure, the processing module 203 is configured to, when it is determined that at least one debugging information is debugging information for debugging the core particle 200, forward at least one debugging information within the core particle 200 for debugging the core particle 200, and when it is determined that at least one debugging information is debugging information for debugging at least one other core particle, send at least one debugging information to at least one inter-core interconnection interface 201_1~201_N, so as to send at least one debugging information to the corresponding at least one other core particle through the at least one inter-core interconnection interface 201_1~201_N.

[0042] In the embodiment of the present disclosure, the processing module 203 may forward at least one debugging information in the chiplet 200 through the bus 204 for debugging the chiplet 200 .

[0043] In the embodiment of the present disclosure, the processing module may be a DMI Interconect (DMI_IC) module.

[0044] In the embodiment of the present disclosure, a core particle can receive debugging information from at least one other core particle through at least one core particle interconnection interface connected to at least one other core particle, and the interaction of debugging information between core particles with communication connection can be realized through at least one core particle interconnection interface, which expands the way of obtaining debugging information and improves the transmission reliability of debugging information, thereby reducing or even eliminating the impact of single point failure. In addition, by adopting the method of the present disclosure, the "JTAG daisy chain" is no longer used to avoid signal integrity problems, and no additional dedicated debugging path wiring is required, which can reduce the complexity and cost of wiring. In theory, it can support the interconnection and debugging of any number of core particles and any topology structure, including high scalability.

[0045] In some embodiments, the processing module 203 is configured to determine, based on the configuration information, an inter-chip interconnection interface among at least one inter-chip interconnection interface 201_1~201_N of the chip 200 corresponding to the target chip when it is determined that at least one debugging information is debugging information for debugging a target chip in at least one other chip, and send at least one debugging information to the corresponding inter-chip interconnection interface, wherein the configuration information includes connection relationship information between the chip 200 and at least one other chip and / or information generated based on the connection relationship information.

[0046] In the embodiment of the present disclosure, the connection relationship information between the core particles can be used to determine the connection path between the core particles, for example, it may include direct connection information or indirect connection information, wherein the direct connection information may include the core particle interconnection interface information of the directly connected core particles, and the indirect connection information may include the core particle interconnection interface information of the core particles through which the connection path passes.

[0047] In some embodiments, each inter-chip interconnection interface 201_i is connected to corresponding other chiplets, and each inter-chip interconnection interface 201_i includes at least two bidirectional transmission interface units; each bidirectional transmission interface unit is used to receive second debugging information from corresponding other chiplets, and is also used to transmit at least one debugging information to corresponding other chiplets.

[0048] In the disclosed embodiment, the bidirectional transmission interface unit may be a bidirectional D2D high-speed interconnect interface. The number of bidirectional D2D high-speed interconnect interfaces may be determined according to the actual data transmission bandwidth. The larger the data transmission bandwidth, the more bidirectional D2D high-speed interconnect interfaces are determined to be used. In this way, when any chiplet or its JTAG interface in a chip using a chiplet architecture fails, debugging information can be obtained through the inter-chip interconnect interfaces of other non-faulty chiplets. At the same time, when some bidirectional D2D high-speed interconnect interfaces are blocked, debugging information can still be obtained through other non-blocked bidirectional D2D high-speed interconnect interfaces, which greatly improves the reliability of the debugging path, thereby reducing or even eliminating the impact of single-point failures on chiplet architecture chip debugging.

[0049] In the disclosed embodiment, the bidirectional D2D high-speed interconnection interface is a high-bandwidth, low-latency interconnection module between chiplets, and can support chiplet high-speed interconnection protocols (such as the Universal Chiplet Interconnect Express (UCIe)).

[0050] In the disclosed embodiments, the bidirectional D2D high-speed interconnect interface may include only a data interface, or may include a data interface and a signaling interface. In the case of including only a data interface, the data interface may be reused to transmit debugging data and debugging instructions. In the case of including a data interface and a signaling interface, the data interface is used to transmit debugging data, and the signaling interface is used to transmit debugging instructions. In this way, debugging data can be transmitted through the bidirectional D2D high-speed interconnect interface, and debugging instructions can be transmitted at the same time, that is, the debugging path between each chiplet reuses the data path between each chiplet, and no additional dedicated debugging path wiring is required, which can reduce the wiring complexity and cost within the chiplet architecture chip, and can simplify the packaging form and requirements.

[0051] In some embodiments, the core particle 200 also includes an external interface 205 for connecting to an external debugging device, and the selection module 202 is connected to the external interface 205, wherein: the external interface 205 is used to receive first debugging information from the external debugging device; the selection module 202 is configured to receive second debugging information from at least one core particle interconnection interface 201_1~201_N and at least one of the first debugging information of the external interface 205, and send at least one debugging information to the processing module 203.

[0052] In the disclosed embodiment, the first debugging information is debugging information sent by an external debugging device and not forwarded by other cores; the second debugging information is debugging information forwarded by other cores.

[0053] In some embodiments, the selection module 202 includes at least one second port for receiving the second debugging information, wherein each second port corresponds to another chiplet, and each other chiplet is connected to one or more chiplet interconnection interfaces among at least one chiplet interconnection interface 201_1 to 201_N of the chiplet 200, and the one or more chiplet interconnection interfaces are connected to the second port corresponding to each other chiplet, and is used to send the second debugging information from the corresponding other chiplet to the corresponding second port. In a possible example, the selection module 202 may also include a first port for receiving the first debugging information.

[0054] In the disclosed embodiment, the chiplet architecture chip may encapsulate only one set of external interfaces, through which any chiplet of the chiplet architecture chip can be connected. The inter-chiplet interconnection interface between the chiplets can realize the interaction of debugging information between adjacent chiplets, thereby realizing the debugging of all chiplets.

[0055] In some embodiments, the external interface 205 is any one of a JTAG interface, a USB interface, an Ethernet interface, a SPI interface, or a UART interface.

[0056] In some embodiments, the core particle 200 also includes a conversion module 206, the selection module 202 is connected to the external interface 205 via the conversion module 206, and the conversion module 206 and the selection module 202 are connected through the bus 204; the conversion module 206 is used to receive the first adjustment information from the external interface 205, convert the first adjustment information into a format suitable for transmission through the bus 204, and send the converted first adjustment information to the selection module 202 through the bus 204.

[0057] In an example, the external interface 205 is a JTAG interface, the bus 204 is a DMI line, and the first debugging information received through the external interface 205 is in the JTAG interface protocol format. The conversion module 206 is used to convert the first debugging information received from the external interface 205 from the JTAG interface protocol format to the DMI protocol format, and send the converted first debugging information to the selection module 202 through the bus 204. The conversion module 206 generates debugging information that can be transmitted through the bus 204. This conversion process ensures that the converted debugging information can meet the DMI protocol format requirements and can therefore be transmitted through the DMI line.

[0058] In the embodiment of the present disclosure, the conversion module may be a debug transport module (DTM).

[0059] It should be noted that the modules included in the core particle in the embodiment of the present disclosure can be independently provided or combined, and there is no limitation on this. For example, the external interface 205 and the conversion module 206 of the core particle 200 can be independently provided or combined.

[0060] Second, refer to the attached Figure 3 , is a schematic diagram of a chip structure provided by an embodiment of the present disclosure, wherein the chip 300 is a chiplet architecture chip, and the chip 300 includes: a first chiplet 301 and one or more second chiplets 302_1 to 302_N, wherein:

[0061] In the disclosed embodiment, any second core particle is represented by 302_i, wherein the value of i ranges from 1 to N, and N is an integer greater than or equal to 1.

[0062] It should be noted that the concepts or implementations involved in the second aspect that are the same as those in the first aspect can be found in the description of the first aspect and will not be repeated in the second aspect.

[0063] In the embodiment of the present disclosure, the first core particle 301 includes one or more inter-core interconnection interfaces 301_1_1~301_1_N corresponding to each second core particle 302_i, each second core particle 302_i includes its own inter-core interconnection interface, and the inter-core interconnection interface of each second core particle 302_i is connected to the corresponding inter-core interconnection interface of the first core particle 301 for communication between the first core particle 301 and each second core particle 302_i.

[0064] In the embodiment of the present disclosure, the chip 300 includes an external interface 301_2 located on the first chiplet 301 , and the external interface 301_2 is used to connect to an external debugging device to receive first debugging information from the external debugging device.

[0065] In the embodiment of the present disclosure, the first chip 301 further includes a selection module 301_3 and a processing module 301_4, wherein:

[0066] In the embodiment of the disclosure, the selection module 301_3 of the first chiplet 301 is connected to the external interface 301_2 and is configured to receive first debugging information received from the external interface 301_2 from an external debugging device and send the first debugging information to the processing module 301_4 of the first chiplet 301 .

[0067] In some embodiments, the selection module 301_3 of the first chiplet 301 , one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N of the first chiplet 301 , and the processing module 301_4 of the first chiplet 301 are all connected to each other via a bus 301_5 .

[0068] In some embodiments, the first core particle 301 further includes a conversion module 301_6, the selection module 301_3 of the first core particle 301 is connected to the external interface 301_2 via the conversion module 301_6, the conversion module 301_6 is connected to the selection module 301_3 of the first core particle 301 through a bus 301_5, and the conversion module 301_6 is configured to receive first debugging information received from the external interface 301_2, convert the first debugging information into a format suitable for transmission through the bus 301_5, and send the converted first debugging information to the selection module 301_3 of the first core particle 301 through the bus 301_5.

[0069] In the embodiment of the present disclosure, the processing module 301_4 of the first core particle 301 is connected to the selection module 301_3 of the first core particle 301 and one or more core particle interconnection interfaces 301_1_1~301_1_N of the first core particle 301, and is configured to, when it is determined that the first debugging information is debugging information for debugging the first core particle 301, forward the first debugging information within the first core particle 301 for debugging the first core particle 301, and when it is determined that the first debugging information is debugging information for debugging a second core particle 302_i among the one or more second core particles 302_1~302_N, send the first debugging information to the core particle interconnection interface corresponding to the second core particle 302_i among the one or more core particle interconnection interfaces 301_1_1~301_1_N of the first core particle 301, so as to send the first debugging information to the second core particle 302_i for debugging the second core particle 302_i.

[0070] In the embodiment of the present disclosure, the processing module 301_4 may forward the first debugging information in the first chiplet 301 through the bus 301_5 for debugging the first chiplet 301 .

[0071] In the embodiments of the present disclosure, each core particle in the chip can be connected through at least one core particle interconnection interface, and the at least one core particle interconnection interface can realize the interaction of debugging information between core particles with communication connection, expand the way of obtaining debugging information, and improve the transmission reliability of debugging information, so as to reduce or even eliminate the impact of single point failure. In addition, the chip in the present disclosure no longer uses the "JTAG daisy chain" to avoid signal integrity problems, does not require additional dedicated debugging path wiring, can reduce the complexity and cost of wiring, and can theoretically support any number and any topology of core particle interconnection and debugging, including high scalability. Moreover, the chiplet architecture chip in the present disclosure can only encapsulate a set of external interfaces, through which any chiplet of the chiplet architecture chip can be connected, and the core particle interconnection interface between each chiplet can realize the interaction of debugging information between adjacent chiplets, thereby realizing the debugging of all chiplets.

[0072] In some embodiments, the processing module 301_4 of the first core particle 301 is configured to determine, according to the configuration information, an inter-core interconnection interface corresponding to the second core particle 302_i among one or more inter-core interconnection interfaces 301_1_1~301_1_N of the first core particle 301 when it is determined that the first debugging information is debugging information for debugging a second core particle 302_i among one or more second core particles 302_1~302_N, and send the first debugging information to an inter-core interconnection interface corresponding to the second core particle 302_i among one or more inter-core interconnection interfaces 301_1_1~301_1_N of the first core particle 301, wherein the configuration information includes connection relationship information between the first core particle 301 and the one or more second core particles 302_1~302_N and / or information generated based on the connection relationship information.

[0073] In the embodiment of the present disclosure, the connection relationship information between the core particles can be used to determine the connection path between the core particles, for example, it may include direct connection information or indirect connection information, wherein the direct connection information may include the core particle interconnection interface information of the directly connected core particles, and the indirect connection information may include the core particle interconnection interface information of the core particles through which the connection path passes.

[0074] In some embodiments, each second core particle 302_i further includes a selection module and a processing module, wherein: the selection module of each second core particle 302_i is connected to the core particle interconnection interface of the second core particle 302_i, and is configured to receive the first tuning information from the first core particle 301 and send the first tuning information to the processing module of the second core particle 302_i; the processing module of each second core particle 302_i is connected to the selection module of the second core particle 302_i and the core particle interconnection interface of the second core particle 302_i, and is configured to forward the first tuning information within the second core particle 302_i for tuning the second core particle 302_i when it is determined that the first tuning information is tuning information for tuning the second core particle 302_i.

[0075] In the embodiment of the present disclosure, the processing module of each second chiplet 302_i may forward the first debugging information within the second chiplet 302_i via a bus for debugging the second chiplet 302_i.

[0076] In some embodiments, the selection module of the second core particle 302_i and the core particle interconnection interface of the second core particle 302_i are connected via a bus; one or more core particle interconnection interfaces 301_1_1~301_1_N of the first core particle 301 and the core particle interconnection interface of the second core particle 302_i are connected via a bus.

[0077] In some embodiments, the selection module of the first chiplet 301 further includes one or more second ports connected to one or more inter-chiplet interconnection interfaces 301_1_1 - 301_1_N of the first chiplet 301 , and the one or more second ports are configured to be in a disabled state.

[0078] In some embodiments, each second core particle 302_i also includes one or more inter-core interconnection interfaces connected to other core particles except the first core particle 301, and the selection module of each second core particle 302_i also includes one or more second ports connected to one or more inter-core interconnection interfaces of other core particles except the first core particle 301, and the one or more second ports of the selection module of each second core particle 302_i are configured to be in a disabled state.

[0079] In the embodiment of the present disclosure, a port being in a disabled state means that the port is in a state where data transmission is not allowed, and the port in the disabled state cannot be used to receive or send data.

[0080] In some embodiments, the chip 300 further includes a third chiplet 303, the third chiplet 303 includes an inter-chiplet interconnection interface, which is used to connect to a corresponding inter-chiplet interconnection interface of a second chiplet 302_i to communicate with the second chiplet 302_i, wherein:

[0081] The processing module 301_4 of the first core 301 is further configured to send the first debugging information to the core interconnection interface corresponding to the second core 302_i connected to the third core 303 among the one or more core interconnection interfaces 301_1_1 to 301_1_N of the first core 301 when determining that the first debugging information is debugging information for debugging the third core 303;

[0082] The processing module of the second core particle 302_i connected to the third core particle 303 is also configured to send the first debugging information to the core particle interconnection interface corresponding to the third core particle 303 of the second core particle 302_i when it is determined that the first debugging information is debugging information for debugging the third core particle 303, so as to send the first debugging information to the third core particle 303 for debugging the third core particle 303.

[0083] In some embodiments, the chip 300 further includes a fourth core-grain 304 and a fifth core-grain 305, the fourth core-grain 304 includes an inter-core interconnection interface, the fifth core-grain 305 includes an inter-core interconnection interface connected to the second core-grain 302_i and an inter-core interconnection interface connected to the fourth core-grain 304, the inter-core interconnection interface of the fourth core-grain 304 is connected to a corresponding inter-core interconnection interface of a second core-grain 302_i via the inter-core interconnection interface of the fifth core-grain 305 to communicate with the second core-grain 302_i, wherein:

[0084] The processing module 301_4 of the first chiplet 301 is further configured to send the first debugging information to the chiplet interconnection interface corresponding to the second chiplet 302_i connected to the fifth chiplet 305 among the one or more chiplet interconnection interfaces 301_1_1 to 301_1_N of the first chiplet 301 when determining that the first debugging information is debugging information for debugging the fourth chiplet 304;

[0085] The processing module of the second core 302_i connected to the fifth core 305 is further configured to send the first debugging information to the core interconnection interface corresponding to the fifth core 305 of the second core 302_i when determining that the first debugging information is debugging information for debugging the fourth core 304, so as to send the first debugging information to the fifth core 305;

[0086] The fifth core particle 305 further includes a selection module and a processing module, wherein:

[0087] The selection module of the fifth chiplet 305 is connected to the inter-chiplet interconnection interface of the fifth chiplet 305 and is configured to receive the first debugging information from the second chiplet 302_i and send the first debugging information to the processing module of the fifth chiplet 305;

[0088] The processing module of the fifth core particle 305 is connected to the selection module of the fifth core particle 305 and the core particle interconnection interface of the fifth core particle 305, and is configured to forward the first tuning information within the fifth core particle 305 for tuning the fifth core particle 305 when it is determined that the first tuning information is tuning information for tuning the fifth core particle 305, and to send the first tuning information to the core particle interconnection interface corresponding to the fourth core particle 304 when it is determined that the first tuning information is for tuning the fourth core particle 304, so as to send the first tuning information to the fourth core particle 304 for tuning the fourth core particle 304.

[0089] In the embodiment of the present disclosure, the processing module of the fifth chiplet 305 may forward the first debugging information in the fifth chiplet 305 through the bus for debugging the fifth chiplet 305 .

[0090] Thirdly, refer to the attached Figure 4 , is a flow chart of a chip debugging method provided in an embodiment of the present disclosure, which can be used to debug the chip 300 in the second aspect and any possible embodiment of the second aspect, and the method includes:

[0091] S401: receiving first debugging information from an external debugging device through the external interface 301_2 of the chip 300 located on the first core 301;

[0092] S402: receiving first debugging information from the external interface 301_2 through the selection module 301_3 of the first chiplet 301 and sending the first debugging information to the processing module 301_4 of the first chiplet 301;

[0093] In some embodiments, the method further includes: receiving first debugging information received from the external interface 301_2 through the conversion module 301_6 of the first core particle 301, converting the first debugging information into a format suitable for transmission through the bus 301_5, and sending the converted first debugging information to the selection module 301_3 of the first core particle 301 through the bus 301_5.

[0094] S403: Executed by the processing module 301_4 of the first core particle 301: when it is determined that the first debugging information is debugging information for debugging the first core particle 301, the first debugging information is forwarded in the first core particle 301 for debugging the first core particle 301; when it is determined that the first debugging information is debugging information for debugging a second core particle 302_i among one or more second core particles 302_1~302_N, the first debugging information is sent to the core particle interconnection interface corresponding to the second core particle 302_i among the one or more core particle interconnection interfaces 301_1_1~301_1_N of the first core particle 301, so as to send the first debugging information to the second core particle 302_i for debugging the second core particle 302_i.

[0095] In the embodiments of the present disclosure, each core particle in the chip can be connected through at least one core particle interconnection interface, and the at least one core particle interconnection interface can realize the interaction of debugging information between core particles with communication connection, expand the way of obtaining debugging information, and improve the transmission reliability of debugging information, so as to reduce or even eliminate the impact of single point failure. In addition, the chip in the present disclosure no longer uses the "JTAG daisy chain" to avoid signal integrity problems, does not require additional dedicated debugging path wiring, can reduce the complexity and cost of wiring, and can theoretically support any number and any topology of core particle interconnection and debugging, including high scalability. Moreover, the chiplet architecture chip in the present disclosure can only encapsulate a set of external interfaces, through which any chiplet of the chiplet architecture chip can be connected, and the core particle interconnection interface between each chiplet can realize the interaction of debugging information between adjacent chiplets, thereby realizing the debugging of all chiplets.

[0096] It should be noted that the concepts or implementations involved in the third aspect that are the same as those in the first aspect or the second aspect can be found in the description of the first aspect or the second aspect, and will not be repeated in the third aspect.

[0097] In some embodiments, the method also includes: receiving the first tuning information from the first core particle 301 through the selection module of each second core particle 302_i and sending the first tuning information to the processing module of the second core particle 302_i; executing through the processing module of each second core particle 302_i: when it is determined that the first tuning information is tuning information for tuning the second core particle 302_i, forwarding the first tuning information within the second core particle 302_i for tuning the second core particle.

[0098] In some embodiments, the method further includes: executing, through the processing module 301_4 of the first core particle 301: when it is determined that the first tuning information is tuning information for tuning the third core particle 303, sending the first tuning information to the inter-core interconnection interface corresponding to the second core particle 302_i connected to the third core particle 301 among one or more inter-core interconnection interfaces 301_1_1~301_1_N of the first core particle 301; executing, through the processing module of the second core particle 302_i connected to the third core particle 303: when it is determined that the first tuning information is tuning information for tuning the third core particle 303, sending the first tuning information to the inter-core interconnection interface corresponding to the third core particle 303 of the second core particle 302_i, so as to send the first tuning information to the third core particle 303 for tuning the third core particle 303.

[0099] In some embodiments, the method further includes: executing, by the processing module 301_4 of the first coregrain 301, when it is determined that the first debugging information is debugging information for debugging the fourth coregrain 304, sending the first debugging information to the coregrain interconnection interface corresponding to the second coregrain 302_i connected to the fifth coregrain 305 among the one or more coregrain interconnection interfaces 301_1_1~301_1_N of the first coregrain 301; executing, by the processing module of the second coregrain 302_i connected to the fifth coregrain 305, when it is determined that the first debugging information is debugging information for debugging the fourth coregrain 304, sending the first debugging information to the coregrain interconnection interface corresponding to the fifth coregrain 305 of the second coregrain 302_i; port to send the first tuning information to the fifth core particle 305; receive the first tuning information from the second core particle 302_i through the selection module of the fifth core particle 305 and send the first tuning information to the processing module of the fifth core particle 305; execute through the processing module of the fifth core particle 305: when it is determined that the first tuning information is the tuning information for tuning the fifth core particle 305, forward the first tuning information within the fifth core particle 305 for tuning the fifth core particle 305; when it is determined that the first tuning information is for tuning the fourth core particle 304, send the first tuning information to the core particle interconnection interface corresponding to the fourth core particle 304, so as to send the first tuning information to the fourth core particle 304 for tuning the fourth core particle 304.

[0100] In some embodiments, the method further includes: executing, by the processing module 301_4 of the first core particle 301: when it is determined that the first debugging information is debugging information for debugging a second core particle 302_i among one or more second core particles 302_1~302_N, determining, according to the configuration information, an inter-core interconnection interface corresponding to the second core particle 302_i among one or more inter-core interconnection interfaces 301_1_1~301_1_N of the first core particle 301, and sending the first debugging information to the inter-core interconnection interface corresponding to the second core particle 302_i among one or more inter-core interconnection interfaces 301_1_1~301_1_N of the first core particle 301, wherein the configuration information includes connection relationship information between the first core particle 301 and the one or more second core particles 302_1~302_N and / or information generated based on the connection relationship information.

[0101] In the embodiments of the present disclosure, the application of chiplet architecture in baseband chips and CPU chips covers a wide range of scenarios from wireless communication devices (such as base stations, terminal devices, etc.), Internet of Things devices, wireless access points to data centers, high-performance computing, enterprise-level applications and edge computing. Through modular and independently optimized design, chips using chiplet architecture meet the requirements of high performance, low power consumption, flexible expansion and high reliability, and provide strong technical support for modern communication and computing devices. For example, it can be applied to high-performance computing and data center scenarios. When applied to servers and supercomputing nodes, by independently designing different modules of multi-chip architecture (such as multi-core processing, memory controller and I / O interface, etc.), chips using chiplet architecture can provide excellent computing power and data processing capabilities in high-performance computing and data centers. The chip debugging method provided by the present disclosure can ensure the collaborative work of each core particle in a complex system, support flexible resource expansion, and improve overall performance and reliability; when applied to cloud computing and virtualization nodes, chips using chiplet architecture can achieve higher computing density and efficiency, can assist in detecting and optimizing various functional modules, and ensure the efficient operation of virtualization technology. For another example, it can be applied to mobile communication scenarios. When applied to wireless communication devices, the baseband chip needs to process complex communication protocols, such as 4G, 5G, Wi-Fi, and Bluetooth. The chip and chip debugging method provided by the present disclosure can assist the chip using the chiplet architecture to allow the processing modules of different communication standards (such as modems, RF front ends, and protocol processors) to be independently optimized and upgraded, providing efficient and low-power communication capabilities. For another example, it can be applied to the Internet of Things (IoT) and edge computing scenarios. When applied to smart cities and industrial Internet of Things, chips using chiplet architecture can be used for data collection and edge computing. Through the chip debugging method, the accuracy and efficiency of each data processing module can be guaranteed; when applied to home Internet of Things devices, the chip and chip debugging method can assist in ensuring the normal operation of various functions of smart home devices (such as smart door locks and surveillance cameras).

[0102] In order to enable those skilled in the art to more clearly understand the technical solutions provided by the embodiments of the present disclosure, the technical solutions provided by the embodiments of the present disclosure are further described below through specific embodiments:

[0103] Refer to the attached Figure 5, is a schematic diagram of the structure of another core particle provided by an embodiment of the present disclosure. In this embodiment, the core particle is chiplet0, the external interface is a JTAG interface, the conversion module is a debug transport module (DTM), the selection module is a MUX, the interconnection interface between core particles is a plurality of sets of bidirectional D2D high-speed interconnection interfaces, the processing module is a DMI interconnection (DMI Interconect, DMI_IC), the bus is a DMI line, and each module can realize the following functions:

[0104] A JTAG interface, used for receiving first debugging information from an external debugging device;

[0105] The DTM is connected to the MUX via a DMI line, and the DTM is used to receive first debugging information from an external debugging device via a JTAG interface, and convert the first debugging information into a format suitable for transmission via the DMI line;

[0106] Multiple sets of bidirectional D2D high-speed interconnection interfaces (abbreviated as D2D in the figure) are connected to MUX and DMI_IC through DMI lines, and the multiple sets of bidirectional D2D high-speed interconnection interfaces are used to receive multiple second debugging information from multiple other chiplets (such as adjacent chiplets of chiplet0) through DMI lines;

[0107] The MUX is configured to receive at least one of the first debugging information after format conversion from the DTM and the second debugging information from the plurality of groups of bidirectional D2D high-speed interconnection interfaces, and send the at least one debugging information to the DMI_IC, Figure 5 In the example, at least one commissioning information is commissioning information received from a DTM;

[0108] DMI_IC is configured to, when it is determined that the tuning information received from MUX is the tuning information for tuning chiplet0 (i.e., the current chiplet), forward the tuning information received from MUX within chiplet0 for tuning chiplet0; when it is determined that the tuning information received from MUX is the tuning information for tuning other chiplets, send the tuning information received from MUX to the bidirectional D2D high-speed interconnection interface corresponding to the other chiplets, so as to send the tuning information to the corresponding other chiplets through the bidirectional D2D high-speed interconnection interface, so that the other chiplets can be tuned based on the tuning information received through the bidirectional D2D high-speed interconnection interface.

[0109] Refer to the attached Figure 6 , is a schematic diagram of the structure of another chip provided in an embodiment of the present disclosure, Figure 6 The chip includes two chiplets. Figure 6The two chiplets are chiplet0 and chiplet1. Each chiplet has the same structure as Figure 5 The chiplet structure is the same, and the components and functions of each component are the same, which will not be repeated here. The differences are described below.

[0110] In this embodiment, based on Figure 6 The chip shown can implement the following chip debugging methods:

[0111] S61: receiving first debugging information from an external debugging device through a JTAG interface located at chiplet0;

[0112] S62: converting, through the DTM of chiplet0, first debugging information received from the external debugging device through the JTAG interface into debugging information suitable for transmission through the DMI line;

[0113] S63: Receive the debug information after format conversion from DTM through the MUX of chiplet0, and send the debug information to the DMI_IC of chiplet0;

[0114] S64a: when it is determined through DMI_IC that the debugging information received from MUX is debugging information for debugging chiplet0 (ie, the current chiplet), the debugging information received from MUX is forwarded in chiplet0 for debugging chiplet0;

[0115] S64b: When it is determined that the debugging information received from the MUX is the debugging information for debugging chiplet1, the debugging information received from the MUX is sent to the bidirectional D2D high-speed interconnection interface corresponding to chiplet1, so as to send the debugging information to the corresponding chiplet1 through the bidirectional D2D high-speed interconnection interface; the MUX of chiplet1 is configured to select the debugging information output through DMI1 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet0) as the debugging information of chiplet1 (see the bold line), so that chiplet1 is debugged based on the debugging information received through DMI1.

[0116] Refer to the attached Figure 7 , is a schematic diagram of the structure of another chip provided in an embodiment of the present disclosure, Figure 7 The chip includes four chiplets. Figure 7 The four chiplets are chiplet0, chiplet1, chiplet2 and chiplet3. The structure of each chiplet is similar to Figure 5The chiplet structures are the same, and the components and functions of the components are the same, which will not be repeated here. The differences are described below.

[0117] In this embodiment, based on Figure 7 The chip shown can implement the following chip debugging methods:

[0118] S71: receiving debugging information from an external debugging device through a JTAG interface located at chiplet0;

[0119] S72: converting, through the DTM of chiplet0, first debugging information received from the external debugging device through the JTAG interface into debugging information suitable for transmission through the DMI line;

[0120] S73: Receive the debug information after format conversion from DTM through the MUX of chiplet0, and send the debug information to the DMI_IC of chiplet0;

[0121] S74a: when it is determined through DMI_IC that the debugging information received from MUX is the debugging information for debugging chiplet0 (ie, the current chiplet), the debugging information received from MUX is forwarded in chiplet0 for debugging chiplet0;

[0122] S74b: when it is determined that the debugging information received from the MUX is the debugging information for debugging chiplet1, the debugging information received from the MUX is sent to the bidirectional D2D high-speed interconnection interface corresponding to chiplet1, so as to send the debugging information to the corresponding chiplet1 through the bidirectional D2D high-speed interconnection interface, and configure the MUX of chiplet1 to select the debugging information output through DMI1 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet0) as the debugging information of chiplet1 (see the bold line), so that chiplet1 is debugged based on the debugging information received through DMI1;

[0123] S74c: when it is determined that the debugging information received from the MUX is the debugging information for debugging chiplet2, the debugging information received from the MUX is sent to the bidirectional D2D high-speed interconnection interface corresponding to chiplet2, so as to send the debugging information to the corresponding chiplet2 through the bidirectional D2D high-speed interconnection interface, and configure the MUX of chiplet2 to select the debugging information output through DMI0 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet0) as the debugging information of chiplet2 (see the bold line), so that chiplet2 is debugged based on the debugging information received through DMI0;

[0124] S74d: When it is determined that the debugging information received from the MUX is the debugging information for debugging chiplet3, the debugging information received from the MUX is sent to the bidirectional D2D high-speed interconnection interface corresponding to chiplet1 or chiplet2 connected to chiplet3, so as to send the debugging information to the corresponding chiplet3 through the bidirectional D2D high-speed interconnection interface, and configure the MUX of chiplet3 to select the debugging information output through DMI0 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet1) or DMI1 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet2) as the debugging information of chiplet3 (see the bold line), so that chiplet3 is debugged based on the debugging information received through DMI0 or DMI1.

[0125] Refer to the attached Figure 8 , is a schematic diagram of the structure of another chip provided in an embodiment of the present disclosure, Figure 8 The chip includes six chiplets. Figure 8 The six chips are chiplet0, chiplet1, chiplet2, chiplet3, chiplet4 and chiplet5. Each chiplet has a similar structure to Figure 5 The chiplet structure is the same, and the components and functions of each component are the same, which will not be repeated here. The differences are described below.

[0126] In this embodiment, based on Figure 8 The chip shown can implement the following chip debugging methods:

[0127] S81: receiving debugging information from an external debugging device through a JTAG interface located at chiplet0;

[0128] S82: converting, through the DTM of chiplet0, first debugging information received from the external debugging device through the JTAG interface into debugging information suitable for transmission through the DMI line;

[0129] S83: Receive the debug information after format conversion from DTM through the MUX of chiplet0, and send the debug information to the DMI_IC of chiplet0;

[0130] S84a: when it is determined through DMI_IC that the debugging information received from MUX is the debugging information for debugging chiplet0 (ie, the current chiplet), the debugging information received from MUX is forwarded in chiplet0 for debugging chiplet0;

[0131] S84b: when it is determined that the debugging information received from the MUX is the debugging information for debugging chiplet1, the debugging information received from the MUX is sent to the bidirectional D2D high-speed interconnection interface corresponding to chiplet1, so as to send the debugging information to the corresponding chiplet1 through the bidirectional D2D high-speed interconnection interface, and configure the MUX of chiplet1 to select the debugging information output through DMI1 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet0) as the debugging information of chiplet1 (see the bold line), so that chiplet1 performs debugging based on the debugging information received through DMI1;

[0132] S84c: when it is determined that the debugging information received from the MUX is the debugging information for debugging chiplet3, the debugging information received from the MUX is sent to the bidirectional D2D high-speed interconnection interface corresponding to chiplet3, so as to send the debugging information to the corresponding chiplet3 through the bidirectional D2D high-speed interconnection interface, and configure the MUX of chiplet3 to select the debugging information output through DMI0 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet0) as the debugging information of chiplet3 (see the bold line), so that chiplet3 is debugged based on the debugging information received through DMI0;

[0133] S84d: When it is determined that the debugging information received from the MUX is the debugging information for debugging chiplet2, the debugging information received from the MUX is sent to the bidirectional D2D high-speed interconnection interface corresponding to chiplet1 connected to chiplet2, so that the debugging information is sent to the corresponding chiplet2 through the bidirectional D2D high-speed interconnection interface, and the MUX of chiplet2 is configured to select the debugging information output through DMI1 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet1) as the debugging information of chiplet2 (see the bold line), so that chiplet2 performs debugging based on the debugging information received through DMI1. It should be noted that when there is a fault in the chiplet0-chiplet1-chiplet2 path, the debugging information can also be transmitted to chiplet2 through the chiplet0-chiplet3-chiplet4-chiplet5-chiplet2 path. The transmission method of the debugging information is similar to the transmission method through the chiplet0-chiplet1-chiplet2 path, which will not be repeated here.

[0134] S84e: When it is determined that the debugging information received from the MUX is the debugging information for debugging chiplet4, the debugging information received from the MUX is sent to the bidirectional D2D high-speed interconnection interface corresponding to chiplet1 or chiplet3 connected to chiplet4, so as to send the debugging information to the corresponding chiplet4 through the bidirectional D2D high-speed interconnection interface, and configure the MUX of chiplet4 to select the debugging information output through DMI0 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet1) or DMI1 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet3) as the debugging information of chiplet4 (see the bold line), so that chiplet4 is debugged based on the debugging information received through DMI0 or DMI1.

[0135] S84f: When it is determined that the debugging information received from the MUX is the debugging information for debugging chiplet5, the debugging information received from the MUX is sent to the chiplet-to-chip interconnection interface corresponding to chiplet2 connected to chiplet5 or chiplet1 or chiplet3 connected to chiplet4, so as to send the debugging information to the corresponding chiplet5 through the bidirectional D2D high-speed interconnection interface, and configure the MUX of chiplet5 to select the debugging information output through DMI0 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet2) or DMI1 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet4) as the debugging information of chiplet5 (see the bold line), so that chiplet5 is debugged based on the debugging information received through DMI0 or DMI1.

[0136] Through the above embodiments, the external JTAG interface can be connected to any chiplet included in the chip, so as to achieve debugging access to all chiplets, and adjacent chiplets are interconnected through the D2D module. When the D2D module between any two chiplets is blocked, debugging can still be initiated through another interconnected chiplet. For example, if the D2D module between chiplet0 and chiplet1 is blocked, chiplet3 can be debugged through the D2D module from chiplet1 to chiplet3. In this way, the reliability of the debugging path is greatly improved, thereby reducing or even eliminating the impact of single-point failures on chip debugging. Through the chip and chip debugging method provided by the present disclosure, debugging information can be transmitted step by step between multiple chiplets, and the debugging of chips using chiplet architecture with any number and any topology can be realized.

[0137] In a fourth aspect, an embodiment of the present disclosure further provides a computer-readable medium having a computer program stored thereon, and when the computer program is executed by a processor, the third aspect and any possible embodiment of the third aspect are implemented.

[0138] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the apparatus disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0139] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may include multiple functions, or one function or step may be performed by several physical components in cooperation.

[0140] Some or all physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only compact disk (CD-ROM), digital versatile disk (DVD) or other optical disk storage; magnetic cassettes, tapes, disk storage or other magnetic storage; any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0141] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A coreparticle, comprising at least one coreparticle interconnection interface for connecting to at least one other coreparticle to communicate with the at least one other coreparticle, a selection module connected to the at least one coreparticle interconnection interface, and a processing module connected to the selection module, wherein: The at least one inter-chiplet interconnection interface is used to receive second debugging information from the at least one other chiplet; The selection module is configured to receive at least one piece of second debugging information from the at least one inter-chip interconnection interface, and send the at least one piece of debugging information to the processing module; The processing module is configured to, when it is determined that the at least one debugging information is debugging information for debugging the current core particle, forward the at least one debugging information within the current core particle for debugging the current core particle, and when it is determined that the at least one debugging information is debugging information for debugging the at least one other core particle, send the at least one debugging information to the at least one inter-core interconnection interface, so as to send the at least one debugging information to the corresponding at least one other core particle through the at least one inter-core interconnection interface; The core particle further includes an external interface for connecting to an external debugging device, and the selection module is connected to the external interface, wherein: The external interface is used to receive the first debugging information from the external debugging device; The selection module is configured to receive at least one of the second debugging information from the at least one inter-chip interconnection interface and the first debugging information from the external interface, and send the at least one debugging information to the processing module.

2. The core particle according to claim 1, wherein The selection module, the at least one inter-chip interconnection interface and the processing module are all connected to each other via a bus.

3. The core particle according to claim 2, wherein The core particle further includes a conversion module, the selection module is connected to the external interface via the conversion module, and the conversion module is connected to the selection module via the bus; The conversion module is configured to receive the first debugging information from the external interface, convert the first debugging information into a format suitable for transmission through the bus, and send the converted first debugging information to the selection module through the bus.

4. The core particle according to claim 1, wherein The selection module includes at least one second port for receiving the second debugging information, wherein each of the second ports corresponds to one of the other core particles, each of the other core particles is connected to one or more core particle interconnection interfaces among the at least one core particle interconnection interface of the core particle, and the one or more core particle interconnection interfaces are connected to the second port corresponding to each of the other core particles, for sending the second debugging information from the corresponding other core particles to the corresponding second port.

5. The core particle according to claim 1, wherein The processing module is configured to determine, based on configuration information, an inter-core interconnection interface among the at least one inter-core interconnection interface of the present core particle corresponding to the target core particle when it is determined that the at least one debugging information is debugging information for debugging a target core particle among the at least one other core particles, and send the at least one debugging information to the corresponding inter-core interconnection interface, wherein the configuration information includes connection relationship information between the present core particle and the at least one other core particle and / or information generated based on the connection relationship information.

6. The core particle according to claim 1, wherein Each of the inter-chiplet interconnection interfaces is connected to corresponding other chiplets, and each of the inter-chiplet interconnection interfaces includes at least two bidirectional transmission interface units; Each of the bidirectional transmission interface units is used to receive the second debugging information from the corresponding other corelet, and is also used to transmit the at least one debugging information to the corresponding other corelet.

7. The core particle according to claim 1, wherein The external interface is any one of a JTAG interface, a USB interface, an Ethernet interface, a SPI interface or a UART interface.

8. The core particle according to claim 1, wherein The debugging information includes debugging data and / or debugging instructions.

9. The core particle according to claim 2, wherein: The bus is a debugging module interface DMI line.

10. A chip, comprising a first core particle and one or more second core particles, wherein: The first core-grain comprises one or more core-grain interconnection interfaces corresponding to each second core-grain, each second core-grain comprises a respective core-grain interconnection interface, and the core-grain interconnection interface of each second core-grain is connected to the corresponding core-grain interconnection interface of the first core-grain for communication between the first core-grain and each second core-grain; The chip includes an external interface located on the first core particle, and the external interface is used to connect to an external debugging device to receive first debugging information from the external debugging device; The first core also includes a selection module and a processing module, wherein: The selection module of the first core is connected to the external interface and is configured to receive the first debugging information and send the first debugging information to the processing module of the first core; The processing module of the first core is connected to the selection module of the first core and the one or more core interconnection interfaces of the first core, and is configured to, when it is determined that the first tuning information is tuning information for tuning the first core, forward the first tuning information within the first core for tuning the first core, and, when it is determined that the first tuning information is tuning information for tuning a second core among the one or more second cores, send the first tuning information to the core interconnection interface corresponding to the second core among the one or more core interconnection interfaces of the first core, so as to send the first tuning information to the second core for tuning the second core; Each second core particle further includes a selection module and a processing module, wherein: The selection module of each second core is connected to the core interconnection interface of the second core and is configured to receive the first debugging information from the first core and send the first debugging information to the processing module of the second core; The processing module of each second core particle is connected to the selection module of the second core particle and the core particle interconnection interface of the second core particle, and is configured to forward the first tuning information within the second core particle for tuning the second core particle when it is determined that the first tuning information is tuning information for tuning the second core particle.

11. The chip according to claim 10, wherein: The selection module of the first core particle, one or more core particle interconnection interfaces of the first core particle, and the processing module of the first core particle are connected to each other through a bus; the selection module of the second core particle and the core particle interconnection interface of the second core particle are connected to each other through a bus; the one or more core particle interconnection interfaces of the first core particle and the core particle interconnection interface of the second core particle are connected to each other through a bus.

12. The chip according to claim 11, wherein: The first core particle also includes a conversion module, and the selection module of the first core particle is connected to the external interface via the conversion module. The conversion module is connected to the selection module of the first core particle through the bus. The conversion module is configured to receive the first adjustment information received from the external interface, convert the first adjustment information into a format suitable for transmission through the bus, and send the converted first adjustment information to the selection module of the first core particle through the bus.

13. The chip according to claim 10, wherein: The selection module of the first core particle further comprises one or more second ports connected to the one or more inter-core particle interconnection interfaces of the first core particle, and the one or more second ports are configured to be in a disabled state.

14. The chip according to claim 10, wherein: Each second core particle also includes one or more core particle interconnection interfaces connected to other core particles except the first core particle, and the selection module of each second core particle also includes one or more second ports connected to one or more core particle interconnection interfaces of other core particles except the first core particle, and the one or more second ports of the selection module of each second core particle are configured to be in a disabled state.

15. The chip according to claim 10, wherein: The chip further includes a third chiplet, the third chiplet including an inter-chiplet interconnection interface, which is used to connect to a corresponding inter-chiplet interconnection interface of a second chiplet to communicate with the second chiplet, wherein: The processing module of the first core is further configured to send the first debugging information to the core interconnection interface corresponding to the second core connected to the third core among the one or more core interconnection interfaces of the first core, if it is determined that the first debugging information is debugging information for debugging the third core; The processing module of the second core particle connected to the third core particle is also configured to send the first tuning information to the inter-core interconnection interface of the second core particle corresponding to the third core particle when it is determined that the first tuning information is tuning information for tuning the third core particle, so as to send the first tuning information to the third core particle for tuning the third core particle.

16. The chip according to claim 10, wherein: The chip further includes a fourth core-grain and a fifth core-grain, the fourth core-grain includes an inter-core interconnection interface, the fifth core-grain includes an inter-core interconnection interface connected to the second core-grain and an inter-core interconnection interface connected to the fourth core-grain, the inter-core interconnection interface of the fourth core-grain is connected to a corresponding inter-core interconnection interface of a second core-grain via the inter-core interconnection interface of the fifth core-grain to communicate with the second core-grain, wherein: The processing module of the first coregear is further configured to, when determining that the first debugging information is debugging information for debugging the fourth coregear, send the first debugging information to the coregear interconnection interface corresponding to the second coregear connected to the fifth coregear among the one or more coregear interconnection interfaces of the first coregear; The processing module of the second core-grain connected to the fifth core-grain is further configured to send the first debugging information to the core-grain interconnection interface of the second core-grain corresponding to the fifth core-grain when determining that the first debugging information is debugging information for debugging the fourth core-grain, so as to send the first debugging information to the fifth core-grain; The fifth core also includes a selection module and a processing module, wherein: The selection module of the fifth chiplet is connected to the inter-chiplet interconnection interface of the fifth chiplet and is configured to receive the first debugging information from the second chiplet and send the first debugging information to the processing module of the fifth chiplet; The processing module of the fifth core particle is connected to the selection module of the fifth core particle and the core particle interconnection interface of the fifth core particle, and is configured to forward the first tuning information within the fifth core particle for tuning the fifth core particle when it is determined that the first tuning information is tuning information for tuning the fifth core particle, and to send the first tuning information to the core particle interconnection interface corresponding to the fourth core particle when it is determined that the first tuning information is for tuning the fourth core particle, so as to send the first tuning information to the fourth core particle for tuning the fourth core particle.

17. The chip according to claim 10, wherein: The processing module of the first core particle is configured to determine the core particle interconnection interface corresponding to the second core particle among the one or more core particle interconnection interfaces of the first core particle according to the configuration information when it is determined that the first debugging information is debugging information for debugging a second core particle among the one or more second core particles, and send the first debugging information to the core particle interconnection interface corresponding to the second core particle among the one or more core particle interconnection interfaces of the first core particle, wherein the configuration information includes connection relationship information between the first core particle and the one or more second core particles and / or information generated based on the connection relationship information.

18. A chip debugging method, for debugging the chip according to any one of claims 10 to 17, the method comprising: Receiving first debugging information from an external debugging device through an external interface of the chip located on the first core; receiving the first debugging information from the external interface through the selection module of the first core particle and sending the first debugging information to the processing module of the first core particle; The processing module of the first core is used to perform: when it is determined that the first debugging information is debugging information for debugging the first core, the first debugging information is forwarded in the first core for debugging the first core, and when it is determined that the first debugging information is debugging information for debugging a second core among the one or more second cores, the first debugging information is sent to the one or more inter-core interconnection interfaces of the first core corresponding to the second core, so as to send the first debugging information to the second core for debugging the second core; receiving the first debugging information from the first core particle through the selection module of each second core particle and sending the first debugging information to the processing module of the second core particle; The processing module of each second core is used to execute: when it is determined that the first tuning information is the tuning information for tuning the second core, the first tuning information is forwarded in the second core for tuning the second core.

19. The method according to claim 18, wherein: The method further comprises: The first debugging information received from the external interface is received by the conversion module of the first core particle, the first debugging information is converted into a format suitable for transmission through a bus, and the converted first debugging information is sent to the selection module of the first core particle through the bus.

20. The method according to claim 18, wherein: The method further comprises: The processing module of the first core is executed: when it is determined that the first debugging information is debugging information for debugging the third core, the first debugging information is sent to the core interconnection interface corresponding to the second core connected to the third core among the one or more core interconnection interfaces of the first core; Executed by a processing module of a second core particle connected to a third core particle: when it is determined that the first tuning information is tuning information for tuning the third core particle, the first tuning information is sent to the core particle interconnection interface of the second core particle corresponding to the third core particle, so as to send the first tuning information to the third core particle for tuning the third core particle.

21. The method according to claim 18, wherein: The method further comprises: When it is determined that the first debugging information is debugging information for debugging the fourth coregear, the processing module of the first coregear sends the first debugging information to the coregear interconnection interface corresponding to the second coregear connected to the fifth coregear among the one or more coregear interconnection interfaces of the first coregear; When determining that the first debugging information is debugging information for debugging the fourth core particle, the processing module of the second core particle connected to the fifth core particle sends the first debugging information to the core particle interconnection interface of the second core particle corresponding to the fifth core particle, so as to send the first debugging information to the fifth core particle; receiving the first debugging information from the second chiplet through the selection module of the fifth chiplet and sending the first debugging information to the processing module of the fifth chiplet; Executed through the processing module of the fifth core particle: when it is determined that the first tuning information is tuning information for tuning the fifth core particle, the first tuning information is forwarded within the fifth core particle for tuning the fifth core particle; when it is determined that the first tuning information is for tuning the fourth core particle, the first tuning information is sent to the inter-core interconnection interface corresponding to the fourth core particle, so as to send the first tuning information to the fourth core particle for tuning the fourth core particle.

22. The method according to claim 18, wherein: The method further comprises: Executed by the processing module of the first core particle: in the case of determining that the first debugging information is debugging information of a second core particle among the one or more second core particles, determining the core particle interconnection interface corresponding to the second core particle among the one or more core particle interconnection interfaces of the first core particle according to the configuration information, and sending the first debugging information to the core particle interconnection interface corresponding to the second core particle among the one or more core particle interconnection interfaces of the first core particle, the configuration information includes connection relationship information between the first core particle and the one or more second core particles and / or information generated based on the connection relationship information.

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