Scan driving circuit, gate driving circuit and display panel

Abstract

The application relates to a scan driving circuit, a gate driving circuit and a display panel. The scan driving circuit is characterized by comprising: a driving module for generating a primary scan signal; a gate-on module connected with the driving module, for receiving a first power signal and a second power signal, and generating a gate scan signal according to the first power signal and the second power signal in response to a reset scan signal, the primary scan signal and a node signal of a preset node of the driving module; wherein if the level of the reset scan signal is a first level, the level of the gate scan signal is the same as that of the primary scan signal, and if the level of the reset scan signal is a second level, the level of the gate scan signal is different from that of the primary scan signal; thus, the structure of the scan driving circuit is simplified, and the frame of the display panel is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a scanning drive circuit, a gate drive circuit, and a display panel. Background Technology

[0002] OLED (Organic Light Emitting Diode) display panels typically consist of horizontal and vertical arrays of pixels. During the display process, a scan driving circuit outputs a scan signal to scan and access each pixel line by line; that is, the scan driving circuit is configured to generate the gate scan voltage for each pixel. GOA (GateOn Array) scan driving circuits are a technology that integrates the scan driving circuitry onto the TFT (Thin Film Transistor) array substrate. Each GOA unit acts as a scan driving circuit, sequentially transmitting the scan signal to the next GOA unit, activating the TFTs line by line, and completing the data writing for each pixel. Currently, when OLED display panels have segmented frequency display capabilities, the corresponding scan driving circuits in related technologies suffer from overly complex structures. Summary of the Invention

[0003] Therefore, it is necessary to provide a scan driving circuit, a gate driving circuit, and a display panel to solve the technical problem that the structure of the scan driving circuit in the related art is too complex.

[0004] In a first aspect, embodiments of this application provide a scan driving circuit, including: a driving module for generating a primary scan signal;

[0005] A gating module, connected to the driving module, is used to receive a first power signal and a second power signal, and in response to a reset scan signal, the primary scan signal, and a node signal of a preset node of the driving module, to generate a gate scan signal based on the first power signal and the second power signal; wherein,

[0006] If the level of the reset scan signal is a first level, the level of the gate scan signal is the same as the level of the primary scan signal; if the level of the reset scan signal is a second level, the level of the gate scan signal is different from the level of the primary scan signal.

[0007] In one embodiment, the gating module includes:

[0008] A first control unit is configured to receive the first power signal and the second power signal, and in response to the reset scan signal and the primary scan signal, generate a strobe node signal;

[0009] A first output unit is configured to receive the first power signal and the second power signal, and in response to the strobe node signal and the node signal of the preset node, generate the gate scan signal based on the first power signal and the second power signal.

[0010] In one embodiment, the first control unit includes:

[0011] A first transistor, wherein a first terminal of the first transistor is used to receive the first power signal, and a control terminal of the first transistor is connected to the output terminal of the drive module, and the control terminal of the first transistor is used to receive the primary scan signal;

[0012] The second transistor has a first terminal connected to the second terminal of the first transistor, the second terminal of the second transistor is used to receive the second power supply signal, and the control terminal of the second transistor is used to receive the reset scan signal.

[0013] A first capacitor, wherein a first terminal of the first capacitor is connected to a first terminal of the first transistor, and a second terminal of the first capacitor is connected to a second terminal of the first transistor, the second terminal of the first capacitor being used to output the gating node signal; wherein...

[0014] The gating node signal is the voltage signal of the common node connecting the first terminal of the second transistor and the second terminal of the first transistor.

[0015] In one embodiment, the first transistor is turned off under the action of the primary scan signal, and the second transistor is turned on under the action of the reset scan signal having the first level;

[0016] Alternatively, the first transistor is turned on by the primary scan signal, and the second transistor is turned off by the reset scan signal having the second level.

[0017] In one embodiment, the first output unit includes:

[0018] The third transistor has a first terminal for receiving the first power signal and a control terminal for receiving the gating node signal.

[0019] A fourth transistor, the first terminal of which is connected to the second terminal of the third transistor, the first terminal of which is used to output the gate scan signal, the second terminal of which is used to receive the second power supply signal, the control terminal of which is connected to a preset node of the driving module, and the control terminal of which is used to receive the node signal of the preset node.

[0020] In one embodiment, the third transistor is turned off under the action of the gating node signal, and the fourth transistor is turned on in response to the node signal of the preset node;

[0021] Alternatively, the third transistor may be turned on by the gating node signal, and the fourth transistor may be turned off in response to the node signal of the preset node.

[0022] In one embodiment, the transistors included in the gating module are all of P-type conductivity; the first level is low level and the second level is high level.

[0023] In one embodiment, the driving module includes:

[0024] The second control unit is connected to both the first node and the second node of the drive module, and is used to receive input signals, the first power signal and the second power signal, and respond to a clock signal to control the signals of the first node and the second node.

[0025] The second output unit, connected to both the first node and the second node, is configured to receive the first power signal and the second power signal, and in response to the signals from the first node and the second node, generate the primary scan signal based on the first power signal and the second power signal; wherein...

[0026] The signal of the second node is the node signal of the preset node, and the signal of the second node is used to control the second output unit to output a primary scan signal with a first level.

[0027] Secondly, embodiments of this application also provide a gate driving circuit, including: at least two cascaded scan driving circuits as described in the first aspect.

[0028] Thirdly, embodiments of this application also provide a display panel, including the gate driving circuit as described in the second aspect.

[0029] In one embodiment, the display panel includes a first display mode and a second display mode;

[0030] In each display frame of the first display mode, during the gate reset phase, the level of the reset scan signal received by each of the gating modules in the gate drive circuit is either a first level or a second level.

[0031] In each display frame of the second display mode, during the gate reset phase, the level of the reset scan signal received by at least one of the gating modules in the gate drive circuit is the first level, and the level of the reset scan signal received by at least one of the gating modules is the second level.

[0032] In one embodiment, the display panel further includes: at least two cascaded reset circuits and a plurality of pixel circuits;

[0033] Each of the reset circuits is connected to the gating module of the scan driving circuit and the target pixel circuit at the same level, respectively, to provide the reset scan signal to the scan driving circuit and the target pixel circuit respectively; wherein, the target pixel circuit is the pixel circuit connected to the scan driving circuit.

[0034] The scan driving circuit, gate driving circuit, and display panel provided in this application embodiment respond to the reset scan signal, the node signal of the preset node of the driving module, and the primary scan signal generated by the driving module through a gating module. Thus, the gating module can generate a gate scan signal (hereinafter referred to as a scan signal) based on the first power supply signal and the second power supply signal. If the level of the reset scan signal is the first level, the level of the gate scan signal is the same as the level of the primary scan signal; if the level of the reset scan signal is the second level, the level of the gate scan signal is different from the level of the primary scan signal. In this way, the gate scan signal is output along with the reset scan signal. The gating module of the scan driving circuit in this application embodiment only needs to introduce one... The reset scan signal can output a gate scan signal that is the same as or different from the primary scan signal. This reset scan signal can be a multiplexing of an existing scan signal in the display panel, such as a multiplexing of the scan signal of the initialization module in the pixel circuit of the display panel. The initialization module may include an initialization transistor. The embodiments of this application thus simplify the structure of the gating module, thereby simplifying the structure of the scan driving circuit. The simplification of the structure of the scan driving circuit helps to reduce the occupancy of the scan driving circuit on the display panel bezel, thereby helping to reduce the bezel of the display device including the display panel, that is, to achieve a narrow bezel of the display device. The simplification of the structure of the scan driving circuit also helps to reduce the cost of the scan driving circuit, thereby reducing the cost of the display panel. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0036] Figure 2 This is one of the structural schematic diagrams of a scanning drive circuit provided in an embodiment of this application;

[0037] Figure 3This is a second schematic diagram of a scanning drive circuit provided in an embodiment of this application;

[0038] Figure 4 This is one of the structural schematic diagrams of a gating module provided in an embodiment of this application;

[0039] Figure 5 This is a second schematic diagram of the structure of a gating module provided in an embodiment of this application;

[0040] Figure 6 This is a schematic diagram of the structure of a driver module provided in an embodiment of this application;

[0041] Figure 7 This is a top view schematic diagram of a display device provided in an embodiment of this application.

[0042] Reference numerals: 100-gate drive circuit, 110-drive module, 120-gating module, 121-first control unit, 122-first output unit, 200-display device. Detailed Implementation

[0043] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0045] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.

[0046] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0047] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0048] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0049] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0050] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0051] The gate scan signal S2N_OUT generated by the scan driving circuit 100 provided in this embodiment can be provided to the pixel circuit of the display panel. The display panel can be, but is not limited to, an OLED display panel, an LCD display panel, etc., and the pixel circuit can be, but is not limited to, a 7T1C pixel circuit, an 8T1C pixel circuit, etc. Figure 1 The diagram illustrates one type of 7T1C pixel circuit, which includes a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, a storage capacitor Cst, a first initialization transistor T5, a second light-emitting control transistor T6, and a second initialization transistor T7.

[0052] In this configuration, the first terminal of the first light-emitting control transistor T1 is connected to a power supply signal PVDD, and the second terminal is connected to the first terminal of the driving transistor T3; the second terminal of the driving transistor T3 is connected to the first terminal of the second light-emitting control transistor T6; the second terminal of the second light-emitting control transistor T6 is connected to the anode of the organic light-emitting diode; the cathode of the organic light-emitting diode is connected to another power supply signal PVEE; and the control terminals of the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are both connected to a light-emitting control signal EM.

[0053] The first terminal of the data writing transistor T2 is connected to the data signal VDATA, and the second terminal is connected to the first terminal of the driving transistor T3. The control terminal is connected to the first scan signal Scan. The first terminal of the threshold compensation transistor T4 is connected to the second terminal of the driving transistor T3, and the second terminal is connected to the control terminal of the driving transistor T3. The control terminal is connected to the second scan signal S2N. The first terminal of the storage capacitor Cst is connected to the power supply signal PVDD, and the second terminal is connected to the control terminal of the driving transistor T3. The first terminal of the first initialization transistor T5 is connected to the first initialization signal VREF1, and the second terminal is connected to the first terminal of the threshold compensation transistor T4. The control terminal is connected to the third scan signal SP. The first terminal of the second initialization transistor T7 is connected to the second initialization signal VREF2, and the second terminal is connected to the anode of the organic light-emitting diode. The control terminal is connected to the fourth scan signal SP*.

[0054] This application does not limit the type of transistors in the pixel circuit; they can be either N-type or P-type. For example, the threshold compensation transistor T4 is N-type, and the first initialization transistor T5 is P-type.

[0055] In one exemplary embodiment, reference is made to Figure 2 A scan driving circuit 100 is provided, which includes a driving module 110 and a gating module 120. The driving module 110 is used to generate a primary scan signal Next. The gating module 120 is connected to the driving module 110 and is used to receive a first power signal VGH and a second power signal VGL. In response to a reset scan signal SP_OUT, the primary scan signal Next, and a node signal Signal of a preset node of the driving module 110, the gating module generates a gate scan signal S2N_OUT based on the first power signal VGH and the second power signal VGL. If the level of the reset scan signal SP_OUT is a first level, the level of the gate scan signal S2N_OUT is the same as the level of the primary scan signal Next. If the level of the reset scan signal SP_OUT is a second level, the level of the gate scan signal S2N_OUT is different from the level of the primary scan signal Next.

[0056] It should be noted that in the display panel of the related technology, since the shift register directly provides the primary scan signal Next to the pixel circuit, the frequency of the primary scan signal Next received by each area of ​​the display panel is the same, which makes it impossible to realize the segmented frequency display of the display panel.

[0057] In this embodiment, the driving module 110 is, for example, a shift register, and the node signal Signal of the preset node of the driving module 110 is, for example, a signal on a preset node inside the shift register. The level of the node signal Signal of the preset node can be the same as the level of the primary scan signal Next. The gate driving circuit also includes a gating module 120, which is connected to the driving module 110 in a one-to-one correspondence. The gating module 120 can control the frequency of the gate scan signal S2N_OUT according to the reset scan signal SP_OUT, so that the frequency of the gate scan signal S2N_OUT can be less than or equal to that of the primary scan signal. The refresh frequency of each area in the display panel is the same when the frequency of the gate scan signal S2N_OUT of each gating module 120 in the display panel is equal to the frequency of the primary scan signal Next. The display panel performs normal display when the frequency of the gate scan signal S2N_OUT of some gating modules 120 in the display panel is equal to the frequency of the primary scan signal Next and the frequency of the gate scan signal S2N_OUT of some gating modules 120 is less than the frequency of the primary scan signal Next. The display panel can achieve different refresh frequencies in different areas, that is, the display panel can perform segmented frequency display.

[0058] Combination Figure 2 and Figure 1 The gate scan signal S2N_OUT can be the second scan signal S2N, used to control the turn-on and turn-off of the threshold compensation transistor T4; the reset scan signal SP_OUT can be a multiplexed third scan signal SP.

[0059] When both the first initialization transistor T5 and the threshold compensation transistor T4 are turned on, the first initialization signal VREF1 is written to the control terminal of the driving transistor T3 through the first initialization transistor T5 and the threshold compensation transistor T4 in sequence, thereby initializing the control terminal of the driving transistor T3; when the first initialization transistor T5 is turned off, the first initialization signal VREF1 does not initialize the control terminal of the driving transistor T3.

[0060] When the first initialization transistor T5 is turned off, and both the threshold compensation transistor T4 and the data writing transistor T2 are turned on, the data signal VDATA is sequentially written to the control terminal of the driving transistor T3 through the data writing transistor T2, the driving transistor T3, and the threshold compensation transistor T4, thus realizing the data writing to the control terminal of the driving transistor T3. The storage capacitor Cst can store the data signal VDATA written to the control terminal of the driving transistor T3. When the threshold compensation transistor T4 is turned off, the data signal VDATA will not be written to the control terminal of the driving transistor T3.

[0061] Specifically, when the first initialization signal VREF1 initializes the control terminal of the driving transistor T3 and the data signal VDATA is written to the control terminal of the driving transistor T3, it indicates that the data at the control terminal of the driving transistor T3 is refreshed, which is reflected in the refresh of the display grayscale of the organic light-emitting diode connected (indirectly connected) to the driving transistor T3; when the first initialization signal VREF1 does not initialize the control terminal of the driving transistor T3 and the data signal VDATA is not written to the control terminal of the driving transistor T3, it indicates that the data at the control terminal of the driving transistor T3 is not refreshed, which is reflected in the absence of a refresh of the display grayscale of the organic light-emitting diode connected (indirectly connected) to the driving transistor T3, and the current display grayscale may be maintained.

[0062] Based on this, in this embodiment, when the level of the primary scan signal Next is high, if the level of the reset scan signal SP_OUT is a first level, then the level of the gate scan signal S2N_OUT is the same as the level of the primary scan signal Next, i.e., high. If the level of the reset scan signal SP_OUT is a second level, then the level of the gate scan signal S2N_OUT is different from the level of the primary scan signal Next, i.e., low. Thus, the primary scan signal Next generated by the driving module 110, after the response of the gating module 120 to the reset scan signal SP_OUT, the gating module 120 can output a gate scan signal S2N_OUT that is the same as the primary scan signal Next or a gate scan signal S2N_OUT that is different from the primary scan signal Next. Providing the gate scan signal S2N_OUT that is the same as the primary scan signal Next and the gate scan signal S2N_OUT that is different from the primary scan signal Next to the threshold compensation transistors T4 of the pixel circuits in different areas of the display panel respectively, can realize the segmented frequency display of the display panel.

[0063] In this embodiment, the gating module 120 of the scan driving circuit 100 only needs to introduce a reset scan signal SP_OUT to output a gate scan signal S2N_OUT that is the same as or different from the primary scan signal Next. Furthermore, the reset scan signal SP_OUT can be a multiplexing of an existing scan signal in the display panel, such as a multiplexing of the third scan signal SP. This simplifies the structure of the gating module 120, thereby simplifying the structure of the scan driving circuit 100. The simplification of the scan driving circuit 100's structure helps reduce its footprint on the display panel bezel, thus reducing the bezel of the display device including the display panel, achieving a narrow bezel. The simplification of the scan driving circuit 100's structure also helps reduce its cost, thereby reducing the cost of the display panel. Since the reset scan signal SP_OUT is a multiplexing of an existing scan signal in the display panel, it saves the cost of providing the reset scan signal SP_OUT and simplifies the structure of the scan driving circuit 100, thus reducing the cost of the scan driving circuit 100.

[0064] In one exemplary embodiment, reference is made to Figure 3 The gating module 120 includes a first control unit 121 and a first output unit 122. The first control unit 121 receives a first power supply signal VGH and a second power supply signal VGL, and generates a gating node signal in response to a reset scan signal SP_OUT and a primary scan signal Next. The first output unit 122 receives the first power supply signal VGH and the second power supply signal VGL, and generates a gate scan signal S2N_OUT in response to the gating node signal and a preset node signal Signal from the driving module 110, based on the first power supply signal VGH and the second power supply signal VGL.

[0065] The node signal Signal of the preset node can have the same level as the primary scan signal Next. When the primary scan signal Next is high, if the reset scan signal SP_OUT is at the first level, the level of the strobe node signal is the level of the second power supply signal VGL, and the level of the gate scan signal S2N_OUT is the same as the primary scan signal Next, also high. When the primary scan signal Next is low, if the reset scan signal SP_OUT is at the second level, the level of the strobe node signal is the level of the first power supply signal VGH, and the level of the gate scan signal S2N_OUT is the same as the primary scan signal Next, also low. Here, the first power supply signal VGH is high, and the second power supply signal VGL is low.

[0066] In this embodiment, the gating module 120 of the scan driving circuit 100 only includes the first control unit 121 and the first output unit 122, which further simplifies the structure of the gating module 120, thereby further simplifying the structure of the scan driving circuit 100, further reducing the display panel bezel, and further reducing the cost of the display panel.

[0067] In one exemplary embodiment, reference is made to Figure 4 The first control unit 121 includes a first transistor T10, a second transistor T20, and a second capacitor C10. The first terminal of the first transistor T10 receives a first power supply signal VGH, and its control terminal is connected to the output terminal of the drive module 110. The control terminal of the first transistor T10 also receives a primary scan signal Next. The first terminal of the second transistor T20 is connected to the second terminal of the first transistor T10, and its second terminal receives a second power supply signal VGL. The control terminal of the second transistor T20 also receives a reset scan signal SP_OUT. The gating node signal is the voltage signal of the common node connecting the first terminal of the second transistor T20 and the second terminal of the first transistor T10. The first terminal of the second capacitor C10 is connected to the first terminal of the first transistor T10, and its second terminal is also connected to the second terminal of the first transistor T10. The second terminal of the second capacitor C10 outputs the gating node signal.

[0068] In this embodiment, the first control unit 121 includes only the first transistor T10, the second transistor T20, and the second capacitor C10, which simplifies the structure of the first control unit 121 and further simplifies the structure of the gating module 120, thereby further simplifying the structure of the scanning drive circuit 100, further reducing the display panel bezel, and further reducing the cost of the display panel.

[0069] In one exemplary embodiment, the first transistor T10 is turned off by the primary scan signal Next, and the second transistor T20 is turned on by the reset scan signal SP_OUT with a first level; or, the first transistor T10 is turned on by the primary scan signal Next, and the second transistor T20 is turned off by the reset scan signal SP_OUT with a second level.

[0070] Specifically, when the primary scan signal Next is high, the first transistor T10 is off, the reset scan signal SP_OUT is at the first level, and the second transistor T20 is on. The level of the selected node signal is the level of the second power supply signal VGL, and the level of the gate scan signal S2N_OUT is the same as the level of the primary scan signal Next, which is also high. When the primary scan signal Next is low, the first transistor T10 is on, the reset scan signal SP_OUT is at the second level, and the second transistor T20 is off. The level of the selected node signal is the level of the first power supply signal VGH, and the level of the gate scan signal S2N_OUT is the same as the level of the primary scan signal Next, which is also low. In this case, the level of the first power supply signal VGH is high, and the level of the second power supply signal VGL is low.

[0071] In one exemplary embodiment, reference is made to Figure 5 The first output unit 122 includes a third transistor T30 and a fourth transistor T40. The first terminal of the third transistor T30 receives a first power supply signal VGH, and the control terminal of the third transistor T30 receives a gate selection signal. The first terminal of the fourth transistor T40 is connected to the second terminal of the third transistor T30, and the first terminal of the fourth transistor T40 outputs a gate scan signal S2N_OUT. The second terminal of the fourth transistor T40 receives a second power supply signal VGL. The control terminal of the fourth transistor T40 is connected to a preset node of the drive module 110, and the control terminal of the fourth transistor T40 receives a node signal Signal from the preset node.

[0072] In this embodiment, the first output unit 122 includes only the third transistor T30 and the fourth transistor T40, which simplifies the structure of the first output unit 122 and further simplifies the structure of the gating module 120, thereby further simplifying the structure of the scanning drive circuit 100, further reducing the display panel bezel, and further reducing the cost of the display panel.

[0073] In one exemplary embodiment, the third transistor T30 is turned off by the gating node signal, and the fourth transistor T40 is turned on in response to the node signal Signal of the preset node; or, the third transistor T30 is turned on by the gating node signal, and the fourth transistor T40 is turned off in response to the node signal Signal of the preset node.

[0074] Specifically, when the primary scan signal Next is high, the first transistor T10 is turned off, the node signal Signal of the preset node of the driving module 110 is the same as the primary scan signal Next, which is also high; the fourth transistor T40 is turned off, the reset scan signal SP_OUT is at the first level; the second transistor T20 is turned on, then the level of the selected node signal is the level of the second power supply signal VGL; the third transistor T30 is turned on, and the level of the gate scan signal S2N_OUT is the same as the level of the primary scan signal Next, which is also high; when the primary scan signal Next is low... When the circuit is flat, the first transistor T10 is turned on, and the node signal Signal of the preset node of the driving module 110 is the same as the primary scan signal Next, which is also low. The fourth transistor T40 is turned on, and the level of the reset scan signal SP_OUT is the second level. When the second transistor T20 is turned off, the level of the selected node signal is the level of the first power supply signal VGH. When the third transistor T30 is turned off, the level of the gate scan signal S2N_OUT is the same as the level of the primary scan signal Next, which is also low. Among them, the level of the first power supply signal VGH is high, and the level of the second power supply signal VGL is low.

[0075] In an exemplary embodiment, the transistors included in the gating module 120 are all P-type transistors; the first level is a low level and the second level is a high level.

[0076] In this embodiment, all transistors in the gating module 120 are P-type. Compared with N-type transistors, P-type transistors have higher reliability, which makes the gating module 120 more reliable, the manufacturing process of the gating module 120 simpler, the structure of the gating module 120 simpler, and the bezel of the display panel narrower.

[0077] In an exemplary embodiment, the drive module 110 includes a second control unit and a second output unit. The second control unit is connected to both the first node and the second node of the drive module 110, and is used to receive an input signal, a first power signal VGH, and a second power signal VGL, and in response to a clock signal, to control the signals of the first node and the second node. The second output unit is connected to both the first node and the second node, and is used to receive the first power signal VGH and the second power signal VGL, and in response to the signals of the first node and the second node, to generate a primary scan signal Next based on the first power signal VGH and the second power signal VGL; wherein the signal of the second node is a node signal Signal of a preset node, and the signal of the second node is used to control the second output unit to output a primary scan signal Next having a first level.

[0078] In one exemplary embodiment, reference is made to Figure 6 The second control unit includes transistors M1, M2, M3, M4, M5, M6, M7, M8, M11, M12, M13, M14, M15, M16, capacitors C1, C2, and C3.

[0079] In one exemplary embodiment, reference continues to... Figure 6 The second output unit includes transistor M9 and transistor M10. The connection node between the control terminal of transistor M10 and the first terminal of transistor M16 serves as the preset node of the drive module 110. The second terminal of transistor M16 is connected to the control terminal of transistor M16.

[0080] Based on the same concept, embodiments of this application also provide a gate driving circuit, which includes at least two cascaded scan driving circuits 100 as provided in any of the above embodiments.

[0081] The scan driving circuit 100 and the gate driving circuit provided in the embodiments of this application belong to the same inventive concept, can solve the same technical problem, and thus achieve the same technical effect. Repeated content will not be repeated here.

[0082] Based on the same concept, this application also provides a display panel that includes the gate driving circuit provided in any of the above embodiments.

[0083] The display panel and gate driving circuit provided in the embodiments of this application belong to the same inventive concept, can solve the same technical problems, and thus achieve the same technical effects. Repeated content will not be repeated here.

[0084] In one exemplary embodiment, the display panel includes a first display mode and a second display mode;

[0085] In each display frame of the first display mode, the reset scan signal SP_OUT received by each gating module 120 in the gate drive circuit is either at the first level or at the second level. Thus, the frequency of the gate scan signal S2N_OUT of each gating module 120 in the display panel is equal to the frequency of the primary scan signal Next. The refresh frequency of each area in the display panel is the same, and the display panel performs normal display.

[0086] In each display frame of the second display mode, the reset scan signal SP_OUT received by at least one gating module 120 in all gate drive circuits is at the first level and the reset scan signal SP_OUT received by at least one gating module 120 is at the second level; thus, the frequency of the gate scan signal S2N_OUT of some gating modules 120 in the display panel is equal to the frequency of the primary scan signal Next, and the frequency of the gate scan signal S2N_OUT of some gating modules 120 is less than the frequency of the primary scan signal Next. The display panel can achieve different refresh frequencies in different areas, that is, the display panel can perform zoned frequency display.

[0087] In one exemplary embodiment, the display panel further includes at least two cascaded reset circuits and a plurality of pixel circuits, wherein the reset circuits may serve as a first reset circuit.

[0088] Each first reset circuit is connected to the gating module 120 of the same level scan drive circuit 100 and the target pixel circuit, respectively, and is used to provide a reset scan signal SP_OUT to the scan drive circuit 100 and the target pixel circuit respectively. Here, the reset scan signal SP_OUT provided to the target pixel circuit can be a third scan signal SP. In other words, the first reset circuit provides a reset scan signal SP_OUT to both the scan drive circuit 100 and the target pixel circuit at the same time. The reset scan signal SP_OUT provided to the target pixel circuit is actually a third scan signal SP provided to the control terminal of the first initialization transistor T5 in the target pixel circuit. The target pixel circuit is a pixel circuit connected to the scan drive circuit 100.

[0089] In one exemplary embodiment, the display panel further includes at least two cascaded second reset circuits, each second reset circuit being used to provide a fourth scan signal SP* to the second initialization transistor T7 in the connected target pixel circuit.

[0090] In one exemplary embodiment, the display panel further includes at least two cascaded light-emitting control circuits, each light-emitting control circuit being used to provide a light-emitting control signal EM to a first light-emitting control transistor T1 and a second light-emitting control transistor T6 in a connected pixel circuit.

[0091] In one exemplary embodiment, the display panel further includes a plurality of scanning circuits, each scanning circuit being configured to provide a first scan signal Scan to the data writing transistor T2 in the connected pixel circuit.

[0092] Based on the same concept, this application also provides a display device. Figure 7 This is a schematic diagram of the structure of the display device 200 provided in the embodiments of this application, as shown below. Figure 7As shown, the display device 200 includes the display panel in any of the above embodiments. Therefore, the display device 200 also has the beneficial effects of the display panel in the above embodiments. The similarities can be understood by referring to the explanation of the display panel above, and will not be repeated below.

[0093] The display device 200 provided in this application embodiment can be a mobile phone or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, industrial control equipment, medical display screen, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0094] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A scan driving circuit, characterized by comprising: include: The driver module is used to generate the primary scan signal; A gating module, connected to the driving module, is used to receive a first power signal and a second power signal, and in response to a reset scan signal, the primary scan signal, and a node signal of a preset node of the driving module, to generate a gate scan signal based on the first power signal and the second power signal; wherein, If the level of the reset scan signal is a first level, the level of the gate scan signal is the same as the level of the primary scan signal; if the level of the reset scan signal is a second level, the level of the gate scan signal is different from the level of the primary scan signal.

2. The scan driving circuit according to claim 1, wherein The gating module includes: A first control unit is configured to receive the first power signal and the second power signal, and in response to the reset scan signal and the primary scan signal, generate a strobe node signal; A first output unit is configured to receive the first power signal and the second power signal, and in response to the strobe node signal and the node signal of the preset node, generate the gate scan signal based on the first power signal and the second power signal.

3. The scan driving circuit according to claim 2, wherein The first control unit includes: A first transistor, wherein a first terminal of the first transistor is used to receive the first power signal, and a control terminal of the first transistor is connected to the output terminal of the drive module, and the control terminal of the first transistor is used to receive the primary scan signal; The second transistor has a first terminal connected to the second terminal of the first transistor, the second terminal of the second transistor is used to receive the second power supply signal, and the control terminal of the second transistor is used to receive the reset scan signal. A first capacitor, wherein a first terminal of the first capacitor is connected to a first terminal of the first transistor, and a second terminal of the first capacitor is connected to a second terminal of the first transistor, the second terminal of the first capacitor being used to output the gating node signal; wherein... The gating node signal is the voltage signal of the common node connecting the first terminal of the second transistor and the second terminal of the first transistor.

4. The scan driving circuit according to claim 3, wherein The first transistor is turned off under the action of the primary scan signal, and the second transistor is turned on under the action of the reset scan signal having the first level; Alternatively, the first transistor is turned on by the primary scan signal, and the second transistor is turned off by the reset scan signal having the second level.

5. The scan driving circuit according to claim 2, wherein The first output unit includes: The third transistor has a first terminal for receiving the first power signal and a control terminal for receiving the gating node signal. A fourth transistor, the first terminal of which is connected to the second terminal of the third transistor, the first terminal of which is used to output the gate scan signal, the second terminal of which is used to receive the second power supply signal, the control terminal of which is connected to a preset node of the driving module, and the control terminal of which is used to receive the node signal of the preset node.

6. The scan driving circuit according to claim 5, wherein The third transistor is turned off under the action of the gate node signal, and the fourth transistor is turned on in response to the action of the node signal of the preset node. Or, the third transistor is turned on under the action of the gate node signal, and the fourth transistor is turned off in response to the action of the node signal of the preset node.

7. The scan driving circuit according to claim 3 or 4, wherein The conductivity type of each transistor included in the gate module is P-type; the first level is a low level, and the second level is a high level.

8. The scan driving circuit according to claim 1, wherein The driving module includes: A second control unit connected to the first node and the second node of the driving module, configured to receive an input signal, the first power signal and the second power signal, and in response to a clock signal, to control the signal of the first node and the signal of the second node; A second output unit connected to the first node and the second node, configured to receive the first power signal and the second power signal, and in response to the signal of the first node and the signal of the second node, to generate the primary scan signal according to the first power signal and the second power signal; wherein, The signal of the second node is the node signal of the preset node, and the signal of the second node is used to control the second output unit to output a primary scan signal with a first level.

9. A gate drive circuit, characterized by It includes: At least two cascaded scan driving circuits as claimed in any one of claims 1-8.

10. A display panel, characterized by, It includes: The gate driving circuit as claimed in claim 9.

11. The display panel of claim 10, wherein, The display panel includes a first display mode and a second display mode; In each display frame in the first display mode, the level of the reset scan signal received by each gate module in each gate driving circuit is either the first level or the second level; In each display frame in the second display mode, the level of the reset scan signal received by at least one gate module in each gate driving circuit is the first level, and the level of the reset scan signal received by at least one gate module is the second level.

12. The display panel of claim 10, wherein, It also includes: At least two cascaded reset circuits and a plurality of pixel circuits; Each reset circuit is respectively connected to a gate module of a scan driving circuit of the same level and a target pixel circuit, and is configured to provide the reset scan signal for the scan driving circuit and the target pixel circuit, respectively; wherein the target pixel circuit is the pixel circuit connected to the scan driving circuit.

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