Storage structure

Abstract

The present application relates to a storage structure comprising a plurality of read transistor units, each comprising a plurality of read transistors arranged in a first arrangement, each comprising a conductive pillar extending in a first direction; and a plurality of write transistor units, each comprising a plurality of write transistors arranged in a second arrangement, each comprising a semiconductor pillar extending in the same direction as the conductive pillar. The conductive pillars within the same read transistor unit are connected to the semiconductor pillar in a different manner, and the semiconductor pillars within the same write transistor unit are connected to the conductive pillar in a different manner. This application can effectively increase storage cell density.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a storage structure. Background Art

[0002] With the development of semiconductor technology, people have higher and higher requirements for memory cell density. However, in traditional DRAM with a one-transistor-one-capacitor (1T1C) cell architecture, the capacitor occupies a large area, thus limiting the improvement of memory cell density.

[0003] In DRAMs with a two-transistor-capacitor-less (2T0C) cell architecture, the parasitic capacitance of the read transistor can be used as a storage element, eliminating the need for a capacitor within the memory cell. Therefore, this 2T0C cell architecture is expected to overcome the key limitation of conventional 1T1C cell architecture DRAMs in increasing memory cell density.

[0004] However, in the current DRAM storage structure based on the 2T0C cell architecture, the storage cell density still needs to be improved. Summary of the Invention

[0005] Based on this, an embodiment of the present application provides a storage structure to improve the density of storage cells.

[0006] A storage structure comprising:

[0007] a plurality of read transistor units, each of the read transistor units including a plurality of read transistors arranged in a first arrangement, each of the read transistors including a conductive pillar extending along a first direction;

[0008] a plurality of write transistor units, each of which includes a plurality of write transistors arranged in a second arrangement, each of which includes a semiconductor column, and each of which has the same extension direction as the conductive column;

[0009] The conductive pillars in the same read transistor unit are connected to the semiconductor pillar in a different manner, and the semiconductor pillars in the same write transistor unit are connected to the conductive pillar in a different manner.

[0010] In one embodiment, one of the first arrangement and the second arrangement is used as a target arrangement.

[0011] The storage structure also includes:

[0012] a plurality of transfer units, each of which is located between the read transistor unit and the write transistor unit in the first direction, and includes a plurality of transfer structures arranged in a target arrangement, the transfer structures connecting the conductive pillars and the semiconductor pillars,

[0013] Among the read transistor and the write transistor, one arranged according to the target arrangement is used as the target transistor, and the other is used as the non-target transistor. In the same switching unit, each switching structure is connected to the non-target transistor in a different way and connected to the target transistor in the same way.

[0014] In one embodiment, between the first arrangement and the second arrangement, the one with a smaller number of transistors contained in a single transistor unit is used as the target arrangement.

[0015] In one embodiment, the first arrangement is a hexagonal arrangement, and the second arrangement is a tetragonal arrangement.

[0016] In one embodiment, the square arrangement is used as the target arrangement, and the transfer structures in the same row contact the corresponding conductive pillars through the same side.

[0017] In one embodiment, the switching structures located in adjacent rows contact the corresponding conductive pillars through opposite sides.

[0018] In one embodiment, the write transistor is located above the read transistor, one end of the transfer structure contacts the upper surface of the conductive pillar, and the other end of the transfer structure contacts the lower surface of the semiconductor pillar.

[0019] In one embodiment, the read transistor is used as the target transistor, and the transfer structure is coaxially arranged with the semiconductor column.

[0020] In one embodiment, on a projection plane perpendicular to the first direction, the orthographic projection of the transfer structure is located within the orthographic projection of the semiconductor column.

[0021] In one embodiment, on a projection plane perpendicular to the first direction, the orthographic projection of the transfer structure is a square, the orthographic projection of the semiconductor column is a circle, and the circle is a circumscribed circle of the square.

[0022] In one embodiment, the write word line of the write transistor and the read word line of the read transistor extend in the same direction, and the write bit line of the write transistor and the read bit line of the read transistor extend in different directions.

[0023] In one embodiment, the channel material of the read transistor and / or the write transistor is an oxide semiconductor.

[0024] In the above-mentioned memory structure, the read transistor unit includes a plurality of read transistors arranged in a first arrangement, and the write transistor unit includes a plurality of write transistors arranged in a second arrangement. The conductive pillars within the same read transistor unit are connected to the semiconductor pillars in a non-identical manner, and the semiconductor pillars within the same write transistor unit are connected to the conductive pillars in a non-identical manner.

[0025] In the storage structure of the embodiment of the present application, the read transistors 100 arranged in different ways can be connected to the write transistors correspondingly to form a plurality of closely arranged memory cells with a 2T0C architecture, thereby effectively improving the density of the memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 A schematic top view of a storage structure provided in one embodiment;

[0028] Figure 2 is a schematic cross-sectional structural diagram of a storage unit provided in one embodiment;

[0029] Figure 3 A schematic diagram of the three-dimensional structure of a storage structure provided in one embodiment;

[0030] Figure 4 is a schematic cross-sectional structural diagram of a storage unit provided in another embodiment;

[0031] Figures 5a to 5c A schematic diagram of a top view of a structure obtained during the preparation of a storage structure in one embodiment is shown;

[0032] Figures 6a to 6c A schematic diagram of the three-dimensional structure of a structure obtained during the preparation of a storage structure in an embodiment is shown.

[0033] Description of reference numerals:

[0034] 100a-read transistor unit, 100-read transistor, 110-conductive pillar, 120-read gate dielectric layer, 130-read channel layer, 140-first electrode, 150-second electrode, 200a-write transistor unit, 210-semiconductor pillar, 211-source region, 212-drain region, 213-channel region, 220-gate dielectric layer, 230-gate layer, 300a-transfer unit, 300-transfer structure, 400-read word line, 500-read bit line, 600-write word line, 700-write bit line, 800-bit line contact structure, 910-first dielectric layer, 920-second dielectric layer, 930-third dielectric layer, 940-fourth dielectric layer, 950-fifth dielectric layer, 960-sixth dielectric layer. DETAILED DESCRIPTION

[0035] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0037] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there can be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0038] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0039] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] In one embodiment, see Figure 1 , provides a storage structure including a read transistor unit 100a and a write transistor unit 200a. In the same storage structure, the number of the read transistor unit 100a and the write transistor unit 200a can be multiple, and the number of the read transistor unit 100a and the number of the write transistor unit 200a can be different.

[0041] The read transistor unit 100a includes a plurality of read transistors 100. The plurality of read transistors 100 in the read transistor unit 100a are arranged in a first arrangement. The number of read transistors 100 in each read transistor unit 100a is the same, and the read transistors 100 in each read transistor unit 100a are arranged in the same first arrangement.

[0042] See also Figure 2 The read transistor 100 includes a conductive pillar 110. The conductive pillar 110 may serve as a gate of the read transistor 100 and may extend along a first direction. The material of the conductive pillar 110 may include, but is not limited to, metal materials such as Co, Ni, Ti, W, Cu, and Al. For example, the material of the conductive pillar 110 may also be doped polysilicon.

[0043] In addition, the read transistor 100 may further include a read gate dielectric layer 120 , a read channel layer 130 , a first electrode 140 and a second electrode 150 .

[0044] The read gate dielectric layer 120 is located between the conductive pillars 110 and the read channel layer 130. The read gate dielectric layer 120 can be formed of a material with a high-k dielectric constant. For example, materials for the read gate dielectric layer 120 include aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3). The material of the read gate dielectric layer 120 is not limited.

[0045] One of the first electrode 140 and the second electrode 150 serves as a source electrode, and the other serves as a drain electrode. The first electrode 140 and / or the second electrode 150 may be made of a metal material including, but not limited to, Co, Ni, Ti, W, Cu, Al, or the like. In the extension direction of the read channel layer 130, the first electrode 140 and the second electrode 150 are spaced apart and disposed opposite each other, and both are connected to the read channel layer 130, thereby forming a conductive channel within the read channel layer 130 between the first electrode 140 and the second electrode 150.

[0046] The channel material of the read transistor 100 (ie, the material of the read channel layer 130 ) may include, but is not limited to, an oxide semiconductor. For example, the material of the read channel layer 130 may include Indium Gallium Zinc Oxide (IGZO).

[0047] As an example, the read transistor 100 may be a Channel-All-Around (CAA) transistor.

[0048] At this time, the read gate dielectric layer 120 surrounds the conductive pillar 110 , the read channel layer 130 surrounds the read gate dielectric layer 120 , and the first electrode 140 and the second electrode 150 both surround the read channel layer 130 .

[0049] Also, see Figure 1 or Figure 3 The second electrodes 150 of the plurality of read transistors 100 are connected to form a read word line 400. The read word line 400 extends along a second direction. The first electrodes 140 of the plurality of read transistors 100 are connected to form a read bit line 500. The read bit line 500 extends along a third direction. The third direction intersects the second direction, and both directions may be perpendicular to the first direction.

[0050] See also Figure 1 , the write transistor unit 200a includes a plurality of write transistors 200. In order to make the figure clearer, Figure 1 The relevant structure of the write transistor 200 is made transparent.

[0051] The number of write transistors 200 in a single write transistor unit 200 a is different from the number of read transistors 100 in a single read transistor unit 100 a .

[0052] The plurality of write transistors 200 in the write transistor unit 200a are arranged in the second arrangement. The number of write transistors 200 in each write transistor unit 200a is the same, and each write transistor 200 in each write transistor unit 200a is arranged in the same second arrangement.

[0053] See also Figure 2 The write transistor 200 includes a semiconductor pillar 210. The channel material of the write transistor 200 (ie, the material of the semiconductor pillar 21) may include, but is not limited to, an oxide semiconductor. For example, the material of the semiconductor pillar 21 may include indium gallium zinc oxide (IGZO).

[0054] The semiconductor pillar 210 may also extend along the first direction, thereby having the same extension direction as the conductive pillar 110. The two ends of the semiconductor pillar 210 may be doped to form a source region 211 and a drain region 212 of the write transistor 200, respectively. The semiconductor pillar 210 between the source region 211 and the drain region 212 may serve as a channel region 213.

[0055] In addition, the write transistor 200 may further include a write gate dielectric layer 220 and a write gate layer 230 . The write gate dielectric layer 220 is located between the write gate layer 230 and the semiconductor pillar 210 .

[0056] The material of the write gate dielectric layer 220 can also be formed of a material with a high-k dielectric constant. For example, the material of the read gate dielectric layer 120 includes aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3). The material of the write gate dielectric layer 220 can be the same as or different from the material of the read gate dielectric layer 120.

[0057] The material of the write gate layer 230 may include, but is not limited to, any one or more of titanium nitride (TiN), titanium (Ti), tungsten silicide (Si2W), and tungsten (W).

[0058] As an example, the write transistor unit 200 a may be a Gate-All-Around (GAA) transistor.

[0059] At this time, the write gate dielectric layer 220 surrounds the semiconductor pillar 210 , and the write gate layer 230 surrounds the write gate dielectric layer 220 .

[0060] See also Figure 1 or Figure 3 , the gate layers 230 of the plurality of write transistors 200 are connected to form a write word line 600. The write word line 600 may extend along a fourth direction. The fourth direction may be perpendicular to the first direction. At the same time, one end of the semiconductor pillar 210 away from the read transistor 100 may be doped to form one of the source region 211 or the drain region 212, which may be connected to the write bit line 700. For example, see Figure 4 The end of the semiconductor pillar 210 away from the read transistor 100 is overdoped to form a source region 211. The source region 211 can be connected to the write bit line 700 through the bit line contact structure 800. Of course, please refer to Figure 2 , the source region 211 can also be directly connected to the write bit line 700. Figure 1 The write bit line 700 may extend along a fifth direction, which intersects the fourth extending direction and may be perpendicular to the first direction.

[0061] Also, see Figure 1 The fourth direction can be set to be the same as the second direction, and the fifth direction can be set to be different from the third direction. That is, the write word line 600 and the read word line 400 extend in the same direction, and the write bit line 700 and the read bit line 500 extend in different directions, thereby facilitating the arrangement of the read transistor 100 and the write transistor 200 in the first arrangement and the second arrangement, respectively.

[0062] Each conductive pillar 110 in the same read transistor unit 100 a is connected to the semiconductor pillar 210 in a non-identical manner, and each semiconductor pillar 210 in the same write transistor unit 200 a is connected to the conductive pillar 110 in a non-identical manner.

[0063] It will be understood that “not completely the same” may mean completely different or partially different.

[0064] Therefore, in the storage structure of this embodiment, the read transistors 100 and the write transistors 200 arranged in different ways can be connected correspondingly to form a plurality of closely arranged memory cells with a 2TOC architecture, thereby effectively improving the density of the memory cells.

[0065] In one embodiment, one of the first arrangement and the second arrangement is used as the target arrangement.

[0066] The storage structure further includes a plurality of switching units 300a. The switching units 300a are located between the read transistor unit 100a and the write transistor unit 200a in the first direction. Furthermore, the switching units 300a include a plurality of switching structures 300 arranged in a target arrangement. Figure 2 , the transfer structure 300 connects the conductive pillar 110 and the semiconductor pillar 210, thereby connecting the read transistor 100 and the write transistor 200. At this point, the memory cell includes the read transistor 100, the write transistor 200, and the transfer structure 300 connecting the two. During the memory structure fabrication process, the read transistor 100, the transfer structure 300, and the write transistor 200 can be fabricated sequentially.

[0067] As an example, Figures 5a to 5c A schematic diagram of the top view of the structure obtained during the preparation of the storage structure is shown.

[0068] As another example, Figures 6a to 6c FIG2 shows a schematic diagram of a three-dimensional structure of a storage structure obtained during the preparation process of another example. In this case, the second arrangement of the write transistor 200 is used as the target arrangement. Figure 5b or Figure 6b The adapter unit 300a includes a plurality of adapter structures 300 arranged according to a target arrangement (a second arrangement).

[0069] As an example, the transfer structure 300 may include a polysilicon layer and a metal layer. The polysilicon layer may be located between the metal layer and the semiconductor pillar 210 , and the metal layer may be located between the polysilicon layer and the conductive pillar 110 , thereby effectively reducing the contact resistance between the conductive pillar 110 and the semiconductor pillar 210 .

[0070] Furthermore, one of the read transistor 100 and the write transistor 200 arranged in the target arrangement is used as the target transistor, and the other is used as the non-target transistor. In the same adapter unit 300a, each adapter structure 300 is connected to the non-target transistor in a different manner and connected to the target transistor in the same manner.

[0071] At this time, in the same switching unit 300a, each switching structure 300 can be connected to transistors with the same arrangement (read transistor 100 or write transistor 200) in the same way; at the same time, the switching structure 300 can be connected to transistors with different arrangements (write transistor 200 or read transistor 100) in a non-completely identical way.

[0072] In this embodiment, a transfer unit 300a is provided between the read transistor unit 100a and the write transistor unit 200a. A transfer structure 300 is formed between the metal conductive pillar 110 and the semiconductor pillar 210, so that the transfer structure 300 can effectively reduce the contact resistance between the two, thereby forming a good contact between the two.

[0073] At the same time, one of the arrangement of the read transistor 100 (first arrangement) and the arrangement of the write transistor 200 (second arrangement) is selected as the arrangement of the adapter structure 300 in the adapter unit 300a, so that the adapter structure 300 can be more easily connected to the conductive column 110 or the semiconductor column 210 in the same way.

[0074] In some examples, the shape and size of the transfer structure 300 may not be restricted by the semiconductor pillars 210 and the conductive pillars 110, thereby facilitating a good connection between the corresponding conductive pillars 110 and the semiconductor pillars 210. Furthermore, actual manufacturing processes often have process variations. In this case, the provision of the transfer structure 300 further facilitates a reliable connection between the conductive pillars 110 and the semiconductor pillars 210.

[0075] In one embodiment, between the first arrangement and the second arrangement, the one with a smaller number of transistors contained in a single transistor unit is used as the target arrangement.

[0076] In the first arrangement, the number of read transistors 100 included in a single read transistor unit 100a is set to n1. Meanwhile, in the second arrangement, the number of write transistors included in a write transistor unit 200a is set to n2.

[0077] When n1 is smaller than n2, the first arrangement is used as the target arrangement. When n1 is larger than n2, the second arrangement is used as the target arrangement.

[0078] When n1 is less than n2 and the first arrangement is used as the target arrangement, the read transistor 100 is used as the target transistor and the write transistor 200 is used as the non-target transistor. In the same adapter unit 300a, each adapter structure 300 is connected to the semiconductor pillar 210 of the write transistor 200 in a different manner, and is connected to the conductive pillar 110 of the read transistor 100 in the same manner.

[0079] When n1 is greater than n2 and the second arrangement is used as the target arrangement, the read transistor 100 is used as the non-target transistor and the write transistor 200 is used as the target transistor. In the same adapter unit 300a, each adapter structure 300 is connected to the conductive pillar 110 of the read transistor 100 in a different manner and is connected to the semiconductor pillar 210 of the write transistor 200 in the same manner.

[0080] At this time, when n1 is less than n2, the number of switching structures 300 in a single switching unit 300a is the same as the number of read transistors 100 in a single read transistor unit 100a. When n1 is greater than n2, the number of switching structures 300 in a single switching unit 300a is the same as the number of write transistors 200 in a single write transistor unit 200a.

[0081] When the number of transistors in a single transistor cell is considered the cell density, the number of transfer structures 300 in a single transfer cell 300a is equal to the number of transistors in a transistor cell with a lower cell density (read transistor cell 100a or write transistor cell 200a). Therefore, in this case, the transfer structure 300 is easier to manufacture and design.

[0082] It should be noted that "cell density" here refers to the number of transistors in a single transistor cell. The areas occupied by the read transistor cell 100a and the write transistor cell 200a may be different. Therefore, "cell density" does not represent the number of transistors per unit area.

[0083] In one embodiment, see Figure 1 The first arrangement is a hexagonal arrangement. The second arrangement is a tetragonal arrangement. That is, in the read transistor unit 100a, the read transistors 100 are arranged in a hexagonal arrangement; in the write transistor unit 200a, the write transistors 200 are arranged in a tetragonal arrangement.

[0084] As an example, you can set the square arrangement as the target arrangement. In this case, see Figure 5b or Figure 6b The transfer structures 300 in the transfer unit 300a are arranged in a quadrilateral arrangement. In the same transfer unit 300a, each transfer structure 300 is connected to the conductive pillar 110 of the read transistor 100 in a different manner and is connected to the semiconductor pillar 210 of the write transistor 200 in the same manner.

[0085] Of course, a hexagonal arrangement can also be set as the target arrangement. In this case, the adapter structures 300 within the adapter unit 300a are arranged in a hexagonal arrangement. In the same adapter unit 300a, each adapter structure 300 connects to the semiconductor pillar 210 of the write transistor 200 in a different manner, and connects to the conductive pillar 110 of the read transistor 100 in the same manner.

[0086] In this embodiment, within the read transistor unit 100a, the read transistors 100 are arranged in a hexagonal arrangement. Within the write transistor unit 200a, the write transistors 200 are arranged in a tetragonal arrangement. In this case, they can be arranged between the conductive pillars 110 and the semiconductor pillars 210, with the conductive pillars 110 having a relatively small diameter and the semiconductor pillars 210 having a relatively large diameter. The thinner conductive pillars 110 are arranged in a hexagonal close-packed arrangement, while the thicker semiconductor pillars 210 are arranged in a tetragonal arrangement, thereby effectively increasing the arrangement density of the memory cells.

[0087] In one embodiment, see Figure 5b or Figure 6b , with a quadrilateral arrangement as the target arrangement. At this time, the adapter structures 300 within the adapter unit 300a are arranged in a quadrilateral arrangement. Each adapter structure 300 is connected to the semiconductor pillar 210 of the write transistor 200 in the same manner.

[0088] At the same time, the transfer structures 300 located in the same row contact the corresponding conductive pillars 110 through the same side, so that the performance of the memory cells located in the same row is more consistent.

[0089] In one embodiment, please refer to Figure 5b or Figure 6b When the quadrilateral arrangement is used as the target arrangement, the transfer structures 300 in the same row contact the corresponding conductive pillars 110 through the same side, and the transfer structures 300 in adjacent rows contact the corresponding conductive pillars 110 through opposite sides.

[0090] At this time, the hexagonal arrangement of the read transistors 100 can be easily and effectively converted into the quadrilateral arrangement of the write transistors 200 , thereby facilitating corresponding connection of the read transistors 100 and the write transistors 200 to form a memory cell.

[0091] In one embodiment, see Figure 2 The write transistor 200 is located above the read transistor 100 . One end of the transfer structure 300 contacts the upper surface of the conductive pillar 110 . The other end of the transfer structure 300 contacts the lower surface of the semiconductor pillar 210 .

[0092] As an example, when fabricating the read transistor 100, a first electrode 140, a first dielectric layer 910, a second electrode 150, and a second dielectric layer 920 can be formed on a substrate (not shown). A first trench is then formed from the second dielectric layer 920 through the first electrode 140. A read channel layer 130 is then formed on the sidewalls and bottom of the first trench, as well as on the surface of the second dielectric layer 920. A read gate dielectric layer 120 is then formed on the surface of the read channel layer 130. A conductive pillar 110 is then formed on the surface of the read gate dielectric layer 120. The conductive pillar 110 can completely fill the first trench.

[0093] Then, a third dielectric layer 930 is formed on the read transistor 100. Then, a contact hole is formed in the third dielectric layer 930. The contact hole is then filled to form the via structure 300.

[0094] Afterwards, a write transistor 200 is fabricated on the transfer structure 300. During the fabrication of the write transistor 200, a fourth dielectric layer 940 is formed on the third dielectric layer 930 and the transfer structure 300. Subsequently, a write gate layer 230 and a fifth dielectric layer 950 are sequentially formed on the fourth dielectric layer 940. A second trench is then formed extending from the fifth dielectric layer 950 to the top surface of the transfer structure 300. A write gate dielectric layer 220 is then formed on the sidewalls of the second trench. The top surface of the write dielectric layer 220 can be lower than the top surface of the fifth dielectric layer 950. Simultaneously, the top surface of the write dielectric layer 220 is higher than or equal to the top surface of the write gate layer 230. The second trench is then filled with semiconductor material to form a semiconductor pillar 210. The semiconductor pillar 210 can be formed through a deposition process, with different process gases introduced during different deposition periods, thereby forming a drain region 212, a channel region 213, and a source region 211 in different portions of the semiconductor pillar 210. After forming the semiconductor pillar 210, a write bit line 700 may be formed on the upper surface of the semiconductor pillar 210 and the upper surface of the fifth dielectric layer 950. Alternatively, see Figure 4 Alternatively, a sixth dielectric layer 960 may be first formed on the semiconductor pillar 210 and the fifth dielectric layer 950. A contact hole may then be formed in the sixth dielectric layer 960. The contact hole in the sixth dielectric layer 960 is then filled with a conductive material to form the bit line contact structure 800. A write bit line 700 may then be formed on the upper surface of the bit line contact structure 800 and the upper surface of the sixth dielectric layer 960.

[0095] It is understood that the first dielectric layer 910, the second dielectric layer 920, the third dielectric layer 930, the fourth dielectric layer 940, the fifth dielectric layer 950, and the sixth dielectric layer 960 are all insulating dielectric layers, and their materials may include, but are not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), or silicon oxynitride (SiON). Furthermore, the first dielectric layer 910, the second dielectric layer 920, the third dielectric layer 930, the fourth dielectric layer 940, the fifth dielectric layer 950, and the sixth dielectric layer 960 may all or partially be made of the same material, or may all be made of different materials.

[0096] In this embodiment, the two ends of the transfer structure 300 contact the upper surface of the conductive pillar 110 and the lower surface of the semiconductor pillar 210, respectively, thereby simplifying the manufacturing process of the transfer structure 300. Of course, in other embodiments, the transfer structure 300 may also contact the side surfaces of the conductive pillar 110 and / or the semiconductor pillar 210. This is not limited here.

[0097] In one embodiment, the read transistor 100 is used as the target transistor. The via structure 300 is coaxially disposed with the semiconductor pillar 210 .

[0098] When the read transistor 100 is used as the target transistor, the transfer structures 300 are arranged in the same manner as the read transistor 100. Each transfer structure 300 is connected to the semiconductor pillar 210 of the write transistor 200 in the same manner. In this case, the transfer structures 300 and the semiconductor pillar 210 are arranged coaxially, thereby further saving the space occupied by the memory cell and improving the memory cell density.

[0099] In one embodiment, the transfer structure 300 is coaxially arranged with the semiconductor pillar 210 and can also be arranged on a projection plane perpendicular to the first direction (the extension direction of the semiconductor pillar 210 ), and the orthographic projection of the transfer structure 300 is located within the orthographic projection of the semiconductor pillar 210 .

[0100] When a transfer unit 300a is provided between the read transistor unit 100a and the write transistor unit 200a to connect the conductive pillar 110 of the read transistor 100 and the semiconductor pillar 210 of the write transistor 200 via the transfer structure 300, the memory cell includes the read transistor 100, the write transistor 200, and the transfer structure 300 connecting the two. Therefore, the areas of the read transistor 100, the write transistor 200, and the transfer structure 300 all affect the area of ​​the memory cell.

[0101] At this time, the orthographic projection of the transfer structure 300 is located within the orthographic projection of the semiconductor column 210 on a projection plane perpendicular to the first direction, so that the setting of the transfer structure 300 does not affect the area occupied by the memory cell, thereby being more conducive to forming a high-density memory cell.

[0102] In one embodiment, see Figure 1 When the adapter structure 300 and the semiconductor pillar 210 are coaxially arranged, on a projection plane perpendicular to the first direction, the orthographic projection of the adapter structure 300 can be a square, and the orthographic projection of the semiconductor pillar 210 can be a circle. At the same time, the projected circle is set as the circumcircle of the projected square.

[0103] In this case, on the one hand, the provision of the transfer structure 300 does not affect the area occupied by the memory cells, thereby further facilitating the formation of high-density memory cells. On the other hand, the transfer structure 300 can be relatively large, thereby increasing the contact area between the transfer structure 300 and the semiconductor pillar 210, as well as the contact area between the transfer structure 300 and the conductive pillar 110. This effectively reduces the contact resistance between the transfer structure 300 and the semiconductor pillar 210, and also reduces the contact resistance between the transfer structure 300 and the conductive pillar 110.

[0104] Of course, in other embodiments, the adapter structure 300 may be configured in other forms. For example, on a projection plane perpendicular to the first direction, the orthographic projection of the adapter structure 300 and the orthographic projection of the semiconductor pillar 210 may intersect, or the orthographic projection of the semiconductor pillar 210 may be located within the orthographic projection of the adapter structure 300. Furthermore, the shapes of the orthographic projections of the adapter structure 300 and the semiconductor pillar 210 are not limited thereto.

[0105] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A storage structure, characterized in that: include: a plurality of read transistor units, each of the read transistor units including a plurality of read transistors arranged in a first arrangement, each of the read transistors including a conductive pillar extending along a first direction; a plurality of write transistor units, each of which includes a plurality of write transistors arranged in a second arrangement, each of which includes a semiconductor column, and each of which has the same extension direction as the conductive column; The conductive pillars in the same read transistor unit are connected to the semiconductor pillar in a different manner, and the semiconductor pillars in the same write transistor unit are connected to the conductive pillar in a different manner; in the first arrangement and the second arrangement, one of them is used as the target arrangement, The storage structure also includes: a plurality of transfer units, each of which is located between the read transistor unit and the write transistor unit in the first direction, and includes a plurality of transfer structures arranged in a target arrangement, the transfer structures connecting the conductive pillars and the semiconductor pillars, Among the read transistor and the write transistor, one arranged according to the target arrangement is used as the target transistor, and the other is used as the non-target transistor. In the same switching unit, each switching structure is connected to the non-target transistor in a different way and connected to the target transistor in the same way.

2. The storage structure according to claim 1, characterized in that: Among the first arrangement and the second arrangement, the one with a smaller number of transistors contained in a single transistor unit is used as the target arrangement.

3. The storage structure according to claim 1, characterized in that: The first arrangement is a hexagonal arrangement, and the second arrangement is a tetragonal arrangement.

4. The storage structure according to claim 3, characterized in that: Taking the square arrangement as the target arrangement, the transfer structures in the same row contact the corresponding conductive pillars through the same side.

5. The storage structure according to claim 4, characterized in that: The transfer structures located in adjacent rows contact the corresponding conductive pillars through opposite sides.

6. The storage structure according to claim 1, characterized in that: The write transistor is located above the read transistor, one end of the transfer structure contacts the upper surface of the conductive column, and the other end of the transfer structure contacts the lower surface of the semiconductor column.

7. The storage structure according to claim 6, characterized in that: The read transistor is used as the target transistor, and the switching structure is coaxially arranged with the semiconductor column.

8. The storage structure according to claim 7, characterized in that: On a projection plane perpendicular to the first direction, the orthographic projection of the transfer structure is located within the orthographic projection of the semiconductor column.

9. The storage structure according to claim 8, characterized in that: On a projection plane perpendicular to the first direction, the orthographic projection of the transition structure is a square, the orthographic projection of the semiconductor column is a circle, and the circle is a circumscribed circle of the square.

10. The storage structure according to claim 1, characterized in that: The write word line of the write transistor and the read word line of the read transistor extend in the same direction, and the write bit line of the write transistor and the read bit line of the read transistor extend in different directions.

11. The storage structure according to any one of claims 1 to 10, characterized in that: A channel material of the read transistor and / or the write transistor is an oxide semiconductor.

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